drivers/memory/omap-gpmc.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * GPMC support functions
   4  *
   5  * Copyright (C) 2005-2006 Nokia Corporation
   6  *
   7  * Author: Juha Yrjola
   8  *
   9  * Copyright (C) 2009 Texas Instruments
  10  * Added OMAP4 support - Santosh Shilimkar <[email protected]>
  11  */
  12 #include <linux/cpu_pm.h>
  13 #include <linux/irq.h>
  14 #include <linux/kernel.h>
  15 #include <linux/init.h>
  16 #include <linux/err.h>
  17 #include <linux/clk.h>
  18 #include <linux/ioport.h>
  19 #include <linux/spinlock.h>
  20 #include <linux/io.h>
  21 #include <linux/gpio/driver.h>
  22 #include <linux/gpio/consumer.h> /* GPIO descriptor enum */
  23 #include <linux/gpio/machine.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/irqdomain.h>
  26 #include <linux/platform_device.h>
  27 #include <linux/of.h>
  28 #include <linux/of_address.h>
  29 #include <linux/of_device.h>
  30 #include <linux/of_platform.h>
  31 #include <linux/omap-gpmc.h>
  32 #include <linux/pm_runtime.h>
  33 #include <linux/sizes.h>
  34
  35 #include <linux/platform_data/mtd-nand-omap2.h>
  36
  37 #define DEVICE_NAME             "omap-gpmc"
  38
  39 /* GPMC register offsets */
  40 #define GPMC_REVISION           0x00
  41 #define GPMC_SYSCONFIG          0x10
  42 #define GPMC_SYSSTATUS          0x14
  43 #define GPMC_IRQSTATUS          0x18
  44 #define GPMC_IRQENABLE          0x1c
  45 #define GPMC_TIMEOUT_CONTROL    0x40
  46 #define GPMC_ERR_ADDRESS        0x44
  47 #define GPMC_ERR_TYPE           0x48
  48 #define GPMC_CONFIG             0x50
  49 #define GPMC_STATUS             0x54
  50 #define GPMC_PREFETCH_CONFIG1   0x1e0
  51 #define GPMC_PREFETCH_CONFIG2   0x1e4
  52 #define GPMC_PREFETCH_CONTROL   0x1ec
  53 #define GPMC_PREFETCH_STATUS    0x1f0
  54 #define GPMC_ECC_CONFIG         0x1f4
  55 #define GPMC_ECC_CONTROL        0x1f8
  56 #define GPMC_ECC_SIZE_CONFIG    0x1fc
  57 #define GPMC_ECC1_RESULT        0x200
  58 #define GPMC_ECC_BCH_RESULT_0   0x240   /* not available on OMAP2 */
  59 #define GPMC_ECC_BCH_RESULT_1   0x244   /* not available on OMAP2 */
  60 #define GPMC_ECC_BCH_RESULT_2   0x248   /* not available on OMAP2 */
  61 #define GPMC_ECC_BCH_RESULT_3   0x24c   /* not available on OMAP2 */
  62 #define GPMC_ECC_BCH_RESULT_4   0x300   /* not available on OMAP2 */
  63 #define GPMC_ECC_BCH_RESULT_5   0x304   /* not available on OMAP2 */
  64 #define GPMC_ECC_BCH_RESULT_6   0x308   /* not available on OMAP2 */
  65
  66 /* GPMC ECC control settings */
  67 #define GPMC_ECC_CTRL_ECCCLEAR          0x100
  68 #define GPMC_ECC_CTRL_ECCDISABLE        0x000
  69 #define GPMC_ECC_CTRL_ECCREG1           0x001
  70 #define GPMC_ECC_CTRL_ECCREG2           0x002
  71 #define GPMC_ECC_CTRL_ECCREG3           0x003
  72 #define GPMC_ECC_CTRL_ECCREG4           0x004
  73 #define GPMC_ECC_CTRL_ECCREG5           0x005
  74 #define GPMC_ECC_CTRL_ECCREG6           0x006
  75 #define GPMC_ECC_CTRL_ECCREG7           0x007
  76 #define GPMC_ECC_CTRL_ECCREG8           0x008
  77 #define GPMC_ECC_CTRL_ECCREG9           0x009
  78
  79 #define GPMC_CONFIG_LIMITEDADDRESS              BIT(1)
  80
  81 #define GPMC_STATUS_EMPTYWRITEBUFFERSTATUS      BIT(0)
  82
  83 #define GPMC_CONFIG2_CSEXTRADELAY               BIT(7)
  84 #define GPMC_CONFIG3_ADVEXTRADELAY              BIT(7)
  85 #define GPMC_CONFIG4_OEEXTRADELAY               BIT(7)
  86 #define GPMC_CONFIG4_WEEXTRADELAY               BIT(23)
  87 #define GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN        BIT(6)
  88 #define GPMC_CONFIG6_CYCLE2CYCLESAMECSEN        BIT(7)
  89
  90 #define GPMC_CS0_OFFSET         0x60
  91 #define GPMC_CS_SIZE            0x30
  92 #define GPMC_BCH_SIZE           0x10
  93
  94 /*
  95  * The first 1MB of GPMC address space is typically mapped to
  96  * the internal ROM. Never allocate the first page, to
  97  * facilitate bug detection; even if we didn't boot from ROM.
  98  * As GPMC minimum partition size is 16MB we can only start from
  99  * there.
 100  */
 101 #define GPMC_MEM_START          0x1000000
 102 #define GPMC_MEM_END            0x3FFFFFFF
 103
 104 #define GPMC_CHUNK_SHIFT        24              /* 16 MB */
 105 #define GPMC_SECTION_SHIFT      28              /* 128 MB */
 106
 107 #define CS_NUM_SHIFT            24
 108 #define ENABLE_PREFETCH         (0x1 << 7)
 109 #define DMA_MPU_MODE            2
 110
 111 #define GPMC_REVISION_MAJOR(l)          (((l) >> 4) & 0xf)
 112 #define GPMC_REVISION_MINOR(l)          ((l) & 0xf)
 113
 114 #define GPMC_HAS_WR_ACCESS              0x1
 115 #define GPMC_HAS_WR_DATA_MUX_BUS        0x2
 116 #define GPMC_HAS_MUX_AAD                0x4
 117
 118 #define GPMC_NR_WAITPINS                4
 119
 120 #define GPMC_CS_CONFIG1         0x00
 121 #define GPMC_CS_CONFIG2         0x04
 122 #define GPMC_CS_CONFIG3         0x08
 123 #define GPMC_CS_CONFIG4         0x0c
 124 #define GPMC_CS_CONFIG5         0x10
 125 #define GPMC_CS_CONFIG6         0x14
 126 #define GPMC_CS_CONFIG7         0x18
 127 #define GPMC_CS_NAND_COMMAND    0x1c
 128 #define GPMC_CS_NAND_ADDRESS    0x20
 129 #define GPMC_CS_NAND_DATA       0x24
 130
 131 /* Control Commands */
 132 #define GPMC_CONFIG_RDY_BSY     0x00000001
 133 #define GPMC_CONFIG_DEV_SIZE    0x00000002
 134 #define GPMC_CONFIG_DEV_TYPE    0x00000003
 135
 136 #define GPMC_CONFIG1_WRAPBURST_SUPP     (1 << 31)
 137 #define GPMC_CONFIG1_READMULTIPLE_SUPP  (1 << 30)
 138 #define GPMC_CONFIG1_READTYPE_ASYNC     (0 << 29)
 139 #define GPMC_CONFIG1_READTYPE_SYNC      (1 << 29)
 140 #define GPMC_CONFIG1_WRITEMULTIPLE_SUPP (1 << 28)
 141 #define GPMC_CONFIG1_WRITETYPE_ASYNC    (0 << 27)
 142 #define GPMC_CONFIG1_WRITETYPE_SYNC     (1 << 27)
 143 #define GPMC_CONFIG1_CLKACTIVATIONTIME(val) (((val) & 3) << 25)
 144 /** CLKACTIVATIONTIME Max Ticks */
 145 #define GPMC_CONFIG1_CLKACTIVATIONTIME_MAX 2
 146 #define GPMC_CONFIG1_PAGE_LEN(val)      (((val) & 3) << 23)
 147 /** ATTACHEDDEVICEPAGELENGTH Max Value */
 148 #define GPMC_CONFIG1_ATTACHEDDEVICEPAGELENGTH_MAX 2
 149 #define GPMC_CONFIG1_WAIT_READ_MON      (1 << 22)
 150 #define GPMC_CONFIG1_WAIT_WRITE_MON     (1 << 21)
 151 #define GPMC_CONFIG1_WAIT_MON_TIME(val) (((val) & 3) << 18)
 152 /** WAITMONITORINGTIME Max Ticks */
 153 #define GPMC_CONFIG1_WAITMONITORINGTIME_MAX  2
 154 #define GPMC_CONFIG1_WAIT_PIN_SEL(val)  (((val) & 3) << 16)
 155 #define GPMC_CONFIG1_DEVICESIZE(val)    (((val) & 3) << 12)
 156 #define GPMC_CONFIG1_DEVICESIZE_16      GPMC_CONFIG1_DEVICESIZE(1)
 157 /** DEVICESIZE Max Value */
 158 #define GPMC_CONFIG1_DEVICESIZE_MAX     1
 159 #define GPMC_CONFIG1_DEVICETYPE(val)    (((val) & 3) << 10)
 160 #define GPMC_CONFIG1_DEVICETYPE_NOR     GPMC_CONFIG1_DEVICETYPE(0)
 161 #define GPMC_CONFIG1_MUXTYPE(val)       (((val) & 3) << 8)
 162 #define GPMC_CONFIG1_TIME_PARA_GRAN     (1 << 4)
 163 #define GPMC_CONFIG1_FCLK_DIV(val)      ((val) & 3)
 164 #define GPMC_CONFIG1_FCLK_DIV2          (GPMC_CONFIG1_FCLK_DIV(1))
 165 #define GPMC_CONFIG1_FCLK_DIV3          (GPMC_CONFIG1_FCLK_DIV(2))
 166 #define GPMC_CONFIG1_FCLK_DIV4          (GPMC_CONFIG1_FCLK_DIV(3))
 167 #define GPMC_CONFIG7_CSVALID            (1 << 6)
 168
 169 #define GPMC_CONFIG7_BASEADDRESS_MASK   0x3f
 170 #define GPMC_CONFIG7_CSVALID_MASK       BIT(6)
 171 #define GPMC_CONFIG7_MASKADDRESS_OFFSET 8
 172 #define GPMC_CONFIG7_MASKADDRESS_MASK   (0xf << GPMC_CONFIG7_MASKADDRESS_OFFSET)
 173 /* All CONFIG7 bits except reserved bits */
 174 #define GPMC_CONFIG7_MASK               (GPMC_CONFIG7_BASEADDRESS_MASK | \
 175                                          GPMC_CONFIG7_CSVALID_MASK |     \
 176                                          GPMC_CONFIG7_MASKADDRESS_MASK)
 177
 178 #define GPMC_DEVICETYPE_NOR             0
 179 #define GPMC_DEVICETYPE_NAND            2
 180 #define GPMC_CONFIG_WRITEPROTECT        0x00000010
 181 #define WR_RD_PIN_MONITORING            0x00600000
 182
 183 /* ECC commands */
 184 #define GPMC_ECC_READ           0 /* Reset Hardware ECC for read */
 185 #define GPMC_ECC_WRITE          1 /* Reset Hardware ECC for write */
 186 #define GPMC_ECC_READSYN        2 /* Reset before syndrom is read back */
 187
 188 #define GPMC_NR_NAND_IRQS       2 /* number of NAND specific IRQs */
 189
 190 enum gpmc_clk_domain {
 191         GPMC_CD_FCLK,
 192         GPMC_CD_CLK
 193 };
 194
 195 struct gpmc_cs_data {
 196         const char *name;
 197
 198 #define GPMC_CS_RESERVED        (1 << 0)
 199         u32 flags;
 200
 201         struct resource mem;
 202 };
 203
 204 /* Structure to save gpmc cs context */
 205 struct gpmc_cs_config {
 206         u32 config1;
 207         u32 config2;
 208         u32 config3;
 209         u32 config4;
 210         u32 config5;
 211         u32 config6;
 212         u32 config7;
 213         int is_valid;
 214 };
 215
 216 /*
 217  * Structure to save/restore gpmc context
 218  * to support core off on OMAP3
 219  */
 220 struct omap3_gpmc_regs {
 221         u32 sysconfig;
 222         u32 irqenable;
 223         u32 timeout_ctrl;
 224         u32 config;
 225         u32 prefetch_config1;
 226         u32 prefetch_config2;
 227         u32 prefetch_control;
 228         struct gpmc_cs_config cs_context[GPMC_CS_NUM];
 229 };
 230
 231 struct gpmc_device {
 232         struct device *dev;
 233         int irq;
 234         struct irq_chip irq_chip;
 235         struct gpio_chip gpio_chip;
 236         struct notifier_block nb;
 237         struct omap3_gpmc_regs context;
 238         int nirqs;
 239         unsigned int is_suspended:1;
 240         struct resource *data;
 241 };
 242
 243 static struct irq_domain *gpmc_irq_domain;
 244
 245 static struct resource  gpmc_mem_root;
 246 static struct gpmc_cs_data gpmc_cs[GPMC_CS_NUM];
 247 static DEFINE_SPINLOCK(gpmc_mem_lock);
 248 /* Define chip-selects as reserved by default until probe completes */
 249 static unsigned int gpmc_cs_num = GPMC_CS_NUM;
 250 static unsigned int gpmc_nr_waitpins;
 251 static unsigned int gpmc_capability;
 252 static void __iomem *gpmc_base;
 253
 254 static struct clk *gpmc_l3_clk;
 255
 256 static irqreturn_t gpmc_handle_irq(int irq, void *dev);
 257
 258 static void gpmc_write_reg(int idx, u32 val)
 259 {
 260         writel_relaxed(val, gpmc_base + idx);
 261 }
 262
 263 static u32 gpmc_read_reg(int idx)
 264 {
 265         return readl_relaxed(gpmc_base + idx);
 266 }
 267
 268 void gpmc_cs_write_reg(int cs, int idx, u32 val)
 269 {
 270         void __iomem *reg_addr;
 271
 272         reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
 273         writel_relaxed(val, reg_addr);
 274 }
 275
 276 static u32 gpmc_cs_read_reg(int cs, int idx)
 277 {
 278         void __iomem *reg_addr;
 279
 280         reg_addr = gpmc_base + GPMC_CS0_OFFSET + (cs * GPMC_CS_SIZE) + idx;
 281         return readl_relaxed(reg_addr);
 282 }
 283
 284 /* TODO: Add support for gpmc_fck to clock framework and use it */
 285 static unsigned long gpmc_get_fclk_period(void)
 286 {
 287         unsigned long rate = clk_get_rate(gpmc_l3_clk);
 288
 289         rate /= 1000;
 290         rate = 1000000000 / rate;       /* In picoseconds */
 291
 292         return rate;
 293 }
 294
 295 /**
 296  * gpmc_get_clk_period - get period of selected clock domain in ps
 297  * @cs: Chip Select Region.
 298  * @cd: Clock Domain.
 299  *
 300  * GPMC_CS_CONFIG1 GPMCFCLKDIVIDER for cs has to be setup
 301  * prior to calling this function with GPMC_CD_CLK.
 302  */
 303 static unsigned long gpmc_get_clk_period(int cs, enum gpmc_clk_domain cd)
 304 {
 305         unsigned long tick_ps = gpmc_get_fclk_period();
 306         u32 l;
 307         int div;
 308
 309         switch (cd) {
 310         case GPMC_CD_CLK:
 311                 /* get current clk divider */
 312                 l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
 313                 div = (l & 0x03) + 1;
 314                 /* get GPMC_CLK period */
 315                 tick_ps *= div;
 316                 break;
 317         case GPMC_CD_FCLK:
 318         default:
 319                 break;
 320         }
 321
 322         return tick_ps;
 323 }
 324
 325 static unsigned int gpmc_ns_to_clk_ticks(unsigned int time_ns, int cs,
 326                                          enum gpmc_clk_domain cd)
 327 {
 328         unsigned long tick_ps;
 329
 330         /* Calculate in picosecs to yield more exact results */
 331         tick_ps = gpmc_get_clk_period(cs, cd);
 332
 333         return (time_ns * 1000 + tick_ps - 1) / tick_ps;
 334 }
 335
 336 static unsigned int gpmc_ns_to_ticks(unsigned int time_ns)
 337 {
 338         return gpmc_ns_to_clk_ticks(time_ns, /* any CS */ 0, GPMC_CD_FCLK);
 339 }
 340
 341 static unsigned int gpmc_ps_to_ticks(unsigned int time_ps)
 342 {
 343         unsigned long tick_ps;
 344
 345         /* Calculate in picosecs to yield more exact results */
 346         tick_ps = gpmc_get_fclk_period();
 347
 348         return (time_ps + tick_ps - 1) / tick_ps;
 349 }
 350
 351 static unsigned int gpmc_clk_ticks_to_ns(unsigned int ticks, int cs,
 352                                          enum gpmc_clk_domain cd)
 353 {
 354         return ticks * gpmc_get_clk_period(cs, cd) / 1000;
 355 }
 356
 357 unsigned int gpmc_ticks_to_ns(unsigned int ticks)
 358 {
 359         return gpmc_clk_ticks_to_ns(ticks, /* any CS */ 0, GPMC_CD_FCLK);
 360 }
 361
 362 static unsigned int gpmc_ticks_to_ps(unsigned int ticks)
 363 {
 364         return ticks * gpmc_get_fclk_period();
 365 }
 366
 367 static unsigned int gpmc_round_ps_to_ticks(unsigned int time_ps)
 368 {
 369         unsigned long ticks = gpmc_ps_to_ticks(time_ps);
 370
 371         return ticks * gpmc_get_fclk_period();
 372 }
 373
 374 static inline void gpmc_cs_modify_reg(int cs, int reg, u32 mask, bool value)
 375 {
 376         u32 l;
 377
 378         l = gpmc_cs_read_reg(cs, reg);
 379         if (value)
 380                 l |= mask;
 381         else
 382                 l &= ~mask;
 383         gpmc_cs_write_reg(cs, reg, l);
 384 }
 385
 386 static void gpmc_cs_bool_timings(int cs, const struct gpmc_bool_timings *p)
 387 {
 388         gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG1,
 389                            GPMC_CONFIG1_TIME_PARA_GRAN,
 390                            p->time_para_granularity);
 391         gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG2,
 392                            GPMC_CONFIG2_CSEXTRADELAY, p->cs_extra_delay);
 393         gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG3,
 394                            GPMC_CONFIG3_ADVEXTRADELAY, p->adv_extra_delay);
 395         gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG4,
 396                            GPMC_CONFIG4_OEEXTRADELAY, p->oe_extra_delay);
 397         gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG4,
 398                            GPMC_CONFIG4_WEEXTRADELAY, p->we_extra_delay);
 399         gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG6,
 400                            GPMC_CONFIG6_CYCLE2CYCLESAMECSEN,
 401                            p->cycle2cyclesamecsen);
 402         gpmc_cs_modify_reg(cs, GPMC_CS_CONFIG6,
 403                            GPMC_CONFIG6_CYCLE2CYCLEDIFFCSEN,
 404                            p->cycle2cyclediffcsen);
 405 }
 406
 407 #ifdef CONFIG_OMAP_GPMC_DEBUG
 408 /**
 409  * get_gpmc_timing_reg - read a timing parameter and print DTS settings for it.
 410  * @cs:      Chip Select Region
 411  * @reg:     GPMC_CS_CONFIGn register offset.
 412  * @st_bit:  Start Bit
 413  * @end_bit: End Bit. Must be >= @st_bit.
 414  * @max:     Maximum parameter value (before optional @shift).
 415  *           If 0, maximum is as high as @st_bit and @end_bit allow.
 416  * @name:    DTS node name, w/o "gpmc,"
 417  * @cd:      Clock Domain of timing parameter.
 418  * @shift:   Parameter value left shifts @shift, which is then printed instead of value.
 419  * @raw:     Raw Format Option.
 420  *           raw format:  gpmc,name = <value>
 421  *           tick format: gpmc,name = <value> /&zwj;* x ns -- y ns; x ticks *&zwj;/
 422  *           Where x ns -- y ns result in the same tick value.
 423  *           When @max is exceeded, "invalid" is printed inside comment.
 424  * @noval:   Parameter values equal to 0 are not printed.
 425  * @return:  Specified timing parameter (after optional @shift).
 426  *
 427  */
 428 static int get_gpmc_timing_reg(
 429         /* timing specifiers */
 430         int cs, int reg, int st_bit, int end_bit, int max,
 431         const char *name, const enum gpmc_clk_domain cd,
 432         /* value transform */
 433         int shift,
 434         /* format specifiers */
 435         bool raw, bool noval)
 436 {
 437         u32 l;
 438         int nr_bits;
 439         int mask;
 440         bool invalid;
 441
 442         l = gpmc_cs_read_reg(cs, reg);
 443         nr_bits = end_bit - st_bit + 1;
 444         mask = (1 << nr_bits) - 1;
 445         l = (l >> st_bit) & mask;
 446         if (!max)
 447                 max = mask;
 448         invalid = l > max;
 449         if (shift)
 450                 l = (shift << l);
 451         if (noval && (l == 0))
 452                 return 0;
 453         if (!raw) {
 454                 /* DTS tick format for timings in ns */
 455                 unsigned int time_ns;
 456                 unsigned int time_ns_min = 0;
 457
 458                 if (l)
 459                         time_ns_min = gpmc_clk_ticks_to_ns(l - 1, cs, cd) + 1;
 460                 time_ns = gpmc_clk_ticks_to_ns(l, cs, cd);
 461                 pr_info("gpmc,%s = <%u>; /* %u ns - %u ns; %i ticks%s*/\n",
 462                         name, time_ns, time_ns_min, time_ns, l,
 463                         invalid ? "; invalid " : " ");
 464         } else {
 465                 /* raw format */
 466                 pr_info("gpmc,%s = <%u>;%s\n", name, l,
 467                         invalid ? " /* invalid */" : "");
 468         }
 469
 470         return l;
 471 }
 472
 473 #define GPMC_PRINT_CONFIG(cs, config) \
 474         pr_info("cs%i %s: 0x%08x\n", cs, #config, \
 475                 gpmc_cs_read_reg(cs, config))
 476 #define GPMC_GET_RAW(reg, st, end, field) \
 477         get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 1, 0)
 478 #define GPMC_GET_RAW_MAX(reg, st, end, max, field) \
 479         get_gpmc_timing_reg(cs, (reg), (st), (end), (max), field, GPMC_CD_FCLK, 0, 1, 0)
 480 #define GPMC_GET_RAW_BOOL(reg, st, end, field) \
 481         get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 1, 1)
 482 #define GPMC_GET_RAW_SHIFT_MAX(reg, st, end, shift, max, field) \
 483         get_gpmc_timing_reg(cs, (reg), (st), (end), (max), field, GPMC_CD_FCLK, (shift), 1, 1)
 484 #define GPMC_GET_TICKS(reg, st, end, field) \
 485         get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, GPMC_CD_FCLK, 0, 0, 0)
 486 #define GPMC_GET_TICKS_CD(reg, st, end, field, cd) \
 487         get_gpmc_timing_reg(cs, (reg), (st), (end), 0, field, (cd), 0, 0, 0)
 488 #define GPMC_GET_TICKS_CD_MAX(reg, st, end, max, field, cd) \
 489         get_gpmc_timing_reg(cs, (reg), (st), (end), (max), field, (cd), 0, 0, 0)
 490
 491 static void gpmc_show_regs(int cs, const char *desc)
 492 {
 493         pr_info("gpmc cs%i %s:\n", cs, desc);
 494         GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG1);
 495         GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG2);
 496         GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG3);
 497         GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG4);
 498         GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG5);
 499         GPMC_PRINT_CONFIG(cs, GPMC_CS_CONFIG6);
 500 }
 501
 502 /*
 503  * Note that gpmc,wait-pin handing wrongly assumes bit 8 is available,
 504  * see commit c9fb809.
 505  */
 506 static void gpmc_cs_show_timings(int cs, const char *desc)
 507 {
 508         gpmc_show_regs(cs, desc);
 509
 510         pr_info("gpmc cs%i access configuration:\n", cs);
 511         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1,  4,  4, "time-para-granularity");
 512         GPMC_GET_RAW(GPMC_CS_CONFIG1,  8,  9, "mux-add-data");
 513         GPMC_GET_RAW_SHIFT_MAX(GPMC_CS_CONFIG1, 12, 13, 1,
 514                                GPMC_CONFIG1_DEVICESIZE_MAX, "device-width");
 515         GPMC_GET_RAW(GPMC_CS_CONFIG1, 16, 17, "wait-pin");
 516         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 21, 21, "wait-on-write");
 517         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 22, 22, "wait-on-read");
 518         GPMC_GET_RAW_SHIFT_MAX(GPMC_CS_CONFIG1, 23, 24, 4,
 519                                GPMC_CONFIG1_ATTACHEDDEVICEPAGELENGTH_MAX,
 520                                "burst-length");
 521         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 27, 27, "sync-write");
 522         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 28, 28, "burst-write");
 523         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 29, 29, "gpmc,sync-read");
 524         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 30, 30, "burst-read");
 525         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG1, 31, 31, "burst-wrap");
 526
 527         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG2,  7,  7, "cs-extra-delay");
 528
 529         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG3,  7,  7, "adv-extra-delay");
 530
 531         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG4, 23, 23, "we-extra-delay");
 532         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG4,  7,  7, "oe-extra-delay");
 533
 534         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG6,  7,  7, "cycle2cycle-samecsen");
 535         GPMC_GET_RAW_BOOL(GPMC_CS_CONFIG6,  6,  6, "cycle2cycle-diffcsen");
 536
 537         pr_info("gpmc cs%i timings configuration:\n", cs);
 538         GPMC_GET_TICKS(GPMC_CS_CONFIG2,  0,  3, "cs-on-ns");
 539         GPMC_GET_TICKS(GPMC_CS_CONFIG2,  8, 12, "cs-rd-off-ns");
 540         GPMC_GET_TICKS(GPMC_CS_CONFIG2, 16, 20, "cs-wr-off-ns");
 541
 542         GPMC_GET_TICKS(GPMC_CS_CONFIG3,  0,  3, "adv-on-ns");
 543         GPMC_GET_TICKS(GPMC_CS_CONFIG3,  8, 12, "adv-rd-off-ns");
 544         GPMC_GET_TICKS(GPMC_CS_CONFIG3, 16, 20, "adv-wr-off-ns");
 545         if (gpmc_capability & GPMC_HAS_MUX_AAD) {
 546                 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 4, 6, "adv-aad-mux-on-ns");
 547                 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 24, 26,
 548                                 "adv-aad-mux-rd-off-ns");
 549                 GPMC_GET_TICKS(GPMC_CS_CONFIG3, 28, 30,
 550                                 "adv-aad-mux-wr-off-ns");
 551         }
 552
 553         GPMC_GET_TICKS(GPMC_CS_CONFIG4,  0,  3, "oe-on-ns");
 554         GPMC_GET_TICKS(GPMC_CS_CONFIG4,  8, 12, "oe-off-ns");
 555         if (gpmc_capability & GPMC_HAS_MUX_AAD) {
 556                 GPMC_GET_TICKS(GPMC_CS_CONFIG4,  4,  6, "oe-aad-mux-on-ns");
 557                 GPMC_GET_TICKS(GPMC_CS_CONFIG4, 13, 15, "oe-aad-mux-off-ns");
 558         }
 559         GPMC_GET_TICKS(GPMC_CS_CONFIG4, 16, 19, "we-on-ns");
 560         GPMC_GET_TICKS(GPMC_CS_CONFIG4, 24, 28, "we-off-ns");
 561
 562         GPMC_GET_TICKS(GPMC_CS_CONFIG5,  0,  4, "rd-cycle-ns");
 563         GPMC_GET_TICKS(GPMC_CS_CONFIG5,  8, 12, "wr-cycle-ns");
 564         GPMC_GET_TICKS(GPMC_CS_CONFIG5, 16, 20, "access-ns");
 565
 566         GPMC_GET_TICKS(GPMC_CS_CONFIG5, 24, 27, "page-burst-access-ns");
 567
 568         GPMC_GET_TICKS(GPMC_CS_CONFIG6, 0, 3, "bus-turnaround-ns");
 569         GPMC_GET_TICKS(GPMC_CS_CONFIG6, 8, 11, "cycle2cycle-delay-ns");
 570
 571         GPMC_GET_TICKS_CD_MAX(GPMC_CS_CONFIG1, 18, 19,
 572                               GPMC_CONFIG1_WAITMONITORINGTIME_MAX,
 573                               "wait-monitoring-ns", GPMC_CD_CLK);
 574         GPMC_GET_TICKS_CD_MAX(GPMC_CS_CONFIG1, 25, 26,
 575                               GPMC_CONFIG1_CLKACTIVATIONTIME_MAX,
 576                               "clk-activation-ns", GPMC_CD_FCLK);
 577
 578         GPMC_GET_TICKS(GPMC_CS_CONFIG6, 16, 19, "wr-data-mux-bus-ns");
 579         GPMC_GET_TICKS(GPMC_CS_CONFIG6, 24, 28, "wr-access-ns");
 580 }
 581 #else
 582 static inline void gpmc_cs_show_timings(int cs, const char *desc)
 583 {
 584 }
 585 #endif
 586
 587 /**
 588  * set_gpmc_timing_reg - set a single timing parameter for Chip Select Region.
 589  * Caller is expected to have initialized CONFIG1 GPMCFCLKDIVIDER
 590  * prior to calling this function with @cd equal to GPMC_CD_CLK.
 591  *
 592  * @cs:      Chip Select Region.
 593  * @reg:     GPMC_CS_CONFIGn register offset.
 594  * @st_bit:  Start Bit
 595  * @end_bit: End Bit. Must be >= @st_bit.
 596  * @max:     Maximum parameter value.
 597  *           If 0, maximum is as high as @st_bit and @end_bit allow.
 598  * @time:    Timing parameter in ns.
 599  * @cd:      Timing parameter clock domain.
 600  * @name:    Timing parameter name.
 601  * @return:  0 on success, -1 on error.
 602  */
 603 static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit, int max,
 604                                int time, enum gpmc_clk_domain cd, const char *name)
 605 {
 606         u32 l;
 607         int ticks, mask, nr_bits;
 608
 609         if (time == 0)
 610                 ticks = 0;
 611         else
 612                 ticks = gpmc_ns_to_clk_ticks(time, cs, cd);
 613         nr_bits = end_bit - st_bit + 1;
 614         mask = (1 << nr_bits) - 1;
 615
 616         if (!max)
 617                 max = mask;
 618
 619         if (ticks > max) {
 620                 pr_err("%s: GPMC CS%d: %s %d ns, %d ticks > %d ticks\n",
 621                        __func__, cs, name, time, ticks, max);
 622
 623                 return -1;
 624         }
 625
 626         l = gpmc_cs_read_reg(cs, reg);
 627 #ifdef CONFIG_OMAP_GPMC_DEBUG
 628         pr_info("GPMC CS%d: %-17s: %3d ticks, %3lu ns (was %3i ticks) %3d ns\n",
 629                 cs, name, ticks, gpmc_get_clk_period(cs, cd) * ticks / 1000,
 630                         (l >> st_bit) & mask, time);
 631 #endif
 632         l &= ~(mask << st_bit);
 633         l |= ticks << st_bit;
 634         gpmc_cs_write_reg(cs, reg, l);
 635
 636         return 0;
 637 }
 638
 639 /**
 640  * gpmc_calc_waitmonitoring_divider - calculate proper GPMCFCLKDIVIDER based on WAITMONITORINGTIME
 641  * WAITMONITORINGTIME will be _at least_ as long as desired, i.e.
 642  * read  --> don't sample bus too early
 643  * write --> data is longer on bus
 644  *
 645  * Formula:
 646  * gpmc_clk_div + 1 = ceil(ceil(waitmonitoringtime_ns / gpmc_fclk_ns)
 647  *                    / waitmonitoring_ticks)
 648  * WAITMONITORINGTIME resulting in 0 or 1 tick with div = 1 are caught by
 649  * div <= 0 check.
 650  *
 651  * @wait_monitoring: WAITMONITORINGTIME in ns.
 652  * @return:          -1 on failure to scale, else proper divider > 0.
 653  */
 654 static int gpmc_calc_waitmonitoring_divider(unsigned int wait_monitoring)
 655 {
 656         int div = gpmc_ns_to_ticks(wait_monitoring);
 657
 658         div += GPMC_CONFIG1_WAITMONITORINGTIME_MAX - 1;
 659         div /= GPMC_CONFIG1_WAITMONITORINGTIME_MAX;
 660
 661         if (div > 4)
 662                 return -1;
 663         if (div <= 0)
 664                 div = 1;
 665
 666         return div;
 667 }
 668
 669 /**
 670  * gpmc_calc_divider - calculate GPMC_FCLK divider for sync_clk GPMC_CLK period.
 671  * @sync_clk: GPMC_CLK period in ps.
 672  * @return:   Returns at least 1 if GPMC_FCLK can be divided to GPMC_CLK.
 673  *            Else, returns -1.
 674  */
 675 int gpmc_calc_divider(unsigned int sync_clk)
 676 {
 677         int div = gpmc_ps_to_ticks(sync_clk);
 678
 679         if (div > 4)
 680                 return -1;
 681         if (div <= 0)
 682                 div = 1;
 683
 684         return div;
 685 }
 686
 687 /**
 688  * gpmc_cs_set_timings - program timing parameters for Chip Select Region.
 689  * @cs:     Chip Select Region.
 690  * @t:      GPMC timing parameters.
 691  * @s:      GPMC timing settings.
 692  * @return: 0 on success, -1 on error.
 693  */
 694 int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t,
 695                         const struct gpmc_settings *s)
 696 {
 697         int div, ret;
 698         u32 l;
 699
 700         div = gpmc_calc_divider(t->sync_clk);
 701         if (div < 0)
 702                 return -EINVAL;
 703
 704         /*
 705          * See if we need to change the divider for waitmonitoringtime.
 706          *
 707          * Calculate GPMCFCLKDIVIDER independent of gpmc,sync-clk-ps in DT for
 708          * pure asynchronous accesses, i.e. both read and write asynchronous.
 709          * However, only do so if WAITMONITORINGTIME is actually used, i.e.
 710          * either WAITREADMONITORING or WAITWRITEMONITORING is set.
 711          *
 712          * This statement must not change div to scale async WAITMONITORINGTIME
 713          * to protect mixed synchronous and asynchronous accesses.
 714          *
 715          * We raise an error later if WAITMONITORINGTIME does not fit.
 716          */
 717         if (!s->sync_read && !s->sync_write &&
 718             (s->wait_on_read || s->wait_on_write)
 719            ) {
 720                 div = gpmc_calc_waitmonitoring_divider(t->wait_monitoring);
 721                 if (div < 0) {
 722                         pr_err("%s: waitmonitoringtime %3d ns too large for greatest gpmcfclkdivider.\n",
 723                                __func__,
 724                                t->wait_monitoring
 725                                );
 726                         return -ENXIO;
 727                 }
 728         }
 729
 730         ret = 0;
 731         ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG2, 0, 3, 0, t->cs_on,
 732                                    GPMC_CD_FCLK, "cs_on");
 733         ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG2, 8, 12, 0, t->cs_rd_off,
 734                                    GPMC_CD_FCLK, "cs_rd_off");
 735         ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG2, 16, 20, 0, t->cs_wr_off,
 736                                    GPMC_CD_FCLK, "cs_wr_off");
 737         if (ret)
 738                 return -ENXIO;
 739
 740         ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG3, 0, 3, 0, t->adv_on,
 741                                    GPMC_CD_FCLK, "adv_on");
 742         ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG3, 8, 12, 0, t->adv_rd_off,
 743                                    GPMC_CD_FCLK, "adv_rd_off");
 744         ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG3, 16, 20, 0, t->adv_wr_off,
 745                                    GPMC_CD_FCLK, "adv_wr_off");
 746         if (ret)
 747                 return -ENXIO;
 748
 749         if (gpmc_capability & GPMC_HAS_MUX_AAD) {
 750                 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG3, 4, 6, 0,
 751                                            t->adv_aad_mux_on, GPMC_CD_FCLK,
 752                                            "adv_aad_mux_on");
 753                 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG3, 24, 26, 0,
 754                                            t->adv_aad_mux_rd_off, GPMC_CD_FCLK,
 755                                            "adv_aad_mux_rd_off");
 756                 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG3, 28, 30, 0,
 757                                            t->adv_aad_mux_wr_off, GPMC_CD_FCLK,
 758                                            "adv_aad_mux_wr_off");
 759                 if (ret)
 760                         return -ENXIO;
 761         }
 762
 763         ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG4, 0, 3, 0, t->oe_on,
 764                                    GPMC_CD_FCLK, "oe_on");
 765         ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG4, 8, 12, 0, t->oe_off,
 766                                    GPMC_CD_FCLK, "oe_off");
 767         if (gpmc_capability & GPMC_HAS_MUX_AAD) {
 768                 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG4, 4, 6, 0,
 769                                            t->oe_aad_mux_on, GPMC_CD_FCLK,
 770                                            "oe_aad_mux_on");
 771                 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG4, 13, 15, 0,
 772                                            t->oe_aad_mux_off, GPMC_CD_FCLK,
 773                                            "oe_aad_mux_off");
 774         }
 775         ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG4, 16, 19, 0, t->we_on,
 776                                    GPMC_CD_FCLK, "we_on");
 777         ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG4, 24, 28, 0, t->we_off,
 778                                    GPMC_CD_FCLK, "we_off");
 779         if (ret)
 780                 return -ENXIO;
 781
 782         ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG5, 0, 4, 0, t->rd_cycle,
 783                                    GPMC_CD_FCLK, "rd_cycle");
 784         ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG5, 8, 12, 0, t->wr_cycle,
 785                                    GPMC_CD_FCLK, "wr_cycle");
 786         ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG5, 16, 20, 0, t->access,
 787                                    GPMC_CD_FCLK, "access");
 788         ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG5, 24, 27, 0,
 789                                    t->page_burst_access, GPMC_CD_FCLK,
 790                                    "page_burst_access");
 791         if (ret)
 792                 return -ENXIO;
 793
 794         ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG6, 0, 3, 0,
 795                                    t->bus_turnaround, GPMC_CD_FCLK,
 796                                    "bus_turnaround");
 797         ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG6, 8, 11, 0,
 798                                    t->cycle2cycle_delay, GPMC_CD_FCLK,
 799                                    "cycle2cycle_delay");
 800         if (ret)
 801                 return -ENXIO;
 802
 803         if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS) {
 804                 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG6, 16, 19, 0,
 805                                            t->wr_data_mux_bus, GPMC_CD_FCLK,
 806                                            "wr_data_mux_bus");
 807                 if (ret)
 808                         return -ENXIO;
 809         }
 810         if (gpmc_capability & GPMC_HAS_WR_ACCESS) {
 811                 ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG6, 24, 28, 0,
 812                                            t->wr_access, GPMC_CD_FCLK,
 813                                            "wr_access");
 814                 if (ret)
 815                         return -ENXIO;
 816         }
 817
 818         l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
 819         l &= ~0x03;
 820         l |= (div - 1);
 821         gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, l);
 822
 823         ret = 0;
 824         ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG1, 18, 19,
 825                                    GPMC_CONFIG1_WAITMONITORINGTIME_MAX,
 826                                    t->wait_monitoring, GPMC_CD_CLK,
 827                                    "wait_monitoring");
 828         ret |= set_gpmc_timing_reg(cs, GPMC_CS_CONFIG1, 25, 26,
 829                                    GPMC_CONFIG1_CLKACTIVATIONTIME_MAX,
 830                                    t->clk_activation, GPMC_CD_FCLK,
 831                                    "clk_activation");
 832         if (ret)
 833                 return -ENXIO;
 834
 835 #ifdef CONFIG_OMAP_GPMC_DEBUG
 836         pr_info("GPMC CS%d CLK period is %lu ns (div %d)\n",
 837                         cs, (div * gpmc_get_fclk_period()) / 1000, div);
 838 #endif
 839
 840         gpmc_cs_bool_timings(cs, &t->bool_timings);
 841         gpmc_cs_show_timings(cs, "after gpmc_cs_set_timings");
 842
 843         return 0;
 844 }
 845
 846 static int gpmc_cs_set_memconf(int cs, u32 base, u32 size)
 847 {
 848         u32 l;
 849         u32 mask;
 850
 851         /*
 852          * Ensure that base address is aligned on a
 853          * boundary equal to or greater than size.
 854          */
 855         if (base & (size - 1))
 856                 return -EINVAL;
 857
 858         base >>= GPMC_CHUNK_SHIFT;
 859         mask = (1 << GPMC_SECTION_SHIFT) - size;
 860         mask >>= GPMC_CHUNK_SHIFT;
 861         mask <<= GPMC_CONFIG7_MASKADDRESS_OFFSET;
 862
 863         l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
 864         l &= ~GPMC_CONFIG7_MASK;
 865         l |= base & GPMC_CONFIG7_BASEADDRESS_MASK;
 866         l |= mask & GPMC_CONFIG7_MASKADDRESS_MASK;
 867         l |= GPMC_CONFIG7_CSVALID;
 868         gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
 869
 870         return 0;
 871 }
 872
 873 static void gpmc_cs_enable_mem(int cs)
 874 {
 875         u32 l;
 876
 877         l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
 878         l |= GPMC_CONFIG7_CSVALID;
 879         gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
 880 }
 881
 882 static void gpmc_cs_disable_mem(int cs)
 883 {
 884         u32 l;
 885
 886         l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
 887         l &= ~GPMC_CONFIG7_CSVALID;
 888         gpmc_cs_write_reg(cs, GPMC_CS_CONFIG7, l);
 889 }
 890
 891 static void gpmc_cs_get_memconf(int cs, u32 *base, u32 *size)
 892 {
 893         u32 l;
 894         u32 mask;
 895
 896         l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
 897         *base = (l & 0x3f) << GPMC_CHUNK_SHIFT;
 898         mask = (l >> 8) & 0x0f;
 899         *size = (1 << GPMC_SECTION_SHIFT) - (mask << GPMC_CHUNK_SHIFT);
 900 }
 901
 902 static int gpmc_cs_mem_enabled(int cs)
 903 {
 904         u32 l;
 905
 906         l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG7);
 907         return l & GPMC_CONFIG7_CSVALID;
 908 }
 909
 910 static void gpmc_cs_set_reserved(int cs, int reserved)
 911 {
 912         struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
 913
 914         gpmc->flags |= GPMC_CS_RESERVED;
 915 }
 916
 917 static bool gpmc_cs_reserved(int cs)
 918 {
 919         struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
 920
 921         return gpmc->flags & GPMC_CS_RESERVED;
 922 }
 923
 924 static unsigned long gpmc_mem_align(unsigned long size)
 925 {
 926         int order;
 927
 928         size = (size - 1) >> (GPMC_CHUNK_SHIFT - 1);
 929         order = GPMC_CHUNK_SHIFT - 1;
 930         do {
 931                 size >>= 1;
 932                 order++;
 933         } while (size);
 934         size = 1 << order;
 935         return size;
 936 }
 937
 938 static int gpmc_cs_insert_mem(int cs, unsigned long base, unsigned long size)
 939 {
 940         struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
 941         struct resource *res = &gpmc->mem;
 942         int r;
 943
 944         size = gpmc_mem_align(size);
 945         spin_lock(&gpmc_mem_lock);
 946         res->start = base;
 947         res->end = base + size - 1;
 948         r = request_resource(&gpmc_mem_root, res);
 949         spin_unlock(&gpmc_mem_lock);
 950
 951         return r;
 952 }
 953
 954 static int gpmc_cs_delete_mem(int cs)
 955 {
 956         struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
 957         struct resource *res = &gpmc->mem;
 958         int r;
 959
 960         spin_lock(&gpmc_mem_lock);
 961         r = release_resource(res);
 962         res->start = 0;
 963         res->end = 0;
 964         spin_unlock(&gpmc_mem_lock);
 965
 966         return r;
 967 }
 968
 969 int gpmc_cs_request(int cs, unsigned long size, unsigned long *base)
 970 {
 971         struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
 972         struct resource *res = &gpmc->mem;
 973         int r = -1;
 974
 975         if (cs >= gpmc_cs_num) {
 976                 pr_err("%s: requested chip-select is disabled\n", __func__);
 977                 return -ENODEV;
 978         }
 979         size = gpmc_mem_align(size);
 980         if (size > (1 << GPMC_SECTION_SHIFT))
 981                 return -ENOMEM;
 982
 983         spin_lock(&gpmc_mem_lock);
 984         if (gpmc_cs_reserved(cs)) {
 985                 r = -EBUSY;
 986                 goto out;
 987         }
 988         if (gpmc_cs_mem_enabled(cs))
 989                 r = adjust_resource(res, res->start & ~(size - 1), size);
 990         if (r < 0)
 991                 r = allocate_resource(&gpmc_mem_root, res, size, 0, ~0,
 992                                       size, NULL, NULL);
 993         if (r < 0)
 994                 goto out;
 995
 996         /* Disable CS while changing base address and size mask */
 997         gpmc_cs_disable_mem(cs);
 998
 999         r = gpmc_cs_set_memconf(cs, res->start, resource_size(res));
1000         if (r < 0) {
1001                 release_resource(res);
1002                 goto out;
1003         }
1004
1005         /* Enable CS */
1006         gpmc_cs_enable_mem(cs);
1007         *base = res->start;
1008         gpmc_cs_set_reserved(cs, 1);
1009 out:
1010         spin_unlock(&gpmc_mem_lock);
1011         return r;
1012 }
1013 EXPORT_SYMBOL(gpmc_cs_request);
1014
1015 void gpmc_cs_free(int cs)
1016 {
1017         struct gpmc_cs_data *gpmc;
1018         struct resource *res;
1019
1020         spin_lock(&gpmc_mem_lock);
1021         if (cs >= gpmc_cs_num || cs < 0 || !gpmc_cs_reserved(cs)) {
1022                 WARN(1, "Trying to free non-reserved GPMC CS%d\n", cs);
1023                 spin_unlock(&gpmc_mem_lock);
1024                 return;
1025         }
1026         gpmc = &gpmc_cs[cs];
1027         res = &gpmc->mem;
1028
1029         gpmc_cs_disable_mem(cs);
1030         if (res->flags)
1031                 release_resource(res);
1032         gpmc_cs_set_reserved(cs, 0);
1033         spin_unlock(&gpmc_mem_lock);
1034 }
1035 EXPORT_SYMBOL(gpmc_cs_free);
1036
1037 /**
1038  * gpmc_configure - write request to configure gpmc
1039  * @cmd: command type
1040  * @wval: value to write
1041  * @return status of the operation
1042  */
1043 int gpmc_configure(int cmd, int wval)
1044 {
1045         u32 regval;
1046
1047         switch (cmd) {
1048         case GPMC_CONFIG_WP:
1049                 regval = gpmc_read_reg(GPMC_CONFIG);
1050                 if (wval)
1051                         regval &= ~GPMC_CONFIG_WRITEPROTECT; /* WP is ON */
1052                 else
1053                         regval |= GPMC_CONFIG_WRITEPROTECT;  /* WP is OFF */
1054                 gpmc_write_reg(GPMC_CONFIG, regval);
1055                 break;
1056
1057         default:
1058                 pr_err("%s: command not supported\n", __func__);
1059                 return -EINVAL;
1060         }
1061
1062         return 0;
1063 }
1064 EXPORT_SYMBOL(gpmc_configure);
1065
1066 static bool gpmc_nand_writebuffer_empty(void)
1067 {
1068         if (gpmc_read_reg(GPMC_STATUS) & GPMC_STATUS_EMPTYWRITEBUFFERSTATUS)
1069                 return true;
1070
1071         return false;
1072 }
1073
1074 static struct gpmc_nand_ops nand_ops = {
1075         .nand_writebuffer_empty = gpmc_nand_writebuffer_empty,
1076 };
1077
1078 /**
1079  * gpmc_omap_get_nand_ops - Get the GPMC NAND interface
1080  * @reg: the GPMC NAND register map exclusive for NAND use.
1081  * @cs: GPMC chip select number on which the NAND sits. The
1082  *      register map returned will be specific to this chip select.
1083  *
1084  * Returns NULL on error e.g. invalid cs.
1085  */
1086 struct gpmc_nand_ops *gpmc_omap_get_nand_ops(struct gpmc_nand_regs *reg, int cs)
1087 {
1088         int i;
1089
1090         if (cs >= gpmc_cs_num)
1091                 return NULL;
1092
1093         reg->gpmc_nand_command = gpmc_base + GPMC_CS0_OFFSET +
1094                                 GPMC_CS_NAND_COMMAND + GPMC_CS_SIZE * cs;
1095         reg->gpmc_nand_address = gpmc_base + GPMC_CS0_OFFSET +
1096                                 GPMC_CS_NAND_ADDRESS + GPMC_CS_SIZE * cs;
1097         reg->gpmc_nand_data = gpmc_base + GPMC_CS0_OFFSET +
1098                                 GPMC_CS_NAND_DATA + GPMC_CS_SIZE * cs;
1099         reg->gpmc_prefetch_config1 = gpmc_base + GPMC_PREFETCH_CONFIG1;
1100         reg->gpmc_prefetch_config2 = gpmc_base + GPMC_PREFETCH_CONFIG2;
1101         reg->gpmc_prefetch_control = gpmc_base + GPMC_PREFETCH_CONTROL;
1102         reg->gpmc_prefetch_status = gpmc_base + GPMC_PREFETCH_STATUS;
1103         reg->gpmc_ecc_config = gpmc_base + GPMC_ECC_CONFIG;
1104         reg->gpmc_ecc_control = gpmc_base + GPMC_ECC_CONTROL;
1105         reg->gpmc_ecc_size_config = gpmc_base + GPMC_ECC_SIZE_CONFIG;
1106         reg->gpmc_ecc1_result = gpmc_base + GPMC_ECC1_RESULT;
1107
1108         for (i = 0; i < GPMC_BCH_NUM_REMAINDER; i++) {
1109                 reg->gpmc_bch_result0[i] = gpmc_base + GPMC_ECC_BCH_RESULT_0 +
1110                                            GPMC_BCH_SIZE * i;
1111                 reg->gpmc_bch_result1[i] = gpmc_base + GPMC_ECC_BCH_RESULT_1 +
1112                                            GPMC_BCH_SIZE * i;
1113                 reg->gpmc_bch_result2[i] = gpmc_base + GPMC_ECC_BCH_RESULT_2 +
1114                                            GPMC_BCH_SIZE * i;
1115                 reg->gpmc_bch_result3[i] = gpmc_base + GPMC_ECC_BCH_RESULT_3 +
1116                                            GPMC_BCH_SIZE * i;
1117                 reg->gpmc_bch_result4[i] = gpmc_base + GPMC_ECC_BCH_RESULT_4 +
1118                                            i * GPMC_BCH_SIZE;
1119                 reg->gpmc_bch_result5[i] = gpmc_base + GPMC_ECC_BCH_RESULT_5 +
1120                                            i * GPMC_BCH_SIZE;
1121                 reg->gpmc_bch_result6[i] = gpmc_base + GPMC_ECC_BCH_RESULT_6 +
1122                                            i * GPMC_BCH_SIZE;
1123         }
1124
1125         return &nand_ops;
1126 }
1127 EXPORT_SYMBOL_GPL(gpmc_omap_get_nand_ops);
1128
1129 static void gpmc_omap_onenand_calc_sync_timings(struct gpmc_timings *t,
1130                                                 struct gpmc_settings *s,
1131                                                 int freq, int latency)
1132 {
1133         struct gpmc_device_timings dev_t;
1134         const int t_cer  = 15;
1135         const int t_avdp = 12;
1136         const int t_cez  = 20; /* max of t_cez, t_oez */
1137         const int t_wpl  = 40;
1138         const int t_wph  = 30;
1139         int min_gpmc_clk_period, t_ces, t_avds, t_avdh, t_ach, t_aavdh, t_rdyo;
1140
1141         switch (freq) {
1142         case 104:
1143                 min_gpmc_clk_period = 9600; /* 104 MHz */
1144                 t_ces   = 3;
1145                 t_avds  = 4;
1146                 t_avdh  = 2;
1147                 t_ach   = 3;
1148                 t_aavdh = 6;
1149                 t_rdyo  = 6;
1150                 break;
1151         case 83:
1152                 min_gpmc_clk_period = 12000; /* 83 MHz */
1153                 t_ces   = 5;
1154                 t_avds  = 4;
1155                 t_avdh  = 2;
1156                 t_ach   = 6;
1157                 t_aavdh = 6;
1158                 t_rdyo  = 9;
1159                 break;
1160         case 66:
1161                 min_gpmc_clk_period = 15000; /* 66 MHz */
1162                 t_ces   = 6;
1163                 t_avds  = 5;
1164                 t_avdh  = 2;
1165                 t_ach   = 6;
1166                 t_aavdh = 6;
1167                 t_rdyo  = 11;
1168                 break;
1169         default:
1170                 min_gpmc_clk_period = 18500; /* 54 MHz */
1171                 t_ces   = 7;
1172                 t_avds  = 7;
1173                 t_avdh  = 7;
1174                 t_ach   = 9;
1175                 t_aavdh = 7;
1176                 t_rdyo  = 15;
1177                 break;
1178         }
1179
1180         /* Set synchronous read timings */
1181         memset(&dev_t, 0, sizeof(dev_t));
1182
1183         if (!s->sync_write) {
1184                 dev_t.t_avdp_w = max(t_avdp, t_cer) * 1000;
1185                 dev_t.t_wpl = t_wpl * 1000;
1186                 dev_t.t_wph = t_wph * 1000;
1187                 dev_t.t_aavdh = t_aavdh * 1000;
1188         }
1189         dev_t.ce_xdelay = true;
1190         dev_t.avd_xdelay = true;
1191         dev_t.oe_xdelay = true;
1192         dev_t.we_xdelay = true;
1193         dev_t.clk = min_gpmc_clk_period;
1194         dev_t.t_bacc = dev_t.clk;
1195         dev_t.t_ces = t_ces * 1000;
1196         dev_t.t_avds = t_avds * 1000;
1197         dev_t.t_avdh = t_avdh * 1000;
1198         dev_t.t_ach = t_ach * 1000;
1199         dev_t.cyc_iaa = (latency + 1);
1200         dev_t.t_cez_r = t_cez * 1000;
1201         dev_t.t_cez_w = dev_t.t_cez_r;
1202         dev_t.cyc_aavdh_oe = 1;
1203         dev_t.t_rdyo = t_rdyo * 1000 + min_gpmc_clk_period;
1204
1205         gpmc_calc_timings(t, s, &dev_t);
1206 }
1207
1208 int gpmc_omap_onenand_set_timings(struct device *dev, int cs, int freq,
1209                                   int latency,
1210                                   struct gpmc_onenand_info *info)
1211 {
1212         int ret;
1213         struct gpmc_timings gpmc_t;
1214         struct gpmc_settings gpmc_s;
1215
1216         gpmc_read_settings_dt(dev->of_node, &gpmc_s);
1217
1218         info->sync_read = gpmc_s.sync_read;
1219         info->sync_write = gpmc_s.sync_write;
1220         info->burst_len = gpmc_s.burst_len;
1221
1222         if (!gpmc_s.sync_read && !gpmc_s.sync_write)
1223                 return 0;
1224
1225         gpmc_omap_onenand_calc_sync_timings(&gpmc_t, &gpmc_s, freq, latency);
1226
1227         ret = gpmc_cs_program_settings(cs, &gpmc_s);
1228         if (ret < 0)
1229                 return ret;
1230
1231         return gpmc_cs_set_timings(cs, &gpmc_t, &gpmc_s);
1232 }
1233 EXPORT_SYMBOL_GPL(gpmc_omap_onenand_set_timings);
1234
1235 int gpmc_get_client_irq(unsigned int irq_config)
1236 {
1237         if (!gpmc_irq_domain) {
1238                 pr_warn("%s called before GPMC IRQ domain available\n",
1239                         __func__);
1240                 return 0;
1241         }
1242
1243         /* we restrict this to NAND IRQs only */
1244         if (irq_config >= GPMC_NR_NAND_IRQS)
1245                 return 0;
1246
1247         return irq_create_mapping(gpmc_irq_domain, irq_config);
1248 }
1249
1250 static int gpmc_irq_endis(unsigned long hwirq, bool endis)
1251 {
1252         u32 regval;
1253
1254         /* bits GPMC_NR_NAND_IRQS to 8 are reserved */
1255         if (hwirq >= GPMC_NR_NAND_IRQS)
1256                 hwirq += 8 - GPMC_NR_NAND_IRQS;
1257
1258         regval = gpmc_read_reg(GPMC_IRQENABLE);
1259         if (endis)
1260                 regval |= BIT(hwirq);
1261         else
1262                 regval &= ~BIT(hwirq);
1263         gpmc_write_reg(GPMC_IRQENABLE, regval);
1264
1265         return 0;
1266 }
1267
1268 static void gpmc_irq_disable(struct irq_data *p)
1269 {
1270         gpmc_irq_endis(p->hwirq, false);
1271 }
1272
1273 static void gpmc_irq_enable(struct irq_data *p)
1274 {
1275         gpmc_irq_endis(p->hwirq, true);
1276 }
1277
1278 static void gpmc_irq_mask(struct irq_data *d)
1279 {
1280         gpmc_irq_endis(d->hwirq, false);
1281 }
1282
1283 static void gpmc_irq_unmask(struct irq_data *d)
1284 {
1285         gpmc_irq_endis(d->hwirq, true);
1286 }
1287
1288 static void gpmc_irq_edge_config(unsigned long hwirq, bool rising_edge)
1289 {
1290         u32 regval;
1291
1292         /* NAND IRQs polarity is not configurable */
1293         if (hwirq < GPMC_NR_NAND_IRQS)
1294                 return;
1295
1296         /* WAITPIN starts at BIT 8 */
1297         hwirq += 8 - GPMC_NR_NAND_IRQS;
1298
1299         regval = gpmc_read_reg(GPMC_CONFIG);
1300         if (rising_edge)
1301                 regval &= ~BIT(hwirq);
1302         else
1303                 regval |= BIT(hwirq);
1304
1305         gpmc_write_reg(GPMC_CONFIG, regval);
1306 }
1307
1308 static void gpmc_irq_ack(struct irq_data *d)
1309 {
1310         unsigned int hwirq = d->hwirq;
1311
1312         /* skip reserved bits */
1313         if (hwirq >= GPMC_NR_NAND_IRQS)
1314                 hwirq += 8 - GPMC_NR_NAND_IRQS;
1315
1316         /* Setting bit to 1 clears (or Acks) the interrupt */
1317         gpmc_write_reg(GPMC_IRQSTATUS, BIT(hwirq));
1318 }
1319
1320 static int gpmc_irq_set_type(struct irq_data *d, unsigned int trigger)
1321 {
1322         /* can't set type for NAND IRQs */
1323         if (d->hwirq < GPMC_NR_NAND_IRQS)
1324                 return -EINVAL;
1325
1326         /* We can support either rising or falling edge at a time */
1327         if (trigger == IRQ_TYPE_EDGE_FALLING)
1328                 gpmc_irq_edge_config(d->hwirq, false);
1329         else if (trigger == IRQ_TYPE_EDGE_RISING)
1330                 gpmc_irq_edge_config(d->hwirq, true);
1331         else
1332                 return -EINVAL;
1333
1334         return 0;
1335 }
1336
1337 static int gpmc_irq_map(struct irq_domain *d, unsigned int virq,
1338                         irq_hw_number_t hw)
1339 {
1340         struct gpmc_device *gpmc = d->host_data;
1341
1342         irq_set_chip_data(virq, gpmc);
1343         if (hw < GPMC_NR_NAND_IRQS) {
1344                 irq_modify_status(virq, IRQ_NOREQUEST, IRQ_NOAUTOEN);
1345                 irq_set_chip_and_handler(virq, &gpmc->irq_chip,
1346                                          handle_simple_irq);
1347         } else {
1348                 irq_set_chip_and_handler(virq, &gpmc->irq_chip,
1349                                          handle_edge_irq);
1350         }
1351
1352         return 0;
1353 }
1354
1355 static const struct irq_domain_ops gpmc_irq_domain_ops = {
1356         .map    = gpmc_irq_map,
1357         .xlate  = irq_domain_xlate_twocell,
1358 };
1359
1360 static irqreturn_t gpmc_handle_irq(int irq, void *data)
1361 {
1362         int hwirq, virq;
1363         u32 regval, regvalx;
1364         struct gpmc_device *gpmc = data;
1365
1366         regval = gpmc_read_reg(GPMC_IRQSTATUS);
1367         regvalx = regval;
1368
1369         if (!regval)
1370                 return IRQ_NONE;
1371
1372         for (hwirq = 0; hwirq < gpmc->nirqs; hwirq++) {
1373                 /* skip reserved status bits */
1374                 if (hwirq == GPMC_NR_NAND_IRQS)
1375                         regvalx >>= 8 - GPMC_NR_NAND_IRQS;
1376
1377                 if (regvalx & BIT(hwirq)) {
1378                         virq = irq_find_mapping(gpmc_irq_domain, hwirq);
1379                         if (!virq) {
1380                                 dev_warn(gpmc->dev,
1381                                          "spurious irq detected hwirq %d, virq %d\n",
1382                                          hwirq, virq);
1383                         }
1384
1385                         generic_handle_irq(virq);
1386                 }
1387         }
1388
1389         gpmc_write_reg(GPMC_IRQSTATUS, regval);
1390
1391         return IRQ_HANDLED;
1392 }
1393
1394 static int gpmc_setup_irq(struct gpmc_device *gpmc)
1395 {
1396         u32 regval;
1397         int rc;
1398
1399         /* Disable interrupts */
1400         gpmc_write_reg(GPMC_IRQENABLE, 0);
1401
1402         /* clear interrupts */
1403         regval = gpmc_read_reg(GPMC_IRQSTATUS);
1404         gpmc_write_reg(GPMC_IRQSTATUS, regval);
1405
1406         gpmc->irq_chip.name = "gpmc";
1407         gpmc->irq_chip.irq_enable = gpmc_irq_enable;
1408         gpmc->irq_chip.irq_disable = gpmc_irq_disable;
1409         gpmc->irq_chip.irq_ack = gpmc_irq_ack;
1410         gpmc->irq_chip.irq_mask = gpmc_irq_mask;
1411         gpmc->irq_chip.irq_unmask = gpmc_irq_unmask;
1412         gpmc->irq_chip.irq_set_type = gpmc_irq_set_type;
1413
1414         gpmc_irq_domain = irq_domain_add_linear(gpmc->dev->of_node,
1415                                                 gpmc->nirqs,
1416                                                 &gpmc_irq_domain_ops,
1417                                                 gpmc);
1418         if (!gpmc_irq_domain) {
1419                 dev_err(gpmc->dev, "IRQ domain add failed\n");
1420                 return -ENODEV;
1421         }
1422
1423         rc = request_irq(gpmc->irq, gpmc_handle_irq, 0, "gpmc", gpmc);
1424         if (rc) {
1425                 dev_err(gpmc->dev, "failed to request irq %d: %d\n",
1426                         gpmc->irq, rc);
1427                 irq_domain_remove(gpmc_irq_domain);
1428                 gpmc_irq_domain = NULL;
1429         }
1430
1431         return rc;
1432 }
1433
1434 static int gpmc_free_irq(struct gpmc_device *gpmc)
1435 {
1436         int hwirq;
1437
1438         free_irq(gpmc->irq, gpmc);
1439
1440         for (hwirq = 0; hwirq < gpmc->nirqs; hwirq++)
1441                 irq_dispose_mapping(irq_find_mapping(gpmc_irq_domain, hwirq));
1442
1443         irq_domain_remove(gpmc_irq_domain);
1444         gpmc_irq_domain = NULL;
1445
1446         return 0;
1447 }
1448
1449 static void gpmc_mem_exit(void)
1450 {
1451         int cs;
1452
1453         for (cs = 0; cs < gpmc_cs_num; cs++) {
1454                 if (!gpmc_cs_mem_enabled(cs))
1455                         continue;
1456                 gpmc_cs_delete_mem(cs);
1457         }
1458 }
1459
1460 static void gpmc_mem_init(struct gpmc_device *gpmc)
1461 {
1462         int cs;
1463
1464         if (!gpmc->data) {
1465                 /* All legacy devices have same data IO window */
1466                 gpmc_mem_root.start = GPMC_MEM_START;
1467                 gpmc_mem_root.end = GPMC_MEM_END;
1468         } else {
1469                 gpmc_mem_root.start = gpmc->data->start;
1470                 gpmc_mem_root.end = gpmc->data->end;
1471         }
1472
1473         /* Reserve all regions that has been set up by bootloader */
1474         for (cs = 0; cs < gpmc_cs_num; cs++) {
1475                 u32 base, size;
1476
1477                 if (!gpmc_cs_mem_enabled(cs))
1478                         continue;
1479                 gpmc_cs_get_memconf(cs, &base, &size);
1480                 if (gpmc_cs_insert_mem(cs, base, size)) {
1481                         pr_warn("%s: disabling cs %d mapped at 0x%x-0x%x\n",
1482                                 __func__, cs, base, base + size);
1483                         gpmc_cs_disable_mem(cs);
1484                 }
1485         }
1486 }
1487
1488 static u32 gpmc_round_ps_to_sync_clk(u32 time_ps, u32 sync_clk)
1489 {
1490         u32 temp;
1491         int div;
1492
1493         div = gpmc_calc_divider(sync_clk);
1494         temp = gpmc_ps_to_ticks(time_ps);
1495         temp = (temp + div - 1) / div;
1496         return gpmc_ticks_to_ps(temp * div);
1497 }
1498
1499 /* XXX: can the cycles be avoided ? */
1500 static int gpmc_calc_sync_read_timings(struct gpmc_timings *gpmc_t,
1501                                        struct gpmc_device_timings *dev_t,
1502                                        bool mux)
1503 {
1504         u32 temp;
1505
1506         /* adv_rd_off */
1507         temp = dev_t->t_avdp_r;
1508         /* XXX: mux check required ? */
1509         if (mux) {
1510                 /* XXX: t_avdp not to be required for sync, only added for tusb
1511                  * this indirectly necessitates requirement of t_avdp_r and
1512                  * t_avdp_w instead of having a single t_avdp
1513                  */
1514                 temp = max_t(u32, temp, gpmc_t->clk_activation + dev_t->t_avdh);
1515                 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
1516         }
1517         gpmc_t->adv_rd_off = gpmc_round_ps_to_ticks(temp);
1518
1519         /* oe_on */
1520         temp = dev_t->t_oeasu; /* XXX: remove this ? */
1521         if (mux) {
1522                 temp = max_t(u32, temp, gpmc_t->clk_activation + dev_t->t_ach);
1523                 temp = max_t(u32, temp, gpmc_t->adv_rd_off +
1524                                 gpmc_ticks_to_ps(dev_t->cyc_aavdh_oe));
1525         }
1526         gpmc_t->oe_on = gpmc_round_ps_to_ticks(temp);
1527
1528         /* access */
1529         /* XXX: any scope for improvement ?, by combining oe_on
1530          * and clk_activation, need to check whether
1531          * access = clk_activation + round to sync clk ?
1532          */
1533         temp = max_t(u32, dev_t->t_iaa, dev_t->cyc_iaa * gpmc_t->sync_clk);
1534         temp += gpmc_t->clk_activation;
1535         if (dev_t->cyc_oe)
1536                 temp = max_t(u32, temp, gpmc_t->oe_on +
1537                                 gpmc_ticks_to_ps(dev_t->cyc_oe));
1538         gpmc_t->access = gpmc_round_ps_to_ticks(temp);
1539
1540         gpmc_t->oe_off = gpmc_t->access + gpmc_ticks_to_ps(1);
1541         gpmc_t->cs_rd_off = gpmc_t->oe_off;
1542
1543         /* rd_cycle */
1544         temp = max_t(u32, dev_t->t_cez_r, dev_t->t_oez);
1545         temp = gpmc_round_ps_to_sync_clk(temp, gpmc_t->sync_clk) +
1546                                                         gpmc_t->access;
1547         /* XXX: barter t_ce_rdyz with t_cez_r ? */
1548         if (dev_t->t_ce_rdyz)
1549                 temp = max_t(u32, temp, gpmc_t->cs_rd_off + dev_t->t_ce_rdyz);
1550         gpmc_t->rd_cycle = gpmc_round_ps_to_ticks(temp);
1551
1552         return 0;
1553 }
1554
1555 static int gpmc_calc_sync_write_timings(struct gpmc_timings *gpmc_t,
1556                                         struct gpmc_device_timings *dev_t,
1557                                         bool mux)
1558 {
1559         u32 temp;
1560
1561         /* adv_wr_off */
1562         temp = dev_t->t_avdp_w;
1563         if (mux) {
1564                 temp = max_t(u32, temp,
1565                         gpmc_t->clk_activation + dev_t->t_avdh);
1566                 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
1567         }
1568         gpmc_t->adv_wr_off = gpmc_round_ps_to_ticks(temp);
1569
1570         /* wr_data_mux_bus */
1571         temp = max_t(u32, dev_t->t_weasu,
1572                         gpmc_t->clk_activation + dev_t->t_rdyo);
1573         /* XXX: shouldn't mux be kept as a whole for wr_data_mux_bus ?,
1574          * and in that case remember to handle we_on properly
1575          */
1576         if (mux) {
1577                 temp = max_t(u32, temp,
1578                         gpmc_t->adv_wr_off + dev_t->t_aavdh);
1579                 temp = max_t(u32, temp, gpmc_t->adv_wr_off +
1580                                 gpmc_ticks_to_ps(dev_t->cyc_aavdh_we));
1581         }
1582         gpmc_t->wr_data_mux_bus = gpmc_round_ps_to_ticks(temp);
1583
1584         /* we_on */
1585         if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
1586                 gpmc_t->we_on = gpmc_round_ps_to_ticks(dev_t->t_weasu);
1587         else
1588                 gpmc_t->we_on = gpmc_t->wr_data_mux_bus;
1589
1590         /* wr_access */
1591         /* XXX: gpmc_capability check reqd ? , even if not, will not harm */
1592         gpmc_t->wr_access = gpmc_t->access;
1593
1594         /* we_off */
1595         temp = gpmc_t->we_on + dev_t->t_wpl;
1596         temp = max_t(u32, temp,
1597                         gpmc_t->wr_access + gpmc_ticks_to_ps(1));
1598         temp = max_t(u32, temp,
1599                 gpmc_t->we_on + gpmc_ticks_to_ps(dev_t->cyc_wpl));
1600         gpmc_t->we_off = gpmc_round_ps_to_ticks(temp);
1601
1602         gpmc_t->cs_wr_off = gpmc_round_ps_to_ticks(gpmc_t->we_off +
1603                                                         dev_t->t_wph);
1604
1605         /* wr_cycle */
1606         temp = gpmc_round_ps_to_sync_clk(dev_t->t_cez_w, gpmc_t->sync_clk);
1607         temp += gpmc_t->wr_access;
1608         /* XXX: barter t_ce_rdyz with t_cez_w ? */
1609         if (dev_t->t_ce_rdyz)
1610                 temp = max_t(u32, temp,
1611                                  gpmc_t->cs_wr_off + dev_t->t_ce_rdyz);
1612         gpmc_t->wr_cycle = gpmc_round_ps_to_ticks(temp);
1613
1614         return 0;
1615 }
1616
1617 static int gpmc_calc_async_read_timings(struct gpmc_timings *gpmc_t,
1618                                         struct gpmc_device_timings *dev_t,
1619                                         bool mux)
1620 {
1621         u32 temp;
1622
1623         /* adv_rd_off */
1624         temp = dev_t->t_avdp_r;
1625         if (mux)
1626                 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
1627         gpmc_t->adv_rd_off = gpmc_round_ps_to_ticks(temp);
1628
1629         /* oe_on */
1630         temp = dev_t->t_oeasu;
1631         if (mux)
1632                 temp = max_t(u32, temp, gpmc_t->adv_rd_off + dev_t->t_aavdh);
1633         gpmc_t->oe_on = gpmc_round_ps_to_ticks(temp);
1634
1635         /* access */
1636         temp = max_t(u32, dev_t->t_iaa, /* XXX: remove t_iaa in async ? */
1637                      gpmc_t->oe_on + dev_t->t_oe);
1638         temp = max_t(u32, temp, gpmc_t->cs_on + dev_t->t_ce);
1639         temp = max_t(u32, temp, gpmc_t->adv_on + dev_t->t_aa);
1640         gpmc_t->access = gpmc_round_ps_to_ticks(temp);
1641
1642         gpmc_t->oe_off = gpmc_t->access + gpmc_ticks_to_ps(1);
1643         gpmc_t->cs_rd_off = gpmc_t->oe_off;
1644
1645         /* rd_cycle */
1646         temp = max_t(u32, dev_t->t_rd_cycle,
1647                         gpmc_t->cs_rd_off + dev_t->t_cez_r);
1648         temp = max_t(u32, temp, gpmc_t->oe_off + dev_t->t_oez);
1649         gpmc_t->rd_cycle = gpmc_round_ps_to_ticks(temp);
1650
1651         return 0;
1652 }
1653
1654 static int gpmc_calc_async_write_timings(struct gpmc_timings *gpmc_t,
1655                                          struct gpmc_device_timings *dev_t,
1656                                          bool mux)
1657 {
1658         u32 temp;
1659
1660         /* adv_wr_off */
1661         temp = dev_t->t_avdp_w;
1662         if (mux)
1663                 temp = max_t(u32, gpmc_t->adv_on + gpmc_ticks_to_ps(1), temp);
1664         gpmc_t->adv_wr_off = gpmc_round_ps_to_ticks(temp);
1665
1666         /* wr_data_mux_bus */
1667         temp = dev_t->t_weasu;
1668         if (mux) {
1669                 temp = max_t(u32, temp, gpmc_t->adv_wr_off + dev_t->t_aavdh);
1670                 temp = max_t(u32, temp, gpmc_t->adv_wr_off +
1671                                 gpmc_ticks_to_ps(dev_t->cyc_aavdh_we));
1672         }
1673         gpmc_t->wr_data_mux_bus = gpmc_round_ps_to_ticks(temp);
1674
1675         /* we_on */
1676         if (gpmc_capability & GPMC_HAS_WR_DATA_MUX_BUS)
1677                 gpmc_t->we_on = gpmc_round_ps_to_ticks(dev_t->t_weasu);
1678         else
1679                 gpmc_t->we_on = gpmc_t->wr_data_mux_bus;
1680
1681         /* we_off */
1682         temp = gpmc_t->we_on + dev_t->t_wpl;
1683         gpmc_t->we_off = gpmc_round_ps_to_ticks(temp);
1684
1685         gpmc_t->cs_wr_off = gpmc_round_ps_to_ticks(gpmc_t->we_off +
1686                                                         dev_t->t_wph);
1687
1688         /* wr_cycle */
1689         temp = max_t(u32, dev_t->t_wr_cycle,
1690                                 gpmc_t->cs_wr_off + dev_t->t_cez_w);
1691         gpmc_t->wr_cycle = gpmc_round_ps_to_ticks(temp);
1692
1693         return 0;
1694 }
1695
1696 static int gpmc_calc_sync_common_timings(struct gpmc_timings *gpmc_t,
1697                         struct gpmc_device_timings *dev_t)
1698 {
1699         u32 temp;
1700
1701         gpmc_t->sync_clk = gpmc_calc_divider(dev_t->clk) *
1702                                                 gpmc_get_fclk_period();
1703
1704         gpmc_t->page_burst_access = gpmc_round_ps_to_sync_clk(
1705                                         dev_t->t_bacc,
1706                                         gpmc_t->sync_clk);
1707
1708         temp = max_t(u32, dev_t->t_ces, dev_t->t_avds);
1709         gpmc_t->clk_activation = gpmc_round_ps_to_ticks(temp);
1710
1711         if (gpmc_calc_divider(gpmc_t->sync_clk) != 1)
1712                 return 0;
1713
1714         if (dev_t->ce_xdelay)
1715                 gpmc_t->bool_timings.cs_extra_delay = true;
1716         if (dev_t->avd_xdelay)
1717                 gpmc_t->bool_timings.adv_extra_delay = true;
1718         if (dev_t->oe_xdelay)
1719                 gpmc_t->bool_timings.oe_extra_delay = true;
1720         if (dev_t->we_xdelay)
1721                 gpmc_t->bool_timings.we_extra_delay = true;
1722
1723         return 0;
1724 }
1725
1726 static int gpmc_calc_common_timings(struct gpmc_timings *gpmc_t,
1727                                     struct gpmc_device_timings *dev_t,
1728                                     bool sync)
1729 {
1730         u32 temp;
1731
1732         /* cs_on */
1733         gpmc_t->cs_on = gpmc_round_ps_to_ticks(dev_t->t_ceasu);
1734
1735         /* adv_on */
1736         temp = dev_t->t_avdasu;
1737         if (dev_t->t_ce_avd)
1738                 temp = max_t(u32, temp,
1739                                 gpmc_t->cs_on + dev_t->t_ce_avd);
1740         gpmc_t->adv_on = gpmc_round_ps_to_ticks(temp);
1741
1742         if (sync)
1743                 gpmc_calc_sync_common_timings(gpmc_t, dev_t);
1744
1745         return 0;
1746 }
1747
1748 /*
1749  * TODO: remove this function once all peripherals are confirmed to
1750  * work with generic timing. Simultaneously gpmc_cs_set_timings()
1751  * has to be modified to handle timings in ps instead of ns
1752  */
1753 static void gpmc_convert_ps_to_ns(struct gpmc_timings *t)
1754 {
1755         t->cs_on /= 1000;
1756         t->cs_rd_off /= 1000;
1757         t->cs_wr_off /= 1000;
1758         t->adv_on /= 1000;
1759         t->adv_rd_off /= 1000;
1760         t->adv_wr_off /= 1000;
1761         t->we_on /= 1000;
1762         t->we_off /= 1000;
1763         t->oe_on /= 1000;
1764         t->oe_off /= 1000;
1765         t->page_burst_access /= 1000;
1766         t->access /= 1000;
1767         t->rd_cycle /= 1000;
1768         t->wr_cycle /= 1000;
1769         t->bus_turnaround /= 1000;
1770         t->cycle2cycle_delay /= 1000;
1771         t->wait_monitoring /= 1000;
1772         t->clk_activation /= 1000;
1773         t->wr_access /= 1000;
1774         t->wr_data_mux_bus /= 1000;
1775 }
1776
1777 int gpmc_calc_timings(struct gpmc_timings *gpmc_t,
1778                       struct gpmc_settings *gpmc_s,
1779                       struct gpmc_device_timings *dev_t)
1780 {
1781         bool mux = false, sync = false;
1782
1783         if (gpmc_s) {
1784                 mux = gpmc_s->mux_add_data ? true : false;
1785                 sync = (gpmc_s->sync_read || gpmc_s->sync_write);
1786         }
1787
1788         memset(gpmc_t, 0, sizeof(*gpmc_t));
1789
1790         gpmc_calc_common_timings(gpmc_t, dev_t, sync);
1791
1792         if (gpmc_s && gpmc_s->sync_read)
1793                 gpmc_calc_sync_read_timings(gpmc_t, dev_t, mux);
1794         else
1795                 gpmc_calc_async_read_timings(gpmc_t, dev_t, mux);
1796
1797         if (gpmc_s && gpmc_s->sync_write)
1798                 gpmc_calc_sync_write_timings(gpmc_t, dev_t, mux);
1799         else
1800                 gpmc_calc_async_write_timings(gpmc_t, dev_t, mux);
1801
1802         /* TODO: remove, see function definition */
1803         gpmc_convert_ps_to_ns(gpmc_t);
1804
1805         return 0;
1806 }
1807
1808 /**
1809  * gpmc_cs_program_settings - programs non-timing related settings
1810  * @cs:         GPMC chip-select to program
1811  * @p:          pointer to GPMC settings structure
1812  *
1813  * Programs non-timing related settings for a GPMC chip-select, such as
1814  * bus-width, burst configuration, etc. Function should be called once
1815  * for each chip-select that is being used and must be called before
1816  * calling gpmc_cs_set_timings() as timing parameters in the CONFIG1
1817  * register will be initialised to zero by this function. Returns 0 on
1818  * success and appropriate negative error code on failure.
1819  */
1820 int gpmc_cs_program_settings(int cs, struct gpmc_settings *p)
1821 {
1822         u32 config1;
1823
1824         if ((!p->device_width) || (p->device_width > GPMC_DEVWIDTH_16BIT)) {
1825                 pr_err("%s: invalid width %d!", __func__, p->device_width);
1826                 return -EINVAL;
1827         }
1828
1829         /* Address-data multiplexing not supported for NAND devices */
1830         if (p->device_nand && p->mux_add_data) {
1831                 pr_err("%s: invalid configuration!\n", __func__);
1832                 return -EINVAL;
1833         }
1834
1835         if ((p->mux_add_data > GPMC_MUX_AD) ||
1836             ((p->mux_add_data == GPMC_MUX_AAD) &&
1837              !(gpmc_capability & GPMC_HAS_MUX_AAD))) {
1838                 pr_err("%s: invalid multiplex configuration!\n", __func__);
1839                 return -EINVAL;
1840         }
1841
1842         /* Page/burst mode supports lengths of 4, 8 and 16 bytes */
1843         if (p->burst_read || p->burst_write) {
1844                 switch (p->burst_len) {
1845                 case GPMC_BURST_4:
1846                 case GPMC_BURST_8:
1847                 case GPMC_BURST_16:
1848                         break;
1849                 default:
1850                         pr_err("%s: invalid page/burst-length (%d)\n",
1851                                __func__, p->burst_len);
1852                         return -EINVAL;
1853                 }
1854         }
1855
1856         if (p->wait_pin > gpmc_nr_waitpins) {
1857                 pr_err("%s: invalid wait-pin (%d)\n", __func__, p->wait_pin);
1858                 return -EINVAL;
1859         }
1860
1861         config1 = GPMC_CONFIG1_DEVICESIZE((p->device_width - 1));
1862
1863         if (p->sync_read)
1864                 config1 |= GPMC_CONFIG1_READTYPE_SYNC;
1865         if (p->sync_write)
1866                 config1 |= GPMC_CONFIG1_WRITETYPE_SYNC;
1867         if (p->wait_on_read)
1868                 config1 |= GPMC_CONFIG1_WAIT_READ_MON;
1869         if (p->wait_on_write)
1870                 config1 |= GPMC_CONFIG1_WAIT_WRITE_MON;
1871         if (p->wait_on_read || p->wait_on_write)
1872                 config1 |= GPMC_CONFIG1_WAIT_PIN_SEL(p->wait_pin);
1873         if (p->device_nand)
1874                 config1 |= GPMC_CONFIG1_DEVICETYPE(GPMC_DEVICETYPE_NAND);
1875         if (p->mux_add_data)
1876                 config1 |= GPMC_CONFIG1_MUXTYPE(p->mux_add_data);
1877         if (p->burst_read)
1878                 config1 |= GPMC_CONFIG1_READMULTIPLE_SUPP;
1879         if (p->burst_write)
1880                 config1 |= GPMC_CONFIG1_WRITEMULTIPLE_SUPP;
1881         if (p->burst_read || p->burst_write) {
1882                 config1 |= GPMC_CONFIG1_PAGE_LEN(p->burst_len >> 3);
1883                 config1 |= p->burst_wrap ? GPMC_CONFIG1_WRAPBURST_SUPP : 0;
1884         }
1885
1886         gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, config1);
1887
1888         return 0;
1889 }
1890
1891 #ifdef CONFIG_OF
1892 static const struct of_device_id gpmc_dt_ids[] = {
1893         { .compatible = "ti,omap2420-gpmc" },
1894         { .compatible = "ti,omap2430-gpmc" },
1895         { .compatible = "ti,omap3430-gpmc" },   /* omap3430 & omap3630 */
1896         { .compatible = "ti,omap4430-gpmc" },   /* omap4430 & omap4460 & omap543x */
1897         { .compatible = "ti,am3352-gpmc" },     /* am335x devices */
1898         { .compatible = "ti,am64-gpmc" },
1899         { }
1900 };
1901
1902 static void gpmc_cs_set_name(int cs, const char *name)
1903 {
1904         struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
1905
1906         gpmc->name = name;
1907 }
1908
1909 static const char *gpmc_cs_get_name(int cs)
1910 {
1911         struct gpmc_cs_data *gpmc = &gpmc_cs[cs];
1912
1913         return gpmc->name;
1914 }
1915
1916 /**
1917  * gpmc_cs_remap - remaps a chip-select physical base address
1918  * @cs:         chip-select to remap
1919  * @base:       physical base address to re-map chip-select to
1920  *
1921  * Re-maps a chip-select to a new physical base address specified by
1922  * "base". Returns 0 on success and appropriate negative error code
1923  * on failure.
1924  */
1925 static int gpmc_cs_remap(int cs, u32 base)
1926 {
1927         int ret;
1928         u32 old_base, size;
1929
1930         if (cs >= gpmc_cs_num) {
1931                 pr_err("%s: requested chip-select is disabled\n", __func__);
1932                 return -ENODEV;
1933         }
1934
1935         /*
1936          * Make sure we ignore any device offsets from the GPMC partition
1937          * allocated for the chip select and that the new base confirms
1938          * to the GPMC 16MB minimum granularity.
1939          */
1940         base &= ~(SZ_16M - 1);
1941
1942         gpmc_cs_get_memconf(cs, &old_base, &size);
1943         if (base == old_base)
1944                 return 0;
1945
1946         ret = gpmc_cs_delete_mem(cs);
1947         if (ret < 0)
1948                 return ret;
1949
1950         ret = gpmc_cs_insert_mem(cs, base, size);
1951         if (ret < 0)
1952                 return ret;
1953
1954         ret = gpmc_cs_set_memconf(cs, base, size);
1955
1956         return ret;
1957 }
1958
1959 /**
1960  * gpmc_read_settings_dt - read gpmc settings from device-tree
1961  * @np:         pointer to device-tree node for a gpmc child device
1962  * @p:          pointer to gpmc settings structure
1963  *
1964  * Reads the GPMC settings for a GPMC child device from device-tree and
1965  * stores them in the GPMC settings structure passed. The GPMC settings
1966  * structure is initialised to zero by this function and so any
1967  * previously stored settings will be cleared.
1968  */
1969 void gpmc_read_settings_dt(struct device_node *np, struct gpmc_settings *p)
1970 {
1971         memset(p, 0, sizeof(struct gpmc_settings));
1972
1973         p->sync_read = of_property_read_bool(np, "gpmc,sync-read");
1974         p->sync_write = of_property_read_bool(np, "gpmc,sync-write");
1975         of_property_read_u32(np, "gpmc,device-width", &p->device_width);
1976         of_property_read_u32(np, "gpmc,mux-add-data", &p->mux_add_data);
1977
1978         if (!of_property_read_u32(np, "gpmc,burst-length", &p->burst_len)) {
1979                 p->burst_wrap = of_property_read_bool(np, "gpmc,burst-wrap");
1980                 p->burst_read = of_property_read_bool(np, "gpmc,burst-read");
1981                 p->burst_write = of_property_read_bool(np, "gpmc,burst-write");
1982                 if (!p->burst_read && !p->burst_write)
1983                         pr_warn("%s: page/burst-length set but not used!\n",
1984                                 __func__);
1985         }
1986
1987         if (!of_property_read_u32(np, "gpmc,wait-pin", &p->wait_pin)) {
1988                 p->wait_on_read = of_property_read_bool(np,
1989                                                         "gpmc,wait-on-read");
1990                 p->wait_on_write = of_property_read_bool(np,
1991                                                          "gpmc,wait-on-write");
1992                 if (!p->wait_on_read && !p->wait_on_write)
1993                         pr_debug("%s: rd/wr wait monitoring not enabled!\n",
1994                                  __func__);
1995         }
1996 }
1997
1998 static void __maybe_unused gpmc_read_timings_dt(struct device_node *np,
1999                                                 struct gpmc_timings *gpmc_t)
2000 {
2001         struct gpmc_bool_timings *p;
2002
2003         if (!np || !gpmc_t)
2004                 return;
2005
2006         memset(gpmc_t, 0, sizeof(*gpmc_t));
2007
2008         /* minimum clock period for syncronous mode */
2009         of_property_read_u32(np, "gpmc,sync-clk-ps", &gpmc_t->sync_clk);
2010
2011         /* chip select timtings */
2012         of_property_read_u32(np, "gpmc,cs-on-ns", &gpmc_t->cs_on);
2013         of_property_read_u32(np, "gpmc,cs-rd-off-ns", &gpmc_t->cs_rd_off);
2014         of_property_read_u32(np, "gpmc,cs-wr-off-ns", &gpmc_t->cs_wr_off);
2015
2016         /* ADV signal timings */
2017         of_property_read_u32(np, "gpmc,adv-on-ns", &gpmc_t->adv_on);
2018         of_property_read_u32(np, "gpmc,adv-rd-off-ns", &gpmc_t->adv_rd_off);
2019         of_property_read_u32(np, "gpmc,adv-wr-off-ns", &gpmc_t->adv_wr_off);
2020         of_property_read_u32(np, "gpmc,adv-aad-mux-on-ns",
2021                              &gpmc_t->adv_aad_mux_on);
2022         of_property_read_u32(np, "gpmc,adv-aad-mux-rd-off-ns",
2023                              &gpmc_t->adv_aad_mux_rd_off);
2024         of_property_read_u32(np, "gpmc,adv-aad-mux-wr-off-ns",
2025                              &gpmc_t->adv_aad_mux_wr_off);
2026
2027         /* WE signal timings */
2028         of_property_read_u32(np, "gpmc,we-on-ns", &gpmc_t->we_on);
2029         of_property_read_u32(np, "gpmc,we-off-ns", &gpmc_t->we_off);
2030
2031         /* OE signal timings */
2032         of_property_read_u32(np, "gpmc,oe-on-ns", &gpmc_t->oe_on);
2033         of_property_read_u32(np, "gpmc,oe-off-ns", &gpmc_t->oe_off);
2034         of_property_read_u32(np, "gpmc,oe-aad-mux-on-ns",
2035                              &gpmc_t->oe_aad_mux_on);
2036         of_property_read_u32(np, "gpmc,oe-aad-mux-off-ns",
2037                              &gpmc_t->oe_aad_mux_off);
2038
2039         /* access and cycle timings */
2040         of_property_read_u32(np, "gpmc,page-burst-access-ns",
2041                              &gpmc_t->page_burst_access);
2042         of_property_read_u32(np, "gpmc,access-ns", &gpmc_t->access);
2043         of_property_read_u32(np, "gpmc,rd-cycle-ns", &gpmc_t->rd_cycle);
2044         of_property_read_u32(np, "gpmc,wr-cycle-ns", &gpmc_t->wr_cycle);
2045         of_property_read_u32(np, "gpmc,bus-turnaround-ns",
2046                              &gpmc_t->bus_turnaround);
2047         of_property_read_u32(np, "gpmc,cycle2cycle-delay-ns",
2048                              &gpmc_t->cycle2cycle_delay);
2049         of_property_read_u32(np, "gpmc,wait-monitoring-ns",
2050                              &gpmc_t->wait_monitoring);
2051         of_property_read_u32(np, "gpmc,clk-activation-ns",
2052                              &gpmc_t->clk_activation);
2053
2054         /* only applicable to OMAP3+ */
2055         of_property_read_u32(np, "gpmc,wr-access-ns", &gpmc_t->wr_access);
2056         of_property_read_u32(np, "gpmc,wr-data-mux-bus-ns",
2057                              &gpmc_t->wr_data_mux_bus);
2058
2059         /* bool timing parameters */
2060         p = &gpmc_t->bool_timings;
2061
2062         p->cycle2cyclediffcsen =
2063                 of_property_read_bool(np, "gpmc,cycle2cycle-diffcsen");
2064         p->cycle2cyclesamecsen =
2065                 of_property_read_bool(np, "gpmc,cycle2cycle-samecsen");
2066         p->we_extra_delay = of_property_read_bool(np, "gpmc,we-extra-delay");
2067         p->oe_extra_delay = of_property_read_bool(np, "gpmc,oe-extra-delay");
2068         p->adv_extra_delay = of_property_read_bool(np, "gpmc,adv-extra-delay");
2069         p->cs_extra_delay = of_property_read_bool(np, "gpmc,cs-extra-delay");
2070         p->time_para_granularity =
2071                 of_property_read_bool(np, "gpmc,time-para-granularity");
2072 }
2073
2074 /**
2075  * gpmc_probe_generic_child - configures the gpmc for a child device
2076  * @pdev:       pointer to gpmc platform device
2077  * @child:      pointer to device-tree node for child device
2078  *
2079  * Allocates and configures a GPMC chip-select for a child device.
2080  * Returns 0 on success and appropriate negative error code on failure.
2081  */
2082 static int gpmc_probe_generic_child(struct platform_device *pdev,
2083                                 struct device_node *child)
2084 {
2085         struct gpmc_settings gpmc_s;
2086         struct gpmc_timings gpmc_t;
2087         struct resource res;
2088         unsigned long base;
2089         const char *name;
2090         int ret, cs;
2091         u32 val;
2092         struct gpio_desc *waitpin_desc = NULL;
2093         struct gpmc_device *gpmc = platform_get_drvdata(pdev);
2094
2095         if (of_property_read_u32(child, "reg", &cs) < 0) {
2096                 dev_err(&pdev->dev, "%pOF has no 'reg' property\n",
2097                         child);
2098                 return -ENODEV;
2099         }
2100
2101         if (of_address_to_resource(child, 0, &res) < 0) {
2102                 dev_err(&pdev->dev, "%pOF has malformed 'reg' property\n",
2103                         child);
2104                 return -ENODEV;
2105         }
2106
2107         /*
2108          * Check if we have multiple instances of the same device
2109          * on a single chip select. If so, use the already initialized
2110          * timings.
2111          */
2112         name = gpmc_cs_get_name(cs);
2113         if (name && of_node_name_eq(child, name))
2114                 goto no_timings;
2115
2116         ret = gpmc_cs_request(cs, resource_size(&res), &base);
2117         if (ret < 0) {
2118                 dev_err(&pdev->dev, "cannot request GPMC CS %d\n", cs);
2119                 return ret;
2120         }
2121         gpmc_cs_set_name(cs, child->full_name);
2122
2123         gpmc_read_settings_dt(child, &gpmc_s);
2124         gpmc_read_timings_dt(child, &gpmc_t);
2125
2126         /*
2127          * For some GPMC devices we still need to rely on the bootloader
2128          * timings because the devices can be connected via FPGA.
2129          * REVISIT: Add timing support from slls644g.pdf.
2130          */
2131         if (!gpmc_t.cs_rd_off) {
2132                 WARN(1, "enable GPMC debug to configure .dts timings for CS%i\n",
2133                         cs);
2134                 gpmc_cs_show_timings(cs,
2135                                      "please add GPMC bootloader timings to .dts");
2136                 goto no_timings;
2137         }
2138
2139         /* CS must be disabled while making changes to gpmc configuration */
2140         gpmc_cs_disable_mem(cs);
2141
2142         /*
2143          * FIXME: gpmc_cs_request() will map the CS to an arbitrary
2144          * location in the gpmc address space. When booting with
2145          * device-tree we want the NOR flash to be mapped to the
2146          * location specified in the device-tree blob. So remap the
2147          * CS to this location. Once DT migration is complete should
2148          * just make gpmc_cs_request() map a specific address.
2149          */
2150         ret = gpmc_cs_remap(cs, res.start);
2151         if (ret < 0) {
2152                 dev_err(&pdev->dev, "cannot remap GPMC CS %d to %pa\n",
2153                         cs, &res.start);
2154                 if (res.start < GPMC_MEM_START) {
2155                         dev_info(&pdev->dev,
2156                                  "GPMC CS %d start cannot be lesser than 0x%x\n",
2157                                  cs, GPMC_MEM_START);
2158                 } else if (res.end > GPMC_MEM_END) {
2159                         dev_info(&pdev->dev,
2160                                  "GPMC CS %d end cannot be greater than 0x%x\n",
2161                                  cs, GPMC_MEM_END);
2162                 }
2163                 goto err;
2164         }
2165
2166         if (of_node_name_eq(child, "nand")) {
2167                 /* Warn about older DT blobs with no compatible property */
2168                 if (!of_property_read_bool(child, "compatible")) {
2169                         dev_warn(&pdev->dev,
2170                                  "Incompatible NAND node: missing compatible");
2171                         ret = -EINVAL;
2172                         goto err;
2173                 }
2174         }
2175
2176         if (of_node_name_eq(child, "onenand")) {
2177                 /* Warn about older DT blobs with no compatible property */
2178                 if (!of_property_read_bool(child, "compatible")) {
2179                         dev_warn(&pdev->dev,
2180                                  "Incompatible OneNAND node: missing compatible");
2181                         ret = -EINVAL;
2182                         goto err;
2183                 }
2184         }
2185
2186         if (of_match_node(omap_nand_ids, child)) {
2187                 /* NAND specific setup */
2188                 val = 8;
2189                 of_property_read_u32(child, "nand-bus-width", &val);
2190                 switch (val) {
2191                 case 8:
2192                         gpmc_s.device_width = GPMC_DEVWIDTH_8BIT;
2193                         break;
2194                 case 16:
2195                         gpmc_s.device_width = GPMC_DEVWIDTH_16BIT;
2196                         break;
2197                 default:
2198                         dev_err(&pdev->dev, "%pOFn: invalid 'nand-bus-width'\n",
2199                                 child);
2200                         ret = -EINVAL;
2201                         goto err;
2202                 }
2203
2204                 /* disable write protect */
2205                 gpmc_configure(GPMC_CONFIG_WP, 0);
2206                 gpmc_s.device_nand = true;
2207         } else {
2208                 ret = of_property_read_u32(child, "bank-width",
2209                                            &gpmc_s.device_width);
2210                 if (ret < 0 && !gpmc_s.device_width) {
2211                         dev_err(&pdev->dev,
2212                                 "%pOF has no 'gpmc,device-width' property\n",
2213                                 child);
2214                         goto err;
2215                 }
2216         }
2217
2218         /* Reserve wait pin if it is required and valid */
2219         if (gpmc_s.wait_on_read || gpmc_s.wait_on_write) {
2220                 unsigned int wait_pin = gpmc_s.wait_pin;
2221
2222                 waitpin_desc = gpiochip_request_own_desc(&gpmc->gpio_chip,
2223                                                          wait_pin, "WAITPIN",
2224                                                          GPIO_ACTIVE_HIGH,
2225                                                          GPIOD_IN);
2226                 if (IS_ERR(waitpin_desc)) {
2227                         dev_err(&pdev->dev, "invalid wait-pin: %d\n", wait_pin);
2228                         ret = PTR_ERR(waitpin_desc);
2229                         goto err;
2230                 }
2231         }
2232
2233         gpmc_cs_show_timings(cs, "before gpmc_cs_program_settings");
2234
2235         ret = gpmc_cs_program_settings(cs, &gpmc_s);
2236         if (ret < 0)
2237                 goto err_cs;
2238
2239         ret = gpmc_cs_set_timings(cs, &gpmc_t, &gpmc_s);
2240         if (ret) {
2241                 dev_err(&pdev->dev, "failed to set gpmc timings for: %pOFn\n",
2242                         child);
2243                 goto err_cs;
2244         }
2245
2246         /* Clear limited address i.e. enable A26-A11 */
2247         val = gpmc_read_reg(GPMC_CONFIG);
2248         val &= ~GPMC_CONFIG_LIMITEDADDRESS;
2249         gpmc_write_reg(GPMC_CONFIG, val);
2250
2251         /* Enable CS region */
2252         gpmc_cs_enable_mem(cs);
2253
2254 no_timings:
2255
2256         /* create platform device, NULL on error or when disabled */
2257         if (!of_platform_device_create(child, NULL, &pdev->dev))
2258                 goto err_child_fail;
2259
2260         /* is child a common bus? */
2261         if (of_match_node(of_default_bus_match_table, child))
2262                 /* create children and other common bus children */
2263                 if (of_platform_default_populate(child, NULL, &pdev->dev))
2264                         goto err_child_fail;
2265
2266         return 0;
2267
2268 err_child_fail:
2269
2270         dev_err(&pdev->dev, "failed to create gpmc child %pOFn\n", child);
2271         ret = -ENODEV;
2272
2273 err_cs:
2274         gpiochip_free_own_desc(waitpin_desc);
2275 err:
2276         gpmc_cs_free(cs);
2277
2278         return ret;
2279 }
2280
2281 static int gpmc_probe_dt(struct platform_device *pdev)
2282 {
2283         int ret;
2284         const struct of_device_id *of_id =
2285                 of_match_device(gpmc_dt_ids, &pdev->dev);
2286
2287         if (!of_id)
2288                 return 0;
2289
2290         ret = of_property_read_u32(pdev->dev.of_node, "gpmc,num-cs",
2291                                    &gpmc_cs_num);
2292         if (ret < 0) {
2293                 pr_err("%s: number of chip-selects not defined\n", __func__);
2294                 return ret;
2295         } else if (gpmc_cs_num < 1) {
2296                 pr_err("%s: all chip-selects are disabled\n", __func__);
2297                 return -EINVAL;
2298         } else if (gpmc_cs_num > GPMC_CS_NUM) {
2299                 pr_err("%s: number of supported chip-selects cannot be > %d\n",
2300                                          __func__, GPMC_CS_NUM);
2301                 return -EINVAL;
2302         }
2303
2304         ret = of_property_read_u32(pdev->dev.of_node, "gpmc,num-waitpins",
2305                                    &gpmc_nr_waitpins);
2306         if (ret < 0) {
2307                 pr_err("%s: number of wait pins not found!\n", __func__);
2308                 return ret;
2309         }
2310
2311         return 0;
2312 }
2313
2314 static void gpmc_probe_dt_children(struct platform_device *pdev)
2315 {
2316         int ret;
2317         struct device_node *child;
2318
2319         for_each_available_child_of_node(pdev->dev.of_node, child) {
2320                 ret = gpmc_probe_generic_child(pdev, child);
2321                 if (ret) {
2322                         dev_err(&pdev->dev, "failed to probe DT child '%pOFn': %d\n",
2323                                 child, ret);
2324                 }
2325         }
2326 }
2327 #else
2328 void gpmc_read_settings_dt(struct device_node *np, struct gpmc_settings *p)
2329 {
2330         memset(p, 0, sizeof(*p));
2331 }
2332 static int gpmc_probe_dt(struct platform_device *pdev)
2333 {
2334         return 0;
2335 }
2336
2337 static void gpmc_probe_dt_children(struct platform_device *pdev)
2338 {
2339 }
2340 #endif /* CONFIG_OF */
2341
2342 static int gpmc_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
2343 {
2344         return 1;       /* we're input only */
2345 }
2346
2347 static int gpmc_gpio_direction_input(struct gpio_chip *chip,
2348                                      unsigned int offset)
2349 {
2350         return 0;       /* we're input only */
2351 }
2352
2353 static int gpmc_gpio_direction_output(struct gpio_chip *chip,
2354                                       unsigned int offset, int value)
2355 {
2356         return -EINVAL; /* we're input only */
2357 }
2358
2359 static void gpmc_gpio_set(struct gpio_chip *chip, unsigned int offset,
2360                           int value)
2361 {
2362 }
2363
2364 static int gpmc_gpio_get(struct gpio_chip *chip, unsigned int offset)
2365 {
2366         u32 reg;
2367
2368         offset += 8;
2369
2370         reg = gpmc_read_reg(GPMC_STATUS) & BIT(offset);
2371
2372         return !!reg;
2373 }
2374
2375 static int gpmc_gpio_init(struct gpmc_device *gpmc)
2376 {
2377         int ret;
2378
2379         gpmc->gpio_chip.parent = gpmc->dev;
2380         gpmc->gpio_chip.owner = THIS_MODULE;
2381         gpmc->gpio_chip.label = DEVICE_NAME;
2382         gpmc->gpio_chip.ngpio = gpmc_nr_waitpins;
2383         gpmc->gpio_chip.get_direction = gpmc_gpio_get_direction;
2384         gpmc->gpio_chip.direction_input = gpmc_gpio_direction_input;
2385         gpmc->gpio_chip.direction_output = gpmc_gpio_direction_output;
2386         gpmc->gpio_chip.set = gpmc_gpio_set;
2387         gpmc->gpio_chip.get = gpmc_gpio_get;
2388         gpmc->gpio_chip.base = -1;
2389
2390         ret = devm_gpiochip_add_data(gpmc->dev, &gpmc->gpio_chip, NULL);
2391         if (ret < 0) {
2392                 dev_err(gpmc->dev, "could not register gpio chip: %d\n", ret);
2393                 return ret;
2394         }
2395
2396         return 0;
2397 }
2398
2399 static void omap3_gpmc_save_context(struct gpmc_device *gpmc)
2400 {
2401         struct omap3_gpmc_regs *gpmc_context;
2402         int i;
2403
2404         if (!gpmc || !gpmc_base)
2405                 return;
2406
2407         gpmc_context = &gpmc->context;
2408
2409         gpmc_context->sysconfig = gpmc_read_reg(GPMC_SYSCONFIG);
2410         gpmc_context->irqenable = gpmc_read_reg(GPMC_IRQENABLE);
2411         gpmc_context->timeout_ctrl = gpmc_read_reg(GPMC_TIMEOUT_CONTROL);
2412         gpmc_context->config = gpmc_read_reg(GPMC_CONFIG);
2413         gpmc_context->prefetch_config1 = gpmc_read_reg(GPMC_PREFETCH_CONFIG1);
2414         gpmc_context->prefetch_config2 = gpmc_read_reg(GPMC_PREFETCH_CONFIG2);
2415         gpmc_context->prefetch_control = gpmc_read_reg(GPMC_PREFETCH_CONTROL);
2416         for (i = 0; i < gpmc_cs_num; i++) {
2417                 gpmc_context->cs_context[i].is_valid = gpmc_cs_mem_enabled(i);
2418                 if (gpmc_context->cs_context[i].is_valid) {
2419                         gpmc_context->cs_context[i].config1 =
2420                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG1);
2421                         gpmc_context->cs_context[i].config2 =
2422                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG2);
2423                         gpmc_context->cs_context[i].config3 =
2424                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG3);
2425                         gpmc_context->cs_context[i].config4 =
2426                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG4);
2427                         gpmc_context->cs_context[i].config5 =
2428                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG5);
2429                         gpmc_context->cs_context[i].config6 =
2430                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG6);
2431                         gpmc_context->cs_context[i].config7 =
2432                                 gpmc_cs_read_reg(i, GPMC_CS_CONFIG7);
2433                 }
2434         }
2435 }
2436
2437 static void omap3_gpmc_restore_context(struct gpmc_device *gpmc)
2438 {
2439         struct omap3_gpmc_regs *gpmc_context;
2440         int i;
2441
2442         if (!gpmc || !gpmc_base)
2443                 return;
2444
2445         gpmc_context = &gpmc->context;
2446
2447         gpmc_write_reg(GPMC_SYSCONFIG, gpmc_context->sysconfig);
2448         gpmc_write_reg(GPMC_IRQENABLE, gpmc_context->irqenable);
2449         gpmc_write_reg(GPMC_TIMEOUT_CONTROL, gpmc_context->timeout_ctrl);
2450         gpmc_write_reg(GPMC_CONFIG, gpmc_context->config);
2451         gpmc_write_reg(GPMC_PREFETCH_CONFIG1, gpmc_context->prefetch_config1);
2452         gpmc_write_reg(GPMC_PREFETCH_CONFIG2, gpmc_context->prefetch_config2);
2453         gpmc_write_reg(GPMC_PREFETCH_CONTROL, gpmc_context->prefetch_control);
2454         for (i = 0; i < gpmc_cs_num; i++) {
2455                 if (gpmc_context->cs_context[i].is_valid) {
2456                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG1,
2457                                           gpmc_context->cs_context[i].config1);
2458                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG2,
2459                                           gpmc_context->cs_context[i].config2);
2460                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG3,
2461                                           gpmc_context->cs_context[i].config3);
2462                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG4,
2463                                           gpmc_context->cs_context[i].config4);
2464                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG5,
2465                                           gpmc_context->cs_context[i].config5);
2466                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG6,
2467                                           gpmc_context->cs_context[i].config6);
2468                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG7,
2469                                           gpmc_context->cs_context[i].config7);
2470                 } else {
2471                         gpmc_cs_write_reg(i, GPMC_CS_CONFIG7, 0);
2472                 }
2473         }
2474 }
2475
2476 static int omap_gpmc_context_notifier(struct notifier_block *nb,
2477                                       unsigned long cmd, void *v)
2478 {
2479         struct gpmc_device *gpmc;
2480
2481         gpmc = container_of(nb, struct gpmc_device, nb);
2482         if (gpmc->is_suspended || pm_runtime_suspended(gpmc->dev))
2483                 return NOTIFY_OK;
2484
2485         switch (cmd) {
2486         case CPU_CLUSTER_PM_ENTER:
2487                 omap3_gpmc_save_context(gpmc);
2488                 break;
2489         case CPU_CLUSTER_PM_ENTER_FAILED:       /* No need to restore context */
2490                 break;
2491         case CPU_CLUSTER_PM_EXIT:
2492                 omap3_gpmc_restore_context(gpmc);
2493                 break;
2494         }
2495
2496         return NOTIFY_OK;
2497 }
2498
2499 static int gpmc_probe(struct platform_device *pdev)
2500 {
2501         int rc;
2502         u32 l;
2503         struct resource *res;
2504         struct gpmc_device *gpmc;
2505
2506         gpmc = devm_kzalloc(&pdev->dev, sizeof(*gpmc), GFP_KERNEL);
2507         if (!gpmc)
2508                 return -ENOMEM;
2509
2510         gpmc->dev = &pdev->dev;
2511         platform_set_drvdata(pdev, gpmc);
2512
2513         res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cfg");
2514         if (!res) {
2515                 /* legacy DT */
2516                 gpmc_base = devm_platform_ioremap_resource(pdev, 0);
2517                 if (IS_ERR(gpmc_base))
2518                         return PTR_ERR(gpmc_base);
2519         } else {
2520                 gpmc_base = devm_ioremap_resource(&pdev->dev, res);
2521                 if (IS_ERR(gpmc_base))
2522                         return PTR_ERR(gpmc_base);
2523
2524                 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "data");
2525                 if (!res) {
2526                         dev_err(&pdev->dev, "couldn't get data reg resource\n");
2527                         return -ENOENT;
2528                 }
2529
2530                 gpmc->data = res;
2531         }
2532
2533         gpmc->irq = platform_get_irq(pdev, 0);
2534         if (gpmc->irq < 0)
2535                 return gpmc->irq;
2536
2537         gpmc_l3_clk = devm_clk_get(&pdev->dev, "fck");
2538         if (IS_ERR(gpmc_l3_clk)) {
2539                 dev_err(&pdev->dev, "Failed to get GPMC fck\n");
2540                 return PTR_ERR(gpmc_l3_clk);
2541         }
2542
2543         if (!clk_get_rate(gpmc_l3_clk)) {
2544                 dev_err(&pdev->dev, "Invalid GPMC fck clock rate\n");
2545                 return -EINVAL;
2546         }
2547
2548         if (pdev->dev.of_node) {
2549                 rc = gpmc_probe_dt(pdev);
2550                 if (rc)
2551                         return rc;
2552         } else {
2553                 gpmc_cs_num = GPMC_CS_NUM;
2554                 gpmc_nr_waitpins = GPMC_NR_WAITPINS;
2555         }
2556
2557         pm_runtime_enable(&pdev->dev);
2558         pm_runtime_get_sync(&pdev->dev);
2559
2560         l = gpmc_read_reg(GPMC_REVISION);
2561
2562         /*
2563          * FIXME: Once device-tree migration is complete the below flags
2564          * should be populated based upon the device-tree compatible
2565          * string. For now just use the IP revision. OMAP3+ devices have
2566          * the wr_access and wr_data_mux_bus register fields. OMAP4+
2567          * devices support the addr-addr-data multiplex protocol.
2568          *
2569          * GPMC IP revisions:
2570          * - OMAP24xx                   = 2.0
2571          * - OMAP3xxx                   = 5.0
2572          * - OMAP44xx/54xx/AM335x       = 6.0
2573          */
2574         if (GPMC_REVISION_MAJOR(l) > 0x4)
2575                 gpmc_capability = GPMC_HAS_WR_ACCESS | GPMC_HAS_WR_DATA_MUX_BUS;
2576         if (GPMC_REVISION_MAJOR(l) > 0x5)
2577                 gpmc_capability |= GPMC_HAS_MUX_AAD;
2578         dev_info(gpmc->dev, "GPMC revision %d.%d\n", GPMC_REVISION_MAJOR(l),
2579                  GPMC_REVISION_MINOR(l));
2580
2581         gpmc_mem_init(gpmc);
2582         rc = gpmc_gpio_init(gpmc);
2583         if (rc)
2584                 goto gpio_init_failed;
2585
2586         gpmc->nirqs = GPMC_NR_NAND_IRQS + gpmc_nr_waitpins;
2587         rc = gpmc_setup_irq(gpmc);
2588         if (rc) {
2589                 dev_err(gpmc->dev, "gpmc_setup_irq failed\n");
2590                 goto gpio_init_failed;
2591         }
2592
2593         gpmc_probe_dt_children(pdev);
2594
2595         gpmc->nb.notifier_call = omap_gpmc_context_notifier;
2596         cpu_pm_register_notifier(&gpmc->nb);
2597
2598         return 0;
2599
2600 gpio_init_failed:
2601         gpmc_mem_exit();
2602         pm_runtime_put_sync(&pdev->dev);
2603         pm_runtime_disable(&pdev->dev);
2604
2605         return rc;
2606 }
2607
2608 static int gpmc_remove(struct platform_device *pdev)
2609 {
2610         struct gpmc_device *gpmc = platform_get_drvdata(pdev);
2611
2612         cpu_pm_unregister_notifier(&gpmc->nb);
2613         gpmc_free_irq(gpmc);
2614         gpmc_mem_exit();
2615         pm_runtime_put_sync(&pdev->dev);
2616         pm_runtime_disable(&pdev->dev);
2617
2618         return 0;
2619 }
2620
2621 #ifdef CONFIG_PM_SLEEP
2622 static int gpmc_suspend(struct device *dev)
2623 {
2624         struct gpmc_device *gpmc = dev_get_drvdata(dev);
2625
2626         omap3_gpmc_save_context(gpmc);
2627         pm_runtime_put_sync(dev);
2628         gpmc->is_suspended = 1;
2629
2630         return 0;
2631 }
2632
2633 static int gpmc_resume(struct device *dev)
2634 {
2635         struct gpmc_device *gpmc = dev_get_drvdata(dev);
2636
2637         pm_runtime_get_sync(dev);
2638         omap3_gpmc_restore_context(gpmc);
2639         gpmc->is_suspended = 0;
2640
2641         return 0;
2642 }
2643 #endif
2644
2645 static SIMPLE_DEV_PM_OPS(gpmc_pm_ops, gpmc_suspend, gpmc_resume);
2646
2647 static struct platform_driver gpmc_driver = {
2648         .probe          = gpmc_probe,
2649         .remove         = gpmc_remove,
2650         .driver         = {
2651                 .name   = DEVICE_NAME,
2652                 .of_match_table = of_match_ptr(gpmc_dt_ids),
2653                 .pm     = &gpmc_pm_ops,
2654         },
2655 };
2656
2657 static __init int gpmc_init(void)
2658 {
2659         return platform_driver_register(&gpmc_driver);
2660 }
2661 postcore_initcall(gpmc_init);