drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/delay.h>
  25 #include <linux/kernel.h>
  26 #include <linux/firmware.h>
  27 #include <linux/module.h>
  28 #include <linux/pci.h>
  29 #include "amdgpu.h"
  30 #include "amdgpu_gfx.h"
  31 #include "amdgpu_psp.h"
  32 #include "amdgpu_smu.h"
  33 #include "nv.h"
  34 #include "nvd.h"
  35
  36 #include "gc/gc_10_1_0_offset.h"
  37 #include "gc/gc_10_1_0_sh_mask.h"
  38 #include "smuio/smuio_11_0_0_offset.h"
  39 #include "smuio/smuio_11_0_0_sh_mask.h"
  40 #include "navi10_enum.h"
  41 #include "hdp/hdp_5_0_0_offset.h"
  42 #include "ivsrcid/gfx/irqsrcs_gfx_10_1.h"
  43
  44 #include "soc15.h"
  45 #include "soc15d.h"
  46 #include "soc15_common.h"
  47 #include "clearstate_gfx10.h"
  48 #include "v10_structs.h"
  49 #include "gfx_v10_0.h"
  50 #include "nbio_v2_3.h"
  51
  52 /**
  53  * Navi10 has two graphic rings to share each graphic pipe.
  54  * 1. Primary ring
  55  * 2. Async ring
  56  */
  57 #define GFX10_NUM_GFX_RINGS_NV1X        1
  58 #define GFX10_NUM_GFX_RINGS_Sienna_Cichlid      1
  59 #define GFX10_MEC_HPD_SIZE      2048
  60
  61 #define F32_CE_PROGRAM_RAM_SIZE         65536
  62 #define RLCG_UCODE_LOADING_START_ADDRESS        0x00002000L
  63
  64 #define mmCGTT_GS_NGG_CLK_CTRL  0x5087
  65 #define mmCGTT_GS_NGG_CLK_CTRL_BASE_IDX 1
  66 #define mmCGTT_SPI_RA0_CLK_CTRL 0x507a
  67 #define mmCGTT_SPI_RA0_CLK_CTRL_BASE_IDX 1
  68 #define mmCGTT_SPI_RA1_CLK_CTRL 0x507b
  69 #define mmCGTT_SPI_RA1_CLK_CTRL_BASE_IDX 1
  70
  71 #define GB_ADDR_CONFIG__NUM_PKRS__SHIFT                                                                       0x8
  72 #define GB_ADDR_CONFIG__NUM_PKRS_MASK                                                                         0x00000700L
  73
  74 #define mmCP_MEC_CNTL_Sienna_Cichlid                      0x0f55
  75 #define mmCP_MEC_CNTL_Sienna_Cichlid_BASE_IDX             0
  76 #define mmRLC_SAFE_MODE_Sienna_Cichlid                  0x4ca0
  77 #define mmRLC_SAFE_MODE_Sienna_Cichlid_BASE_IDX         1
  78 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid              0x4ca1
  79 #define mmRLC_CP_SCHEDULERS_Sienna_Cichlid_BASE_IDX     1
  80 #define mmSPI_CONFIG_CNTL_Sienna_Cichlid                        0x11ec
  81 #define mmSPI_CONFIG_CNTL_Sienna_Cichlid_BASE_IDX               0
  82 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid             0x0fc1
  83 #define mmVGT_ESGS_RING_SIZE_Sienna_Cichlid_BASE_IDX    0
  84 #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid             0x0fc2
  85 #define mmVGT_GSVS_RING_SIZE_Sienna_Cichlid_BASE_IDX    0
  86 #define mmVGT_TF_RING_SIZE_Sienna_Cichlid                       0x0fc3
  87 #define mmVGT_TF_RING_SIZE_Sienna_Cichlid_BASE_IDX      0
  88 #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid           0x0fc4
  89 #define mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid_BASE_IDX  0
  90 #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid             0x0fc5
  91 #define mmVGT_TF_MEMORY_BASE_Sienna_Cichlid_BASE_IDX    0
  92 #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid          0x0fc6
  93 #define mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid_BASE_IDX 0
  94 #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid__SHIFT    0x1a
  95 #define GRBM_STATUS2__RLC_BUSY_Sienna_Cichlid_MASK      0x04000000L
  96 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid_MASK    0x00000FFCL
  97 #define CP_RB_DOORBELL_RANGE_LOWER__DOORBELL_RANGE_LOWER_Sienna_Cichlid__SHIFT  0x2
  98 #define CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK    0x00000FFCL
  99 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid                       0x1580
 100 #define mmGCR_GENERAL_CNTL_Sienna_Cichlid_BASE_IDX      0
 101
 102 #define mmCP_HYP_PFP_UCODE_ADDR                 0x5814
 103 #define mmCP_HYP_PFP_UCODE_ADDR_BASE_IDX        1
 104 #define mmCP_HYP_PFP_UCODE_DATA                 0x5815
 105 #define mmCP_HYP_PFP_UCODE_DATA_BASE_IDX        1
 106 #define mmCP_HYP_CE_UCODE_ADDR                  0x5818
 107 #define mmCP_HYP_CE_UCODE_ADDR_BASE_IDX         1
 108 #define mmCP_HYP_CE_UCODE_DATA                  0x5819
 109 #define mmCP_HYP_CE_UCODE_DATA_BASE_IDX         1
 110 #define mmCP_HYP_ME_UCODE_ADDR                  0x5816
 111 #define mmCP_HYP_ME_UCODE_ADDR_BASE_IDX         1
 112 #define mmCP_HYP_ME_UCODE_DATA                  0x5817
 113 #define mmCP_HYP_ME_UCODE_DATA_BASE_IDX         1
 114
 115 MODULE_FIRMWARE("amdgpu/navi10_ce.bin");
 116 MODULE_FIRMWARE("amdgpu/navi10_pfp.bin");
 117 MODULE_FIRMWARE("amdgpu/navi10_me.bin");
 118 MODULE_FIRMWARE("amdgpu/navi10_mec.bin");
 119 MODULE_FIRMWARE("amdgpu/navi10_mec2.bin");
 120 MODULE_FIRMWARE("amdgpu/navi10_rlc.bin");
 121
 122 MODULE_FIRMWARE("amdgpu/navi14_ce_wks.bin");
 123 MODULE_FIRMWARE("amdgpu/navi14_pfp_wks.bin");
 124 MODULE_FIRMWARE("amdgpu/navi14_me_wks.bin");
 125 MODULE_FIRMWARE("amdgpu/navi14_mec_wks.bin");
 126 MODULE_FIRMWARE("amdgpu/navi14_mec2_wks.bin");
 127 MODULE_FIRMWARE("amdgpu/navi14_ce.bin");
 128 MODULE_FIRMWARE("amdgpu/navi14_pfp.bin");
 129 MODULE_FIRMWARE("amdgpu/navi14_me.bin");
 130 MODULE_FIRMWARE("amdgpu/navi14_mec.bin");
 131 MODULE_FIRMWARE("amdgpu/navi14_mec2.bin");
 132 MODULE_FIRMWARE("amdgpu/navi14_rlc.bin");
 133
 134 MODULE_FIRMWARE("amdgpu/navi12_ce.bin");
 135 MODULE_FIRMWARE("amdgpu/navi12_pfp.bin");
 136 MODULE_FIRMWARE("amdgpu/navi12_me.bin");
 137 MODULE_FIRMWARE("amdgpu/navi12_mec.bin");
 138 MODULE_FIRMWARE("amdgpu/navi12_mec2.bin");
 139 MODULE_FIRMWARE("amdgpu/navi12_rlc.bin");
 140
 141 MODULE_FIRMWARE("amdgpu/sienna_cichlid_ce.bin");
 142 MODULE_FIRMWARE("amdgpu/sienna_cichlid_pfp.bin");
 143 MODULE_FIRMWARE("amdgpu/sienna_cichlid_me.bin");
 144 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec.bin");
 145 MODULE_FIRMWARE("amdgpu/sienna_cichlid_mec2.bin");
 146 MODULE_FIRMWARE("amdgpu/sienna_cichlid_rlc.bin");
 147
 148 MODULE_FIRMWARE("amdgpu/navy_flounder_ce.bin");
 149 MODULE_FIRMWARE("amdgpu/navy_flounder_pfp.bin");
 150 MODULE_FIRMWARE("amdgpu/navy_flounder_me.bin");
 151 MODULE_FIRMWARE("amdgpu/navy_flounder_mec.bin");
 152 MODULE_FIRMWARE("amdgpu/navy_flounder_mec2.bin");
 153 MODULE_FIRMWARE("amdgpu/navy_flounder_rlc.bin");
 154
 155 static const struct soc15_reg_golden golden_settings_gc_10_1[] =
 156 {
 157         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x00400014),
 158         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_CPF_CLK_CTRL, 0xfcff8fff, 0xf8000100),
 159         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100),
 160         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0x60000ff0, 0x60000100),
 161         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000000, 0x40000100),
 162         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
 163         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xfeff8fff, 0xfeff8100),
 164         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
 165         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000),
 166         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x000007ff, 0x000005ff),
 167         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0x20000000, 0x20000000),
 168         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
 169         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200),
 170         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07900000, 0x04900000),
 171         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
 172         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
 173         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
 174         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe),
 175         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
 176         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032),
 177         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231),
 178         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
 179         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
 180         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0x10000000, 0x10000100),
 181         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
 182         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffff9fff, 0x00001188),
 183         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
 184         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
 185         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000),
 186         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
 187         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
 188         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
 189         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070104),
 190         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
 191         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000100, 0x00000130),
 192         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
 193         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
 194         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010),
 195         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CGTT_CLK_CTRL, 0xfeff0fff, 0x40000100),
 196         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000)
 197 };
 198
 199 static const struct soc15_reg_golden golden_settings_gc_10_0_nv10[] =
 200 {
 201         /* Pending on emulation bring up */
 202 };
 203
 204 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_0_nv10[] =
 205 {
 206         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000, 0x0),
 207         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 208         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
 209         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 210         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 211         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 212         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
 213         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 214         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 215         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 216         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
 217         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 218         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 219         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 220         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
 221         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 222         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 223         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 224         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
 225         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 226         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 227         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 228         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
 229         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 230         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 231         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 232         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
 233         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 234         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 235         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 236         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
 237         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 238         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 239         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 240         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
 241         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 242         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 243         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 244         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
 245         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 246         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 247         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 248         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
 249         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 250         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
 251         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 252         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
 253         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 254         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 255         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 256         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
 257         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 258         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
 259         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 260         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
 261         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 262         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 263         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 264         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
 265         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 266         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 267         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 268         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
 269         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 270         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 271         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 272         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
 273         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 274         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 275         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 276         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
 277         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 278         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 279         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 280         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
 281         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 282         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 283         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 284         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
 285         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 286         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 287         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 288         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
 289         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 290         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 291         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 292         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
 293         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 294         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 295         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 296         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
 297         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 298         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 299         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 300         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
 301         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 302         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
 303         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 304         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
 305         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 306         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
 307         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 308         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
 309         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 310         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 311         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 312         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
 313         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 314         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 315         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 316         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
 317         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 318         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 319         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 320         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
 321         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 322         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 323         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 324         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
 325         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 326         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 327         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 328         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
 329         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 330         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 331         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 332         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
 333         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 334         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 335         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 336         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
 337         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 338         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 339         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 340         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
 341         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 342         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 343         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 344         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
 345         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 346         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 347         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 348         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
 349         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 350         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 351         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 352         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
 353         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 354         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 355         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 356         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
 357         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 358         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 359         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 360         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
 361         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 362         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
 363         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 364         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
 365         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 366         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 367         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 368         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
 369         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 370         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 371         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 372         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
 373         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 374         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 375         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 376         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
 377         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 378         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 379         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 380         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
 381         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 382         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
 383         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 384         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
 385         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 386         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 387         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 388         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
 389         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 390         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 391         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 392         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
 393         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 394         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
 395         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 396         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
 397         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 398         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
 399         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 400         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
 401         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 402         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 403         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 404         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
 405         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 406         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 407         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 408         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
 409         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 410         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 411         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 412         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
 413         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 414         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 415         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 416         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
 417         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 418         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
 419         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 420         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
 421         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 422         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 423         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 424         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
 425         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 426         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
 427         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 428         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
 429         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 430         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 431         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 432         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
 433         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 434         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 435         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 436         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
 437         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 438         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 439         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 440         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
 441         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 442         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 443         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 444         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
 445         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 446         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 447         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 448         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
 449         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 450         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 451         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 452         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
 453         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 454         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 455         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 456         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
 457         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 458         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 459         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 460         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
 461         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 462         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 463         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 464         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
 465         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 466         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 467         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 468         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
 469         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 470         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 471         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 472         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
 473         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 474         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 475         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 476         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
 477         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 478         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 479         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 480         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
 481         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 482         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 483         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 484         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
 485         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 486         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 487         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 488         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
 489         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 490         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 491         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 492         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
 493         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 494         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 495         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 496         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
 497         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 498         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 499         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 500         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
 501         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 502         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 503         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 504         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
 505         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 506         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 507         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 508         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
 509         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 510         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 511         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 512         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
 513         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 514         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 515         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 516         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
 517         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 518         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 519         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 520         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
 521         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 522         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 523         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 524         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
 525         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 526         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 527         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 528         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
 529         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 530         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 531         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 532         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
 533         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 534         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 535         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 536         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
 537         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 538         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
 539         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 540         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
 541         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 542         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
 543         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 544         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
 545         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 546         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 547         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 548         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
 549         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 550         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 551         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 552         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
 553         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 554         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 555         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 556         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
 557         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 558         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
 559         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 560         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
 561         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 562         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
 563         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 564         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
 565         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 566         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
 567         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 568         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
 569         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 570         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 571         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 572         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
 573         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 574         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 575         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 576         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
 577         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 578         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
 579         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 580         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
 581         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 582         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
 583         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 584         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
 585         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 586         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 587         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 588         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
 589         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 590         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 591         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 592         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
 593         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 594         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 595         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 596         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
 597         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 598         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 599         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 600         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
 601         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 602         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
 603         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 604         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
 605         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 606         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
 607         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 608         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
 609         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 610         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 611         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 612         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
 613         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 614         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 615         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 616         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
 617         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 618         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 619         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 620         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
 621         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 622         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 623         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 624         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
 625         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 626         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 627         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 628         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
 629         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 630         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 631         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 632         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
 633         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 634         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
 635         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 636         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
 637         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 638         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
 639         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 640         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
 641         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 642         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 643         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 644         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
 645         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 646         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 647         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 648         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
 649         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 650         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 651         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 652         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
 653         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 654         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 655         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 656         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
 657         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 658         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 659         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 660         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
 661         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 662         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 663         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 664         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
 665         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 666         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 667         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 668         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
 669         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 670         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 671         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 672         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
 673         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 674         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 675         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 676         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
 677         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 678         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 679         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 680         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
 681         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 682         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 683         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 684         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
 685         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 686         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 687         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 688         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
 689         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 690         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 691         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 692         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
 693         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 694         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 695         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 696         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
 697         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 698         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 699         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 700         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
 701         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 702         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 703         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 704         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
 705         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 706         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
 707         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 708         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
 709         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 710         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
 711         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 712         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
 713         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 714         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 715         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 716         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
 717         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 718         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
 719         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 720         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
 721         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 722         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 723         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 724         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
 725         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 726         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
 727         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 728         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
 729         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 730         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 731         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 732         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
 733         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 734         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 735         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 736         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
 737         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 738         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 739         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 740         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
 741         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 742         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 743         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 744         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
 745         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 746         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 747         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 748         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
 749         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 750         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 751         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 752         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
 753         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 754         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 755         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 756         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
 757         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 758         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 759         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 760         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
 761         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 762         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 763         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 764         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
 765         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 766         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 767         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 768         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
 769         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 770         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 771         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 772         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
 773         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 774         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 775         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 776         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
 777         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 778         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 779         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 780         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
 781         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 782         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 783         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 784         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
 785         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 786         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 787         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 788         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
 789         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 790         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
 791         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 792         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
 793         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 794         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 795         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 796         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
 797         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 798         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 799         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 800         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
 801         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 802         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 803         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 804         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
 805         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 806         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
 807         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 808         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
 809         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 810         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 811         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 812         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
 813         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 814         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 815         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 816         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
 817         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 818         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 819         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 820         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
 821         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 822         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
 823         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 824         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
 825         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 826         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 827         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 828         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
 829         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 830         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 831         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 832         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
 833         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 834         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 835         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 836         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
 837         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 838         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 839         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 840         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
 841         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 842         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 843         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 844         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
 845         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 846         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 847         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 848         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
 849         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 850         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 851         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 852         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
 853         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 854         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
 855         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 856         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
 857         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 858         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 859         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 860         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
 861         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 862         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 863         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 864         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
 865         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 866         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 867         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 868         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
 869         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 870         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
 871         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 872         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
 873         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 874         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 875         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 876         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
 877         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 878         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
 879         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 880         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
 881         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 882         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 883         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 884         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
 885         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 886         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 887         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 888         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
 889         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 890         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 891         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 892         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
 893         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 894         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 895         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 896         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
 897         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 898         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 899         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 900         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
 901         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 902         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 903         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 904         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
 905         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 906         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 907         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 908         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
 909         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 910         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 911         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 912         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
 913         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 914         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 915         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 916         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
 917         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 918         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 919         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 920         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
 921         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 922         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 923         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 924         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
 925         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 926         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
 927         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 928         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
 929         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 930         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 931         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 932         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
 933         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 934         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
 935         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 936         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
 937         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 938         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 939         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 940         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
 941         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 942         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 943         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 944         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
 945         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 946         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 947         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 948         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
 949         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 950         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
 951         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 952         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
 953         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 954         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 955         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 956         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
 957         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 958         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 959         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 960         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
 961         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 962         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 963         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 964         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
 965         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 966         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
 967         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 968         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
 969         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 970         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
 971         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 972         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
 973         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 974         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
 975         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 976         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
 977         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 978         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 979         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 980         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
 981         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 982         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
 983         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 984         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
 985         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 986         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 987         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 988         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
 989         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 990         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
 991         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 992         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
 993         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
 994         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 995         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 996         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
 997         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
 998         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
 999         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1000         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
1001         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1002         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1003         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1004         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
1005         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1006         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1007         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1008         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
1009         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1010         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1011         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1012         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
1013         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1014         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1015         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1016         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
1017         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1018         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1019         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1020         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
1021         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1022         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1023         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1024         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
1025         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1026         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1027         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1028         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
1029         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1030         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1031         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1032         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
1033         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1034         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1035         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1036         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
1037         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1038         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1039         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1040         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
1041         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1042         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1043         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1044         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
1045         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1046         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1047         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1048         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
1049         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1050         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1051         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1052         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
1053         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1054         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1055         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1056         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
1057         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1058         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1059         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1060         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
1061         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1062         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1063         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1064         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
1065         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1066         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1067         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1068         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
1069         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1070         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1071         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1072         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
1073         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1074         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
1075         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1076         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
1077         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1078         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
1079         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1080         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
1081         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1082         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1083         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1084         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
1085         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1086         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1087         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1088         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
1089         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1090         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
1091         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1092         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
1093         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1094         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
1095         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1096         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
1097         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1098         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1099         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1100         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
1101         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1102         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1103         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1104         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
1105         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1106         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1107         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1108         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
1109         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1110         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1111         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1112         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
1113         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1114         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1115         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1116         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
1117         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1118         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1119         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1120         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
1121         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1122         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1123         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1124         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
1125         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1126         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1127         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1128         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
1129         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1130         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1131         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1132         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
1133         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1134         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1135         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1136         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
1137         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1138         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1139         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1140         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
1141         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1142         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1143         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1144         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
1145         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1146         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1147         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1148         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
1149         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1150         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1151         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1152         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
1153         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1154         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1155         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1156         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
1157         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1158         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1159         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1160         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
1161         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1162         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1163         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1164         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
1165         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1166         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
1167         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1168         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
1169         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1170         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1171         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1172         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
1173         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1174         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1175         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1176         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
1177         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1178         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1179         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1180         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
1181         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1182         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1183         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1184         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
1185         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1186         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1187         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1188         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
1189         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1190         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1191         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1192         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
1193         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1194         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1195         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1196         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
1197         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1198         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1199         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1200         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
1201         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1202         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1203         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1204         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
1205         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1206         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1207         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1208         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
1209         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1210         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1211         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1212         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
1213         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1214         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1215         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1216         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
1217         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1218         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
1219         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1220         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
1221         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1222         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1223         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1224         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1225         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1226         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
1227         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1228         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1229         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1230         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
1231         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1232         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1233         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1234         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
1235         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1236         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1237         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1238         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
1239         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1240         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
1241         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1242         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
1243         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1244         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x19),
1245         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1246         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x20),
1247         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1248         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x5),
1249         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1250         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xa),
1251         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1252         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x14),
1253         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
1254         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x19),
1255         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1256         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x33),
1257         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
1258 };
1259
1260 static const struct soc15_reg_golden golden_settings_gc_10_1_1[] =
1261 {
1262         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0xffffffff, 0x003c0014),
1263         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100),
1264         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100),
1265         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xcd000000, 0x0d000100),
1266         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xf8ff0fff, 0x60000100),
1267         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0x40000ff0, 0x40000100),
1268         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
1269         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100),
1270         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1271         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000002, 0x00000000),
1272         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
1273         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
1274         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
1275         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000200, 0x00000200),
1276         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04900000),
1277         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
1278         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
1279         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
1280         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x000007ff, 0x000001fe),
1281         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1282         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7),
1283         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffe7),
1284         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100),
1285         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
1286         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188),
1287         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
1288         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
1289         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00400000, 0x04440000),
1290         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000800, 0x00000820),
1291         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
1292         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
1293         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x001f0000, 0x00070105),
1294         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
1295         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130),
1296         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
1297         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
1298         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0x60000010, 0x479c0010),
1299         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0x00c00000, 0x00c00000),
1300 };
1301
1302 static const struct soc15_reg_golden golden_settings_gc_10_1_2[] =
1303 {
1304         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_4, 0x003e001f, 0x003c0014),
1305         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_GS_NGG_CLK_CTRL, 0xffff8fff, 0xffff8100),
1306         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_IA_CLK_CTRL, 0xffff0fff, 0xffff0100),
1307         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_CLK_CTRL, 0xff7f0fff, 0x0d000100),
1308         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQ_CLK_CTRL, 0xffffcfff, 0x60000100),
1309         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SQG_CLK_CTRL, 0xffff0fff, 0x40000100),
1310         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xffff8fff, 0xffff8100),
1311         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_WD_CLK_CTRL, 0xffff8fff, 0xffff8100),
1312         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1313         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCH_VC5_ENABLE, 0x00000003, 0x00000000),
1314         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCP_SD_CNTL, 0x800007ff, 0x000005ff),
1315         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG, 0xffffffff, 0x20000000),
1316         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xffffffff, 0x00000420),
1317         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000200),
1318         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x04800000),
1319         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DFSM_TILES_IN_FLIGHT, 0x0000ffff, 0x0000003f),
1320         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_LAST_OF_BURST_CONFIG, 0xffffffff, 0x03860204),
1321         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x1ff0ffff, 0x00000500),
1322         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PRIV_CONTROL, 0x00007fff, 0x000001fe),
1323         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL1_PIPE_STEER, 0xffffffff, 0xe4e4e4e4),
1324         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_0, 0x77777777, 0x10321032),
1325         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2_PIPE_STEER_1, 0x77777777, 0x02310231),
1326         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
1327         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
1328         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CGTT_SCLK_CTRL, 0xffff0fff, 0x10000100),
1329         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL2, 0xffffffff, 0x1402002f),
1330         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xffffbfff, 0x00000188),
1331         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_0, 0xffffffff, 0x842a4c02),
1332         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
1333         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x08000009),
1334         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04440000),
1335         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0x00000820, 0x00000820),
1336         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
1337         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_SPARE, 0xffffffff, 0xffff3101),
1338         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ALU_CLK_CTRL, 0xffffffff, 0xffffffff),
1339         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_ARB_CONFIG, 0x00000133, 0x00000130),
1340         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_LDS_CLK_CTRL, 0xffffffff, 0xffffffff),
1341         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
1342         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CNTL, 0xffdf80ff, 0x479c0010),
1343         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffffffff, 0x00800000)
1344 };
1345
1346 static void gfx_v10_rlcg_wreg(struct amdgpu_device *adev, u32 offset, u32 v)
1347 {
1348         static void *scratch_reg0;
1349         static void *scratch_reg1;
1350         static void *scratch_reg2;
1351         static void *scratch_reg3;
1352         static void *spare_int;
1353         static uint32_t grbm_cntl;
1354         static uint32_t grbm_idx;
1355         uint32_t i = 0;
1356         uint32_t retries = 50000;
1357
1358         scratch_reg0 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG0_BASE_IDX] + mmSCRATCH_REG0)*4;
1359         scratch_reg1 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG1)*4;
1360         scratch_reg2 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG2)*4;
1361         scratch_reg3 = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmSCRATCH_REG1_BASE_IDX] + mmSCRATCH_REG3)*4;
1362         spare_int = adev->rmmio + (adev->reg_offset[GC_HWIP][0][mmRLC_SPARE_INT_BASE_IDX] + mmRLC_SPARE_INT)*4;
1363
1364         grbm_cntl = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_CNTL_BASE_IDX] + mmGRBM_GFX_CNTL;
1365         grbm_idx = adev->reg_offset[GC_HWIP][0][mmGRBM_GFX_INDEX_BASE_IDX] + mmGRBM_GFX_INDEX;
1366
1367         if (amdgpu_sriov_runtime(adev)) {
1368                 pr_err("shouldn't call rlcg write register during runtime\n");
1369                 return;
1370         }
1371
1372         writel(v, scratch_reg0);
1373         writel(offset | 0x80000000, scratch_reg1);
1374         writel(1, spare_int);
1375         for (i = 0; i < retries; i++) {
1376                 u32 tmp;
1377
1378                 tmp = readl(scratch_reg1);
1379                 if (!(tmp & 0x80000000))
1380                         break;
1381
1382                 udelay(10);
1383         }
1384
1385         if (i >= retries)
1386                 pr_err("timeout: rlcg program reg:0x%05x failed !\n", offset);
1387 }
1388
1389 static const struct soc15_reg_golden golden_settings_gc_10_1_nv14[] =
1390 {
1391         /* Pending on emulation bring up */
1392 };
1393
1394 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_nv14[] =
1395 {
1396         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xE0000000L, 0x0),
1397         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1398         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
1399         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1400         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1401         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1402         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
1403         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1404         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1405         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1406         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
1407         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1408         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
1409         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1410         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
1411         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1412         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1413         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1414         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
1415         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1416         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1417         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1418         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
1419         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1420         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1421         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1422         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
1423         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1424         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1425         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1426         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1427         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1428         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1429         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1430         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1431         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1432         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1433         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1434         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1435         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1436         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1437         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1438         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
1439         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1440         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1441         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1442         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1443         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1444         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1445         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1446         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
1447         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1448         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1449         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1450         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
1451         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1452         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1453         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1454         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
1455         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1456         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1457         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1458         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
1459         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1460         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1461         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1462         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
1463         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1464         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1465         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1466         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
1467         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1468         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1469         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1470         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
1471         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1472         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1473         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1474         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
1475         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1476         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1477         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1478         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
1479         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1480         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1481         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1482         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
1483         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1484         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1485         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1486         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
1487         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1488         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1489         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1490         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
1491         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1492         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1493         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1494         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
1495         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1496         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1497         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1498         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
1499         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1500         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1501         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1502         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
1503         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1504         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1505         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1506         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
1507         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1508         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1509         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1510         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
1511         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1512         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1513         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1514         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
1515         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1516         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1517         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1518         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
1519         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1520         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1521         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1522         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
1523         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1524         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
1525         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1526         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
1527         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1528         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
1529         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1530         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
1531         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1532         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
1533         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1534         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
1535         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1536         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
1537         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1538         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
1539         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1540         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1541         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1542         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
1543         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1544         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1545         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1546         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
1547         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1548         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1549         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1550         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
1551         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1552         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1553         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1554         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
1555         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1556         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1557         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1558         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
1559         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1560         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1561         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1562         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
1563         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1564         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1565         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1566         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
1567         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1568         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1569         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1570         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
1571         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1572         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1573         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1574         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
1575         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1576         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
1577         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1578         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
1579         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1580         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1581         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1582         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
1583         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1584         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1585         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1586         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
1587         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1588         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1589         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1590         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
1591         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1592         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1593         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1594         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
1595         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1596         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1597         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1598         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
1599         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1600         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1601         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1602         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
1603         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1604         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1605         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1606         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
1607         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1608         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1609         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1610         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
1611         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1612         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1e),
1613         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1614         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
1615         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1616         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1617         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1618         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
1619         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1620         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1621         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1622         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
1623         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1624         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1625         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1626         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
1627         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1628         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1629         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1630         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
1631         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1632         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1633         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1634         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
1635         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1636         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1637         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1638         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
1639         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1640         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1641         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1642         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
1643         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1644         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1645         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1646         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
1647         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1648         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1649         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1650         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
1651         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1652         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1653         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1654         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
1655         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1656         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1657         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1658         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
1659         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1660         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1661         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1662         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
1663         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1664         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1665         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1666         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
1667         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1668         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1669         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1670         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
1671         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1672         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1673         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1674         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
1675         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1676         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1677         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1678         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
1679         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1680         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1681         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1682         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
1683         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1684         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1685         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1686         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
1687         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1688         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1689         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1690         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
1691         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1692         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1693         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1694         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
1695         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1696         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1697         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1698         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
1699         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1700         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1701         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1702         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
1703         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1704         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1705         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1706         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
1707         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1708         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
1709         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1710         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
1711         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1712         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1713         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1714         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
1715         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1716         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1717         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1718         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
1719         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1720         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1721         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1722         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
1723         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1724         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1725         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1726         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
1727         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1728         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1729         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1730         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
1731         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1732         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1733         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1734         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
1735         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1736         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1737         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1738         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
1739         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1740         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1741         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1742         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
1743         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1744         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1745         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1746         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
1747         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1748         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1749         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1750         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
1751         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1752         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1753         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1754         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
1755         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1756         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1757         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1758         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe4),
1759         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1760         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1761         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1762         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
1763         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1764         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1765         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1766         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
1767         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1768         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1769         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1770         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
1771         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1772         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1773         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1774         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
1775         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1776         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1777         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1778         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
1779         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1780         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1781         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1782         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
1783         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1784         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1785         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1786         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
1787         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1788         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1789         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1790         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
1791         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1792         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1793         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1794         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
1795         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1796         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
1797         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1798         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
1799         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1800         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1801         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1802         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
1803         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1804         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1805         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1806         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
1807         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1808         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1809         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1810         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
1811         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1812         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1813         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1814         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
1815         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1816         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1817         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1818         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
1819         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1820         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1821         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1822         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
1823         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1824         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1825         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1826         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
1827         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1828         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1829         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1830         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
1831         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1832         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
1833         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1834         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
1835         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1836         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
1837         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1838         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
1839         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1840         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1841         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1842         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
1843         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1844         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1845         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1846         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
1847         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1848         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1849         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1850         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
1851         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1852         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1853         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1854         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
1855         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1856         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1857         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1858         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
1859         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1860         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1861         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1862         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
1863         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1864         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1865         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1866         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
1867         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1868         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1869         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1870         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
1871         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1872         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1873         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1874         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
1875         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1876         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1877         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1878         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
1879         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1880         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1881         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1882         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
1883         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1884         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1885         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1886         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
1887         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1888         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1889         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1890         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
1891         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1892         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1893         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1894         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
1895         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1896         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1897         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1898         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
1899         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1900         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
1901         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1902         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
1903         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1904         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
1905         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1906         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
1907         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1908         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
1909         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1910         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
1911         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1912         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1913         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1914         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
1915         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1916         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1917         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1918         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
1919         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1920         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
1921         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1922         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
1923         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1924         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1925         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1926         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
1927         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1928         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
1929         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1930         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
1931         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1932         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
1933         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1934         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a0),
1935         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1936         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1937         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1938         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a4),
1939         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1940         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1941         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1942         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b0),
1943         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1944         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1945         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1946         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b4),
1947         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1948         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
1949         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1950         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1a8),
1951         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1952         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1953         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1954         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1ac),
1955         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1956         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1957         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1958         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1b8),
1959         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1960         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1961         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1962         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1bc),
1963         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1964         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1965         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1966         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c8),
1967         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1968         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
1969         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1970         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1cc),
1971         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1972         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1973         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1974         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c0),
1975         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1976         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
1977         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1978         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c4),
1979         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1980         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
1981         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1982         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
1983         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1984         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1985         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1986         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
1987         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1988         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
1989         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1990         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
1991         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1992         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1993         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1994         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
1995         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1996         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x20),
1997         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
1998         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
1999         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2000         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2001         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2002         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x26),
2003         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2004         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x28),
2005         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2006         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0xf),
2007         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2008         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x15),
2009         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2010         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x1f),
2011         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2012         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x25),
2013         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2014         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x3b),
2015         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
2016 };
2017
2018 static const struct soc15_reg_golden golden_settings_gc_10_1_2_nv12[] =
2019 {
2020         /* Pending on emulation bring up */
2021 };
2022
2023 static const struct soc15_reg_golden golden_settings_gc_rlc_spm_10_1_2_nv12[] =
2024 {
2025         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000L, 0x0),
2026         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2027         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
2028         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2029         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2030         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2031         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
2032         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2033         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2034         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2035         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
2036         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2037         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2038         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2039         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
2040         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2041         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2042         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2043         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
2044         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2045         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2046         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2047         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
2048         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2049         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2050         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2051         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
2052         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2053         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2054         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2055         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2056         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2057         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2058         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2059         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2060         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2061         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2062         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2063         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2064         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2065         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2066         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2067         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
2068         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2069         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2070         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2071         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8),
2072         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2073         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2074         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2075         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
2076         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2077         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2078         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2079         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2080         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2081         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2082         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2083         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2084         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2085         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2086         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2087         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2088         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2089         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2090         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2091         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2092         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2093         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
2094         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2095         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2096         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2097         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2098         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2099         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2100         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2101         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2102         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2103         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2104         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2105         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2106         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2107         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2108         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2109         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2110         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2111         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2112         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2113         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2114         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2115         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2116         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2117         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2118         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2119         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2120         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2121         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x2),
2122         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2123         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2124         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2125         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
2126         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2127         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2128         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2129         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2130         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2131         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2132         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2133         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2134         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2135         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2136         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2137         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1),
2138         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2139         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2140         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2141         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2142         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2143         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2144         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2145         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2146         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2147         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2148         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2149         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2150         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2151         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2152         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2153         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2154         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2155         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc),
2156         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2157         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2158         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2159         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2160         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2161         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2162         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2163         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2164         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2165         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2166         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2167         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2168         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2169         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2170         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2171         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2172         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2173         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2174         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2175         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2176         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2177         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2178         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2179         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2180         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2181         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2182         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2183         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2184         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2185         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2186         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2187         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2188         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2189         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
2190         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2191         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2192         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2193         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2194         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2195         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2196         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2197         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x8),
2198         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2199         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2200         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2201         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2202         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2203         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2204         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2205         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2206         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2207         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2208         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2209         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2210         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2211         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2212         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2213         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2214         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2215         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2216         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2217         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
2218         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2219         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2220         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2221         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2222         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2223         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2224         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2225         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2226         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2227         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2228         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2229         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
2230         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2231         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2232         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2233         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2234         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2235         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2236         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2237         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2238         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2239         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2240         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2241         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2242         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2243         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x1c),
2244         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2245         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x3),
2246         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2247         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2248         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2249         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2250         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2251         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
2252         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2253         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
2254         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2255         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x20),
2256         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2257         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1c),
2258         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2259         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2260         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2261         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2262         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2263         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x24),
2264         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2265         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2266         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2267         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
2268         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2269         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2270         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2271         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x28),
2272         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2273         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2274         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2275         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
2276         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2277         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2278         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2279         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
2280         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2281         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2282         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2283         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
2284         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2285         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
2286         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2287         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
2288         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2289         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
2290         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2291         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
2292         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2293         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2294         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2295         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
2296         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2297         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2298         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2299         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2300         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2301         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2302         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2303         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x38),
2304         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2305         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2306         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2307         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2308         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2309         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2310         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2311         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x3c),
2312         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2313         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2314         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2315         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2316         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2317         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2318         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2319         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18),
2320         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2321         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x18),
2322         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2323         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2324         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2325         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2326         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2327         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x50),
2328         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2329         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2330         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2331         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2332         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2333         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2334         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2335         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x54),
2336         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2337         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2338         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2339         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2340         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2341         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2342         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2343         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x58),
2344         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2345         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2346         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2347         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2348         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2349         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2350         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2351         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x5c),
2352         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2353         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2354         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2355         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2356         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2357         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2358         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2359         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14),
2360         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2361         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2362         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2363         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2364         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2365         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2366         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2367         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x48),
2368         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2369         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2370         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2371         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2372         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2373         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2374         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2375         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4c),
2376         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2377         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2378         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2379         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2380         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2381         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2382         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2383         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x40),
2384         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2385         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2386         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2387         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2388         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2389         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2390         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2391         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x44),
2392         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2393         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1a),
2394         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2395         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2396         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2397         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2398         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2399         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10),
2400         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2401         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2402         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2403         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2404         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2405         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2406         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2407         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x60),
2408         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2409         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2410         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2411         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2412         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2413         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2414         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2415         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x64),
2416         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2417         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2418         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2419         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2420         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2421         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2422         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2423         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x70),
2424         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2425         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2426         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2427         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2428         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2429         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2430         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2431         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x74),
2432         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2433         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2434         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2435         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2436         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2437         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2438         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2439         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x68),
2440         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2441         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2442         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2443         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2444         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2445         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2446         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2447         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x6c),
2448         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2449         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2450         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2451         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2452         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2453         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2454         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2455         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x78),
2456         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2457         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2458         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2459         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2460         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2461         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2462         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2463         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x7c),
2464         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2465         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2466         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2467         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2468         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2469         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2470         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2471         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x88),
2472         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2473         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2474         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2475         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2476         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2477         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2478         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2479         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x8c),
2480         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2481         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2482         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2483         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2484         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2485         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2486         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2487         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x80),
2488         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2489         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2490         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2491         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2492         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2493         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2494         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2495         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x84),
2496         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2497         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2498         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2499         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2500         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2501         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2502         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2503         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x90),
2504         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2505         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2506         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2507         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2508         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2509         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2510         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2511         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x94),
2512         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2513         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2514         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2515         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2516         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2517         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2518         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2519         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa0),
2520         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2521         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2522         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2523         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2524         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2525         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2526         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2527         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa4),
2528         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2529         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2530         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2531         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2532         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2533         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2534         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2535         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x98),
2536         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2537         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2538         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2539         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2540         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2541         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2542         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2543         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x9c),
2544         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2545         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x4),
2546         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2547         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2548         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2549         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2550         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2551         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xa8),
2552         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2553         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2554         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2555         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2556         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2557         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2558         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2559         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xac),
2560         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2561         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2562         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2563         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2564         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2565         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2566         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2567         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb8),
2568         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2569         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2570         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2571         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2572         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2573         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2574         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2575         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xbc),
2576         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2577         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2578         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2579         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2580         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2581         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2582         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2583         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb0),
2584         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2585         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2586         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2587         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2588         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2589         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2590         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2591         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xb4),
2592         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2593         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2594         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2595         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2596         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2597         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2598         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2599         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc0),
2600         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2601         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2602         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2603         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2604         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2605         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2606         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2607         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc4),
2608         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2609         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2610         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2611         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
2612         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2613         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2614         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2615         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd0),
2616         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2617         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2618         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2619         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2620         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2621         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2622         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2623         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd4),
2624         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2625         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2626         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2627         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
2628         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2629         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2630         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2631         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xc8),
2632         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2633         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2634         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2635         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
2636         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2637         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2638         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2639         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xcc),
2640         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2641         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
2642         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2643         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
2644         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2645         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2646         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2647         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe8),
2648         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2649         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2650         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2651         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
2652         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2653         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2654         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2655         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xec),
2656         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2657         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x16),
2658         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2659         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
2660         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2661         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2662         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2663         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf0),
2664         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2665         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2666         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2667         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
2668         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2669         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2670         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2671         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf4),
2672         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2673         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2674         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2675         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
2676         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2677         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2678         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2679         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xf8),
2680         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2681         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2682         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2683         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
2684         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2685         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
2686         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2687         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xfc),
2688         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2689         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x17),
2690         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2691         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
2692         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2693         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2694         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2695         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x100),
2696         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2697         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x13),
2698         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2699         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
2700         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2701         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2702         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2703         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x104),
2704         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2705         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
2706         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2707         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
2708         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2709         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2710         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2711         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xe0),
2712         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2713         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2714         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2715         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
2716         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2717         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2718         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2719         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x118),
2720         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2721         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2722         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2723         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
2724         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2725         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2726         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2727         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x11c),
2728         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2729         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2730         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2731         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
2732         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2733         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2734         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2735         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x120),
2736         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2737         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2738         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2739         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
2740         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2741         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2742         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2743         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x124),
2744         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2745         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2746         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2747         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
2748         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2749         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2750         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2751         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xdc),
2752         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2753         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2754         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2755         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
2756         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2757         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2758         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2759         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x110),
2760         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2761         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x15),
2762         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2763         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
2764         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2765         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2766         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2767         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x114),
2768         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2769         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x14),
2770         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2771         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
2772         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2773         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2774         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2775         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x108),
2776         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2777         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2778         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2779         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
2780         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2781         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2782         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2783         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x10c),
2784         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2785         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x19),
2786         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2787         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
2788         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2789         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2790         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2791         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0xd8),
2792         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2793         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1b),
2794         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2795         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
2796         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2797         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2798         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2799         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x128),
2800         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2801         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2802         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2803         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
2804         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2805         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2806         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2807         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x12c),
2808         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2809         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2810         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2811         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
2812         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2813         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2814         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2815         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x138),
2816         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2817         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2818         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2819         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
2820         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2821         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2822         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2823         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x13c),
2824         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2825         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2826         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2827         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
2828         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2829         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2830         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2831         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x130),
2832         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2833         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x12),
2834         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2835         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
2836         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2837         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
2838         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2839         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x134),
2840         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2841         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xf),
2842         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2843         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
2844         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2845         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2846         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2847         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x140),
2848         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2849         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2850         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2851         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
2852         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2853         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2854         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2855         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x144),
2856         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2857         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2858         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2859         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
2860         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2861         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2862         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2863         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x150),
2864         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2865         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2866         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2867         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
2868         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2869         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2870         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2871         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x154),
2872         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2873         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
2874         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2875         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
2876         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2877         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2878         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2879         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x148),
2880         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2881         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2882         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2883         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
2884         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2885         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2886         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2887         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x14c),
2888         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2889         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x7),
2890         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2891         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
2892         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2893         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2894         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2895         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x158),
2896         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2897         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2898         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2899         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
2900         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2901         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2902         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2903         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x15c),
2904         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2905         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2906         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2907         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
2908         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2909         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2910         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2911         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x168),
2912         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2913         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xa),
2914         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2915         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
2916         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2917         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2918         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2919         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x16c),
2920         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2921         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x9),
2922         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2923         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
2924         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2925         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2926         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2927         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x160),
2928         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2929         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2930         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2931         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
2932         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2933         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2934         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2935         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x164),
2936         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2937         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x0),
2938         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2939         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
2940         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2941         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2942         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2943         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x170),
2944         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2945         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2946         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2947         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
2948         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2949         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2950         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2951         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x174),
2952         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2953         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2954         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2955         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
2956         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2957         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2958         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2959         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x180),
2960         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2961         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2962         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2963         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
2964         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2965         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2966         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2967         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x184),
2968         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2969         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2970         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2971         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
2972         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2973         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2974         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2975         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x178),
2976         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2977         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x10),
2978         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2979         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
2980         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2981         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2982         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2983         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x17c),
2984         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2985         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2986         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2987         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
2988         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2989         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2990         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2991         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x188),
2992         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2993         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
2994         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2995         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
2996         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
2997         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
2998         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
2999         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x18c),
3000         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3001         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x5),
3002         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3003         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
3004         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3005         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
3006         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3007         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x198),
3008         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3009         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xc),
3010         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3011         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
3012         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3013         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
3014         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3015         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x19c),
3016         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3017         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
3018         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3019         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
3020         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3021         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3022         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3023         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x190),
3024         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3025         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xe),
3026         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3027         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
3028         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3029         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
3030         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3031         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x194),
3032         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3033         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x6),
3034         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3035         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x30),
3036         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3037         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xd),
3038         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3039         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x34),
3040         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3041         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x11),
3042         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3043         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
3044         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3045         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
3046         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3047         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x0),
3048         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3049         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1d),
3050         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3051         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
3052         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3053         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
3054         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3055         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x4),
3056         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3057         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0x1f),
3058         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3059         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_ADDR, 0xFFFFFFFF, 0x2c),
3060         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3061         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLB_SAMPLEDELAY_IND_DATA, 0xFFFFFFFF, 0xb),
3062         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3063         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_SAMPLE_SKEW, 0x000000FF, 0x1f),
3064         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3065         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_GLOBALS_MUXSEL_SKEW, 0x000000FF, 0x22),
3066         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3067         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x1),
3068         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3069         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_SAMPLE_SKEW, 0x000000FF, 0x6),
3070         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3071         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x10),
3072         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x10000),
3073         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_SE_MUXSEL_SKEW, 0x000000FF, 0x15),
3074         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xffffff, 0x0),
3075         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_DESER_START_SKEW, 0x000000FF, 0x35),
3076         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_GFX_INDEX, 0xFFFFFFFF, 0xe0000000)
3077 };
3078
3079 static const struct soc15_reg_golden golden_settings_gc_10_3[] =
3080 {
3081         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3082         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),
3083         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100),
3084         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3085         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3086         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3087         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000),
3088         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500),
3089         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400),
3090         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3091         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3092         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3093         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x10f80988),
3094         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3095         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3096         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3097         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104),
3098         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070),
3099         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3100         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3101         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3102         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3103         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3104         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3105         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3106         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3107         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3108         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3109         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3110         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3111         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3112         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3113         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3114         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3115         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3116         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000)
3117 };
3118
3119 static const struct soc15_reg_golden golden_settings_gc_10_3_sienna_cichlid[] =
3120 {
3121         /* Pending on emulation bring up */
3122 };
3123
3124 static const struct soc15_reg_golden golden_settings_gc_10_3_2[] =
3125 {
3126         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_PS_CLK_CTRL, 0xff7f0fff, 0x78000100),
3127         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA0_CLK_CTRL, 0xff7f0fff, 0x30000100),
3128         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCGTT_SPI_RA1_CLK_CTRL, 0xff7f0fff, 0x7e000100),
3129         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
3130         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0xffffffff, 0x00000280),
3131         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0xffffffff, 0x00800000),
3132         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_EXCEPTION_CONTROL, 0x7fff0f1f, 0x00b80000),
3133         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x1ff1ffff, 0x00000500),
3134         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003fffff, 0x00280400),
3135         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3136         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
3137         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CM_CTRL1, 0xff8fff0f, 0x580f1008),
3138         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_CTRL3, 0xf7ffffff, 0x00f80988),
3139         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_CL_ENHANCE, 0xf17fffff, 0x01200007),
3140         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_TIMEOUT_COUNTER, 0xffffffff, 0x00000800),
3141         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_2, 0xffffffbf, 0x00000820),
3142         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffffffff, 0x00070104),
3143         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_START_PHASE, 0x000000ff, 0x00000004),
3144         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_CONFIG, 0xe07df47f, 0x00180070),
3145         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER0_SELECT, 0xf0f001ff, 0x00000000),
3146         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER1_SELECT, 0xf0f001ff, 0x00000000),
3147         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER10_SELECT, 0xf0f001ff, 0x00000000),
3148         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER11_SELECT, 0xf0f001ff, 0x00000000),
3149         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER12_SELECT, 0xf0f001ff, 0x00000000),
3150         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER13_SELECT, 0xf0f001ff, 0x00000000),
3151         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER14_SELECT, 0xf0f001ff, 0x00000000),
3152         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER15_SELECT, 0xf0f001ff, 0x00000000),
3153         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER2_SELECT, 0xf0f001ff, 0x00000000),
3154         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER3_SELECT, 0xf0f001ff, 0x00000000),
3155         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER4_SELECT, 0xf0f001ff, 0x00000000),
3156         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER5_SELECT, 0xf0f001ff, 0x00000000),
3157         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER6_SELECT, 0xf0f001ff, 0x00000000),
3158         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER7_SELECT, 0xf0f001ff, 0x00000000),
3159         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER8_SELECT, 0xf0f001ff, 0x00000000),
3160         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQ_PERFCOUNTER9_SELECT, 0xf0f001ff, 0x00000000),
3161         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfff7ffff, 0x01030000),
3162         SOC15_REG_GOLDEN_VALUE(GC, 0, mmUTCL1_CTRL, 0xffbfffff, 0x00a00000),
3163         SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff)
3164 };
3165
3166 #define DEFAULT_SH_MEM_CONFIG \
3167         ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \
3168          (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \
3169          (SH_MEM_RETRY_MODE_ALL << SH_MEM_CONFIG__RETRY_MODE__SHIFT) | \
3170          (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT))
3171
3172
3173 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev);
3174 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev);
3175 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev);
3176 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev);
3177 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,
3178                                  struct amdgpu_cu_info *cu_info);
3179 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev);
3180 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
3181                                    u32 sh_num, u32 instance);
3182 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev);
3183
3184 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev);
3185 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev);
3186 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev);
3187 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev);
3188 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume);
3189 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume);
3190 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, bool secure);
3191
3192 static void gfx10_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask)
3193 {
3194         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));
3195         amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) |
3196                           PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */
3197         amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */
3198         amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */
3199         amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */
3200         amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */
3201         amdgpu_ring_write(kiq_ring, 0); /* oac mask */
3202         amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */
3203 }
3204
3205 static void gfx10_kiq_map_queues(struct amdgpu_ring *kiq_ring,
3206                                  struct amdgpu_ring *ring)
3207 {
3208         struct amdgpu_device *adev = kiq_ring->adev;
3209         uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
3210         uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
3211         uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
3212
3213         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
3214         /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/
3215         amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3216                           PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */
3217                           PACKET3_MAP_QUEUES_VMID(0) | /* VMID */
3218                           PACKET3_MAP_QUEUES_QUEUE(ring->queue) |
3219                           PACKET3_MAP_QUEUES_PIPE(ring->pipe) |
3220                           PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) |
3221                           PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */
3222                           PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */
3223                           PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) |
3224                           PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */
3225         amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index));
3226         amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr));
3227         amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr));
3228         amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr));
3229         amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));
3230 }
3231
3232 static void gfx10_kiq_unmap_queues(struct amdgpu_ring *kiq_ring,
3233                                    struct amdgpu_ring *ring,
3234                                    enum amdgpu_unmap_queues_action action,
3235                                    u64 gpu_addr, u64 seq)
3236 {
3237         uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
3238
3239         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));
3240         amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3241                           PACKET3_UNMAP_QUEUES_ACTION(action) |
3242                           PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) |
3243                           PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) |
3244                           PACKET3_UNMAP_QUEUES_NUM_QUEUES(1));
3245         amdgpu_ring_write(kiq_ring,
3246                   PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index));
3247
3248         if (action == PREEMPT_QUEUES_NO_UNMAP) {
3249                 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr));
3250                 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr));
3251                 amdgpu_ring_write(kiq_ring, seq);
3252         } else {
3253                 amdgpu_ring_write(kiq_ring, 0);
3254                 amdgpu_ring_write(kiq_ring, 0);
3255                 amdgpu_ring_write(kiq_ring, 0);
3256         }
3257 }
3258
3259 static void gfx10_kiq_query_status(struct amdgpu_ring *kiq_ring,
3260                                    struct amdgpu_ring *ring,
3261                                    u64 addr,
3262                                    u64 seq)
3263 {
3264         uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
3265
3266         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5));
3267         amdgpu_ring_write(kiq_ring,
3268                           PACKET3_QUERY_STATUS_CONTEXT_ID(0) |
3269                           PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) |
3270                           PACKET3_QUERY_STATUS_COMMAND(2));
3271         amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3272                           PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) |
3273                           PACKET3_QUERY_STATUS_ENG_SEL(eng_sel));
3274         amdgpu_ring_write(kiq_ring, lower_32_bits(addr));
3275         amdgpu_ring_write(kiq_ring, upper_32_bits(addr));
3276         amdgpu_ring_write(kiq_ring, lower_32_bits(seq));
3277         amdgpu_ring_write(kiq_ring, upper_32_bits(seq));
3278 }
3279
3280 static void gfx10_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring,
3281                                 uint16_t pasid, uint32_t flush_type,
3282                                 bool all_hub)
3283 {
3284         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0));
3285         amdgpu_ring_write(kiq_ring,
3286                         PACKET3_INVALIDATE_TLBS_DST_SEL(1) |
3287                         PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) |
3288                         PACKET3_INVALIDATE_TLBS_PASID(pasid) |
3289                         PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type));
3290 }
3291
3292 static const struct kiq_pm4_funcs gfx_v10_0_kiq_pm4_funcs = {
3293         .kiq_set_resources = gfx10_kiq_set_resources,
3294         .kiq_map_queues = gfx10_kiq_map_queues,
3295         .kiq_unmap_queues = gfx10_kiq_unmap_queues,
3296         .kiq_query_status = gfx10_kiq_query_status,
3297         .kiq_invalidate_tlbs = gfx10_kiq_invalidate_tlbs,
3298         .set_resources_size = 8,
3299         .map_queues_size = 7,
3300         .unmap_queues_size = 6,
3301         .query_status_size = 7,
3302         .invalidate_tlbs_size = 2,
3303 };
3304
3305 static void gfx_v10_0_set_kiq_pm4_funcs(struct amdgpu_device *adev)
3306 {
3307         adev->gfx.kiq.pmf = &gfx_v10_0_kiq_pm4_funcs;
3308 }
3309
3310 static void gfx_v10_0_init_spm_golden_registers(struct amdgpu_device *adev)
3311 {
3312         switch (adev->asic_type) {
3313         case CHIP_NAVI10:
3314                 soc15_program_register_sequence(adev,
3315                                                 golden_settings_gc_rlc_spm_10_0_nv10,
3316                                                 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_0_nv10));
3317                 break;
3318         case CHIP_NAVI14:
3319                 soc15_program_register_sequence(adev,
3320                                                 golden_settings_gc_rlc_spm_10_1_nv14,
3321                                                 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_nv14));
3322                 break;
3323         case CHIP_NAVI12:
3324                 soc15_program_register_sequence(adev,
3325                                                 golden_settings_gc_rlc_spm_10_1_2_nv12,
3326                                                 (const u32)ARRAY_SIZE(golden_settings_gc_rlc_spm_10_1_2_nv12));
3327                 break;
3328         default:
3329                 break;
3330         }
3331 }
3332
3333 static void gfx_v10_0_init_golden_registers(struct amdgpu_device *adev)
3334 {
3335         switch (adev->asic_type) {
3336         case CHIP_NAVI10:
3337                 soc15_program_register_sequence(adev,
3338                                                 golden_settings_gc_10_1,
3339                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1));
3340                 soc15_program_register_sequence(adev,
3341                                                 golden_settings_gc_10_0_nv10,
3342                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_0_nv10));
3343                 break;
3344         case CHIP_NAVI14:
3345                 soc15_program_register_sequence(adev,
3346                                                 golden_settings_gc_10_1_1,
3347                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_1));
3348                 soc15_program_register_sequence(adev,
3349                                                 golden_settings_gc_10_1_nv14,
3350                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_nv14));
3351                 break;
3352         case CHIP_NAVI12:
3353                 soc15_program_register_sequence(adev,
3354                                                 golden_settings_gc_10_1_2,
3355                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2));
3356                 soc15_program_register_sequence(adev,
3357                                                 golden_settings_gc_10_1_2_nv12,
3358                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_1_2_nv12));
3359                 break;
3360         case CHIP_SIENNA_CICHLID:
3361                 soc15_program_register_sequence(adev,
3362                                                 golden_settings_gc_10_3,
3363                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3));
3364                 soc15_program_register_sequence(adev,
3365                                                 golden_settings_gc_10_3_sienna_cichlid,
3366                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_sienna_cichlid));
3367                 break;
3368         case CHIP_NAVY_FLOUNDER:
3369                 soc15_program_register_sequence(adev,
3370                                                 golden_settings_gc_10_3_2,
3371                                                 (const u32)ARRAY_SIZE(golden_settings_gc_10_3_2));
3372                 break;
3373
3374         default:
3375                 break;
3376         }
3377         gfx_v10_0_init_spm_golden_registers(adev);
3378 }
3379
3380 static void gfx_v10_0_scratch_init(struct amdgpu_device *adev)
3381 {
3382         adev->gfx.scratch.num_reg = 8;
3383         adev->gfx.scratch.reg_base = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);
3384         adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1;
3385 }
3386
3387 static void gfx_v10_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel,
3388                                        bool wc, uint32_t reg, uint32_t val)
3389 {
3390         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
3391         amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) |
3392                           WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0));
3393         amdgpu_ring_write(ring, reg);
3394         amdgpu_ring_write(ring, 0);
3395         amdgpu_ring_write(ring, val);
3396 }
3397
3398 static void gfx_v10_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,
3399                                   int mem_space, int opt, uint32_t addr0,
3400                                   uint32_t addr1, uint32_t ref, uint32_t mask,
3401                                   uint32_t inv)
3402 {
3403         amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
3404         amdgpu_ring_write(ring,
3405                           /* memory (1) or register (0) */
3406                           (WAIT_REG_MEM_MEM_SPACE(mem_space) |
3407                            WAIT_REG_MEM_OPERATION(opt) | /* wait */
3408                            WAIT_REG_MEM_FUNCTION(3) |  /* equal */
3409                            WAIT_REG_MEM_ENGINE(eng_sel)));
3410
3411         if (mem_space)
3412                 BUG_ON(addr0 & 0x3); /* Dword align */
3413         amdgpu_ring_write(ring, addr0);
3414         amdgpu_ring_write(ring, addr1);
3415         amdgpu_ring_write(ring, ref);
3416         amdgpu_ring_write(ring, mask);
3417         amdgpu_ring_write(ring, inv); /* poll interval */
3418 }
3419
3420 static int gfx_v10_0_ring_test_ring(struct amdgpu_ring *ring)
3421 {
3422         struct amdgpu_device *adev = ring->adev;
3423         uint32_t scratch;
3424         uint32_t tmp = 0;
3425         unsigned i;
3426         int r;
3427
3428         r = amdgpu_gfx_scratch_get(adev, &scratch);
3429         if (r) {
3430                 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r);
3431                 return r;
3432         }
3433
3434         WREG32(scratch, 0xCAFEDEAD);
3435
3436         r = amdgpu_ring_alloc(ring, 3);
3437         if (r) {
3438                 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
3439                           ring->idx, r);
3440                 amdgpu_gfx_scratch_free(adev, scratch);
3441                 return r;
3442         }
3443
3444         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
3445         amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
3446         amdgpu_ring_write(ring, 0xDEADBEEF);
3447         amdgpu_ring_commit(ring);
3448
3449         for (i = 0; i < adev->usec_timeout; i++) {
3450                 tmp = RREG32(scratch);
3451                 if (tmp == 0xDEADBEEF)
3452                         break;
3453                 if (amdgpu_emu_mode == 1)
3454                         msleep(1);
3455                 else
3456                         udelay(1);
3457         }
3458
3459         if (i >= adev->usec_timeout)
3460                 r = -ETIMEDOUT;
3461
3462         amdgpu_gfx_scratch_free(adev, scratch);
3463
3464         return r;
3465 }
3466
3467 static int gfx_v10_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
3468 {
3469         struct amdgpu_device *adev = ring->adev;
3470         struct amdgpu_ib ib;
3471         struct dma_fence *f = NULL;
3472         unsigned index;
3473         uint64_t gpu_addr;
3474         uint32_t tmp;
3475         long r;
3476
3477         r = amdgpu_device_wb_get(adev, &index);
3478         if (r)
3479                 return r;
3480
3481         gpu_addr = adev->wb.gpu_addr + (index * 4);
3482         adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD);
3483         memset(&ib, 0, sizeof(ib));
3484         r = amdgpu_ib_get(adev, NULL, 16,
3485                                         AMDGPU_IB_POOL_DIRECT, &ib);
3486         if (r)
3487                 goto err1;
3488
3489         ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3);
3490         ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
3491         ib.ptr[2] = lower_32_bits(gpu_addr);
3492         ib.ptr[3] = upper_32_bits(gpu_addr);
3493         ib.ptr[4] = 0xDEADBEEF;
3494         ib.length_dw = 5;
3495
3496         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
3497         if (r)
3498                 goto err2;
3499
3500         r = dma_fence_wait_timeout(f, false, timeout);
3501         if (r == 0) {
3502                 r = -ETIMEDOUT;
3503                 goto err2;
3504         } else if (r < 0) {
3505                 goto err2;
3506         }
3507
3508         tmp = adev->wb.wb[index];
3509         if (tmp == 0xDEADBEEF)
3510                 r = 0;
3511         else
3512                 r = -EINVAL;
3513 err2:
3514         amdgpu_ib_free(adev, &ib, NULL);
3515         dma_fence_put(f);
3516 err1:
3517         amdgpu_device_wb_free(adev, index);
3518         return r;
3519 }
3520
3521 static void gfx_v10_0_free_microcode(struct amdgpu_device *adev)
3522 {
3523         release_firmware(adev->gfx.pfp_fw);
3524         adev->gfx.pfp_fw = NULL;
3525         release_firmware(adev->gfx.me_fw);
3526         adev->gfx.me_fw = NULL;
3527         release_firmware(adev->gfx.ce_fw);
3528         adev->gfx.ce_fw = NULL;
3529         release_firmware(adev->gfx.rlc_fw);
3530         adev->gfx.rlc_fw = NULL;
3531         release_firmware(adev->gfx.mec_fw);
3532         adev->gfx.mec_fw = NULL;
3533         release_firmware(adev->gfx.mec2_fw);
3534         adev->gfx.mec2_fw = NULL;
3535
3536         kfree(adev->gfx.rlc.register_list_format);
3537 }
3538
3539 static void gfx_v10_0_check_fw_write_wait(struct amdgpu_device *adev)
3540 {
3541         adev->gfx.cp_fw_write_wait = false;
3542
3543         switch (adev->asic_type) {
3544         case CHIP_NAVI10:
3545         case CHIP_NAVI12:
3546         case CHIP_NAVI14:
3547                 if ((adev->gfx.me_fw_version >= 0x00000046) &&
3548                     (adev->gfx.me_feature_version >= 27) &&
3549                     (adev->gfx.pfp_fw_version >= 0x00000068) &&
3550                     (adev->gfx.pfp_feature_version >= 27) &&
3551                     (adev->gfx.mec_fw_version >= 0x0000005b) &&
3552                     (adev->gfx.mec_feature_version >= 27))
3553                         adev->gfx.cp_fw_write_wait = true;
3554                 break;
3555         case CHIP_SIENNA_CICHLID:
3556         case CHIP_NAVY_FLOUNDER:
3557                 adev->gfx.cp_fw_write_wait = true;
3558                 break;
3559         default:
3560                 break;
3561         }
3562
3563         if (!adev->gfx.cp_fw_write_wait)
3564                 DRM_WARN_ONCE("CP firmware version too old, please update!");
3565 }
3566
3567
3568 static void gfx_v10_0_init_rlc_ext_microcode(struct amdgpu_device *adev)
3569 {
3570         const struct rlc_firmware_header_v2_1 *rlc_hdr;
3571
3572         rlc_hdr = (const struct rlc_firmware_header_v2_1 *)adev->gfx.rlc_fw->data;
3573         adev->gfx.rlc_srlc_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_ucode_ver);
3574         adev->gfx.rlc_srlc_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_feature_ver);
3575         adev->gfx.rlc.save_restore_list_cntl_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_cntl_size_bytes);
3576         adev->gfx.rlc.save_restore_list_cntl = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_cntl_offset_bytes);
3577         adev->gfx.rlc_srlg_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_ucode_ver);
3578         adev->gfx.rlc_srlg_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_feature_ver);
3579         adev->gfx.rlc.save_restore_list_gpm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_gpm_size_bytes);
3580         adev->gfx.rlc.save_restore_list_gpm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_gpm_offset_bytes);
3581         adev->gfx.rlc_srls_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_ucode_ver);
3582         adev->gfx.rlc_srls_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_feature_ver);
3583         adev->gfx.rlc.save_restore_list_srm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_srm_size_bytes);
3584         adev->gfx.rlc.save_restore_list_srm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_srm_offset_bytes);
3585         adev->gfx.rlc.reg_list_format_direct_reg_list_length =
3586                         le32_to_cpu(rlc_hdr->reg_list_format_direct_reg_list_length);
3587 }
3588
3589 static bool gfx_v10_0_navi10_gfxoff_should_enable(struct amdgpu_device *adev)
3590 {
3591         bool ret = false;
3592
3593         switch (adev->pdev->revision) {
3594         case 0xc2:
3595         case 0xc3:
3596                 ret = true;
3597                 break;
3598         default:
3599                 ret = false;
3600                 break;
3601         }
3602
3603         return ret ;
3604 }
3605
3606 static void gfx_v10_0_check_gfxoff_flag(struct amdgpu_device *adev)
3607 {
3608         switch (adev->asic_type) {
3609         case CHIP_NAVI10:
3610                 if (!gfx_v10_0_navi10_gfxoff_should_enable(adev))
3611                         adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
3612                 break;
3613         case CHIP_NAVY_FLOUNDER:
3614                 adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
3615                 break;
3616         default:
3617                 break;
3618         }
3619 }
3620
3621 static int gfx_v10_0_init_microcode(struct amdgpu_device *adev)
3622 {
3623         const char *chip_name;
3624         char fw_name[40];
3625         char wks[10];
3626         int err;
3627         struct amdgpu_firmware_info *info = NULL;
3628         const struct common_firmware_header *header = NULL;
3629         const struct gfx_firmware_header_v1_0 *cp_hdr;
3630         const struct rlc_firmware_header_v2_0 *rlc_hdr;
3631         unsigned int *tmp = NULL;
3632         unsigned int i = 0;
3633         uint16_t version_major;
3634         uint16_t version_minor;
3635
3636         DRM_DEBUG("\n");
3637
3638         memset(wks, 0, sizeof(wks));
3639         switch (adev->asic_type) {
3640         case CHIP_NAVI10:
3641                 chip_name = "navi10";
3642                 break;
3643         case CHIP_NAVI14:
3644                 chip_name = "navi14";
3645                 if (!(adev->pdev->device == 0x7340 &&
3646                       adev->pdev->revision != 0x00))
3647                         snprintf(wks, sizeof(wks), "_wks");
3648                 break;
3649         case CHIP_NAVI12:
3650                 chip_name = "navi12";
3651                 break;
3652         case CHIP_SIENNA_CICHLID:
3653                 chip_name = "sienna_cichlid";
3654                 break;
3655         case CHIP_NAVY_FLOUNDER:
3656                 chip_name = "navy_flounder";
3657                 break;
3658         default:
3659                 BUG();
3660         }
3661
3662         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp%s.bin", chip_name, wks);
3663         err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
3664         if (err)
3665                 goto out;
3666         err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
3667         if (err)
3668                 goto out;
3669         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
3670         adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
3671         adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
3672
3673         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me%s.bin", chip_name, wks);
3674         err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
3675         if (err)
3676                 goto out;
3677         err = amdgpu_ucode_validate(adev->gfx.me_fw);
3678         if (err)
3679                 goto out;
3680         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
3681         adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
3682         adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
3683
3684         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce%s.bin", chip_name, wks);
3685         err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
3686         if (err)
3687                 goto out;
3688         err = amdgpu_ucode_validate(adev->gfx.ce_fw);
3689         if (err)
3690                 goto out;
3691         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
3692         adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
3693         adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
3694
3695         if (!amdgpu_sriov_vf(adev)) {
3696                 snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
3697                 err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
3698                 if (err)
3699                         goto out;
3700                 err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
3701                 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
3702                 version_major = le16_to_cpu(rlc_hdr->header.header_version_major);
3703                 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor);
3704                 if (version_major == 2 && version_minor == 1)
3705                         adev->gfx.rlc.is_rlc_v2_1 = true;
3706
3707                 adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);
3708                 adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version);
3709                 adev->gfx.rlc.save_and_restore_offset =
3710                         le32_to_cpu(rlc_hdr->save_and_restore_offset);
3711                 adev->gfx.rlc.clear_state_descriptor_offset =
3712                         le32_to_cpu(rlc_hdr->clear_state_descriptor_offset);
3713                 adev->gfx.rlc.avail_scratch_ram_locations =
3714                         le32_to_cpu(rlc_hdr->avail_scratch_ram_locations);
3715                 adev->gfx.rlc.reg_restore_list_size =
3716                         le32_to_cpu(rlc_hdr->reg_restore_list_size);
3717                 adev->gfx.rlc.reg_list_format_start =
3718                         le32_to_cpu(rlc_hdr->reg_list_format_start);
3719                 adev->gfx.rlc.reg_list_format_separate_start =
3720                         le32_to_cpu(rlc_hdr->reg_list_format_separate_start);
3721                 adev->gfx.rlc.starting_offsets_start =
3722                         le32_to_cpu(rlc_hdr->starting_offsets_start);
3723                 adev->gfx.rlc.reg_list_format_size_bytes =
3724                         le32_to_cpu(rlc_hdr->reg_list_format_size_bytes);
3725                 adev->gfx.rlc.reg_list_size_bytes =
3726                         le32_to_cpu(rlc_hdr->reg_list_size_bytes);
3727                 adev->gfx.rlc.register_list_format =
3728                         kmalloc(adev->gfx.rlc.reg_list_format_size_bytes +
3729                                         adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL);
3730                 if (!adev->gfx.rlc.register_list_format) {
3731                         err = -ENOMEM;
3732                         goto out;
3733                 }
3734
3735                 tmp = (unsigned int *)((uintptr_t)rlc_hdr +
3736                                                            le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes));
3737                 for (i = 0 ; i < (rlc_hdr->reg_list_format_size_bytes >> 2); i++)
3738                         adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]);
3739
3740                 adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i;
3741
3742                 tmp = (unsigned int *)((uintptr_t)rlc_hdr +
3743                                                            le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes));
3744                 for (i = 0 ; i < (rlc_hdr->reg_list_size_bytes >> 2); i++)
3745                         adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]);
3746
3747                 if (adev->gfx.rlc.is_rlc_v2_1)
3748                         gfx_v10_0_init_rlc_ext_microcode(adev);
3749         }
3750
3751         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec%s.bin", chip_name, wks);
3752         err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
3753         if (err)
3754                 goto out;
3755         err = amdgpu_ucode_validate(adev->gfx.mec_fw);
3756         if (err)
3757                 goto out;
3758         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
3759         adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
3760         adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
3761
3762         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2%s.bin", chip_name, wks);
3763         err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
3764         if (!err) {
3765                 err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
3766                 if (err)
3767                         goto out;
3768                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
3769                 adev->gfx.mec2_fw->data;
3770                 adev->gfx.mec2_fw_version =
3771                 le32_to_cpu(cp_hdr->header.ucode_version);
3772                 adev->gfx.mec2_feature_version =
3773                 le32_to_cpu(cp_hdr->ucode_feature_version);
3774         } else {
3775                 err = 0;
3776                 adev->gfx.mec2_fw = NULL;
3777         }
3778
3779         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
3780                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP];
3781                 info->ucode_id = AMDGPU_UCODE_ID_CP_PFP;
3782                 info->fw = adev->gfx.pfp_fw;
3783                 header = (const struct common_firmware_header *)info->fw->data;
3784                 adev->firmware.fw_size +=
3785                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
3786
3787                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME];
3788                 info->ucode_id = AMDGPU_UCODE_ID_CP_ME;
3789                 info->fw = adev->gfx.me_fw;
3790                 header = (const struct common_firmware_header *)info->fw->data;
3791                 adev->firmware.fw_size +=
3792                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
3793
3794                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE];
3795                 info->ucode_id = AMDGPU_UCODE_ID_CP_CE;
3796                 info->fw = adev->gfx.ce_fw;
3797                 header = (const struct common_firmware_header *)info->fw->data;
3798                 adev->firmware.fw_size +=
3799                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
3800
3801                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G];
3802                 info->ucode_id = AMDGPU_UCODE_ID_RLC_G;
3803                 info->fw = adev->gfx.rlc_fw;
3804                 if (info->fw) {
3805                         header = (const struct common_firmware_header *)info->fw->data;
3806                         adev->firmware.fw_size +=
3807                                 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
3808                 }
3809                 if (adev->gfx.rlc.is_rlc_v2_1 &&
3810                     adev->gfx.rlc.save_restore_list_cntl_size_bytes &&
3811                     adev->gfx.rlc.save_restore_list_gpm_size_bytes &&
3812                     adev->gfx.rlc.save_restore_list_srm_size_bytes) {
3813                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL];
3814                         info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL;
3815                         info->fw = adev->gfx.rlc_fw;
3816                         adev->firmware.fw_size +=
3817                                 ALIGN(adev->gfx.rlc.save_restore_list_cntl_size_bytes, PAGE_SIZE);
3818
3819                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM];
3820                         info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM;
3821                         info->fw = adev->gfx.rlc_fw;
3822                         adev->firmware.fw_size +=
3823                                 ALIGN(adev->gfx.rlc.save_restore_list_gpm_size_bytes, PAGE_SIZE);
3824
3825                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM];
3826                         info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM;
3827                         info->fw = adev->gfx.rlc_fw;
3828                         adev->firmware.fw_size +=
3829                                 ALIGN(adev->gfx.rlc.save_restore_list_srm_size_bytes, PAGE_SIZE);
3830                 }
3831
3832                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1];
3833                 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1;
3834                 info->fw = adev->gfx.mec_fw;
3835                 header = (const struct common_firmware_header *)info->fw->data;
3836                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
3837                 adev->firmware.fw_size +=
3838                         ALIGN(le32_to_cpu(header->ucode_size_bytes) -
3839                               le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
3840
3841                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1_JT];
3842                 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1_JT;
3843                 info->fw = adev->gfx.mec_fw;
3844                 adev->firmware.fw_size +=
3845                         ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
3846
3847                 if (adev->gfx.mec2_fw) {
3848                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2];
3849                         info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
3850                         info->fw = adev->gfx.mec2_fw;
3851                         header = (const struct common_firmware_header *)info->fw->data;
3852                         cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
3853                         adev->firmware.fw_size +=
3854                                 ALIGN(le32_to_cpu(header->ucode_size_bytes) -
3855                                       le32_to_cpu(cp_hdr->jt_size) * 4,
3856                                       PAGE_SIZE);
3857                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2_JT];
3858                         info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2_JT;
3859                         info->fw = adev->gfx.mec2_fw;
3860                         adev->firmware.fw_size +=
3861                                 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4,
3862                                       PAGE_SIZE);
3863                 }
3864         }
3865
3866         gfx_v10_0_check_fw_write_wait(adev);
3867 out:
3868         if (err) {
3869                 dev_err(adev->dev,
3870                         "gfx10: Failed to load firmware \"%s\"\n",
3871                         fw_name);
3872                 release_firmware(adev->gfx.pfp_fw);
3873                 adev->gfx.pfp_fw = NULL;
3874                 release_firmware(adev->gfx.me_fw);
3875                 adev->gfx.me_fw = NULL;
3876                 release_firmware(adev->gfx.ce_fw);
3877                 adev->gfx.ce_fw = NULL;
3878                 release_firmware(adev->gfx.rlc_fw);
3879                 adev->gfx.rlc_fw = NULL;
3880                 release_firmware(adev->gfx.mec_fw);
3881                 adev->gfx.mec_fw = NULL;
3882                 release_firmware(adev->gfx.mec2_fw);
3883                 adev->gfx.mec2_fw = NULL;
3884         }
3885
3886         gfx_v10_0_check_gfxoff_flag(adev);
3887
3888         return err;
3889 }
3890
3891 static u32 gfx_v10_0_get_csb_size(struct amdgpu_device *adev)
3892 {
3893         u32 count = 0;
3894         const struct cs_section_def *sect = NULL;
3895         const struct cs_extent_def *ext = NULL;
3896
3897         /* begin clear state */
3898         count += 2;
3899         /* context control state */
3900         count += 3;
3901
3902         for (sect = gfx10_cs_data; sect->section != NULL; ++sect) {
3903                 for (ext = sect->section; ext->extent != NULL; ++ext) {
3904                         if (sect->id == SECT_CONTEXT)
3905                                 count += 2 + ext->reg_count;
3906                         else
3907                                 return 0;
3908                 }
3909         }
3910
3911         /* set PA_SC_TILE_STEERING_OVERRIDE */
3912         count += 3;
3913         /* end clear state */
3914         count += 2;
3915         /* clear state */
3916         count += 2;
3917
3918         return count;
3919 }
3920
3921 static void gfx_v10_0_get_csb_buffer(struct amdgpu_device *adev,
3922                                     volatile u32 *buffer)
3923 {
3924         u32 count = 0, i;
3925         const struct cs_section_def *sect = NULL;
3926         const struct cs_extent_def *ext = NULL;
3927         int ctx_reg_offset;
3928
3929         if (adev->gfx.rlc.cs_data == NULL)
3930                 return;
3931         if (buffer == NULL)
3932                 return;
3933
3934         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
3935         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
3936
3937         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
3938         buffer[count++] = cpu_to_le32(0x80000000);
3939         buffer[count++] = cpu_to_le32(0x80000000);
3940
3941         for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
3942                 for (ext = sect->section; ext->extent != NULL; ++ext) {
3943                         if (sect->id == SECT_CONTEXT) {
3944                                 buffer[count++] =
3945                                         cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
3946                                 buffer[count++] = cpu_to_le32(ext->reg_index -
3947                                                 PACKET3_SET_CONTEXT_REG_START);
3948                                 for (i = 0; i < ext->reg_count; i++)
3949                                         buffer[count++] = cpu_to_le32(ext->extent[i]);
3950                         } else {
3951                                 return;
3952                         }
3953                 }
3954         }
3955
3956         ctx_reg_offset =
3957                 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;
3958         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1));
3959         buffer[count++] = cpu_to_le32(ctx_reg_offset);
3960         buffer[count++] = cpu_to_le32(adev->gfx.config.pa_sc_tile_steering_override);
3961
3962         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
3963         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
3964
3965         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
3966         buffer[count++] = cpu_to_le32(0);
3967 }
3968
3969 static void gfx_v10_0_rlc_fini(struct amdgpu_device *adev)
3970 {
3971         /* clear state block */
3972         amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
3973                         &adev->gfx.rlc.clear_state_gpu_addr,
3974                         (void **)&adev->gfx.rlc.cs_ptr);
3975
3976         /* jump table block */
3977         amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
3978                         &adev->gfx.rlc.cp_table_gpu_addr,
3979                         (void **)&adev->gfx.rlc.cp_table_ptr);
3980 }
3981
3982 static int gfx_v10_0_rlc_init(struct amdgpu_device *adev)
3983 {
3984         const struct cs_section_def *cs_data;
3985         int r;
3986
3987         adev->gfx.rlc.cs_data = gfx10_cs_data;
3988
3989         cs_data = adev->gfx.rlc.cs_data;
3990
3991         if (cs_data) {
3992                 /* init clear state block */
3993                 r = amdgpu_gfx_rlc_init_csb(adev);
3994                 if (r)
3995                         return r;
3996         }
3997
3998         /* init spm vmid with 0xf */
3999         if (adev->gfx.rlc.funcs->update_spm_vmid)
4000                 adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf);
4001
4002         return 0;
4003 }
4004
4005 static void gfx_v10_0_mec_fini(struct amdgpu_device *adev)
4006 {
4007         amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
4008         amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL);
4009 }
4010
4011 static int gfx_v10_0_me_init(struct amdgpu_device *adev)
4012 {
4013         int r;
4014
4015         bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES);
4016
4017         amdgpu_gfx_graphics_queue_acquire(adev);
4018
4019         r = gfx_v10_0_init_microcode(adev);
4020         if (r)
4021                 DRM_ERROR("Failed to load gfx firmware!\n");
4022
4023         return r;
4024 }
4025
4026 static int gfx_v10_0_mec_init(struct amdgpu_device *adev)
4027 {
4028         int r;
4029         u32 *hpd;
4030         const __le32 *fw_data = NULL;
4031         unsigned fw_size;
4032         u32 *fw = NULL;
4033         size_t mec_hpd_size;
4034
4035         const struct gfx_firmware_header_v1_0 *mec_hdr = NULL;
4036
4037         bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
4038
4039         /* take ownership of the relevant compute queues */
4040         amdgpu_gfx_compute_queue_acquire(adev);
4041         mec_hpd_size = adev->gfx.num_compute_rings * GFX10_MEC_HPD_SIZE;
4042
4043         if (mec_hpd_size) {
4044                 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE,
4045                                               AMDGPU_GEM_DOMAIN_GTT,
4046                                               &adev->gfx.mec.hpd_eop_obj,
4047                                               &adev->gfx.mec.hpd_eop_gpu_addr,
4048                                               (void **)&hpd);
4049                 if (r) {
4050                         dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
4051                         gfx_v10_0_mec_fini(adev);
4052                         return r;
4053                 }
4054
4055                 memset(hpd, 0, mec_hpd_size);
4056
4057                 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
4058                 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
4059         }
4060
4061         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
4062                 mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
4063
4064                 fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
4065                          le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
4066                 fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes);
4067
4068                 r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes,
4069                                               PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
4070                                               &adev->gfx.mec.mec_fw_obj,
4071                                               &adev->gfx.mec.mec_fw_gpu_addr,
4072                                               (void **)&fw);
4073                 if (r) {
4074                         dev_err(adev->dev, "(%d) failed to create mec fw bo\n", r);
4075                         gfx_v10_0_mec_fini(adev);
4076                         return r;
4077                 }
4078
4079                 memcpy(fw, fw_data, fw_size);
4080
4081                 amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj);
4082                 amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
4083         }
4084
4085         return 0;
4086 }
4087
4088 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address)
4089 {
4090         WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
4091                 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
4092                 (address << SQ_IND_INDEX__INDEX__SHIFT));
4093         return RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
4094 }
4095
4096 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave,
4097                            uint32_t thread, uint32_t regno,
4098                            uint32_t num, uint32_t *out)
4099 {
4100         WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
4101                 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
4102                 (regno << SQ_IND_INDEX__INDEX__SHIFT) |
4103                 (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) |
4104                 (SQ_IND_INDEX__AUTO_INCR_MASK));
4105         while (num--)
4106                 *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
4107 }
4108
4109 static void gfx_v10_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
4110 {
4111         /* in gfx10 the SIMD_ID is specified as part of the INSTANCE
4112          * field when performing a select_se_sh so it should be
4113          * zero here */
4114         WARN_ON(simd != 0);
4115
4116         /* type 2 wave data */
4117         dst[(*no_fields)++] = 2;
4118         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS);
4119         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO);
4120         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI);
4121         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO);
4122         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI);
4123         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1);
4124         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2);
4125         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_INST_DW0);
4126         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC);
4127         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC);
4128         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAPSTS);
4129         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS);
4130         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2);
4131         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1);
4132         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0);
4133 }
4134
4135 static void gfx_v10_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
4136                                      uint32_t wave, uint32_t start,
4137                                      uint32_t size, uint32_t *dst)
4138 {
4139         WARN_ON(simd != 0);
4140
4141         wave_read_regs(
4142                 adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size,
4143                 dst);
4144 }
4145
4146 static void gfx_v10_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t simd,
4147                                       uint32_t wave, uint32_t thread,
4148                                       uint32_t start, uint32_t size,
4149                                       uint32_t *dst)
4150 {
4151         wave_read_regs(
4152                 adev, wave, thread,
4153                 start + SQIND_WAVE_VGPRS_OFFSET, size, dst);
4154 }
4155
4156 static void gfx_v10_0_select_me_pipe_q(struct amdgpu_device *adev,
4157                                                                           u32 me, u32 pipe, u32 q, u32 vm)
4158  {
4159        nv_grbm_select(adev, me, pipe, q, vm);
4160  }
4161
4162
4163 static const struct amdgpu_gfx_funcs gfx_v10_0_gfx_funcs = {
4164         .get_gpu_clock_counter = &gfx_v10_0_get_gpu_clock_counter,
4165         .select_se_sh = &gfx_v10_0_select_se_sh,
4166         .read_wave_data = &gfx_v10_0_read_wave_data,
4167         .read_wave_sgprs = &gfx_v10_0_read_wave_sgprs,
4168         .read_wave_vgprs = &gfx_v10_0_read_wave_vgprs,
4169         .select_me_pipe_q = &gfx_v10_0_select_me_pipe_q,
4170         .init_spm_golden = &gfx_v10_0_init_spm_golden_registers,
4171 };
4172
4173 static void gfx_v10_0_gpu_early_init(struct amdgpu_device *adev)
4174 {
4175         u32 gb_addr_config;
4176
4177         adev->gfx.funcs = &gfx_v10_0_gfx_funcs;
4178
4179         switch (adev->asic_type) {
4180         case CHIP_NAVI10:
4181         case CHIP_NAVI14:
4182         case CHIP_NAVI12:
4183                 adev->gfx.config.max_hw_contexts = 8;
4184                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4185                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4186                 adev->gfx.config.sc_hiz_tile_fifo_size = 0;
4187                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
4188                 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
4189                 break;
4190         case CHIP_SIENNA_CICHLID:
4191         case CHIP_NAVY_FLOUNDER:
4192                 adev->gfx.config.max_hw_contexts = 8;
4193                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
4194                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
4195                 adev->gfx.config.sc_hiz_tile_fifo_size = 0;
4196                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
4197                 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
4198                 adev->gfx.config.gb_addr_config_fields.num_pkrs =
4199                         1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS);
4200                 break;
4201         default:
4202                 BUG();
4203                 break;
4204         }
4205
4206         adev->gfx.config.gb_addr_config = gb_addr_config;
4207
4208         adev->gfx.config.gb_addr_config_fields.num_pipes = 1 <<
4209                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4210                                       GB_ADDR_CONFIG, NUM_PIPES);
4211
4212         adev->gfx.config.max_tile_pipes =
4213                 adev->gfx.config.gb_addr_config_fields.num_pipes;
4214
4215         adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 <<
4216                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4217                                       GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS);
4218         adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 <<
4219                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4220                                       GB_ADDR_CONFIG, NUM_RB_PER_SE);
4221         adev->gfx.config.gb_addr_config_fields.num_se = 1 <<
4222                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4223                                       GB_ADDR_CONFIG, NUM_SHADER_ENGINES);
4224         adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 +
4225                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4226                                       GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE));
4227 }
4228
4229 static int gfx_v10_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id,
4230                                    int me, int pipe, int queue)
4231 {
4232         int r;
4233         struct amdgpu_ring *ring;
4234         unsigned int irq_type;
4235
4236         ring = &adev->gfx.gfx_ring[ring_id];
4237
4238         ring->me = me;
4239         ring->pipe = pipe;
4240         ring->queue = queue;
4241
4242         ring->ring_obj = NULL;
4243         ring->use_doorbell = true;
4244
4245         if (!ring_id)
4246                 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1;
4247         else
4248                 ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1;
4249         sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue);
4250
4251         irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe;
4252         r = amdgpu_ring_init(adev, ring, 1024,
4253                              &adev->gfx.eop_irq, irq_type,
4254                              AMDGPU_RING_PRIO_DEFAULT);
4255         if (r)
4256                 return r;
4257         return 0;
4258 }
4259
4260 static int gfx_v10_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
4261                                        int mec, int pipe, int queue)
4262 {
4263         int r;
4264         unsigned irq_type;
4265         struct amdgpu_ring *ring;
4266         unsigned int hw_prio;
4267
4268         ring = &adev->gfx.compute_ring[ring_id];
4269
4270         /* mec0 is me1 */
4271         ring->me = mec + 1;
4272         ring->pipe = pipe;
4273         ring->queue = queue;
4274
4275         ring->ring_obj = NULL;
4276         ring->use_doorbell = true;
4277         ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1;
4278         ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr
4279                                 + (ring_id * GFX10_MEC_HPD_SIZE);
4280         sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
4281
4282         irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
4283                 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
4284                 + ring->pipe;
4285         hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring->queue) ?
4286                         AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL;
4287         /* type-2 packets are deprecated on MEC, use type-3 instead */
4288         r = amdgpu_ring_init(adev, ring, 1024,
4289                              &adev->gfx.eop_irq, irq_type, hw_prio);
4290         if (r)
4291                 return r;
4292
4293         return 0;
4294 }
4295
4296 static int gfx_v10_0_sw_init(void *handle)
4297 {
4298         int i, j, k, r, ring_id = 0;
4299         struct amdgpu_kiq *kiq;
4300         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4301
4302         switch (adev->asic_type) {
4303         case CHIP_NAVI10:
4304         case CHIP_NAVI14:
4305         case CHIP_NAVI12:
4306                 adev->gfx.me.num_me = 1;
4307                 adev->gfx.me.num_pipe_per_me = 1;
4308                 adev->gfx.me.num_queue_per_pipe = 1;
4309                 adev->gfx.mec.num_mec = 2;
4310                 adev->gfx.mec.num_pipe_per_mec = 4;
4311                 adev->gfx.mec.num_queue_per_pipe = 8;
4312                 break;
4313         case CHIP_SIENNA_CICHLID:
4314         case CHIP_NAVY_FLOUNDER:
4315                 adev->gfx.me.num_me = 1;
4316                 adev->gfx.me.num_pipe_per_me = 1;
4317                 adev->gfx.me.num_queue_per_pipe = 1;
4318                 adev->gfx.mec.num_mec = 2;
4319                 adev->gfx.mec.num_pipe_per_mec = 4;
4320                 adev->gfx.mec.num_queue_per_pipe = 4;
4321                 break;
4322         default:
4323                 adev->gfx.me.num_me = 1;
4324                 adev->gfx.me.num_pipe_per_me = 1;
4325                 adev->gfx.me.num_queue_per_pipe = 1;
4326                 adev->gfx.mec.num_mec = 1;
4327                 adev->gfx.mec.num_pipe_per_mec = 4;
4328                 adev->gfx.mec.num_queue_per_pipe = 8;
4329                 break;
4330         }
4331
4332         /* KIQ event */
4333         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP,
4334                               GFX_10_1__SRCID__CP_IB2_INTERRUPT_PKT,
4335                               &adev->gfx.kiq.irq);
4336         if (r)
4337                 return r;
4338
4339         /* EOP Event */
4340         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP,
4341                               GFX_10_1__SRCID__CP_EOP_INTERRUPT,
4342                               &adev->gfx.eop_irq);
4343         if (r)
4344                 return r;
4345
4346         /* Privileged reg */
4347         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_REG_FAULT,
4348                               &adev->gfx.priv_reg_irq);
4349         if (r)
4350                 return r;
4351
4352         /* Privileged inst */
4353         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_10_1__SRCID__CP_PRIV_INSTR_FAULT,
4354                               &adev->gfx.priv_inst_irq);
4355         if (r)
4356                 return r;
4357
4358         adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
4359
4360         gfx_v10_0_scratch_init(adev);
4361
4362         r = gfx_v10_0_me_init(adev);
4363         if (r)
4364                 return r;
4365
4366         r = gfx_v10_0_rlc_init(adev);
4367         if (r) {
4368                 DRM_ERROR("Failed to init rlc BOs!\n");
4369                 return r;
4370         }
4371
4372         r = gfx_v10_0_mec_init(adev);
4373         if (r) {
4374                 DRM_ERROR("Failed to init MEC BOs!\n");
4375                 return r;
4376         }
4377
4378         /* set up the gfx ring */
4379         for (i = 0; i < adev->gfx.me.num_me; i++) {
4380                 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) {
4381                         for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) {
4382                                 if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j))
4383                                         continue;
4384
4385                                 r = gfx_v10_0_gfx_ring_init(adev, ring_id,
4386                                                             i, k, j);
4387                                 if (r)
4388                                         return r;
4389                                 ring_id++;
4390                         }
4391                 }
4392         }
4393
4394         ring_id = 0;
4395         /* set up the compute queues - allocate horizontally across pipes */
4396         for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
4397                 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
4398                         for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
4399                                 if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k,
4400                                                                      j))
4401                                         continue;
4402
4403                                 r = gfx_v10_0_compute_ring_init(adev, ring_id,
4404                                                                 i, k, j);
4405                                 if (r)
4406                                         return r;
4407
4408                                 ring_id++;
4409                         }
4410                 }
4411         }
4412
4413         r = amdgpu_gfx_kiq_init(adev, GFX10_MEC_HPD_SIZE);
4414         if (r) {
4415                 DRM_ERROR("Failed to init KIQ BOs!\n");
4416                 return r;
4417         }
4418
4419         kiq = &adev->gfx.kiq;
4420         r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq);
4421         if (r)
4422                 return r;
4423
4424         r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v10_compute_mqd));
4425         if (r)
4426                 return r;
4427
4428         /* allocate visible FB for rlc auto-loading fw */
4429         if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
4430                 r = gfx_v10_0_rlc_backdoor_autoload_buffer_init(adev);
4431                 if (r)
4432                         return r;
4433         }
4434
4435         adev->gfx.ce_ram_size = F32_CE_PROGRAM_RAM_SIZE;
4436
4437         gfx_v10_0_gpu_early_init(adev);
4438
4439         return 0;
4440 }
4441
4442 static void gfx_v10_0_pfp_fini(struct amdgpu_device *adev)
4443 {
4444         amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj,
4445                               &adev->gfx.pfp.pfp_fw_gpu_addr,
4446                               (void **)&adev->gfx.pfp.pfp_fw_ptr);
4447 }
4448
4449 static void gfx_v10_0_ce_fini(struct amdgpu_device *adev)
4450 {
4451         amdgpu_bo_free_kernel(&adev->gfx.ce.ce_fw_obj,
4452                               &adev->gfx.ce.ce_fw_gpu_addr,
4453                               (void **)&adev->gfx.ce.ce_fw_ptr);
4454 }
4455
4456 static void gfx_v10_0_me_fini(struct amdgpu_device *adev)
4457 {
4458         amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj,
4459                               &adev->gfx.me.me_fw_gpu_addr,
4460                               (void **)&adev->gfx.me.me_fw_ptr);
4461 }
4462
4463 static int gfx_v10_0_sw_fini(void *handle)
4464 {
4465         int i;
4466         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4467
4468         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
4469                 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
4470         for (i = 0; i < adev->gfx.num_compute_rings; i++)
4471                 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
4472
4473         amdgpu_gfx_mqd_sw_fini(adev);
4474         amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring);
4475         amdgpu_gfx_kiq_fini(adev);
4476
4477         gfx_v10_0_pfp_fini(adev);
4478         gfx_v10_0_ce_fini(adev);
4479         gfx_v10_0_me_fini(adev);
4480         gfx_v10_0_rlc_fini(adev);
4481         gfx_v10_0_mec_fini(adev);
4482
4483         if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO)
4484                 gfx_v10_0_rlc_backdoor_autoload_buffer_fini(adev);
4485
4486         gfx_v10_0_free_microcode(adev);
4487
4488         return 0;
4489 }
4490
4491 static void gfx_v10_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
4492                                    u32 sh_num, u32 instance)
4493 {
4494         u32 data;
4495
4496         if (instance == 0xffffffff)
4497                 data = REG_SET_FIELD(0, GRBM_GFX_INDEX,
4498                                      INSTANCE_BROADCAST_WRITES, 1);
4499         else
4500                 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX,
4501                                      instance);
4502
4503         if (se_num == 0xffffffff)
4504                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES,
4505                                      1);
4506         else
4507                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
4508
4509         if (sh_num == 0xffffffff)
4510                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES,
4511                                      1);
4512         else
4513                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num);
4514
4515         WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);
4516 }
4517
4518 static u32 gfx_v10_0_get_rb_active_bitmap(struct amdgpu_device *adev)
4519 {
4520         u32 data, mask;
4521
4522         data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE);
4523         data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE);
4524
4525         data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
4526         data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
4527
4528         mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se /
4529                                          adev->gfx.config.max_sh_per_se);
4530
4531         return (~data) & mask;
4532 }
4533
4534 static void gfx_v10_0_setup_rb(struct amdgpu_device *adev)
4535 {
4536         int i, j;
4537         u32 data;
4538         u32 active_rbs = 0;
4539         u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
4540                                         adev->gfx.config.max_sh_per_se;
4541
4542         mutex_lock(&adev->grbm_idx_mutex);
4543         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
4544                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
4545                         gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
4546                         data = gfx_v10_0_get_rb_active_bitmap(adev);
4547                         active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
4548                                                rb_bitmap_width_per_sh);
4549                 }
4550         }
4551         gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
4552         mutex_unlock(&adev->grbm_idx_mutex);
4553
4554         adev->gfx.config.backend_enable_mask = active_rbs;
4555         adev->gfx.config.num_rbs = hweight32(active_rbs);
4556 }
4557
4558 static u32 gfx_v10_0_init_pa_sc_tile_steering_override(struct amdgpu_device *adev)
4559 {
4560         uint32_t num_sc;
4561         uint32_t enabled_rb_per_sh;
4562         uint32_t active_rb_bitmap;
4563         uint32_t num_rb_per_sc;
4564         uint32_t num_packer_per_sc;
4565         uint32_t pa_sc_tile_steering_override;
4566
4567         /* for ASICs that integrates GFX v10.3
4568          * pa_sc_tile_steering_override should be set to 0 */
4569         if (adev->asic_type == CHIP_SIENNA_CICHLID ||
4570             adev->asic_type == CHIP_NAVY_FLOUNDER)
4571                 return 0;
4572
4573         /* init num_sc */
4574         num_sc = adev->gfx.config.max_shader_engines * adev->gfx.config.max_sh_per_se *
4575                         adev->gfx.config.num_sc_per_sh;
4576         /* init num_rb_per_sc */
4577         active_rb_bitmap = gfx_v10_0_get_rb_active_bitmap(adev);
4578         enabled_rb_per_sh = hweight32(active_rb_bitmap);
4579         num_rb_per_sc = enabled_rb_per_sh / adev->gfx.config.num_sc_per_sh;
4580         /* init num_packer_per_sc */
4581         num_packer_per_sc = adev->gfx.config.num_packer_per_sc;
4582
4583         pa_sc_tile_steering_override = 0;
4584         pa_sc_tile_steering_override |=
4585                 (order_base_2(num_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_SC__SHIFT) &
4586                 PA_SC_TILE_STEERING_OVERRIDE__NUM_SC_MASK;
4587         pa_sc_tile_steering_override |=
4588                 (order_base_2(num_rb_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC__SHIFT) &
4589                 PA_SC_TILE_STEERING_OVERRIDE__NUM_RB_PER_SC_MASK;
4590         pa_sc_tile_steering_override |=
4591                 (order_base_2(num_packer_per_sc) << PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC__SHIFT) &
4592                 PA_SC_TILE_STEERING_OVERRIDE__NUM_PACKER_PER_SC_MASK;
4593
4594         return pa_sc_tile_steering_override;
4595 }
4596
4597 #define DEFAULT_SH_MEM_BASES    (0x6000)
4598
4599 static void gfx_v10_0_init_compute_vmid(struct amdgpu_device *adev)
4600 {
4601         int i;
4602         uint32_t sh_mem_bases;
4603
4604         /*
4605          * Configure apertures:
4606          * LDS:         0x60000000'00000000 - 0x60000001'00000000 (4GB)
4607          * Scratch:     0x60000001'00000000 - 0x60000002'00000000 (4GB)
4608          * GPUVM:       0x60010000'00000000 - 0x60020000'00000000 (1TB)
4609          */
4610         sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
4611
4612         mutex_lock(&adev->srbm_mutex);
4613         for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
4614                 nv_grbm_select(adev, 0, 0, 0, i);
4615                 /* CP and shaders */
4616                 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
4617                 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases);
4618         }
4619         nv_grbm_select(adev, 0, 0, 0, 0);
4620         mutex_unlock(&adev->srbm_mutex);
4621
4622         /* Initialize all compute VMIDs to have no GDS, GWS, or OA
4623            acccess. These should be enabled by FW for target VMIDs. */
4624         for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
4625                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * i, 0);
4626                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * i, 0);
4627                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, i, 0);
4628                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, i, 0);
4629         }
4630 }
4631
4632 static void gfx_v10_0_init_gds_vmid(struct amdgpu_device *adev)
4633 {
4634         int vmid;
4635
4636         /*
4637          * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA
4638          * access. Compute VMIDs should be enabled by FW for target VMIDs,
4639          * the driver can enable them for graphics. VMID0 should maintain
4640          * access so that HWS firmware can save/restore entries.
4641          */
4642         for (vmid = 1; vmid < 16; vmid++) {
4643                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_BASE, 2 * vmid, 0);
4644                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_VMID0_SIZE, 2 * vmid, 0);
4645                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_GWS_VMID0, vmid, 0);
4646                 WREG32_SOC15_OFFSET(GC, 0, mmGDS_OA_VMID0, vmid, 0);
4647         }
4648 }
4649
4650
4651 static void gfx_v10_0_tcp_harvest(struct amdgpu_device *adev)
4652 {
4653         int i, j, k;
4654         int max_wgp_per_sh = adev->gfx.config.max_cu_per_sh >> 1;
4655         u32 tmp, wgp_active_bitmap = 0;
4656         u32 gcrd_targets_disable_tcp = 0;
4657         u32 utcl_invreq_disable = 0;
4658         /*
4659          * GCRD_TARGETS_DISABLE field contains
4660          * for Navi10/Navi12: GL1C=[18:15], SQC=[14:10], TCP=[9:0]
4661          * for Navi14: GL1C=[21:18], SQC=[17:12], TCP=[11:0]
4662          */
4663         u32 gcrd_targets_disable_mask = amdgpu_gfx_create_bitmask(
4664                 2 * max_wgp_per_sh + /* TCP */
4665                 max_wgp_per_sh + /* SQC */
4666                 4); /* GL1C */
4667         /*
4668          * UTCL1_UTCL0_INVREQ_DISABLE field contains
4669          * for Navi10Navi12: SQG=[24], RMI=[23:20], SQC=[19:10], TCP=[9:0]
4670          * for Navi14: SQG=[28], RMI=[27:24], SQC=[23:12], TCP=[11:0]
4671          */
4672         u32 utcl_invreq_disable_mask = amdgpu_gfx_create_bitmask(
4673                 2 * max_wgp_per_sh + /* TCP */
4674                 2 * max_wgp_per_sh + /* SQC */
4675                 4 + /* RMI */
4676                 1); /* SQG */
4677
4678         if (adev->asic_type == CHIP_NAVI10 ||
4679             adev->asic_type == CHIP_NAVI14 ||
4680             adev->asic_type == CHIP_NAVI12) {
4681                 mutex_lock(&adev->grbm_idx_mutex);
4682                 for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
4683                         for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
4684                                 gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
4685                                 wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev);
4686                                 /*
4687                                  * Set corresponding TCP bits for the inactive WGPs in
4688                                  * GCRD_SA_TARGETS_DISABLE
4689                                  */
4690                                 gcrd_targets_disable_tcp = 0;
4691                                 /* Set TCP & SQC bits in UTCL1_UTCL0_INVREQ_DISABLE */
4692                                 utcl_invreq_disable = 0;
4693
4694                                 for (k = 0; k < max_wgp_per_sh; k++) {
4695                                         if (!(wgp_active_bitmap & (1 << k))) {
4696                                                 gcrd_targets_disable_tcp |= 3 << (2 * k);
4697                                                 utcl_invreq_disable |= (3 << (2 * k)) |
4698                                                         (3 << (2 * (max_wgp_per_sh + k)));
4699                                         }
4700                                 }
4701
4702                                 tmp = RREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE);
4703                                 /* only override TCP & SQC bits */
4704                                 tmp &= 0xffffffff << (4 * max_wgp_per_sh);
4705                                 tmp |= (utcl_invreq_disable & utcl_invreq_disable_mask);
4706                                 WREG32_SOC15(GC, 0, mmUTCL1_UTCL0_INVREQ_DISABLE, tmp);
4707
4708                                 tmp = RREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE);
4709                                 /* only override TCP bits */
4710                                 tmp &= 0xffffffff << (2 * max_wgp_per_sh);
4711                                 tmp |= (gcrd_targets_disable_tcp & gcrd_targets_disable_mask);
4712                                 WREG32_SOC15(GC, 0, mmGCRD_SA_TARGETS_DISABLE, tmp);
4713                         }
4714                 }
4715
4716                 gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
4717                 mutex_unlock(&adev->grbm_idx_mutex);
4718         }
4719 }
4720
4721 static void gfx_v10_0_get_tcc_info(struct amdgpu_device *adev)
4722 {
4723         /* TCCs are global (not instanced). */
4724         uint32_t tcc_disable = RREG32_SOC15(GC, 0, mmCGTS_TCC_DISABLE) |
4725                                RREG32_SOC15(GC, 0, mmCGTS_USER_TCC_DISABLE);
4726
4727         adev->gfx.config.tcc_disabled_mask =
4728                 REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, TCC_DISABLE) |
4729                 (REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, HI_TCC_DISABLE) << 16);
4730 }
4731
4732 static void gfx_v10_0_constants_init(struct amdgpu_device *adev)
4733 {
4734         u32 tmp;
4735         int i;
4736
4737         WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff);
4738
4739         gfx_v10_0_setup_rb(adev);
4740         gfx_v10_0_get_cu_info(adev, &adev->gfx.cu_info);
4741         gfx_v10_0_get_tcc_info(adev);
4742         adev->gfx.config.pa_sc_tile_steering_override =
4743                 gfx_v10_0_init_pa_sc_tile_steering_override(adev);
4744
4745         /* XXX SH_MEM regs */
4746         /* where to put LDS, scratch, GPUVM in FSA64 space */
4747         mutex_lock(&adev->srbm_mutex);
4748         for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB_0].num_ids; i++) {
4749                 nv_grbm_select(adev, 0, 0, 0, i);
4750                 /* CP and shaders */
4751                 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
4752                 if (i != 0) {
4753                         tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE,
4754                                 (adev->gmc.private_aperture_start >> 48));
4755                         tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE,
4756                                 (adev->gmc.shared_aperture_start >> 48));
4757                         WREG32_SOC15(GC, 0, mmSH_MEM_BASES, tmp);
4758                 }
4759         }
4760         nv_grbm_select(adev, 0, 0, 0, 0);
4761
4762         mutex_unlock(&adev->srbm_mutex);
4763
4764         gfx_v10_0_init_compute_vmid(adev);
4765         gfx_v10_0_init_gds_vmid(adev);
4766
4767 }
4768
4769 static void gfx_v10_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
4770                                                bool enable)
4771 {
4772         u32 tmp;
4773
4774         if (amdgpu_sriov_vf(adev))
4775                 return;
4776
4777         tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);
4778
4779         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE,
4780                             enable ? 1 : 0);
4781         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE,
4782                             enable ? 1 : 0);
4783         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE,
4784                             enable ? 1 : 0);
4785         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE,
4786                             enable ? 1 : 0);
4787
4788         WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp);
4789 }
4790
4791 static int gfx_v10_0_init_csb(struct amdgpu_device *adev)
4792 {
4793         adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr);
4794
4795         /* csib */
4796         if (adev->asic_type == CHIP_NAVI12) {
4797                 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_HI,
4798                                 adev->gfx.rlc.clear_state_gpu_addr >> 32);
4799                 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_ADDR_LO,
4800                                 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
4801                 WREG32_SOC15_RLC(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);
4802         } else {
4803                 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_HI,
4804                                 adev->gfx.rlc.clear_state_gpu_addr >> 32);
4805                 WREG32_SOC15(GC, 0, mmRLC_CSIB_ADDR_LO,
4806                                 adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
4807                 WREG32_SOC15(GC, 0, mmRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);
4808         }
4809         return 0;
4810 }
4811
4812 void gfx_v10_0_rlc_stop(struct amdgpu_device *adev)
4813 {
4814         u32 tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
4815
4816         tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);
4817         WREG32_SOC15(GC, 0, mmRLC_CNTL, tmp);
4818 }
4819
4820 static void gfx_v10_0_rlc_reset(struct amdgpu_device *adev)
4821 {
4822         WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
4823         udelay(50);
4824         WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
4825         udelay(50);
4826 }
4827
4828 static void gfx_v10_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev,
4829                                              bool enable)
4830 {
4831         uint32_t rlc_pg_cntl;
4832
4833         rlc_pg_cntl = RREG32_SOC15(GC, 0, mmRLC_PG_CNTL);
4834
4835         if (!enable) {
4836                 /* RLC_PG_CNTL[23] = 0 (default)
4837                  * RLC will wait for handshake acks with SMU
4838                  * GFXOFF will be enabled
4839                  * RLC_PG_CNTL[23] = 1
4840                  * RLC will not issue any message to SMU
4841                  * hence no handshake between SMU & RLC
4842                  * GFXOFF will be disabled
4843                  */
4844                 rlc_pg_cntl |= 0x800000;
4845         } else
4846                 rlc_pg_cntl &= ~0x800000;
4847         WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, rlc_pg_cntl);
4848 }
4849
4850 static void gfx_v10_0_rlc_start(struct amdgpu_device *adev)
4851 {
4852         /* TODO: enable rlc & smu handshake until smu
4853          * and gfxoff feature works as expected */
4854         if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK))
4855                 gfx_v10_0_rlc_smu_handshake_cntl(adev, false);
4856
4857         WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1);
4858         udelay(50);
4859 }
4860
4861 static void gfx_v10_0_rlc_enable_srm(struct amdgpu_device *adev)
4862 {
4863         uint32_t tmp;
4864
4865         /* enable Save Restore Machine */
4866         tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL));
4867         tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK;
4868         tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK;
4869         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL), tmp);
4870 }
4871
4872 static int gfx_v10_0_rlc_load_microcode(struct amdgpu_device *adev)
4873 {
4874         const struct rlc_firmware_header_v2_0 *hdr;
4875         const __le32 *fw_data;
4876         unsigned i, fw_size;
4877
4878         if (!adev->gfx.rlc_fw)
4879                 return -EINVAL;
4880
4881         hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
4882         amdgpu_ucode_print_rlc_hdr(&hdr->header);
4883
4884         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
4885                            le32_to_cpu(hdr->header.ucode_array_offset_bytes));
4886         fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
4887
4888         WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR,
4889                      RLCG_UCODE_LOADING_START_ADDRESS);
4890
4891         for (i = 0; i < fw_size; i++)
4892                 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA,
4893                              le32_to_cpup(fw_data++));
4894
4895         WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
4896
4897         return 0;
4898 }
4899
4900 static int gfx_v10_0_rlc_resume(struct amdgpu_device *adev)
4901 {
4902         int r;
4903
4904         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
4905
4906                 r = gfx_v10_0_wait_for_rlc_autoload_complete(adev);
4907                 if (r)
4908                         return r;
4909
4910                 gfx_v10_0_init_csb(adev);
4911
4912                 if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */
4913                         gfx_v10_0_rlc_enable_srm(adev);
4914         } else {
4915                 if (amdgpu_sriov_vf(adev)) {
4916                         gfx_v10_0_init_csb(adev);
4917                         return 0;
4918                 }
4919
4920                 adev->gfx.rlc.funcs->stop(adev);
4921
4922                 /* disable CG */
4923                 WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0);
4924
4925                 /* disable PG */
4926                 WREG32_SOC15(GC, 0, mmRLC_PG_CNTL, 0);
4927
4928                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
4929                         /* legacy rlc firmware loading */
4930                         r = gfx_v10_0_rlc_load_microcode(adev);
4931                         if (r)
4932                                 return r;
4933                 } else if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
4934                         /* rlc backdoor autoload firmware */
4935                         r = gfx_v10_0_rlc_backdoor_autoload_enable(adev);
4936                         if (r)
4937                                 return r;
4938                 }
4939
4940                 gfx_v10_0_init_csb(adev);
4941
4942                 adev->gfx.rlc.funcs->start(adev);
4943
4944                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
4945                         r = gfx_v10_0_wait_for_rlc_autoload_complete(adev);
4946                         if (r)
4947                                 return r;
4948                 }
4949         }
4950         return 0;
4951 }
4952
4953 static struct {
4954         FIRMWARE_ID     id;
4955         unsigned int    offset;
4956         unsigned int    size;
4957 } rlc_autoload_info[FIRMWARE_ID_MAX];
4958
4959 static int gfx_v10_0_parse_rlc_toc(struct amdgpu_device *adev)
4960 {
4961         int ret;
4962         RLC_TABLE_OF_CONTENT *rlc_toc;
4963
4964         ret = amdgpu_bo_create_reserved(adev, adev->psp.toc_bin_size, PAGE_SIZE,
4965                                         AMDGPU_GEM_DOMAIN_GTT,
4966                                         &adev->gfx.rlc.rlc_toc_bo,
4967                                         &adev->gfx.rlc.rlc_toc_gpu_addr,
4968                                         (void **)&adev->gfx.rlc.rlc_toc_buf);
4969         if (ret) {
4970                 dev_err(adev->dev, "(%d) failed to create rlc toc bo\n", ret);
4971                 return ret;
4972         }
4973
4974         /* Copy toc from psp sos fw to rlc toc buffer */
4975         memcpy(adev->gfx.rlc.rlc_toc_buf, adev->psp.toc_start_addr, adev->psp.toc_bin_size);
4976
4977         rlc_toc = (RLC_TABLE_OF_CONTENT *)adev->gfx.rlc.rlc_toc_buf;
4978         while (rlc_toc && (rlc_toc->id > FIRMWARE_ID_INVALID) &&
4979                 (rlc_toc->id < FIRMWARE_ID_MAX)) {
4980                 if ((rlc_toc->id >= FIRMWARE_ID_CP_CE) &&
4981                     (rlc_toc->id <= FIRMWARE_ID_CP_MES)) {
4982                         /* Offset needs 4KB alignment */
4983                         rlc_toc->offset = ALIGN(rlc_toc->offset * 4, PAGE_SIZE);
4984                 }
4985
4986                 rlc_autoload_info[rlc_toc->id].id = rlc_toc->id;
4987                 rlc_autoload_info[rlc_toc->id].offset = rlc_toc->offset * 4;
4988                 rlc_autoload_info[rlc_toc->id].size = rlc_toc->size * 4;
4989
4990                 rlc_toc++;
4991         }
4992
4993         return 0;
4994 }
4995
4996 static uint32_t gfx_v10_0_calc_toc_total_size(struct amdgpu_device *adev)
4997 {
4998         uint32_t total_size = 0;
4999         FIRMWARE_ID id;
5000         int ret;
5001
5002         ret = gfx_v10_0_parse_rlc_toc(adev);
5003         if (ret) {
5004                 dev_err(adev->dev, "failed to parse rlc toc\n");
5005                 return 0;
5006         }
5007
5008         for (id = FIRMWARE_ID_RLC_G_UCODE; id < FIRMWARE_ID_MAX; id++)
5009                 total_size += rlc_autoload_info[id].size;
5010
5011         /* In case the offset in rlc toc ucode is aligned */
5012         if (total_size < rlc_autoload_info[FIRMWARE_ID_MAX-1].offset)
5013                 total_size = rlc_autoload_info[FIRMWARE_ID_MAX-1].offset +
5014                                 rlc_autoload_info[FIRMWARE_ID_MAX-1].size;
5015
5016         return total_size;
5017 }
5018
5019 static int gfx_v10_0_rlc_backdoor_autoload_buffer_init(struct amdgpu_device *adev)
5020 {
5021         int r;
5022         uint32_t total_size;
5023
5024         total_size = gfx_v10_0_calc_toc_total_size(adev);
5025
5026         r = amdgpu_bo_create_reserved(adev, total_size, PAGE_SIZE,
5027                                       AMDGPU_GEM_DOMAIN_GTT,
5028                                       &adev->gfx.rlc.rlc_autoload_bo,
5029                                       &adev->gfx.rlc.rlc_autoload_gpu_addr,
5030                                       (void **)&adev->gfx.rlc.rlc_autoload_ptr);
5031         if (r) {
5032                 dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r);
5033                 return r;
5034         }
5035
5036         return 0;
5037 }
5038
5039 static void gfx_v10_0_rlc_backdoor_autoload_buffer_fini(struct amdgpu_device *adev)
5040 {
5041         amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_toc_bo,
5042                               &adev->gfx.rlc.rlc_toc_gpu_addr,
5043                               (void **)&adev->gfx.rlc.rlc_toc_buf);
5044         amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo,
5045                               &adev->gfx.rlc.rlc_autoload_gpu_addr,
5046                               (void **)&adev->gfx.rlc.rlc_autoload_ptr);
5047 }
5048
5049 static void gfx_v10_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev,
5050                                                        FIRMWARE_ID id,
5051                                                        const void *fw_data,
5052                                                        uint32_t fw_size)
5053 {
5054         uint32_t toc_offset;
5055         uint32_t toc_fw_size;
5056         char *ptr = adev->gfx.rlc.rlc_autoload_ptr;
5057
5058         if (id <= FIRMWARE_ID_INVALID || id >= FIRMWARE_ID_MAX)
5059                 return;
5060
5061         toc_offset = rlc_autoload_info[id].offset;
5062         toc_fw_size = rlc_autoload_info[id].size;
5063
5064         if (fw_size == 0)
5065                 fw_size = toc_fw_size;
5066
5067         if (fw_size > toc_fw_size)
5068                 fw_size = toc_fw_size;
5069
5070         memcpy(ptr + toc_offset, fw_data, fw_size);
5071
5072         if (fw_size < toc_fw_size)
5073                 memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size);
5074 }
5075
5076 static void gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev)
5077 {
5078         void *data;
5079         uint32_t size;
5080
5081         data = adev->gfx.rlc.rlc_toc_buf;
5082         size = rlc_autoload_info[FIRMWARE_ID_RLC_TOC].size;
5083
5084         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5085                                                    FIRMWARE_ID_RLC_TOC,
5086                                                    data, size);
5087 }
5088
5089 static void gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev)
5090 {
5091         const __le32 *fw_data;
5092         uint32_t fw_size;
5093         const struct gfx_firmware_header_v1_0 *cp_hdr;
5094         const struct rlc_firmware_header_v2_0 *rlc_hdr;
5095
5096         /* pfp ucode */
5097         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5098                 adev->gfx.pfp_fw->data;
5099         fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
5100                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5101         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
5102         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5103                                                    FIRMWARE_ID_CP_PFP,
5104                                                    fw_data, fw_size);
5105
5106         /* ce ucode */
5107         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5108                 adev->gfx.ce_fw->data;
5109         fw_data = (const __le32 *)(adev->gfx.ce_fw->data +
5110                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5111         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
5112         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5113                                                    FIRMWARE_ID_CP_CE,
5114                                                    fw_data, fw_size);
5115
5116         /* me ucode */
5117         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5118                 adev->gfx.me_fw->data;
5119         fw_data = (const __le32 *)(adev->gfx.me_fw->data +
5120                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5121         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
5122         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5123                                                    FIRMWARE_ID_CP_ME,
5124                                                    fw_data, fw_size);
5125
5126         /* rlc ucode */
5127         rlc_hdr = (const struct rlc_firmware_header_v2_0 *)
5128                 adev->gfx.rlc_fw->data;
5129         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
5130                 le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes));
5131         fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes);
5132         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5133                                                    FIRMWARE_ID_RLC_G_UCODE,
5134                                                    fw_data, fw_size);
5135
5136         /* mec1 ucode */
5137         cp_hdr = (const struct gfx_firmware_header_v1_0 *)
5138                 adev->gfx.mec_fw->data;
5139         fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
5140                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
5141         fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) -
5142                 cp_hdr->jt_size * 4;
5143         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5144                                                    FIRMWARE_ID_CP_MEC,
5145                                                    fw_data, fw_size);
5146         /* mec2 ucode is not necessary if mec2 ucode is same as mec1 */
5147 }
5148
5149 /* Temporarily put sdma part here */
5150 static void gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev)
5151 {
5152         const __le32 *fw_data;
5153         uint32_t fw_size;
5154         const struct sdma_firmware_header_v1_0 *sdma_hdr;
5155         int i;
5156
5157         for (i = 0; i < adev->sdma.num_instances; i++) {
5158                 sdma_hdr = (const struct sdma_firmware_header_v1_0 *)
5159                         adev->sdma.instance[i].fw->data;
5160                 fw_data = (const __le32 *) (adev->sdma.instance[i].fw->data +
5161                         le32_to_cpu(sdma_hdr->header.ucode_array_offset_bytes));
5162                 fw_size = le32_to_cpu(sdma_hdr->header.ucode_size_bytes);
5163
5164                 if (i == 0) {
5165                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5166                                 FIRMWARE_ID_SDMA0_UCODE, fw_data, fw_size);
5167                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5168                                 FIRMWARE_ID_SDMA0_JT,
5169                                 (uint32_t *)fw_data +
5170                                 sdma_hdr->jt_offset,
5171                                 sdma_hdr->jt_size * 4);
5172                 } else if (i == 1) {
5173                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5174                                 FIRMWARE_ID_SDMA1_UCODE, fw_data, fw_size);
5175                         gfx_v10_0_rlc_backdoor_autoload_copy_ucode(adev,
5176                                 FIRMWARE_ID_SDMA1_JT,
5177                                 (uint32_t *)fw_data +
5178                                 sdma_hdr->jt_offset,
5179                                 sdma_hdr->jt_size * 4);
5180                 }
5181         }
5182 }
5183
5184 static int gfx_v10_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev)
5185 {
5186         uint32_t rlc_g_offset, rlc_g_size, tmp;
5187         uint64_t gpu_addr;
5188
5189         gfx_v10_0_rlc_backdoor_autoload_copy_toc_ucode(adev);
5190         gfx_v10_0_rlc_backdoor_autoload_copy_sdma_ucode(adev);
5191         gfx_v10_0_rlc_backdoor_autoload_copy_gfx_ucode(adev);
5192
5193         rlc_g_offset = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].offset;
5194         rlc_g_size = rlc_autoload_info[FIRMWARE_ID_RLC_G_UCODE].size;
5195         gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset;
5196
5197         WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_HI, upper_32_bits(gpu_addr));
5198         WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_ADDR_LO, lower_32_bits(gpu_addr));
5199         WREG32_SOC15(GC, 0, mmRLC_HYP_BOOTLOAD_SIZE, rlc_g_size);
5200
5201         tmp = RREG32_SOC15(GC, 0, mmRLC_HYP_RESET_VECTOR);
5202         if (!(tmp & (RLC_HYP_RESET_VECTOR__COLD_BOOT_EXIT_MASK |
5203                    RLC_HYP_RESET_VECTOR__VDDGFX_EXIT_MASK))) {
5204                 DRM_ERROR("Neither COLD_BOOT_EXIT nor VDDGFX_EXIT is set\n");
5205                 return -EINVAL;
5206         }
5207
5208         tmp = RREG32_SOC15(GC, 0, mmRLC_CNTL);
5209         if (tmp & RLC_CNTL__RLC_ENABLE_F32_MASK) {
5210                 DRM_ERROR("RLC ROM should halt itself\n");
5211                 return -EINVAL;
5212         }
5213
5214         return 0;
5215 }
5216
5217 static int gfx_v10_0_rlc_backdoor_autoload_config_me_cache(struct amdgpu_device *adev)
5218 {
5219         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5220         uint32_t tmp;
5221         int i;
5222         uint64_t addr;
5223
5224         /* Trigger an invalidation of the L1 instruction caches */
5225         tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5226         tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5227         WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp);
5228
5229         /* Wait for invalidation complete */
5230         for (i = 0; i < usec_timeout; i++) {
5231                 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5232                 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
5233                         INVALIDATE_CACHE_COMPLETE))
5234                         break;
5235                 udelay(1);
5236         }
5237
5238         if (i >= usec_timeout) {
5239                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5240                 return -EINVAL;
5241         }
5242
5243         /* Program me ucode address into intruction cache address register */
5244         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5245                 rlc_autoload_info[FIRMWARE_ID_CP_ME].offset;
5246         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO,
5247                         lower_32_bits(addr) & 0xFFFFF000);
5248         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI,
5249                         upper_32_bits(addr));
5250
5251         return 0;
5252 }
5253
5254 static int gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(struct amdgpu_device *adev)
5255 {
5256         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5257         uint32_t tmp;
5258         int i;
5259         uint64_t addr;
5260
5261         /* Trigger an invalidation of the L1 instruction caches */
5262         tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5263         tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5264         WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp);
5265
5266         /* Wait for invalidation complete */
5267         for (i = 0; i < usec_timeout; i++) {
5268                 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5269                 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL,
5270                         INVALIDATE_CACHE_COMPLETE))
5271                         break;
5272                 udelay(1);
5273         }
5274
5275         if (i >= usec_timeout) {
5276                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5277                 return -EINVAL;
5278         }
5279
5280         /* Program ce ucode address into intruction cache address register */
5281         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5282                 rlc_autoload_info[FIRMWARE_ID_CP_CE].offset;
5283         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO,
5284                         lower_32_bits(addr) & 0xFFFFF000);
5285         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI,
5286                         upper_32_bits(addr));
5287
5288         return 0;
5289 }
5290
5291 static int gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(struct amdgpu_device *adev)
5292 {
5293         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5294         uint32_t tmp;
5295         int i;
5296         uint64_t addr;
5297
5298         /* Trigger an invalidation of the L1 instruction caches */
5299         tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5300         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5301         WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp);
5302
5303         /* Wait for invalidation complete */
5304         for (i = 0; i < usec_timeout; i++) {
5305                 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5306                 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
5307                         INVALIDATE_CACHE_COMPLETE))
5308                         break;
5309                 udelay(1);
5310         }
5311
5312         if (i >= usec_timeout) {
5313                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5314                 return -EINVAL;
5315         }
5316
5317         /* Program pfp ucode address into intruction cache address register */
5318         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5319                 rlc_autoload_info[FIRMWARE_ID_CP_PFP].offset;
5320         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO,
5321                         lower_32_bits(addr) & 0xFFFFF000);
5322         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI,
5323                         upper_32_bits(addr));
5324
5325         return 0;
5326 }
5327
5328 static int gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(struct amdgpu_device *adev)
5329 {
5330         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5331         uint32_t tmp;
5332         int i;
5333         uint64_t addr;
5334
5335         /* Trigger an invalidation of the L1 instruction caches */
5336         tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
5337         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5338         WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp);
5339
5340         /* Wait for invalidation complete */
5341         for (i = 0; i < usec_timeout; i++) {
5342                 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
5343                 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
5344                         INVALIDATE_CACHE_COMPLETE))
5345                         break;
5346                 udelay(1);
5347         }
5348
5349         if (i >= usec_timeout) {
5350                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5351                 return -EINVAL;
5352         }
5353
5354         /* Program mec1 ucode address into intruction cache address register */
5355         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
5356                 rlc_autoload_info[FIRMWARE_ID_CP_MEC].offset;
5357         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO,
5358                         lower_32_bits(addr) & 0xFFFFF000);
5359         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
5360                         upper_32_bits(addr));
5361
5362         return 0;
5363 }
5364
5365 static int gfx_v10_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev)
5366 {
5367         uint32_t cp_status;
5368         uint32_t bootload_status;
5369         int i, r;
5370
5371         for (i = 0; i < adev->usec_timeout; i++) {
5372                 cp_status = RREG32_SOC15(GC, 0, mmCP_STAT);
5373                 bootload_status = RREG32_SOC15(GC, 0, mmRLC_RLCS_BOOTLOAD_STATUS);
5374                 if ((cp_status == 0) &&
5375                     (REG_GET_FIELD(bootload_status,
5376                         RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) {
5377                         break;
5378                 }
5379                 udelay(1);
5380         }
5381
5382         if (i >= adev->usec_timeout) {
5383                 dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n");
5384                 return -ETIMEDOUT;
5385         }
5386
5387         if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
5388                 r = gfx_v10_0_rlc_backdoor_autoload_config_me_cache(adev);
5389                 if (r)
5390                         return r;
5391
5392                 r = gfx_v10_0_rlc_backdoor_autoload_config_ce_cache(adev);
5393                 if (r)
5394                         return r;
5395
5396                 r = gfx_v10_0_rlc_backdoor_autoload_config_pfp_cache(adev);
5397                 if (r)
5398                         return r;
5399
5400                 r = gfx_v10_0_rlc_backdoor_autoload_config_mec_cache(adev);
5401                 if (r)
5402                         return r;
5403         }
5404
5405         return 0;
5406 }
5407
5408 static int gfx_v10_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
5409 {
5410         int i;
5411         u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL);
5412
5413         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);
5414         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);
5415         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1);
5416
5417         if (adev->asic_type == CHIP_NAVI12) {
5418                 WREG32_SOC15_RLC(GC, 0, mmCP_ME_CNTL, tmp);
5419         } else {
5420                 WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp);
5421         }
5422
5423         for (i = 0; i < adev->usec_timeout; i++) {
5424                 if (RREG32_SOC15(GC, 0, mmCP_STAT) == 0)
5425                         break;
5426                 udelay(1);
5427         }
5428
5429         if (i >= adev->usec_timeout)
5430                 DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt");
5431
5432         return 0;
5433 }
5434
5435 static int gfx_v10_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev)
5436 {
5437         int r;
5438         const struct gfx_firmware_header_v1_0 *pfp_hdr;
5439         const __le32 *fw_data;
5440         unsigned i, fw_size;
5441         uint32_t tmp;
5442         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5443
5444         pfp_hdr = (const struct gfx_firmware_header_v1_0 *)
5445                 adev->gfx.pfp_fw->data;
5446
5447         amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
5448
5449         fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
5450                 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
5451         fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes);
5452
5453         r = amdgpu_bo_create_reserved(adev, pfp_hdr->header.ucode_size_bytes,
5454                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
5455                                       &adev->gfx.pfp.pfp_fw_obj,
5456                                       &adev->gfx.pfp.pfp_fw_gpu_addr,
5457                                       (void **)&adev->gfx.pfp.pfp_fw_ptr);
5458         if (r) {
5459                 dev_err(adev->dev, "(%d) failed to create pfp fw bo\n", r);
5460                 gfx_v10_0_pfp_fini(adev);
5461                 return r;
5462         }
5463
5464         memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_data, fw_size);
5465
5466         amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj);
5467         amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj);
5468
5469         /* Trigger an invalidation of the L1 instruction caches */
5470         tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5471         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5472         WREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL, tmp);
5473
5474         /* Wait for invalidation complete */
5475         for (i = 0; i < usec_timeout; i++) {
5476                 tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_OP_CNTL);
5477                 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
5478                         INVALIDATE_CACHE_COMPLETE))
5479                         break;
5480                 udelay(1);
5481         }
5482
5483         if (i >= usec_timeout) {
5484                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5485                 return -EINVAL;
5486         }
5487
5488         if (amdgpu_emu_mode == 1)
5489                 adev->nbio.funcs->hdp_flush(adev, NULL);
5490
5491         tmp = RREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL);
5492         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0);
5493         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0);
5494         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0);
5495         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
5496         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_CNTL, tmp);
5497         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_LO,
5498                 adev->gfx.pfp.pfp_fw_gpu_addr & 0xFFFFF000);
5499         WREG32_SOC15(GC, 0, mmCP_PFP_IC_BASE_HI,
5500                 upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr));
5501
5502         WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, 0);
5503
5504         for (i = 0; i < pfp_hdr->jt_size; i++)
5505                 WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_DATA,
5506                              le32_to_cpup(fw_data + pfp_hdr->jt_offset + i));
5507
5508         WREG32_SOC15(GC, 0, mmCP_HYP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);
5509
5510         return 0;
5511 }
5512
5513 static int gfx_v10_0_cp_gfx_load_ce_microcode(struct amdgpu_device *adev)
5514 {
5515         int r;
5516         const struct gfx_firmware_header_v1_0 *ce_hdr;
5517         const __le32 *fw_data;
5518         unsigned i, fw_size;
5519         uint32_t tmp;
5520         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5521
5522         ce_hdr = (const struct gfx_firmware_header_v1_0 *)
5523                 adev->gfx.ce_fw->data;
5524
5525         amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
5526
5527         fw_data = (const __le32 *)(adev->gfx.ce_fw->data +
5528                 le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
5529         fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes);
5530
5531         r = amdgpu_bo_create_reserved(adev, ce_hdr->header.ucode_size_bytes,
5532                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
5533                                       &adev->gfx.ce.ce_fw_obj,
5534                                       &adev->gfx.ce.ce_fw_gpu_addr,
5535                                       (void **)&adev->gfx.ce.ce_fw_ptr);
5536         if (r) {
5537                 dev_err(adev->dev, "(%d) failed to create ce fw bo\n", r);
5538                 gfx_v10_0_ce_fini(adev);
5539                 return r;
5540         }
5541
5542         memcpy(adev->gfx.ce.ce_fw_ptr, fw_data, fw_size);
5543
5544         amdgpu_bo_kunmap(adev->gfx.ce.ce_fw_obj);
5545         amdgpu_bo_unreserve(adev->gfx.ce.ce_fw_obj);
5546
5547         /* Trigger an invalidation of the L1 instruction caches */
5548         tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5549         tmp = REG_SET_FIELD(tmp, CP_CE_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5550         WREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL, tmp);
5551
5552         /* Wait for invalidation complete */
5553         for (i = 0; i < usec_timeout; i++) {
5554                 tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_OP_CNTL);
5555                 if (1 == REG_GET_FIELD(tmp, CP_CE_IC_OP_CNTL,
5556                         INVALIDATE_CACHE_COMPLETE))
5557                         break;
5558                 udelay(1);
5559         }
5560
5561         if (i >= usec_timeout) {
5562                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5563                 return -EINVAL;
5564         }
5565
5566         if (amdgpu_emu_mode == 1)
5567                 adev->nbio.funcs->hdp_flush(adev, NULL);
5568
5569         tmp = RREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_CNTL);
5570         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, VMID, 0);
5571         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, CACHE_POLICY, 0);
5572         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, EXE_DISABLE, 0);
5573         tmp = REG_SET_FIELD(tmp, CP_CE_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
5574         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_LO,
5575                 adev->gfx.ce.ce_fw_gpu_addr & 0xFFFFF000);
5576         WREG32_SOC15(GC, 0, mmCP_CE_IC_BASE_HI,
5577                 upper_32_bits(adev->gfx.ce.ce_fw_gpu_addr));
5578
5579         WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, 0);
5580
5581         for (i = 0; i < ce_hdr->jt_size; i++)
5582                 WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_DATA,
5583                              le32_to_cpup(fw_data + ce_hdr->jt_offset + i));
5584
5585         WREG32_SOC15(GC, 0, mmCP_HYP_CE_UCODE_ADDR, adev->gfx.ce_fw_version);
5586
5587         return 0;
5588 }
5589
5590 static int gfx_v10_0_cp_gfx_load_me_microcode(struct amdgpu_device *adev)
5591 {
5592         int r;
5593         const struct gfx_firmware_header_v1_0 *me_hdr;
5594         const __le32 *fw_data;
5595         unsigned i, fw_size;
5596         uint32_t tmp;
5597         uint32_t usec_timeout = 50000;  /* wait for 50ms */
5598
5599         me_hdr = (const struct gfx_firmware_header_v1_0 *)
5600                 adev->gfx.me_fw->data;
5601
5602         amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
5603
5604         fw_data = (const __le32 *)(adev->gfx.me_fw->data +
5605                 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
5606         fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes);
5607
5608         r = amdgpu_bo_create_reserved(adev, me_hdr->header.ucode_size_bytes,
5609                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
5610                                       &adev->gfx.me.me_fw_obj,
5611                                       &adev->gfx.me.me_fw_gpu_addr,
5612                                       (void **)&adev->gfx.me.me_fw_ptr);
5613         if (r) {
5614                 dev_err(adev->dev, "(%d) failed to create me fw bo\n", r);
5615                 gfx_v10_0_me_fini(adev);
5616                 return r;
5617         }
5618
5619         memcpy(adev->gfx.me.me_fw_ptr, fw_data, fw_size);
5620
5621         amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj);
5622         amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj);
5623
5624         /* Trigger an invalidation of the L1 instruction caches */
5625         tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5626         tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5627         WREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL, tmp);
5628
5629         /* Wait for invalidation complete */
5630         for (i = 0; i < usec_timeout; i++) {
5631                 tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_OP_CNTL);
5632                 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
5633                         INVALIDATE_CACHE_COMPLETE))
5634                         break;
5635                 udelay(1);
5636         }
5637
5638         if (i >= usec_timeout) {
5639                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
5640                 return -EINVAL;
5641         }
5642
5643         if (amdgpu_emu_mode == 1)
5644                 adev->nbio.funcs->hdp_flush(adev, NULL);
5645
5646         tmp = RREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_CNTL);
5647         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0);
5648         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0);
5649         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0);
5650         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
5651         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_LO,
5652                 adev->gfx.me.me_fw_gpu_addr & 0xFFFFF000);
5653         WREG32_SOC15(GC, 0, mmCP_ME_IC_BASE_HI,
5654                 upper_32_bits(adev->gfx.me.me_fw_gpu_addr));
5655
5656         WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, 0);
5657
5658         for (i = 0; i < me_hdr->jt_size; i++)
5659                 WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_DATA,
5660                              le32_to_cpup(fw_data + me_hdr->jt_offset + i));
5661
5662         WREG32_SOC15(GC, 0, mmCP_HYP_ME_UCODE_ADDR, adev->gfx.me_fw_version);
5663
5664         return 0;
5665 }
5666
5667 static int gfx_v10_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
5668 {
5669         int r;
5670
5671         if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
5672                 return -EINVAL;
5673
5674         gfx_v10_0_cp_gfx_enable(adev, false);
5675
5676         r = gfx_v10_0_cp_gfx_load_pfp_microcode(adev);
5677         if (r) {
5678                 dev_err(adev->dev, "(%d) failed to load pfp fw\n", r);
5679                 return r;
5680         }
5681
5682         r = gfx_v10_0_cp_gfx_load_ce_microcode(adev);
5683         if (r) {
5684                 dev_err(adev->dev, "(%d) failed to load ce fw\n", r);
5685                 return r;
5686         }
5687
5688         r = gfx_v10_0_cp_gfx_load_me_microcode(adev);
5689         if (r) {
5690                 dev_err(adev->dev, "(%d) failed to load me fw\n", r);
5691                 return r;
5692         }
5693
5694         return 0;
5695 }
5696
5697 static int gfx_v10_0_cp_gfx_start(struct amdgpu_device *adev)
5698 {
5699         struct amdgpu_ring *ring;
5700         const struct cs_section_def *sect = NULL;
5701         const struct cs_extent_def *ext = NULL;
5702         int r, i;
5703         int ctx_reg_offset;
5704
5705         /* init the CP */
5706         WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT,
5707                      adev->gfx.config.max_hw_contexts - 1);
5708         WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1);
5709
5710         gfx_v10_0_cp_gfx_enable(adev, true);
5711
5712         ring = &adev->gfx.gfx_ring[0];
5713         r = amdgpu_ring_alloc(ring, gfx_v10_0_get_csb_size(adev) + 4);
5714         if (r) {
5715                 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
5716                 return r;
5717         }
5718
5719         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
5720         amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
5721
5722         amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
5723         amdgpu_ring_write(ring, 0x80000000);
5724         amdgpu_ring_write(ring, 0x80000000);
5725
5726         for (sect = gfx10_cs_data; sect->section != NULL; ++sect) {
5727                 for (ext = sect->section; ext->extent != NULL; ++ext) {
5728                         if (sect->id == SECT_CONTEXT) {
5729                                 amdgpu_ring_write(ring,
5730                                                   PACKET3(PACKET3_SET_CONTEXT_REG,
5731                                                           ext->reg_count));
5732                                 amdgpu_ring_write(ring, ext->reg_index -
5733                                                   PACKET3_SET_CONTEXT_REG_START);
5734                                 for (i = 0; i < ext->reg_count; i++)
5735                                         amdgpu_ring_write(ring, ext->extent[i]);
5736                         }
5737                 }
5738         }
5739
5740         ctx_reg_offset =
5741                 SOC15_REG_OFFSET(GC, 0, mmPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;
5742         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
5743         amdgpu_ring_write(ring, ctx_reg_offset);
5744         amdgpu_ring_write(ring, adev->gfx.config.pa_sc_tile_steering_override);
5745
5746         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
5747         amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
5748
5749         amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
5750         amdgpu_ring_write(ring, 0);
5751
5752         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
5753         amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
5754         amdgpu_ring_write(ring, 0x8000);
5755         amdgpu_ring_write(ring, 0x8000);
5756
5757         amdgpu_ring_commit(ring);
5758
5759         /* submit cs packet to copy state 0 to next available state */
5760         if (adev->gfx.num_gfx_rings > 1) {
5761                 /* maximum supported gfx ring is 2 */
5762                 ring = &adev->gfx.gfx_ring[1];
5763                 r = amdgpu_ring_alloc(ring, 2);
5764                 if (r) {
5765                         DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
5766                         return r;
5767                 }
5768
5769                 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
5770                 amdgpu_ring_write(ring, 0);
5771
5772                 amdgpu_ring_commit(ring);
5773         }
5774         return 0;
5775 }
5776
5777 static void gfx_v10_0_cp_gfx_switch_pipe(struct amdgpu_device *adev,
5778                                          CP_PIPE_ID pipe)
5779 {
5780         u32 tmp;
5781
5782         tmp = RREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL);
5783         tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe);
5784
5785         WREG32_SOC15(GC, 0, mmGRBM_GFX_CNTL, tmp);
5786 }
5787
5788 static void gfx_v10_0_cp_gfx_set_doorbell(struct amdgpu_device *adev,
5789                                           struct amdgpu_ring *ring)
5790 {
5791         u32 tmp;
5792
5793         tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
5794         if (ring->use_doorbell) {
5795                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
5796                                     DOORBELL_OFFSET, ring->doorbell_index);
5797                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
5798                                     DOORBELL_EN, 1);
5799         } else {
5800                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
5801                                     DOORBELL_EN, 0);
5802         }
5803         WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp);
5804         switch (adev->asic_type) {
5805         case CHIP_SIENNA_CICHLID:
5806         case CHIP_NAVY_FLOUNDER:
5807                 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
5808                                     DOORBELL_RANGE_LOWER_Sienna_Cichlid, ring->doorbell_index);
5809                 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
5810
5811                 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,
5812                              CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_Sienna_Cichlid_MASK);
5813                 break;
5814         default:
5815                 tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
5816                                     DOORBELL_RANGE_LOWER, ring->doorbell_index);
5817                 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
5818
5819                 WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,
5820                              CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
5821                 break;
5822         }
5823 }
5824
5825 static int gfx_v10_0_cp_gfx_resume(struct amdgpu_device *adev)
5826 {
5827         struct amdgpu_ring *ring;
5828         u32 tmp;
5829         u32 rb_bufsz;
5830         u64 rb_addr, rptr_addr, wptr_gpu_addr;
5831         u32 i;
5832
5833         /* Set the write pointer delay */
5834         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0);
5835
5836         /* set the RB to use vmid 0 */
5837         WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0);
5838
5839         /* Init gfx ring 0 for pipe 0 */
5840         mutex_lock(&adev->srbm_mutex);
5841         gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
5842
5843         /* Set ring buffer size */
5844         ring = &adev->gfx.gfx_ring[0];
5845         rb_bufsz = order_base_2(ring->ring_size / 8);
5846         tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
5847         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
5848 #ifdef __BIG_ENDIAN
5849         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
5850 #endif
5851         WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
5852
5853         /* Initialize the ring buffer's write pointers */
5854         ring->wptr = 0;
5855         WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
5856         WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
5857
5858         /* set the wb address wether it's enabled or not */
5859         rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
5860         WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
5861         WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
5862                      CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
5863
5864         wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
5865         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO,
5866                      lower_32_bits(wptr_gpu_addr));
5867         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI,
5868                      upper_32_bits(wptr_gpu_addr));
5869
5870         mdelay(1);
5871         WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
5872
5873         rb_addr = ring->gpu_addr >> 8;
5874         WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr);
5875         WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
5876
5877         WREG32_SOC15(GC, 0, mmCP_RB_ACTIVE, 1);
5878
5879         gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
5880         mutex_unlock(&adev->srbm_mutex);
5881
5882         /* Init gfx ring 1 for pipe 1 */
5883         if (adev->gfx.num_gfx_rings > 1) {
5884                 mutex_lock(&adev->srbm_mutex);
5885                 gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID1);
5886                 /* maximum supported gfx ring is 2 */
5887                 ring = &adev->gfx.gfx_ring[1];
5888                 rb_bufsz = order_base_2(ring->ring_size / 8);
5889                 tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz);
5890                 tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2);
5891                 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp);
5892                 /* Initialize the ring buffer's write pointers */
5893                 ring->wptr = 0;
5894                 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR, lower_32_bits(ring->wptr));
5895                 WREG32_SOC15(GC, 0, mmCP_RB1_WPTR_HI, upper_32_bits(ring->wptr));
5896                 /* Set the wb address wether it's enabled or not */
5897                 rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
5898                 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr));
5899                 WREG32_SOC15(GC, 0, mmCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
5900                              CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
5901                 wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
5902                 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO,
5903                              lower_32_bits(wptr_gpu_addr));
5904                 WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI,
5905                              upper_32_bits(wptr_gpu_addr));
5906
5907                 mdelay(1);
5908                 WREG32_SOC15(GC, 0, mmCP_RB1_CNTL, tmp);
5909
5910                 rb_addr = ring->gpu_addr >> 8;
5911                 WREG32_SOC15(GC, 0, mmCP_RB1_BASE, rb_addr);
5912                 WREG32_SOC15(GC, 0, mmCP_RB1_BASE_HI, upper_32_bits(rb_addr));
5913                 WREG32_SOC15(GC, 0, mmCP_RB1_ACTIVE, 1);
5914
5915                 gfx_v10_0_cp_gfx_set_doorbell(adev, ring);
5916                 mutex_unlock(&adev->srbm_mutex);
5917         }
5918         /* Switch to pipe 0 */
5919         mutex_lock(&adev->srbm_mutex);
5920         gfx_v10_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
5921         mutex_unlock(&adev->srbm_mutex);
5922
5923         /* start the ring */
5924         gfx_v10_0_cp_gfx_start(adev);
5925
5926         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
5927                 ring = &adev->gfx.gfx_ring[i];
5928                 ring->sched.ready = true;
5929         }
5930
5931         return 0;
5932 }
5933
5934 static void gfx_v10_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
5935 {
5936         if (enable) {
5937                 switch (adev->asic_type) {
5938                 case CHIP_SIENNA_CICHLID:
5939                 case CHIP_NAVY_FLOUNDER:
5940                         WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid, 0);
5941                         break;
5942                 default:
5943                         WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0);
5944                         break;
5945                 }
5946         } else {
5947                 switch (adev->asic_type) {
5948                 case CHIP_SIENNA_CICHLID:
5949                 case CHIP_NAVY_FLOUNDER:
5950                         WREG32_SOC15(GC, 0, mmCP_MEC_CNTL_Sienna_Cichlid,
5951                                      (CP_MEC_CNTL__MEC_ME1_HALT_MASK |
5952                                       CP_MEC_CNTL__MEC_ME2_HALT_MASK));
5953                         break;
5954                 default:
5955                         WREG32_SOC15(GC, 0, mmCP_MEC_CNTL,
5956                                      (CP_MEC_CNTL__MEC_ME1_HALT_MASK |
5957                                       CP_MEC_CNTL__MEC_ME2_HALT_MASK));
5958                         break;
5959                 }
5960                 adev->gfx.kiq.ring.sched.ready = false;
5961         }
5962         udelay(50);
5963 }
5964
5965 static int gfx_v10_0_cp_compute_load_microcode(struct amdgpu_device *adev)
5966 {
5967         const struct gfx_firmware_header_v1_0 *mec_hdr;
5968         const __le32 *fw_data;
5969         unsigned i;
5970         u32 tmp;
5971         u32 usec_timeout = 50000; /* Wait for 50 ms */
5972
5973         if (!adev->gfx.mec_fw)
5974                 return -EINVAL;
5975
5976         gfx_v10_0_cp_compute_enable(adev, false);
5977
5978         mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
5979         amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
5980
5981         fw_data = (const __le32 *)
5982                 (adev->gfx.mec_fw->data +
5983                  le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
5984
5985         /* Trigger an invalidation of the L1 instruction caches */
5986         tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
5987         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
5988         WREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL, tmp);
5989
5990         /* Wait for invalidation complete */
5991         for (i = 0; i < usec_timeout; i++) {
5992                 tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_OP_CNTL);
5993                 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
5994                                        INVALIDATE_CACHE_COMPLETE))
5995                         break;
5996                 udelay(1);
5997         }
5998
5999         if (i >= usec_timeout) {
6000                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
6001                 return -EINVAL;
6002         }
6003
6004         if (amdgpu_emu_mode == 1)
6005                 adev->nbio.funcs->hdp_flush(adev, NULL);
6006
6007         tmp = RREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL);
6008         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
6009         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0);
6010         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
6011         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp);
6012
6013         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr &
6014                      0xFFFFF000);
6015         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
6016                      upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr));
6017
6018         /* MEC1 */
6019         WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, 0);
6020
6021         for (i = 0; i < mec_hdr->jt_size; i++)
6022                 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA,
6023                              le32_to_cpup(fw_data + mec_hdr->jt_offset + i));
6024
6025         WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version);
6026
6027         /*
6028          * TODO: Loading MEC2 firmware is only necessary if MEC2 should run
6029          * different microcode than MEC1.
6030          */
6031
6032         return 0;
6033 }
6034
6035 static void gfx_v10_0_kiq_setting(struct amdgpu_ring *ring)
6036 {
6037         uint32_t tmp;
6038         struct amdgpu_device *adev = ring->adev;
6039
6040         /* tell RLC which is KIQ queue */
6041         switch (adev->asic_type) {
6042         case CHIP_SIENNA_CICHLID:
6043         case CHIP_NAVY_FLOUNDER:
6044                 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid);
6045                 tmp &= 0xffffff00;
6046                 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
6047                 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp);
6048                 tmp |= 0x80;
6049                 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS_Sienna_Cichlid, tmp);
6050                 break;
6051         default:
6052                 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
6053                 tmp &= 0xffffff00;
6054                 tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
6055                 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
6056                 tmp |= 0x80;
6057                 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
6058                 break;
6059         }
6060 }
6061
6062 static int gfx_v10_0_gfx_mqd_init(struct amdgpu_ring *ring)
6063 {
6064         struct amdgpu_device *adev = ring->adev;
6065         struct v10_gfx_mqd *mqd = ring->mqd_ptr;
6066         uint64_t hqd_gpu_addr, wb_gpu_addr;
6067         uint32_t tmp;
6068         uint32_t rb_bufsz;
6069
6070         /* set up gfx hqd wptr */
6071         mqd->cp_gfx_hqd_wptr = 0;
6072         mqd->cp_gfx_hqd_wptr_hi = 0;
6073
6074         /* set the pointer to the MQD */
6075         mqd->cp_mqd_base_addr = ring->mqd_gpu_addr & 0xfffffffc;
6076         mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
6077
6078         /* set up mqd control */
6079         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL);
6080         tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0);
6081         tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1);
6082         tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0);
6083         mqd->cp_gfx_mqd_control = tmp;
6084
6085         /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */
6086         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID);
6087         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0);
6088         mqd->cp_gfx_hqd_vmid = 0;
6089
6090         /* set up default queue priority level
6091          * 0x0 = low priority, 0x1 = high priority */
6092         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY);
6093         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, 0);
6094         mqd->cp_gfx_hqd_queue_priority = tmp;
6095
6096         /* set up time quantum */
6097         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM);
6098         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1);
6099         mqd->cp_gfx_hqd_quantum = tmp;
6100
6101         /* set up gfx hqd base. this is similar as CP_RB_BASE */
6102         hqd_gpu_addr = ring->gpu_addr >> 8;
6103         mqd->cp_gfx_hqd_base = hqd_gpu_addr;
6104         mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr);
6105
6106         /* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */
6107         wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
6108         mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc;
6109         mqd->cp_gfx_hqd_rptr_addr_hi =
6110                 upper_32_bits(wb_gpu_addr) & 0xffff;
6111
6112         /* set up rb_wptr_poll addr */
6113         wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
6114         mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
6115         mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
6116
6117         /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */
6118         rb_bufsz = order_base_2(ring->ring_size / 4) - 1;
6119         tmp = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL);
6120         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz);
6121         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2);
6122 #ifdef __BIG_ENDIAN
6123         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1);
6124 #endif
6125         mqd->cp_gfx_hqd_cntl = tmp;
6126
6127         /* set up cp_doorbell_control */
6128         tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
6129         if (ring->use_doorbell) {
6130                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6131                                     DOORBELL_OFFSET, ring->doorbell_index);
6132                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6133                                     DOORBELL_EN, 1);
6134         } else
6135                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
6136                                     DOORBELL_EN, 0);
6137         mqd->cp_rb_doorbell_control = tmp;
6138
6139         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
6140         ring->wptr = 0;
6141         mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR);
6142
6143         /* active the queue */
6144         mqd->cp_gfx_hqd_active = 1;
6145
6146         return 0;
6147 }
6148
6149 #ifdef BRING_UP_DEBUG
6150 static int gfx_v10_0_gfx_queue_init_register(struct amdgpu_ring *ring)
6151 {
6152         struct amdgpu_device *adev = ring->adev;
6153         struct v10_gfx_mqd *mqd = ring->mqd_ptr;
6154
6155         /* set mmCP_GFX_HQD_WPTR/_HI to 0 */
6156         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR, mqd->cp_gfx_hqd_wptr);
6157         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_WPTR_HI, mqd->cp_gfx_hqd_wptr_hi);
6158
6159         /* set GFX_MQD_BASE */
6160         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR, mqd->cp_mqd_base_addr);
6161         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI, mqd->cp_mqd_base_addr_hi);
6162
6163         /* set GFX_MQD_CONTROL */
6164         WREG32_SOC15(GC, 0, mmCP_GFX_MQD_CONTROL, mqd->cp_gfx_mqd_control);
6165
6166         /* set GFX_HQD_VMID to 0 */
6167         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_VMID, mqd->cp_gfx_hqd_vmid);
6168
6169         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUEUE_PRIORITY,
6170                         mqd->cp_gfx_hqd_queue_priority);
6171         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_QUANTUM, mqd->cp_gfx_hqd_quantum);
6172
6173         /* set GFX_HQD_BASE, similar as CP_RB_BASE */
6174         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE, mqd->cp_gfx_hqd_base);
6175         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_BASE_HI, mqd->cp_gfx_hqd_base_hi);
6176
6177         /* set GFX_HQD_RPTR_ADDR, similar as CP_RB_RPTR */
6178         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR, mqd->cp_gfx_hqd_rptr_addr);
6179         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_RPTR_ADDR_HI, mqd->cp_gfx_hqd_rptr_addr_hi);
6180
6181         /* set GFX_HQD_CNTL, similar as CP_RB_CNTL */
6182         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_CNTL, mqd->cp_gfx_hqd_cntl);
6183
6184         /* set RB_WPTR_POLL_ADDR */
6185         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, mqd->cp_rb_wptr_poll_addr_lo);
6186         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, mqd->cp_rb_wptr_poll_addr_hi);
6187
6188         /* set RB_DOORBELL_CONTROL */
6189         WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, mqd->cp_rb_doorbell_control);
6190
6191         /* active the queue */
6192         WREG32_SOC15(GC, 0, mmCP_GFX_HQD_ACTIVE, mqd->cp_gfx_hqd_active);
6193
6194         return 0;
6195 }
6196 #endif
6197
6198 static int gfx_v10_0_gfx_init_queue(struct amdgpu_ring *ring)
6199 {
6200         struct amdgpu_device *adev = ring->adev;
6201         struct v10_gfx_mqd *mqd = ring->mqd_ptr;
6202         int mqd_idx = ring - &adev->gfx.gfx_ring[0];
6203
6204         if (!amdgpu_in_reset(adev) && !adev->in_suspend) {
6205                 memset((void *)mqd, 0, sizeof(*mqd));
6206                 mutex_lock(&adev->srbm_mutex);
6207                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6208                 gfx_v10_0_gfx_mqd_init(ring);
6209 #ifdef BRING_UP_DEBUG
6210                 gfx_v10_0_gfx_queue_init_register(ring);
6211 #endif
6212                 nv_grbm_select(adev, 0, 0, 0, 0);
6213                 mutex_unlock(&adev->srbm_mutex);
6214                 if (adev->gfx.me.mqd_backup[mqd_idx])
6215                         memcpy(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
6216         } else if (amdgpu_in_reset(adev)) {
6217                 /* reset mqd with the backup copy */
6218                 if (adev->gfx.me.mqd_backup[mqd_idx])
6219                         memcpy(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd));
6220                 /* reset the ring */
6221                 ring->wptr = 0;
6222                 adev->wb.wb[ring->wptr_offs] = 0;
6223                 amdgpu_ring_clear_ring(ring);
6224 #ifdef BRING_UP_DEBUG
6225                 mutex_lock(&adev->srbm_mutex);
6226                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6227                 gfx_v10_0_gfx_queue_init_register(ring);
6228                 nv_grbm_select(adev, 0, 0, 0, 0);
6229                 mutex_unlock(&adev->srbm_mutex);
6230 #endif
6231         } else {
6232                 amdgpu_ring_clear_ring(ring);
6233         }
6234
6235         return 0;
6236 }
6237
6238 #ifndef BRING_UP_DEBUG
6239 static int gfx_v10_0_kiq_enable_kgq(struct amdgpu_device *adev)
6240 {
6241         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
6242         struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring;
6243         int r, i;
6244
6245         if (!kiq->pmf || !kiq->pmf->kiq_map_queues)
6246                 return -EINVAL;
6247
6248         r = amdgpu_ring_alloc(kiq_ring, kiq->pmf->map_queues_size *
6249                                         adev->gfx.num_gfx_rings);
6250         if (r) {
6251                 DRM_ERROR("Failed to lock KIQ (%d).\n", r);
6252                 return r;
6253         }
6254
6255         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
6256                 kiq->pmf->kiq_map_queues(kiq_ring, &adev->gfx.gfx_ring[i]);
6257
6258         return amdgpu_ring_test_helper(kiq_ring);
6259 }
6260 #endif
6261
6262 static int gfx_v10_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev)
6263 {
6264         int r, i;
6265         struct amdgpu_ring *ring;
6266
6267         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
6268                 ring = &adev->gfx.gfx_ring[i];
6269
6270                 r = amdgpu_bo_reserve(ring->mqd_obj, false);
6271                 if (unlikely(r != 0))
6272                         goto done;
6273
6274                 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
6275                 if (!r) {
6276                         r = gfx_v10_0_gfx_init_queue(ring);
6277                         amdgpu_bo_kunmap(ring->mqd_obj);
6278                         ring->mqd_ptr = NULL;
6279                 }
6280                 amdgpu_bo_unreserve(ring->mqd_obj);
6281                 if (r)
6282                         goto done;
6283         }
6284 #ifndef BRING_UP_DEBUG
6285         r = gfx_v10_0_kiq_enable_kgq(adev);
6286         if (r)
6287                 goto done;
6288 #endif
6289         r = gfx_v10_0_cp_gfx_start(adev);
6290         if (r)
6291                 goto done;
6292
6293         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
6294                 ring = &adev->gfx.gfx_ring[i];
6295                 ring->sched.ready = true;
6296         }
6297 done:
6298         return r;
6299 }
6300
6301 static void gfx_v10_0_compute_mqd_set_priority(struct amdgpu_ring *ring, struct v10_compute_mqd *mqd)
6302 {
6303         struct amdgpu_device *adev = ring->adev;
6304
6305         if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
6306                 if (amdgpu_gfx_is_high_priority_compute_queue(adev, ring->queue)) {
6307                         mqd->cp_hqd_pipe_priority = AMDGPU_GFX_PIPE_PRIO_HIGH;
6308                         mqd->cp_hqd_queue_priority =
6309                                 AMDGPU_GFX_QUEUE_PRIORITY_MAXIMUM;
6310                 }
6311         }
6312 }
6313
6314 static int gfx_v10_0_compute_mqd_init(struct amdgpu_ring *ring)
6315 {
6316         struct amdgpu_device *adev = ring->adev;
6317         struct v10_compute_mqd *mqd = ring->mqd_ptr;
6318         uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;
6319         uint32_t tmp;
6320
6321         mqd->header = 0xC0310800;
6322         mqd->compute_pipelinestat_enable = 0x00000001;
6323         mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
6324         mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
6325         mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
6326         mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
6327         mqd->compute_misc_reserved = 0x00000003;
6328
6329         eop_base_addr = ring->eop_gpu_addr >> 8;
6330         mqd->cp_hqd_eop_base_addr_lo = eop_base_addr;
6331         mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
6332
6333         /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
6334         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL);
6335         tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
6336                         (order_base_2(GFX10_MEC_HPD_SIZE / 4) - 1));
6337
6338         mqd->cp_hqd_eop_control = tmp;
6339
6340         /* enable doorbell? */
6341         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
6342
6343         if (ring->use_doorbell) {
6344                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6345                                     DOORBELL_OFFSET, ring->doorbell_index);
6346                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6347                                     DOORBELL_EN, 1);
6348                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6349                                     DOORBELL_SOURCE, 0);
6350                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6351                                     DOORBELL_HIT, 0);
6352         } else {
6353                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6354                                     DOORBELL_EN, 0);
6355         }
6356
6357         mqd->cp_hqd_pq_doorbell_control = tmp;
6358
6359         /* disable the queue if it's active */
6360         ring->wptr = 0;
6361         mqd->cp_hqd_dequeue_request = 0;
6362         mqd->cp_hqd_pq_rptr = 0;
6363         mqd->cp_hqd_pq_wptr_lo = 0;
6364         mqd->cp_hqd_pq_wptr_hi = 0;
6365
6366         /* set the pointer to the MQD */
6367         mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc;
6368         mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
6369
6370         /* set MQD vmid to 0 */
6371         tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL);
6372         tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
6373         mqd->cp_mqd_control = tmp;
6374
6375         /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
6376         hqd_gpu_addr = ring->gpu_addr >> 8;
6377         mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
6378         mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
6379
6380         /* set up the HQD, this is similar to CP_RB0_CNTL */
6381         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL);
6382         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
6383                             (order_base_2(ring->ring_size / 4) - 1));
6384         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
6385                             ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));
6386 #ifdef __BIG_ENDIAN
6387         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
6388 #endif
6389         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
6390         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0);
6391         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
6392         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
6393         mqd->cp_hqd_pq_control = tmp;
6394
6395         /* set the wb address whether it's enabled or not */
6396         wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
6397         mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
6398         mqd->cp_hqd_pq_rptr_report_addr_hi =
6399                 upper_32_bits(wb_gpu_addr) & 0xffff;
6400
6401         /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
6402         wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
6403         mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
6404         mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
6405
6406         tmp = 0;
6407         /* enable the doorbell if requested */
6408         if (ring->use_doorbell) {
6409                 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
6410                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6411                                 DOORBELL_OFFSET, ring->doorbell_index);
6412
6413                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6414                                     DOORBELL_EN, 1);
6415                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6416                                     DOORBELL_SOURCE, 0);
6417                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
6418                                     DOORBELL_HIT, 0);
6419         }
6420
6421         mqd->cp_hqd_pq_doorbell_control = tmp;
6422
6423         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
6424         ring->wptr = 0;
6425         mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR);
6426
6427         /* set the vmid for the queue */
6428         mqd->cp_hqd_vmid = 0;
6429
6430         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE);
6431         tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
6432         mqd->cp_hqd_persistent_state = tmp;
6433
6434         /* set MIN_IB_AVAIL_SIZE */
6435         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL);
6436         tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
6437         mqd->cp_hqd_ib_control = tmp;
6438
6439         /* set static priority for a compute queue/ring */
6440         gfx_v10_0_compute_mqd_set_priority(ring, mqd);
6441
6442         /* map_queues packet doesn't need activate the queue,
6443          * so only kiq need set this field.
6444          */
6445         if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ)
6446                 mqd->cp_hqd_active = 1;
6447
6448         return 0;
6449 }
6450
6451 static int gfx_v10_0_kiq_init_register(struct amdgpu_ring *ring)
6452 {
6453         struct amdgpu_device *adev = ring->adev;
6454         struct v10_compute_mqd *mqd = ring->mqd_ptr;
6455         int j;
6456
6457         /* inactivate the queue */
6458         if (amdgpu_sriov_vf(adev))
6459                 WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 0);
6460
6461         /* disable wptr polling */
6462         WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
6463
6464         /* write the EOP addr */
6465         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR,
6466                mqd->cp_hqd_eop_base_addr_lo);
6467         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI,
6468                mqd->cp_hqd_eop_base_addr_hi);
6469
6470         /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
6471         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL,
6472                mqd->cp_hqd_eop_control);
6473
6474         /* enable doorbell? */
6475         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
6476                mqd->cp_hqd_pq_doorbell_control);
6477
6478         /* disable the queue if it's active */
6479         if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) {
6480                 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1);
6481                 for (j = 0; j < adev->usec_timeout; j++) {
6482                         if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))
6483                                 break;
6484                         udelay(1);
6485                 }
6486                 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST,
6487                        mqd->cp_hqd_dequeue_request);
6488                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR,
6489                        mqd->cp_hqd_pq_rptr);
6490                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
6491                        mqd->cp_hqd_pq_wptr_lo);
6492                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
6493                        mqd->cp_hqd_pq_wptr_hi);
6494         }
6495
6496         /* set the pointer to the MQD */
6497         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR,
6498                mqd->cp_mqd_base_addr_lo);
6499         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI,
6500                mqd->cp_mqd_base_addr_hi);
6501
6502         /* set MQD vmid to 0 */
6503         WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL,
6504                mqd->cp_mqd_control);
6505
6506         /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
6507         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE,
6508                mqd->cp_hqd_pq_base_lo);
6509         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI,
6510                mqd->cp_hqd_pq_base_hi);
6511
6512         /* set up the HQD, this is similar to CP_RB0_CNTL */
6513         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL,
6514                mqd->cp_hqd_pq_control);
6515
6516         /* set the wb address whether it's enabled or not */
6517         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR,
6518                 mqd->cp_hqd_pq_rptr_report_addr_lo);
6519         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
6520                 mqd->cp_hqd_pq_rptr_report_addr_hi);
6521
6522         /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
6523         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR,
6524                mqd->cp_hqd_pq_wptr_poll_addr_lo);
6525         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
6526                mqd->cp_hqd_pq_wptr_poll_addr_hi);
6527
6528         /* enable the doorbell if requested */
6529         if (ring->use_doorbell) {
6530                 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER,
6531                         (adev->doorbell_index.kiq * 2) << 2);
6532                 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER,
6533                         (adev->doorbell_index.userqueue_end * 2) << 2);
6534         }
6535
6536         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
6537                mqd->cp_hqd_pq_doorbell_control);
6538
6539         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
6540         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
6541                mqd->cp_hqd_pq_wptr_lo);
6542         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
6543                mqd->cp_hqd_pq_wptr_hi);
6544
6545         /* set the vmid for the queue */
6546         WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid);
6547
6548         WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE,
6549                mqd->cp_hqd_persistent_state);
6550
6551         /* activate the queue */
6552         WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE,
6553                mqd->cp_hqd_active);
6554
6555         if (ring->use_doorbell)
6556                 WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
6557
6558         return 0;
6559 }
6560
6561 static int gfx_v10_0_kiq_init_queue(struct amdgpu_ring *ring)
6562 {
6563         struct amdgpu_device *adev = ring->adev;
6564         struct v10_compute_mqd *mqd = ring->mqd_ptr;
6565         int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS;
6566
6567         gfx_v10_0_kiq_setting(ring);
6568
6569         if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */
6570                 /* reset MQD to a clean status */
6571                 if (adev->gfx.mec.mqd_backup[mqd_idx])
6572                         memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
6573
6574                 /* reset ring buffer */
6575                 ring->wptr = 0;
6576                 amdgpu_ring_clear_ring(ring);
6577
6578                 mutex_lock(&adev->srbm_mutex);
6579                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6580                 gfx_v10_0_kiq_init_register(ring);
6581                 nv_grbm_select(adev, 0, 0, 0, 0);
6582                 mutex_unlock(&adev->srbm_mutex);
6583         } else {
6584                 memset((void *)mqd, 0, sizeof(*mqd));
6585                 mutex_lock(&adev->srbm_mutex);
6586                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6587                 gfx_v10_0_compute_mqd_init(ring);
6588                 gfx_v10_0_kiq_init_register(ring);
6589                 nv_grbm_select(adev, 0, 0, 0, 0);
6590                 mutex_unlock(&adev->srbm_mutex);
6591
6592                 if (adev->gfx.mec.mqd_backup[mqd_idx])
6593                         memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
6594         }
6595
6596         return 0;
6597 }
6598
6599 static int gfx_v10_0_kcq_init_queue(struct amdgpu_ring *ring)
6600 {
6601         struct amdgpu_device *adev = ring->adev;
6602         struct v10_compute_mqd *mqd = ring->mqd_ptr;
6603         int mqd_idx = ring - &adev->gfx.compute_ring[0];
6604
6605         if (!amdgpu_in_reset(adev) && !adev->in_suspend) {
6606                 memset((void *)mqd, 0, sizeof(*mqd));
6607                 mutex_lock(&adev->srbm_mutex);
6608                 nv_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
6609                 gfx_v10_0_compute_mqd_init(ring);
6610                 nv_grbm_select(adev, 0, 0, 0, 0);
6611                 mutex_unlock(&adev->srbm_mutex);
6612
6613                 if (adev->gfx.mec.mqd_backup[mqd_idx])
6614                         memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
6615         } else if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */
6616                 /* reset MQD to a clean status */
6617                 if (adev->gfx.mec.mqd_backup[mqd_idx])
6618                         memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
6619
6620                 /* reset ring buffer */
6621                 ring->wptr = 0;
6622                 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], 0);
6623                 amdgpu_ring_clear_ring(ring);
6624         } else {
6625                 amdgpu_ring_clear_ring(ring);
6626         }
6627
6628         return 0;
6629 }
6630
6631 static int gfx_v10_0_kiq_resume(struct amdgpu_device *adev)
6632 {
6633         struct amdgpu_ring *ring;
6634         int r;
6635
6636         ring = &adev->gfx.kiq.ring;
6637
6638         r = amdgpu_bo_reserve(ring->mqd_obj, false);
6639         if (unlikely(r != 0))
6640                 return r;
6641
6642         r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
6643         if (unlikely(r != 0))
6644                 return r;
6645
6646         gfx_v10_0_kiq_init_queue(ring);
6647         amdgpu_bo_kunmap(ring->mqd_obj);
6648         ring->mqd_ptr = NULL;
6649         amdgpu_bo_unreserve(ring->mqd_obj);
6650         ring->sched.ready = true;
6651         return 0;
6652 }
6653
6654 static int gfx_v10_0_kcq_resume(struct amdgpu_device *adev)
6655 {
6656         struct amdgpu_ring *ring = NULL;
6657         int r = 0, i;
6658
6659         gfx_v10_0_cp_compute_enable(adev, true);
6660
6661         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
6662                 ring = &adev->gfx.compute_ring[i];
6663
6664                 r = amdgpu_bo_reserve(ring->mqd_obj, false);
6665                 if (unlikely(r != 0))
6666                         goto done;
6667                 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
6668                 if (!r) {
6669                         r = gfx_v10_0_kcq_init_queue(ring);
6670                         amdgpu_bo_kunmap(ring->mqd_obj);
6671                         ring->mqd_ptr = NULL;
6672                 }
6673                 amdgpu_bo_unreserve(ring->mqd_obj);
6674                 if (r)
6675                         goto done;
6676         }
6677
6678         r = amdgpu_gfx_enable_kcq(adev);
6679 done:
6680         return r;
6681 }
6682
6683 static int gfx_v10_0_cp_resume(struct amdgpu_device *adev)
6684 {
6685         int r, i;
6686         struct amdgpu_ring *ring;
6687
6688         if (!(adev->flags & AMD_IS_APU))
6689                 gfx_v10_0_enable_gui_idle_interrupt(adev, false);
6690
6691         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
6692                 /* legacy firmware loading */
6693                 r = gfx_v10_0_cp_gfx_load_microcode(adev);
6694                 if (r)
6695                         return r;
6696
6697                 r = gfx_v10_0_cp_compute_load_microcode(adev);
6698                 if (r)
6699                         return r;
6700         }
6701
6702         r = gfx_v10_0_kiq_resume(adev);
6703         if (r)
6704                 return r;
6705
6706         r = gfx_v10_0_kcq_resume(adev);
6707         if (r)
6708                 return r;
6709
6710         if (!amdgpu_async_gfx_ring) {
6711                 r = gfx_v10_0_cp_gfx_resume(adev);
6712                 if (r)
6713                         return r;
6714         } else {
6715                 r = gfx_v10_0_cp_async_gfx_ring_resume(adev);
6716                 if (r)
6717                         return r;
6718         }
6719
6720         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
6721                 ring = &adev->gfx.gfx_ring[i];
6722                 r = amdgpu_ring_test_helper(ring);
6723                 if (r)
6724                         return r;
6725         }
6726
6727         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
6728                 ring = &adev->gfx.compute_ring[i];
6729                 r = amdgpu_ring_test_helper(ring);
6730                 if (r)
6731                         return r;
6732         }
6733
6734         return 0;
6735 }
6736
6737 static void gfx_v10_0_cp_enable(struct amdgpu_device *adev, bool enable)
6738 {
6739         gfx_v10_0_cp_gfx_enable(adev, enable);
6740         gfx_v10_0_cp_compute_enable(adev, enable);
6741 }
6742
6743 static bool gfx_v10_0_check_grbm_cam_remapping(struct amdgpu_device *adev)
6744 {
6745         uint32_t data, pattern = 0xDEADBEEF;
6746
6747         /* check if mmVGT_ESGS_RING_SIZE_UMD
6748          * has been remapped to mmVGT_ESGS_RING_SIZE */
6749         switch (adev->asic_type) {
6750         case CHIP_SIENNA_CICHLID:
6751         case CHIP_NAVY_FLOUNDER:
6752                 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid);
6753                 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, 0);
6754                 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern);
6755
6756                 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) == pattern) {
6757                         WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD , data);
6758                         return true;
6759                 } else {
6760                         WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid, data);
6761                         return false;
6762                 }
6763                 break;
6764         default:
6765                 data = RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE);
6766                 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, 0);
6767                 WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, pattern);
6768
6769                 if (RREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE) == pattern) {
6770                         WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE_UMD, data);
6771                         return true;
6772                 } else {
6773                         WREG32_SOC15(GC, 0, mmVGT_ESGS_RING_SIZE, data);
6774                         return false;
6775                 }
6776                 break;
6777         }
6778 }
6779
6780 static void gfx_v10_0_setup_grbm_cam_remapping(struct amdgpu_device *adev)
6781 {
6782         uint32_t data;
6783
6784         /* initialize cam_index to 0
6785          * index will auto-inc after each data writting */
6786         WREG32_SOC15(GC, 0, mmGRBM_CAM_INDEX, 0);
6787
6788         switch (adev->asic_type) {
6789         case CHIP_SIENNA_CICHLID:
6790         case CHIP_NAVY_FLOUNDER:
6791                 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */
6792                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) <<
6793                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6794                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_Sienna_Cichlid) <<
6795                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6796                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6797                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6798
6799                 /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */
6800                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) <<
6801                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6802                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_Sienna_Cichlid) <<
6803                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6804                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6805                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6806
6807                 /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */
6808                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) <<
6809                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6810                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_Sienna_Cichlid) <<
6811                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6812                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6813                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6814
6815                 /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */
6816                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) <<
6817                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6818                        (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_Sienna_Cichlid) <<
6819                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6820                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6821                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6822
6823                 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */
6824                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) <<
6825                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6826                        (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_Sienna_Cichlid) <<
6827                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6828                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6829                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6830
6831                 /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */
6832                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) <<
6833                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6834                        (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_Sienna_Cichlid) <<
6835                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6836                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6837                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6838
6839                 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */
6840                 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) <<
6841                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6842                        (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_Sienna_Cichlid) <<
6843                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6844                 break;
6845         default:
6846                 /* mmVGT_TF_RING_SIZE_UMD -> mmVGT_TF_RING_SIZE */
6847                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE_UMD) <<
6848                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6849                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_RING_SIZE) <<
6850                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6851                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6852                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6853
6854                 /* mmVGT_TF_MEMORY_BASE_UMD -> mmVGT_TF_MEMORY_BASE */
6855                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_UMD) <<
6856                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6857                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE) <<
6858                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6859                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6860                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6861
6862                 /* mmVGT_TF_MEMORY_BASE_HI_UMD -> mmVGT_TF_MEMORY_BASE_HI */
6863                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI_UMD) <<
6864                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6865                        (SOC15_REG_OFFSET(GC, 0, mmVGT_TF_MEMORY_BASE_HI) <<
6866                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6867                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6868                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6869
6870                 /* mmVGT_HS_OFFCHIP_PARAM_UMD -> mmVGT_HS_OFFCHIP_PARAM */
6871                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM_UMD) <<
6872                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6873                        (SOC15_REG_OFFSET(GC, 0, mmVGT_HS_OFFCHIP_PARAM) <<
6874                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6875                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6876                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6877
6878                 /* mmVGT_ESGS_RING_SIZE_UMD -> mmVGT_ESGS_RING_SIZE */
6879                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE_UMD) <<
6880                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6881                        (SOC15_REG_OFFSET(GC, 0, mmVGT_ESGS_RING_SIZE) <<
6882                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6883                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6884                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6885
6886                 /* mmVGT_GSVS_RING_SIZE_UMD -> mmVGT_GSVS_RING_SIZE */
6887                 data = (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE_UMD) <<
6888                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6889                        (SOC15_REG_OFFSET(GC, 0, mmVGT_GSVS_RING_SIZE) <<
6890                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6891                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6892                 WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6893
6894                 /* mmSPI_CONFIG_CNTL_REMAP -> mmSPI_CONFIG_CNTL */
6895                 data = (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL_REMAP) <<
6896                         GRBM_CAM_DATA__CAM_ADDR__SHIFT) |
6897                        (SOC15_REG_OFFSET(GC, 0, mmSPI_CONFIG_CNTL) <<
6898                         GRBM_CAM_DATA__CAM_REMAPADDR__SHIFT);
6899                 break;
6900         }
6901
6902         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA_UPPER, 0);
6903         WREG32_SOC15(GC, 0, mmGRBM_CAM_DATA, data);
6904 }
6905
6906 static int gfx_v10_0_hw_init(void *handle)
6907 {
6908         int r;
6909         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6910
6911         if (!amdgpu_emu_mode)
6912                 gfx_v10_0_init_golden_registers(adev);
6913
6914         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
6915                 /**
6916                  * For gfx 10, rlc firmware loading relies on smu firmware is
6917                  * loaded firstly, so in direct type, it has to load smc ucode
6918                  * here before rlc.
6919                  */
6920                 if (adev->smu.ppt_funcs != NULL) {
6921                         r = smu_load_microcode(&adev->smu);
6922                         if (r)
6923                                 return r;
6924
6925                         r = smu_check_fw_status(&adev->smu);
6926                         if (r) {
6927                                 pr_err("SMC firmware status is not correct\n");
6928                                 return r;
6929                         }
6930                 }
6931         }
6932
6933         /* if GRBM CAM not remapped, set up the remapping */
6934         if (!gfx_v10_0_check_grbm_cam_remapping(adev))
6935                 gfx_v10_0_setup_grbm_cam_remapping(adev);
6936
6937         gfx_v10_0_constants_init(adev);
6938
6939         r = gfx_v10_0_rlc_resume(adev);
6940         if (r)
6941                 return r;
6942
6943         /*
6944          * init golden registers and rlc resume may override some registers,
6945          * reconfig them here
6946          */
6947         gfx_v10_0_tcp_harvest(adev);
6948
6949         r = gfx_v10_0_cp_resume(adev);
6950         if (r)
6951                 return r;
6952
6953         return r;
6954 }
6955
6956 #ifndef BRING_UP_DEBUG
6957 static int gfx_v10_0_kiq_disable_kgq(struct amdgpu_device *adev)
6958 {
6959         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
6960         struct amdgpu_ring *kiq_ring = &kiq->ring;
6961         int i;
6962
6963         if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
6964                 return -EINVAL;
6965
6966         if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size *
6967                                         adev->gfx.num_gfx_rings))
6968                 return -ENOMEM;
6969
6970         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
6971                 kiq->pmf->kiq_unmap_queues(kiq_ring, &adev->gfx.gfx_ring[i],
6972                                            PREEMPT_QUEUES, 0, 0);
6973
6974         return amdgpu_ring_test_helper(kiq_ring);
6975 }
6976 #endif
6977
6978 static int gfx_v10_0_hw_fini(void *handle)
6979 {
6980         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
6981         int r;
6982         uint32_t tmp;
6983
6984         amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
6985         amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
6986
6987         if (!adev->in_pci_err_recovery) {
6988 #ifndef BRING_UP_DEBUG
6989                 if (amdgpu_async_gfx_ring) {
6990                         r = gfx_v10_0_kiq_disable_kgq(adev);
6991                         if (r)
6992                                 DRM_ERROR("KGQ disable failed\n");
6993                 }
6994 #endif
6995                 if (amdgpu_gfx_disable_kcq(adev))
6996                         DRM_ERROR("KCQ disable failed\n");
6997         }
6998
6999         if (amdgpu_sriov_vf(adev)) {
7000                 gfx_v10_0_cp_gfx_enable(adev, false);
7001                 /* Program KIQ position of RLC_CP_SCHEDULERS during destroy */
7002                 tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
7003                 tmp &= 0xffffff00;
7004                 WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
7005
7006                 return 0;
7007         }
7008         gfx_v10_0_cp_enable(adev, false);
7009         gfx_v10_0_enable_gui_idle_interrupt(adev, false);
7010
7011         return 0;
7012 }
7013
7014 static int gfx_v10_0_suspend(void *handle)
7015 {
7016         return gfx_v10_0_hw_fini(handle);
7017 }
7018
7019 static int gfx_v10_0_resume(void *handle)
7020 {
7021         return gfx_v10_0_hw_init(handle);
7022 }
7023
7024 static bool gfx_v10_0_is_idle(void *handle)
7025 {
7026         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7027
7028         if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS),
7029                                 GRBM_STATUS, GUI_ACTIVE))
7030                 return false;
7031         else
7032                 return true;
7033 }
7034
7035 static int gfx_v10_0_wait_for_idle(void *handle)
7036 {
7037         unsigned i;
7038         u32 tmp;
7039         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7040
7041         for (i = 0; i < adev->usec_timeout; i++) {
7042                 /* read MC_STATUS */
7043                 tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS) &
7044                         GRBM_STATUS__GUI_ACTIVE_MASK;
7045
7046                 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE))
7047                         return 0;
7048                 udelay(1);
7049         }
7050         return -ETIMEDOUT;
7051 }
7052
7053 static int gfx_v10_0_soft_reset(void *handle)
7054 {
7055         u32 grbm_soft_reset = 0;
7056         u32 tmp;
7057         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7058
7059         /* GRBM_STATUS */
7060         tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS);
7061         if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
7062                    GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
7063                    GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__DB_BUSY_MASK |
7064                    GRBM_STATUS__CB_BUSY_MASK | GRBM_STATUS__GDS_BUSY_MASK |
7065                    GRBM_STATUS__SPI_BUSY_MASK | GRBM_STATUS__GE_BUSY_NO_DMA_MASK)) {
7066                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7067                                                 GRBM_SOFT_RESET, SOFT_RESET_CP,
7068                                                 1);
7069                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7070                                                 GRBM_SOFT_RESET, SOFT_RESET_GFX,
7071                                                 1);
7072         }
7073
7074         if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
7075                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7076                                                 GRBM_SOFT_RESET, SOFT_RESET_CP,
7077                                                 1);
7078         }
7079
7080         /* GRBM_STATUS2 */
7081         tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2);
7082         switch (adev->asic_type) {
7083         case CHIP_SIENNA_CICHLID:
7084         case CHIP_NAVY_FLOUNDER:
7085                 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY_Sienna_Cichlid))
7086                         grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7087                                                         GRBM_SOFT_RESET,
7088                                                         SOFT_RESET_RLC,
7089                                                         1);
7090                 break;
7091         default:
7092                 if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
7093                         grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
7094                                                         GRBM_SOFT_RESET,
7095                                                         SOFT_RESET_RLC,
7096                                                         1);
7097                 break;
7098         }
7099
7100         if (grbm_soft_reset) {
7101                 /* stop the rlc */
7102                 gfx_v10_0_rlc_stop(adev);
7103
7104                 /* Disable GFX parsing/prefetching */
7105                 gfx_v10_0_cp_gfx_enable(adev, false);
7106
7107                 /* Disable MEC parsing/prefetching */
7108                 gfx_v10_0_cp_compute_enable(adev, false);
7109
7110                 if (grbm_soft_reset) {
7111                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
7112                         tmp |= grbm_soft_reset;
7113                         dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
7114                         WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
7115                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
7116
7117                         udelay(50);
7118
7119                         tmp &= ~grbm_soft_reset;
7120                         WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
7121                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
7122                 }
7123
7124                 /* Wait a little for things to settle down */
7125                 udelay(50);
7126         }
7127         return 0;
7128 }
7129
7130 static uint64_t gfx_v10_0_get_gpu_clock_counter(struct amdgpu_device *adev)
7131 {
7132         uint64_t clock;
7133
7134         amdgpu_gfx_off_ctrl(adev, false);
7135         mutex_lock(&adev->gfx.gpu_clock_mutex);
7136         clock = (uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_LOWER) |
7137                 ((uint64_t)RREG32_SOC15(SMUIO, 0, mmGOLDEN_TSC_COUNT_UPPER) << 32ULL);
7138         mutex_unlock(&adev->gfx.gpu_clock_mutex);
7139         amdgpu_gfx_off_ctrl(adev, true);
7140         return clock;
7141 }
7142
7143 static void gfx_v10_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
7144                                            uint32_t vmid,
7145                                            uint32_t gds_base, uint32_t gds_size,
7146                                            uint32_t gws_base, uint32_t gws_size,
7147                                            uint32_t oa_base, uint32_t oa_size)
7148 {
7149         struct amdgpu_device *adev = ring->adev;
7150
7151         /* GDS Base */
7152         gfx_v10_0_write_data_to_reg(ring, 0, false,
7153                                     SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid,
7154                                     gds_base);
7155
7156         /* GDS Size */
7157         gfx_v10_0_write_data_to_reg(ring, 0, false,
7158                                     SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE) + 2 * vmid,
7159                                     gds_size);
7160
7161         /* GWS */
7162         gfx_v10_0_write_data_to_reg(ring, 0, false,
7163                                     SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0) + vmid,
7164                                     gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
7165
7166         /* OA */
7167         gfx_v10_0_write_data_to_reg(ring, 0, false,
7168                                     SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) + vmid,
7169                                     (1 << (oa_size + oa_base)) - (1 << oa_base));
7170 }
7171
7172 static int gfx_v10_0_early_init(void *handle)
7173 {
7174         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7175
7176         switch (adev->asic_type) {
7177         case CHIP_NAVI10:
7178         case CHIP_NAVI14:
7179         case CHIP_NAVI12:
7180                 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_NV1X;
7181                 break;
7182         case CHIP_SIENNA_CICHLID:
7183         case CHIP_NAVY_FLOUNDER:
7184                 adev->gfx.num_gfx_rings = GFX10_NUM_GFX_RINGS_Sienna_Cichlid;
7185                 break;
7186         default:
7187                 break;
7188         }
7189
7190         adev->gfx.num_compute_rings = amdgpu_num_kcq;
7191
7192         gfx_v10_0_set_kiq_pm4_funcs(adev);
7193         gfx_v10_0_set_ring_funcs(adev);
7194         gfx_v10_0_set_irq_funcs(adev);
7195         gfx_v10_0_set_gds_init(adev);
7196         gfx_v10_0_set_rlc_funcs(adev);
7197
7198         return 0;
7199 }
7200
7201 static int gfx_v10_0_late_init(void *handle)
7202 {
7203         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7204         int r;
7205
7206         r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
7207         if (r)
7208                 return r;
7209
7210         r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
7211         if (r)
7212                 return r;
7213
7214         return 0;
7215 }
7216
7217 static bool gfx_v10_0_is_rlc_enabled(struct amdgpu_device *adev)
7218 {
7219         uint32_t rlc_cntl;
7220
7221         /* if RLC is not enabled, do nothing */
7222         rlc_cntl = RREG32_SOC15(GC, 0, mmRLC_CNTL);
7223         return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false;
7224 }
7225
7226 static void gfx_v10_0_set_safe_mode(struct amdgpu_device *adev)
7227 {
7228         uint32_t data;
7229         unsigned i;
7230
7231         data = RLC_SAFE_MODE__CMD_MASK;
7232         data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT);
7233
7234         switch (adev->asic_type) {
7235         case CHIP_SIENNA_CICHLID:
7236         case CHIP_NAVY_FLOUNDER:
7237                 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data);
7238
7239                 /* wait for RLC_SAFE_MODE */
7240                 for (i = 0; i < adev->usec_timeout; i++) {
7241                         if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid),
7242                                            RLC_SAFE_MODE, CMD))
7243                                 break;
7244                         udelay(1);
7245                 }
7246                 break;
7247         default:
7248                 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
7249
7250                 /* wait for RLC_SAFE_MODE */
7251                 for (i = 0; i < adev->usec_timeout; i++) {
7252                         if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE),
7253                                            RLC_SAFE_MODE, CMD))
7254                                 break;
7255                         udelay(1);
7256                 }
7257                 break;
7258         }
7259 }
7260
7261 static void gfx_v10_0_unset_safe_mode(struct amdgpu_device *adev)
7262 {
7263         uint32_t data;
7264
7265         data = RLC_SAFE_MODE__CMD_MASK;
7266         switch (adev->asic_type) {
7267         case CHIP_SIENNA_CICHLID:
7268         case CHIP_NAVY_FLOUNDER:
7269                 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE_Sienna_Cichlid, data);
7270                 break;
7271         default:
7272                 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
7273                 break;
7274         }
7275 }
7276
7277 static void gfx_v10_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
7278                                                       bool enable)
7279 {
7280         uint32_t data, def;
7281
7282         /* It is disabled by HW by default */
7283         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
7284                 /* 0 - Disable some blocks' MGCG */
7285                 WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, 0xe0000000);
7286                 WREG32_SOC15(GC, 0, mmCGTT_WD_CLK_CTRL, 0xff000000);
7287                 WREG32_SOC15(GC, 0, mmCGTT_VGT_CLK_CTRL, 0xff000000);
7288                 WREG32_SOC15(GC, 0, mmCGTT_IA_CLK_CTRL, 0xff000000);
7289
7290                 /* 1 - RLC_CGTT_MGCG_OVERRIDE */
7291                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7292                 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
7293                           RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
7294                           RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK |
7295                           RLC_CGTT_MGCG_OVERRIDE__ENABLE_CGTS_LEGACY_MASK);
7296
7297                 if (def != data)
7298                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7299
7300                 /* MGLS is a global flag to control all MGLS in GFX */
7301                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
7302                         /* 2 - RLC memory Light sleep */
7303                         if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) {
7304                                 def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
7305                                 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
7306                                 if (def != data)
7307                                         WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
7308                         }
7309                         /* 3 - CP memory Light sleep */
7310                         if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
7311                                 def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
7312                                 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
7313                                 if (def != data)
7314                                         WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
7315                         }
7316                 }
7317         } else {
7318                 /* 1 - MGCG_OVERRIDE */
7319                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7320                 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
7321                          RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
7322                          RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
7323                          RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);
7324                 if (def != data)
7325                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7326
7327                 /* 2 - disable MGLS in CP */
7328                 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
7329                 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
7330                         data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
7331                         WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
7332                 }
7333
7334                 /* 3 - disable MGLS in RLC */
7335                 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
7336                 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
7337                         data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
7338                         WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
7339                 }
7340
7341         }
7342 }
7343
7344 static void gfx_v10_0_update_3d_clock_gating(struct amdgpu_device *adev,
7345                                            bool enable)
7346 {
7347         uint32_t data, def;
7348
7349         /* Enable 3D CGCG/CGLS */
7350         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)) {
7351                 /* write cmd to clear cgcg/cgls ov */
7352                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7353                 /* unset CGCG override */
7354                 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK;
7355                 /* update CGCG and CGLS override bits */
7356                 if (def != data)
7357                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7358                 /* enable 3Dcgcg FSM(0x0000363f) */
7359                 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
7360                 data = (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
7361                         RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
7362                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
7363                         data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
7364                                 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
7365                 if (def != data)
7366                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
7367
7368                 /* set IDLE_POLL_COUNT(0x00900100) */
7369                 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
7370                 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
7371                         (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
7372                 if (def != data)
7373                         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
7374         } else {
7375                 /* Disable CGCG/CGLS */
7376                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
7377                 /* disable cgcg, cgls should be disabled */
7378                 data &= ~(RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK |
7379                           RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK);
7380                 /* disable cgcg and cgls in FSM */
7381                 if (def != data)
7382                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
7383         }
7384 }
7385
7386 static void gfx_v10_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
7387                                                       bool enable)
7388 {
7389         uint32_t def, data;
7390
7391         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
7392                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
7393                 /* unset CGCG override */
7394                 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK;
7395                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
7396                         data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
7397                 else
7398                         data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
7399                 /* update CGCG and CGLS override bits */
7400                 if (def != data)
7401                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
7402
7403                 /* enable cgcg FSM(0x0000363F) */
7404                 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
7405                 data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
7406                         RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
7407                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
7408                         data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
7409                                 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
7410                 if (def != data)
7411                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
7412
7413                 /* set IDLE_POLL_COUNT(0x00900100) */
7414                 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
7415                 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
7416                         (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
7417                 if (def != data)
7418                         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
7419         } else {
7420                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
7421                 /* reset CGCG/CGLS bits */
7422                 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
7423                 /* disable cgcg and cgls in FSM */
7424                 if (def != data)
7425                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
7426         }
7427 }
7428
7429 static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev,
7430                                             bool enable)
7431 {
7432         amdgpu_gfx_rlc_enter_safe_mode(adev);
7433
7434         if (enable) {
7435                 /* CGCG/CGLS should be enabled after MGCG/MGLS
7436                  * ===  MGCG + MGLS ===
7437                  */
7438                 gfx_v10_0_update_medium_grain_clock_gating(adev, enable);
7439                 /* ===  CGCG /CGLS for GFX 3D Only === */
7440                 gfx_v10_0_update_3d_clock_gating(adev, enable);
7441                 /* ===  CGCG + CGLS === */
7442                 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable);
7443         } else {
7444                 /* CGCG/CGLS should be disabled before MGCG/MGLS
7445                  * ===  CGCG + CGLS ===
7446                  */
7447                 gfx_v10_0_update_coarse_grain_clock_gating(adev, enable);
7448                 /* ===  CGCG /CGLS for GFX 3D Only === */
7449                 gfx_v10_0_update_3d_clock_gating(adev, enable);
7450                 /* ===  MGCG + MGLS === */
7451                 gfx_v10_0_update_medium_grain_clock_gating(adev, enable);
7452         }
7453
7454         if (adev->cg_flags &
7455             (AMD_CG_SUPPORT_GFX_MGCG |
7456              AMD_CG_SUPPORT_GFX_CGLS |
7457              AMD_CG_SUPPORT_GFX_CGCG |
7458              AMD_CG_SUPPORT_GFX_3D_CGCG |
7459              AMD_CG_SUPPORT_GFX_3D_CGLS))
7460                 gfx_v10_0_enable_gui_idle_interrupt(adev, enable);
7461
7462         amdgpu_gfx_rlc_exit_safe_mode(adev);
7463
7464         return 0;
7465 }
7466
7467 static void gfx_v10_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid)
7468 {
7469         u32 reg, data;
7470
7471         reg = SOC15_REG_OFFSET(GC, 0, mmRLC_SPM_MC_CNTL);
7472         if (amdgpu_sriov_is_pp_one_vf(adev))
7473                 data = RREG32_NO_KIQ(reg);
7474         else
7475                 data = RREG32(reg);
7476
7477         data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK;
7478         data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT;
7479
7480         if (amdgpu_sriov_is_pp_one_vf(adev))
7481                 WREG32_SOC15_NO_KIQ(GC, 0, mmRLC_SPM_MC_CNTL, data);
7482         else
7483                 WREG32_SOC15(GC, 0, mmRLC_SPM_MC_CNTL, data);
7484 }
7485
7486 static bool gfx_v10_0_check_rlcg_range(struct amdgpu_device *adev,
7487                                         uint32_t offset,
7488                                         struct soc15_reg_rlcg *entries, int arr_size)
7489 {
7490         int i;
7491         uint32_t reg;
7492
7493         if (!entries)
7494                 return false;
7495
7496         for (i = 0; i < arr_size; i++) {
7497                 const struct soc15_reg_rlcg *entry;
7498
7499                 entry = &entries[i];
7500                 reg = adev->reg_offset[entry->hwip][entry->instance][entry->segment] + entry->reg;
7501                 if (offset == reg)
7502                         return true;
7503         }
7504
7505         return false;
7506 }
7507
7508 static bool gfx_v10_0_is_rlcg_access_range(struct amdgpu_device *adev, u32 offset)
7509 {
7510         return gfx_v10_0_check_rlcg_range(adev, offset, NULL, 0);
7511 }
7512
7513 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs = {
7514         .is_rlc_enabled = gfx_v10_0_is_rlc_enabled,
7515         .set_safe_mode = gfx_v10_0_set_safe_mode,
7516         .unset_safe_mode = gfx_v10_0_unset_safe_mode,
7517         .init = gfx_v10_0_rlc_init,
7518         .get_csb_size = gfx_v10_0_get_csb_size,
7519         .get_csb_buffer = gfx_v10_0_get_csb_buffer,
7520         .resume = gfx_v10_0_rlc_resume,
7521         .stop = gfx_v10_0_rlc_stop,
7522         .reset = gfx_v10_0_rlc_reset,
7523         .start = gfx_v10_0_rlc_start,
7524         .update_spm_vmid = gfx_v10_0_update_spm_vmid,
7525 };
7526
7527 static const struct amdgpu_rlc_funcs gfx_v10_0_rlc_funcs_sriov = {
7528         .is_rlc_enabled = gfx_v10_0_is_rlc_enabled,
7529         .set_safe_mode = gfx_v10_0_set_safe_mode,
7530         .unset_safe_mode = gfx_v10_0_unset_safe_mode,
7531         .init = gfx_v10_0_rlc_init,
7532         .get_csb_size = gfx_v10_0_get_csb_size,
7533         .get_csb_buffer = gfx_v10_0_get_csb_buffer,
7534         .resume = gfx_v10_0_rlc_resume,
7535         .stop = gfx_v10_0_rlc_stop,
7536         .reset = gfx_v10_0_rlc_reset,
7537         .start = gfx_v10_0_rlc_start,
7538         .update_spm_vmid = gfx_v10_0_update_spm_vmid,
7539         .rlcg_wreg = gfx_v10_rlcg_wreg,
7540         .is_rlcg_access_range = gfx_v10_0_is_rlcg_access_range,
7541 };
7542
7543 static int gfx_v10_0_set_powergating_state(void *handle,
7544                                           enum amd_powergating_state state)
7545 {
7546         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7547         bool enable = (state == AMD_PG_STATE_GATE);
7548
7549         if (amdgpu_sriov_vf(adev))
7550                 return 0;
7551
7552         switch (adev->asic_type) {
7553         case CHIP_NAVI10:
7554         case CHIP_NAVI14:
7555         case CHIP_NAVI12:
7556         case CHIP_SIENNA_CICHLID:
7557         case CHIP_NAVY_FLOUNDER:
7558                 amdgpu_gfx_off_ctrl(adev, enable);
7559                 break;
7560         default:
7561                 break;
7562         }
7563         return 0;
7564 }
7565
7566 static int gfx_v10_0_set_clockgating_state(void *handle,
7567                                           enum amd_clockgating_state state)
7568 {
7569         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7570
7571         if (amdgpu_sriov_vf(adev))
7572                 return 0;
7573
7574         switch (adev->asic_type) {
7575         case CHIP_NAVI10:
7576         case CHIP_NAVI14:
7577         case CHIP_NAVI12:
7578         case CHIP_SIENNA_CICHLID:
7579         case CHIP_NAVY_FLOUNDER:
7580                 gfx_v10_0_update_gfx_clock_gating(adev,
7581                                                  state == AMD_CG_STATE_GATE);
7582                 break;
7583         default:
7584                 break;
7585         }
7586         return 0;
7587 }
7588
7589 static void gfx_v10_0_get_clockgating_state(void *handle, u32 *flags)
7590 {
7591         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
7592         int data;
7593
7594         /* AMD_CG_SUPPORT_GFX_MGCG */
7595         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE));
7596         if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK))
7597                 *flags |= AMD_CG_SUPPORT_GFX_MGCG;
7598
7599         /* AMD_CG_SUPPORT_GFX_CGCG */
7600         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL));
7601         if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK)
7602                 *flags |= AMD_CG_SUPPORT_GFX_CGCG;
7603
7604         /* AMD_CG_SUPPORT_GFX_CGLS */
7605         if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK)
7606                 *flags |= AMD_CG_SUPPORT_GFX_CGLS;
7607
7608         /* AMD_CG_SUPPORT_GFX_RLC_LS */
7609         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_MEM_SLP_CNTL));
7610         if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK)
7611                 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS;
7612
7613         /* AMD_CG_SUPPORT_GFX_CP_LS */
7614         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmCP_MEM_SLP_CNTL));
7615         if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK)
7616                 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS;
7617
7618         /* AMD_CG_SUPPORT_GFX_3D_CGCG */
7619         data = RREG32_KIQ(SOC15_REG_OFFSET(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D));
7620         if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK)
7621                 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG;
7622
7623         /* AMD_CG_SUPPORT_GFX_3D_CGLS */
7624         if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK)
7625                 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS;
7626 }
7627
7628 static u64 gfx_v10_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
7629 {
7630         return ring->adev->wb.wb[ring->rptr_offs]; /* gfx10 is 32bit rptr*/
7631 }
7632
7633 static u64 gfx_v10_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
7634 {
7635         struct amdgpu_device *adev = ring->adev;
7636         u64 wptr;
7637
7638         /* XXX check if swapping is necessary on BE */
7639         if (ring->use_doorbell) {
7640                 wptr = atomic64_read((atomic64_t *)&adev->wb.wb[ring->wptr_offs]);
7641         } else {
7642                 wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR);
7643                 wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32;
7644         }
7645
7646         return wptr;
7647 }
7648
7649 static void gfx_v10_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
7650 {
7651         struct amdgpu_device *adev = ring->adev;
7652
7653         if (ring->use_doorbell) {
7654                 /* XXX check if swapping is necessary on BE */
7655                 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr);
7656                 WDOORBELL64(ring->doorbell_index, ring->wptr);
7657         } else {
7658                 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
7659                 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
7660         }
7661 }
7662
7663 static u64 gfx_v10_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
7664 {
7665         return ring->adev->wb.wb[ring->rptr_offs]; /* gfx10 hardware is 32bit rptr */
7666 }
7667
7668 static u64 gfx_v10_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
7669 {
7670         u64 wptr;
7671
7672         /* XXX check if swapping is necessary on BE */
7673         if (ring->use_doorbell)
7674                 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]);
7675         else
7676                 BUG();
7677         return wptr;
7678 }
7679
7680 static void gfx_v10_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
7681 {
7682         struct amdgpu_device *adev = ring->adev;
7683
7684         /* XXX check if swapping is necessary on BE */
7685         if (ring->use_doorbell) {
7686                 atomic64_set((atomic64_t *)&adev->wb.wb[ring->wptr_offs], ring->wptr);
7687                 WDOORBELL64(ring->doorbell_index, ring->wptr);
7688         } else {
7689                 BUG(); /* only DOORBELL method supported on gfx10 now */
7690         }
7691 }
7692
7693 static void gfx_v10_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
7694 {
7695         struct amdgpu_device *adev = ring->adev;
7696         u32 ref_and_mask, reg_mem_engine;
7697         const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
7698
7699         if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
7700                 switch (ring->me) {
7701                 case 1:
7702                         ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe;
7703                         break;
7704                 case 2:
7705                         ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe;
7706                         break;
7707                 default:
7708                         return;
7709                 }
7710                 reg_mem_engine = 0;
7711         } else {
7712                 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0;
7713                 reg_mem_engine = 1; /* pfp */
7714         }
7715
7716         gfx_v10_0_wait_reg_mem(ring, reg_mem_engine, 0, 1,
7717                                adev->nbio.funcs->get_hdp_flush_req_offset(adev),
7718                                adev->nbio.funcs->get_hdp_flush_done_offset(adev),
7719                                ref_and_mask, ref_and_mask, 0x20);
7720 }
7721
7722 static void gfx_v10_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
7723                                        struct amdgpu_job *job,
7724                                        struct amdgpu_ib *ib,
7725                                        uint32_t flags)
7726 {
7727         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
7728         u32 header, control = 0;
7729
7730         if (ib->flags & AMDGPU_IB_FLAG_CE)
7731                 header = PACKET3(PACKET3_INDIRECT_BUFFER_CNST, 2);
7732         else
7733                 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
7734
7735         control |= ib->length_dw | (vmid << 24);
7736
7737         if ((amdgpu_sriov_vf(ring->adev) || amdgpu_mcbp) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) {
7738                 control |= INDIRECT_BUFFER_PRE_ENB(1);
7739
7740                 if (flags & AMDGPU_IB_PREEMPTED)
7741                         control |= INDIRECT_BUFFER_PRE_RESUME(1);
7742
7743                 if (!(ib->flags & AMDGPU_IB_FLAG_CE) && vmid)
7744                         gfx_v10_0_ring_emit_de_meta(ring,
7745                                     (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false);
7746         }
7747
7748         amdgpu_ring_write(ring, header);
7749         BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
7750         amdgpu_ring_write(ring,
7751 #ifdef __BIG_ENDIAN
7752                 (2 << 0) |
7753 #endif
7754                 lower_32_bits(ib->gpu_addr));
7755         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
7756         amdgpu_ring_write(ring, control);
7757 }
7758
7759 static void gfx_v10_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
7760                                            struct amdgpu_job *job,
7761                                            struct amdgpu_ib *ib,
7762                                            uint32_t flags)
7763 {
7764         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
7765         u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);
7766
7767         /* Currently, there is a high possibility to get wave ID mismatch
7768          * between ME and GDS, leading to a hw deadlock, because ME generates
7769          * different wave IDs than the GDS expects. This situation happens
7770          * randomly when at least 5 compute pipes use GDS ordered append.
7771          * The wave IDs generated by ME are also wrong after suspend/resume.
7772          * Those are probably bugs somewhere else in the kernel driver.
7773          *
7774          * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and
7775          * GDS to 0 for this ring (me/pipe).
7776          */
7777         if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) {
7778                 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
7779                 amdgpu_ring_write(ring, mmGDS_COMPUTE_MAX_WAVE_ID);
7780                 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id);
7781         }
7782
7783         amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
7784         BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
7785         amdgpu_ring_write(ring,
7786 #ifdef __BIG_ENDIAN
7787                                 (2 << 0) |
7788 #endif
7789                                 lower_32_bits(ib->gpu_addr));
7790         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
7791         amdgpu_ring_write(ring, control);
7792 }
7793
7794 static void gfx_v10_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
7795                                      u64 seq, unsigned flags)
7796 {
7797         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
7798         bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
7799
7800         /* RELEASE_MEM - flush caches, send int */
7801         amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6));
7802         amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ |
7803                                  PACKET3_RELEASE_MEM_GCR_GL2_WB |
7804                                  PACKET3_RELEASE_MEM_GCR_GLM_INV | /* must be set with GLM_WB */
7805                                  PACKET3_RELEASE_MEM_GCR_GLM_WB |
7806                                  PACKET3_RELEASE_MEM_CACHE_POLICY(3) |
7807                                  PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
7808                                  PACKET3_RELEASE_MEM_EVENT_INDEX(5)));
7809         amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) |
7810                                  PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0)));
7811
7812         /*
7813          * the address should be Qword aligned if 64bit write, Dword
7814          * aligned if only send 32bit data low (discard data high)
7815          */
7816         if (write64bit)
7817                 BUG_ON(addr & 0x7);
7818         else
7819                 BUG_ON(addr & 0x3);
7820         amdgpu_ring_write(ring, lower_32_bits(addr));
7821         amdgpu_ring_write(ring, upper_32_bits(addr));
7822         amdgpu_ring_write(ring, lower_32_bits(seq));
7823         amdgpu_ring_write(ring, upper_32_bits(seq));
7824         amdgpu_ring_write(ring, 0);
7825 }
7826
7827 static void gfx_v10_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
7828 {
7829         int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
7830         uint32_t seq = ring->fence_drv.sync_seq;
7831         uint64_t addr = ring->fence_drv.gpu_addr;
7832
7833         gfx_v10_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr),
7834                                upper_32_bits(addr), seq, 0xffffffff, 4);
7835 }
7836
7837 static void gfx_v10_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
7838                                          unsigned vmid, uint64_t pd_addr)
7839 {
7840         amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
7841
7842         /* compute doesn't have PFP */
7843         if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) {
7844                 /* sync PFP to ME, otherwise we might get invalid PFP reads */
7845                 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
7846                 amdgpu_ring_write(ring, 0x0);
7847         }
7848 }
7849
7850 static void gfx_v10_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr,
7851                                           u64 seq, unsigned int flags)
7852 {
7853         struct amdgpu_device *adev = ring->adev;
7854
7855         /* we only allocate 32bit for each seq wb address */
7856         BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
7857
7858         /* write fence seq to the "addr" */
7859         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
7860         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
7861                                  WRITE_DATA_DST_SEL(5) | WR_CONFIRM));
7862         amdgpu_ring_write(ring, lower_32_bits(addr));
7863         amdgpu_ring_write(ring, upper_32_bits(addr));
7864         amdgpu_ring_write(ring, lower_32_bits(seq));
7865
7866         if (flags & AMDGPU_FENCE_FLAG_INT) {
7867                 /* set register to trigger INT */
7868                 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
7869                 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
7870                                          WRITE_DATA_DST_SEL(0) | WR_CONFIRM));
7871                 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS));
7872                 amdgpu_ring_write(ring, 0);
7873                 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */
7874         }
7875 }
7876
7877 static void gfx_v10_0_ring_emit_sb(struct amdgpu_ring *ring)
7878 {
7879         amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
7880         amdgpu_ring_write(ring, 0);
7881 }
7882
7883 static void gfx_v10_0_ring_emit_cntxcntl(struct amdgpu_ring *ring,
7884                                          uint32_t flags)
7885 {
7886         uint32_t dw2 = 0;
7887
7888         if (amdgpu_mcbp || amdgpu_sriov_vf(ring->adev))
7889                 gfx_v10_0_ring_emit_ce_meta(ring,
7890                                     (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false);
7891
7892         dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
7893         if (flags & AMDGPU_HAVE_CTX_SWITCH) {
7894                 /* set load_global_config & load_global_uconfig */
7895                 dw2 |= 0x8001;
7896                 /* set load_cs_sh_regs */
7897                 dw2 |= 0x01000000;
7898                 /* set load_per_context_state & load_gfx_sh_regs for GFX */
7899                 dw2 |= 0x10002;
7900
7901                 /* set load_ce_ram if preamble presented */
7902                 if (AMDGPU_PREAMBLE_IB_PRESENT & flags)
7903                         dw2 |= 0x10000000;
7904         } else {
7905                 /* still load_ce_ram if this is the first time preamble presented
7906                  * although there is no context switch happens.
7907                  */
7908                 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags)
7909                         dw2 |= 0x10000000;
7910         }
7911
7912         amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
7913         amdgpu_ring_write(ring, dw2);
7914         amdgpu_ring_write(ring, 0);
7915 }
7916
7917 static unsigned gfx_v10_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring)
7918 {
7919         unsigned ret;
7920
7921         amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3));
7922         amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
7923         amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
7924         amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */
7925         ret = ring->wptr & ring->buf_mask;
7926         amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */
7927
7928         return ret;
7929 }
7930
7931 static void gfx_v10_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset)
7932 {
7933         unsigned cur;
7934         BUG_ON(offset > ring->buf_mask);
7935         BUG_ON(ring->ring[offset] != 0x55aa55aa);
7936
7937         cur = (ring->wptr - 1) & ring->buf_mask;
7938         if (likely(cur > offset))
7939                 ring->ring[offset] = cur - offset;
7940         else
7941                 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur;
7942 }
7943
7944 static int gfx_v10_0_ring_preempt_ib(struct amdgpu_ring *ring)
7945 {
7946         int i, r = 0;
7947         struct amdgpu_device *adev = ring->adev;
7948         struct amdgpu_kiq *kiq = &adev->gfx.kiq;
7949         struct amdgpu_ring *kiq_ring = &kiq->ring;
7950         unsigned long flags;
7951
7952         if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
7953                 return -EINVAL;
7954
7955         spin_lock_irqsave(&kiq->ring_lock, flags);
7956
7957         if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) {
7958                 spin_unlock_irqrestore(&kiq->ring_lock, flags);
7959                 return -ENOMEM;
7960         }
7961
7962         /* assert preemption condition */
7963         amdgpu_ring_set_preempt_cond_exec(ring, false);
7964
7965         /* assert IB preemption, emit the trailing fence */
7966         kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP,
7967                                    ring->trail_fence_gpu_addr,
7968                                    ++ring->trail_seq);
7969         amdgpu_ring_commit(kiq_ring);
7970
7971         spin_unlock_irqrestore(&kiq->ring_lock, flags);
7972
7973         /* poll the trailing fence */
7974         for (i = 0; i < adev->usec_timeout; i++) {
7975                 if (ring->trail_seq ==
7976                     le32_to_cpu(*(ring->trail_fence_cpu_addr)))
7977                         break;
7978                 udelay(1);
7979         }
7980
7981         if (i >= adev->usec_timeout) {
7982                 r = -EINVAL;
7983                 DRM_ERROR("ring %d failed to preempt ib\n", ring->idx);
7984         }
7985
7986         /* deassert preemption condition */
7987         amdgpu_ring_set_preempt_cond_exec(ring, true);
7988         return r;
7989 }
7990
7991 static void gfx_v10_0_ring_emit_ce_meta(struct amdgpu_ring *ring, bool resume)
7992 {
7993         struct amdgpu_device *adev = ring->adev;
7994         struct v10_ce_ib_state ce_payload = {0};
7995         uint64_t csa_addr;
7996         int cnt;
7997
7998         cnt = (sizeof(ce_payload) >> 2) + 4 - 2;
7999         csa_addr = amdgpu_csa_vaddr(ring->adev);
8000
8001         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
8002         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) |
8003                                  WRITE_DATA_DST_SEL(8) |
8004                                  WR_CONFIRM) |
8005                                  WRITE_DATA_CACHE_POLICY(0));
8006         amdgpu_ring_write(ring, lower_32_bits(csa_addr +
8007                               offsetof(struct v10_gfx_meta_data, ce_payload)));
8008         amdgpu_ring_write(ring, upper_32_bits(csa_addr +
8009                               offsetof(struct v10_gfx_meta_data, ce_payload)));
8010
8011         if (resume)
8012                 amdgpu_ring_write_multiple(ring, adev->virt.csa_cpu_addr +
8013                                            offsetof(struct v10_gfx_meta_data,
8014                                                     ce_payload),
8015                                            sizeof(ce_payload) >> 2);
8016         else
8017                 amdgpu_ring_write_multiple(ring, (void *)&ce_payload,
8018                                            sizeof(ce_payload) >> 2);
8019 }
8020
8021 static void gfx_v10_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume)
8022 {
8023         struct amdgpu_device *adev = ring->adev;
8024         struct v10_de_ib_state de_payload = {0};
8025         uint64_t csa_addr, gds_addr;
8026         int cnt;
8027
8028         csa_addr = amdgpu_csa_vaddr(ring->adev);
8029         gds_addr = ALIGN(csa_addr + AMDGPU_CSA_SIZE - adev->gds.gds_size,
8030                          PAGE_SIZE);
8031         de_payload.gds_backup_addrlo = lower_32_bits(gds_addr);
8032         de_payload.gds_backup_addrhi = upper_32_bits(gds_addr);
8033
8034         cnt = (sizeof(de_payload) >> 2) + 4 - 2;
8035         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
8036         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
8037                                  WRITE_DATA_DST_SEL(8) |
8038                                  WR_CONFIRM) |
8039                                  WRITE_DATA_CACHE_POLICY(0));
8040         amdgpu_ring_write(ring, lower_32_bits(csa_addr +
8041                               offsetof(struct v10_gfx_meta_data, de_payload)));
8042         amdgpu_ring_write(ring, upper_32_bits(csa_addr +
8043                               offsetof(struct v10_gfx_meta_data, de_payload)));
8044
8045         if (resume)
8046                 amdgpu_ring_write_multiple(ring, adev->virt.csa_cpu_addr +
8047                                            offsetof(struct v10_gfx_meta_data,
8048                                                     de_payload),
8049                                            sizeof(de_payload) >> 2);
8050         else
8051                 amdgpu_ring_write_multiple(ring, (void *)&de_payload,
8052                                            sizeof(de_payload) >> 2);
8053 }
8054
8055 static void gfx_v10_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start,
8056                                     bool secure)
8057 {
8058         uint32_t v = secure ? FRAME_TMZ : 0;
8059
8060         amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0));
8061         amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1));
8062 }
8063
8064 static void gfx_v10_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg,
8065                                      uint32_t reg_val_offs)
8066 {
8067         struct amdgpu_device *adev = ring->adev;
8068
8069         amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));
8070         amdgpu_ring_write(ring, 0 |     /* src: register*/
8071                                 (5 << 8) |      /* dst: memory */
8072                                 (1 << 20));     /* write confirm */
8073         amdgpu_ring_write(ring, reg);
8074         amdgpu_ring_write(ring, 0);
8075         amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
8076                                 reg_val_offs * 4));
8077         amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +
8078                                 reg_val_offs * 4));
8079 }
8080
8081 static void gfx_v10_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
8082                                    uint32_t val)
8083 {
8084         uint32_t cmd = 0;
8085
8086         switch (ring->funcs->type) {
8087         case AMDGPU_RING_TYPE_GFX:
8088                 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM;
8089                 break;
8090         case AMDGPU_RING_TYPE_KIQ:
8091                 cmd = (1 << 16); /* no inc addr */
8092                 break;
8093         default:
8094                 cmd = WR_CONFIRM;
8095                 break;
8096         }
8097         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
8098         amdgpu_ring_write(ring, cmd);
8099         amdgpu_ring_write(ring, reg);
8100         amdgpu_ring_write(ring, 0);
8101         amdgpu_ring_write(ring, val);
8102 }
8103
8104 static void gfx_v10_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
8105                                         uint32_t val, uint32_t mask)
8106 {
8107         gfx_v10_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20);
8108 }
8109
8110 static void gfx_v10_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
8111                                                    uint32_t reg0, uint32_t reg1,
8112                                                    uint32_t ref, uint32_t mask)
8113 {
8114         int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
8115         struct amdgpu_device *adev = ring->adev;
8116         bool fw_version_ok = false;
8117
8118         fw_version_ok = adev->gfx.cp_fw_write_wait;
8119
8120         if (fw_version_ok)
8121                 gfx_v10_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1,
8122                                        ref, mask, 0x20);
8123         else
8124                 amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1,
8125                                                            ref, mask);
8126 }
8127
8128 static void gfx_v10_0_ring_soft_recovery(struct amdgpu_ring *ring,
8129                                          unsigned vmid)
8130 {
8131         struct amdgpu_device *adev = ring->adev;
8132         uint32_t value = 0;
8133
8134         value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03);
8135         value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01);
8136         value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1);
8137         value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid);
8138         WREG32_SOC15(GC, 0, mmSQ_CMD, value);
8139 }
8140
8141 static void
8142 gfx_v10_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
8143                                       uint32_t me, uint32_t pipe,
8144                                       enum amdgpu_interrupt_state state)
8145 {
8146         uint32_t cp_int_cntl, cp_int_cntl_reg;
8147
8148         if (!me) {
8149                 switch (pipe) {
8150                 case 0:
8151                         cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING0);
8152                         break;
8153                 case 1:
8154                         cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_INT_CNTL_RING1);
8155                         break;
8156                 default:
8157                         DRM_DEBUG("invalid pipe %d\n", pipe);
8158                         return;
8159                 }
8160         } else {
8161                 DRM_DEBUG("invalid me %d\n", me);
8162                 return;
8163         }
8164
8165         switch (state) {
8166         case AMDGPU_IRQ_STATE_DISABLE:
8167                 cp_int_cntl = RREG32(cp_int_cntl_reg);
8168                 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
8169                                             TIME_STAMP_INT_ENABLE, 0);
8170                 WREG32(cp_int_cntl_reg, cp_int_cntl);
8171                 break;
8172         case AMDGPU_IRQ_STATE_ENABLE:
8173                 cp_int_cntl = RREG32(cp_int_cntl_reg);
8174                 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
8175                                             TIME_STAMP_INT_ENABLE, 1);
8176                 WREG32(cp_int_cntl_reg, cp_int_cntl);
8177                 break;
8178         default:
8179                 break;
8180         }
8181 }
8182
8183 static void gfx_v10_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
8184                                                      int me, int pipe,
8185                                                      enum amdgpu_interrupt_state state)
8186 {
8187         u32 mec_int_cntl, mec_int_cntl_reg;
8188
8189         /*
8190          * amdgpu controls only the first MEC. That's why this function only
8191          * handles the setting of interrupts for this specific MEC. All other
8192          * pipes' interrupts are set by amdkfd.
8193          */
8194
8195         if (me == 1) {
8196                 switch (pipe) {
8197                 case 0:
8198                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
8199                         break;
8200                 case 1:
8201                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL);
8202                         break;
8203                 case 2:
8204                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL);
8205                         break;
8206                 case 3:
8207                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL);
8208                         break;
8209                 default:
8210                         DRM_DEBUG("invalid pipe %d\n", pipe);
8211                         return;
8212                 }
8213         } else {
8214                 DRM_DEBUG("invalid me %d\n", me);
8215                 return;
8216         }
8217
8218         switch (state) {
8219         case AMDGPU_IRQ_STATE_DISABLE:
8220                 mec_int_cntl = RREG32(mec_int_cntl_reg);
8221                 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
8222                                              TIME_STAMP_INT_ENABLE, 0);
8223                 WREG32(mec_int_cntl_reg, mec_int_cntl);
8224                 break;
8225         case AMDGPU_IRQ_STATE_ENABLE:
8226                 mec_int_cntl = RREG32(mec_int_cntl_reg);
8227                 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
8228                                              TIME_STAMP_INT_ENABLE, 1);
8229                 WREG32(mec_int_cntl_reg, mec_int_cntl);
8230                 break;
8231         default:
8232                 break;
8233         }
8234 }
8235
8236 static int gfx_v10_0_set_eop_interrupt_state(struct amdgpu_device *adev,
8237                                             struct amdgpu_irq_src *src,
8238                                             unsigned type,
8239                                             enum amdgpu_interrupt_state state)
8240 {
8241         switch (type) {
8242         case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP:
8243                 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 0, state);
8244                 break;
8245         case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP:
8246                 gfx_v10_0_set_gfx_eop_interrupt_state(adev, 0, 1, state);
8247                 break;
8248         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
8249                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
8250                 break;
8251         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
8252                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
8253                 break;
8254         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
8255                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
8256                 break;
8257         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
8258                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
8259                 break;
8260         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
8261                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
8262                 break;
8263         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
8264                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
8265                 break;
8266         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
8267                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
8268                 break;
8269         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
8270                 gfx_v10_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
8271                 break;
8272         default:
8273                 break;
8274         }
8275         return 0;
8276 }
8277
8278 static int gfx_v10_0_eop_irq(struct amdgpu_device *adev,
8279                              struct amdgpu_irq_src *source,
8280                              struct amdgpu_iv_entry *entry)
8281 {
8282         int i;
8283         u8 me_id, pipe_id, queue_id;
8284         struct amdgpu_ring *ring;
8285
8286         DRM_DEBUG("IH: CP EOP\n");
8287         me_id = (entry->ring_id & 0x0c) >> 2;
8288         pipe_id = (entry->ring_id & 0x03) >> 0;
8289         queue_id = (entry->ring_id & 0x70) >> 4;
8290
8291         switch (me_id) {
8292         case 0:
8293                 if (pipe_id == 0)
8294                         amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
8295                 else
8296                         amdgpu_fence_process(&adev->gfx.gfx_ring[1]);
8297                 break;
8298         case 1:
8299         case 2:
8300                 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
8301                         ring = &adev->gfx.compute_ring[i];
8302                         /* Per-queue interrupt is supported for MEC starting from VI.
8303                           * The interrupt can only be enabled/disabled per pipe instead of per queue.
8304                           */
8305                         if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id))
8306                                 amdgpu_fence_process(ring);
8307                 }
8308                 break;
8309         }
8310         return 0;
8311 }
8312
8313 static int gfx_v10_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
8314                                               struct amdgpu_irq_src *source,
8315                                               unsigned type,
8316                                               enum amdgpu_interrupt_state state)
8317 {
8318         switch (state) {
8319         case AMDGPU_IRQ_STATE_DISABLE:
8320         case AMDGPU_IRQ_STATE_ENABLE:
8321                 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
8322                                PRIV_REG_INT_ENABLE,
8323                                state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
8324                 break;
8325         default:
8326                 break;
8327         }
8328
8329         return 0;
8330 }
8331
8332 static int gfx_v10_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
8333                                                struct amdgpu_irq_src *source,
8334                                                unsigned type,
8335                                                enum amdgpu_interrupt_state state)
8336 {
8337         switch (state) {
8338         case AMDGPU_IRQ_STATE_DISABLE:
8339         case AMDGPU_IRQ_STATE_ENABLE:
8340                 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
8341                                PRIV_INSTR_INT_ENABLE,
8342                                state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
8343         default:
8344                 break;
8345         }
8346
8347         return 0;
8348 }
8349
8350 static void gfx_v10_0_handle_priv_fault(struct amdgpu_device *adev,
8351                                         struct amdgpu_iv_entry *entry)
8352 {
8353         u8 me_id, pipe_id, queue_id;
8354         struct amdgpu_ring *ring;
8355         int i;
8356
8357         me_id = (entry->ring_id & 0x0c) >> 2;
8358         pipe_id = (entry->ring_id & 0x03) >> 0;
8359         queue_id = (entry->ring_id & 0x70) >> 4;
8360
8361         switch (me_id) {
8362         case 0:
8363                 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
8364                         ring = &adev->gfx.gfx_ring[i];
8365                         /* we only enabled 1 gfx queue per pipe for now */
8366                         if (ring->me == me_id && ring->pipe == pipe_id)
8367                                 drm_sched_fault(&ring->sched);
8368                 }
8369                 break;
8370         case 1:
8371         case 2:
8372                 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
8373                         ring = &adev->gfx.compute_ring[i];
8374                         if (ring->me == me_id && ring->pipe == pipe_id &&
8375                             ring->queue == queue_id)
8376                                 drm_sched_fault(&ring->sched);
8377                 }
8378                 break;
8379         default:
8380                 BUG();
8381         }
8382 }
8383
8384 static int gfx_v10_0_priv_reg_irq(struct amdgpu_device *adev,
8385                                   struct amdgpu_irq_src *source,
8386                                   struct amdgpu_iv_entry *entry)
8387 {
8388         DRM_ERROR("Illegal register access in command stream\n");
8389         gfx_v10_0_handle_priv_fault(adev, entry);
8390         return 0;
8391 }
8392
8393 static int gfx_v10_0_priv_inst_irq(struct amdgpu_device *adev,
8394                                    struct amdgpu_irq_src *source,
8395                                    struct amdgpu_iv_entry *entry)
8396 {
8397         DRM_ERROR("Illegal instruction in command stream\n");
8398         gfx_v10_0_handle_priv_fault(adev, entry);
8399         return 0;
8400 }
8401
8402 static int gfx_v10_0_kiq_set_interrupt_state(struct amdgpu_device *adev,
8403                                              struct amdgpu_irq_src *src,
8404                                              unsigned int type,
8405                                              enum amdgpu_interrupt_state state)
8406 {
8407         uint32_t tmp, target;
8408         struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
8409
8410         if (ring->me == 1)
8411                 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
8412         else
8413                 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME2_PIPE0_INT_CNTL);
8414         target += ring->pipe;
8415
8416         switch (type) {
8417         case AMDGPU_CP_KIQ_IRQ_DRIVER0:
8418                 if (state == AMDGPU_IRQ_STATE_DISABLE) {
8419                         tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
8420                         tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
8421                                             GENERIC2_INT_ENABLE, 0);
8422                         WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
8423
8424                         tmp = RREG32(target);
8425                         tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
8426                                             GENERIC2_INT_ENABLE, 0);
8427                         WREG32(target, tmp);
8428                 } else {
8429                         tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
8430                         tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
8431                                             GENERIC2_INT_ENABLE, 1);
8432                         WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
8433
8434                         tmp = RREG32(target);
8435                         tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
8436                                             GENERIC2_INT_ENABLE, 1);
8437                         WREG32(target, tmp);
8438                 }
8439                 break;
8440         default:
8441                 BUG(); /* kiq only support GENERIC2_INT now */
8442                 break;
8443         }
8444         return 0;
8445 }
8446
8447 static int gfx_v10_0_kiq_irq(struct amdgpu_device *adev,
8448                              struct amdgpu_irq_src *source,
8449                              struct amdgpu_iv_entry *entry)
8450 {
8451         u8 me_id, pipe_id, queue_id;
8452         struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
8453
8454         me_id = (entry->ring_id & 0x0c) >> 2;
8455         pipe_id = (entry->ring_id & 0x03) >> 0;
8456         queue_id = (entry->ring_id & 0x70) >> 4;
8457         DRM_DEBUG("IH: CPC GENERIC2_INT, me:%d, pipe:%d, queue:%d\n",
8458                    me_id, pipe_id, queue_id);
8459
8460         amdgpu_fence_process(ring);
8461         return 0;
8462 }
8463
8464 static void gfx_v10_0_emit_mem_sync(struct amdgpu_ring *ring)
8465 {
8466         const unsigned int gcr_cntl =
8467                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(1) |
8468                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(1) |
8469                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(1) |
8470                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(1) |
8471                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(1) |
8472                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(1) |
8473                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(1) |
8474                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(1);
8475
8476         /* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */
8477         amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6));
8478         amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */
8479         amdgpu_ring_write(ring, 0xffffffff);  /* CP_COHER_SIZE */
8480         amdgpu_ring_write(ring, 0xffffff);  /* CP_COHER_SIZE_HI */
8481         amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */
8482         amdgpu_ring_write(ring, 0);  /* CP_COHER_BASE_HI */
8483         amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */
8484         amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */
8485 }
8486
8487 static const struct amd_ip_funcs gfx_v10_0_ip_funcs = {
8488         .name = "gfx_v10_0",
8489         .early_init = gfx_v10_0_early_init,
8490         .late_init = gfx_v10_0_late_init,
8491         .sw_init = gfx_v10_0_sw_init,
8492         .sw_fini = gfx_v10_0_sw_fini,
8493         .hw_init = gfx_v10_0_hw_init,
8494         .hw_fini = gfx_v10_0_hw_fini,
8495         .suspend = gfx_v10_0_suspend,
8496         .resume = gfx_v10_0_resume,
8497         .is_idle = gfx_v10_0_is_idle,
8498         .wait_for_idle = gfx_v10_0_wait_for_idle,
8499         .soft_reset = gfx_v10_0_soft_reset,
8500         .set_clockgating_state = gfx_v10_0_set_clockgating_state,
8501         .set_powergating_state = gfx_v10_0_set_powergating_state,
8502         .get_clockgating_state = gfx_v10_0_get_clockgating_state,
8503 };
8504
8505 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = {
8506         .type = AMDGPU_RING_TYPE_GFX,
8507         .align_mask = 0xff,
8508         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
8509         .support_64bit_ptrs = true,
8510         .vmhub = AMDGPU_GFXHUB_0,
8511         .get_rptr = gfx_v10_0_ring_get_rptr_gfx,
8512         .get_wptr = gfx_v10_0_ring_get_wptr_gfx,
8513         .set_wptr = gfx_v10_0_ring_set_wptr_gfx,
8514         .emit_frame_size = /* totally 242 maximum if 16 IBs */
8515                 5 + /* COND_EXEC */
8516                 7 + /* PIPELINE_SYNC */
8517                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
8518                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
8519                 2 + /* VM_FLUSH */
8520                 8 + /* FENCE for VM_FLUSH */
8521                 20 + /* GDS switch */
8522                 4 + /* double SWITCH_BUFFER,
8523                      * the first COND_EXEC jump to the place
8524                      * just prior to this double SWITCH_BUFFER
8525                      */
8526                 5 + /* COND_EXEC */
8527                 7 + /* HDP_flush */
8528                 4 + /* VGT_flush */
8529                 14 + /* CE_META */
8530                 31 + /* DE_META */
8531                 3 + /* CNTX_CTRL */
8532                 5 + /* HDP_INVL */
8533                 8 + 8 + /* FENCE x2 */
8534                 2 + /* SWITCH_BUFFER */
8535                 8, /* gfx_v10_0_emit_mem_sync */
8536         .emit_ib_size = 4, /* gfx_v10_0_ring_emit_ib_gfx */
8537         .emit_ib = gfx_v10_0_ring_emit_ib_gfx,
8538         .emit_fence = gfx_v10_0_ring_emit_fence,
8539         .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync,
8540         .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush,
8541         .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch,
8542         .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush,
8543         .test_ring = gfx_v10_0_ring_test_ring,
8544         .test_ib = gfx_v10_0_ring_test_ib,
8545         .insert_nop = amdgpu_ring_insert_nop,
8546         .pad_ib = amdgpu_ring_generic_pad_ib,
8547         .emit_switch_buffer = gfx_v10_0_ring_emit_sb,
8548         .emit_cntxcntl = gfx_v10_0_ring_emit_cntxcntl,
8549         .init_cond_exec = gfx_v10_0_ring_emit_init_cond_exec,
8550         .patch_cond_exec = gfx_v10_0_ring_emit_patch_cond_exec,
8551         .preempt_ib = gfx_v10_0_ring_preempt_ib,
8552         .emit_frame_cntl = gfx_v10_0_ring_emit_frame_cntl,
8553         .emit_wreg = gfx_v10_0_ring_emit_wreg,
8554         .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
8555         .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
8556         .soft_recovery = gfx_v10_0_ring_soft_recovery,
8557         .emit_mem_sync = gfx_v10_0_emit_mem_sync,
8558 };
8559
8560 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_compute = {
8561         .type = AMDGPU_RING_TYPE_COMPUTE,
8562         .align_mask = 0xff,
8563         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
8564         .support_64bit_ptrs = true,
8565         .vmhub = AMDGPU_GFXHUB_0,
8566         .get_rptr = gfx_v10_0_ring_get_rptr_compute,
8567         .get_wptr = gfx_v10_0_ring_get_wptr_compute,
8568         .set_wptr = gfx_v10_0_ring_set_wptr_compute,
8569         .emit_frame_size =
8570                 20 + /* gfx_v10_0_ring_emit_gds_switch */
8571                 7 + /* gfx_v10_0_ring_emit_hdp_flush */
8572                 5 + /* hdp invalidate */
8573                 7 + /* gfx_v10_0_ring_emit_pipeline_sync */
8574                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
8575                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
8576                 2 + /* gfx_v10_0_ring_emit_vm_flush */
8577                 8 + 8 + 8 + /* gfx_v10_0_ring_emit_fence x3 for user fence, vm fence */
8578                 8, /* gfx_v10_0_emit_mem_sync */
8579         .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */
8580         .emit_ib = gfx_v10_0_ring_emit_ib_compute,
8581         .emit_fence = gfx_v10_0_ring_emit_fence,
8582         .emit_pipeline_sync = gfx_v10_0_ring_emit_pipeline_sync,
8583         .emit_vm_flush = gfx_v10_0_ring_emit_vm_flush,
8584         .emit_gds_switch = gfx_v10_0_ring_emit_gds_switch,
8585         .emit_hdp_flush = gfx_v10_0_ring_emit_hdp_flush,
8586         .test_ring = gfx_v10_0_ring_test_ring,
8587         .test_ib = gfx_v10_0_ring_test_ib,
8588         .insert_nop = amdgpu_ring_insert_nop,
8589         .pad_ib = amdgpu_ring_generic_pad_ib,
8590         .emit_wreg = gfx_v10_0_ring_emit_wreg,
8591         .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
8592         .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
8593         .emit_mem_sync = gfx_v10_0_emit_mem_sync,
8594 };
8595
8596 static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_kiq = {
8597         .type = AMDGPU_RING_TYPE_KIQ,
8598         .align_mask = 0xff,
8599         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
8600         .support_64bit_ptrs = true,
8601         .vmhub = AMDGPU_GFXHUB_0,
8602         .get_rptr = gfx_v10_0_ring_get_rptr_compute,
8603         .get_wptr = gfx_v10_0_ring_get_wptr_compute,
8604         .set_wptr = gfx_v10_0_ring_set_wptr_compute,
8605         .emit_frame_size =
8606                 20 + /* gfx_v10_0_ring_emit_gds_switch */
8607                 7 + /* gfx_v10_0_ring_emit_hdp_flush */
8608                 5 + /*hdp invalidate */
8609                 7 + /* gfx_v10_0_ring_emit_pipeline_sync */
8610                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
8611                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
8612                 2 + /* gfx_v10_0_ring_emit_vm_flush */
8613                 8 + 8 + 8, /* gfx_v10_0_ring_emit_fence_kiq x3 for user fence, vm fence */
8614         .emit_ib_size = 7, /* gfx_v10_0_ring_emit_ib_compute */
8615         .emit_ib = gfx_v10_0_ring_emit_ib_compute,
8616         .emit_fence = gfx_v10_0_ring_emit_fence_kiq,
8617         .test_ring = gfx_v10_0_ring_test_ring,
8618         .test_ib = gfx_v10_0_ring_test_ib,
8619         .insert_nop = amdgpu_ring_insert_nop,
8620         .pad_ib = amdgpu_ring_generic_pad_ib,
8621         .emit_rreg = gfx_v10_0_ring_emit_rreg,
8622         .emit_wreg = gfx_v10_0_ring_emit_wreg,
8623         .emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,
8624         .emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait,
8625 };
8626
8627 static void gfx_v10_0_set_ring_funcs(struct amdgpu_device *adev)
8628 {
8629         int i;
8630
8631         adev->gfx.kiq.ring.funcs = &gfx_v10_0_ring_funcs_kiq;
8632
8633         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
8634                 adev->gfx.gfx_ring[i].funcs = &gfx_v10_0_ring_funcs_gfx;
8635
8636         for (i = 0; i < adev->gfx.num_compute_rings; i++)
8637                 adev->gfx.compute_ring[i].funcs = &gfx_v10_0_ring_funcs_compute;
8638 }
8639
8640 static const struct amdgpu_irq_src_funcs gfx_v10_0_eop_irq_funcs = {
8641         .set = gfx_v10_0_set_eop_interrupt_state,
8642         .process = gfx_v10_0_eop_irq,
8643 };
8644
8645 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_reg_irq_funcs = {
8646         .set = gfx_v10_0_set_priv_reg_fault_state,
8647         .process = gfx_v10_0_priv_reg_irq,
8648 };
8649
8650 static const struct amdgpu_irq_src_funcs gfx_v10_0_priv_inst_irq_funcs = {
8651         .set = gfx_v10_0_set_priv_inst_fault_state,
8652         .process = gfx_v10_0_priv_inst_irq,
8653 };
8654
8655 static const struct amdgpu_irq_src_funcs gfx_v10_0_kiq_irq_funcs = {
8656         .set = gfx_v10_0_kiq_set_interrupt_state,
8657         .process = gfx_v10_0_kiq_irq,
8658 };
8659
8660 static void gfx_v10_0_set_irq_funcs(struct amdgpu_device *adev)
8661 {
8662         adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
8663         adev->gfx.eop_irq.funcs = &gfx_v10_0_eop_irq_funcs;
8664
8665         adev->gfx.kiq.irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST;
8666         adev->gfx.kiq.irq.funcs = &gfx_v10_0_kiq_irq_funcs;
8667
8668         adev->gfx.priv_reg_irq.num_types = 1;
8669         adev->gfx.priv_reg_irq.funcs = &gfx_v10_0_priv_reg_irq_funcs;
8670
8671         adev->gfx.priv_inst_irq.num_types = 1;
8672         adev->gfx.priv_inst_irq.funcs = &gfx_v10_0_priv_inst_irq_funcs;
8673 }
8674
8675 static void gfx_v10_0_set_rlc_funcs(struct amdgpu_device *adev)
8676 {
8677         switch (adev->asic_type) {
8678         case CHIP_NAVI10:
8679         case CHIP_NAVI14:
8680         case CHIP_SIENNA_CICHLID:
8681         case CHIP_NAVY_FLOUNDER:
8682                 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs;
8683                 break;
8684         case CHIP_NAVI12:
8685                 adev->gfx.rlc.funcs = &gfx_v10_0_rlc_funcs_sriov;
8686                 break;
8687         default:
8688                 break;
8689         }
8690 }
8691
8692 static void gfx_v10_0_set_gds_init(struct amdgpu_device *adev)
8693 {
8694         unsigned total_cu = adev->gfx.config.max_cu_per_sh *
8695                             adev->gfx.config.max_sh_per_se *
8696                             adev->gfx.config.max_shader_engines;
8697
8698         adev->gds.gds_size = 0x10000;
8699         adev->gds.gds_compute_max_wave_id = total_cu * 32 - 1;
8700         adev->gds.gws_size = 64;
8701         adev->gds.oa_size = 16;
8702 }
8703
8704 static void gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev,
8705                                                           u32 bitmap)
8706 {
8707         u32 data;
8708
8709         if (!bitmap)
8710                 return;
8711
8712         data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
8713         data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
8714
8715         WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data);
8716 }
8717
8718 static u32 gfx_v10_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev)
8719 {
8720         u32 data, wgp_bitmask;
8721         data = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG);
8722         data |= RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG);
8723
8724         data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
8725         data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
8726
8727         wgp_bitmask =
8728                 amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1);
8729
8730         return (~data) & wgp_bitmask;
8731 }
8732
8733 static u32 gfx_v10_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev)
8734 {
8735         u32 wgp_idx, wgp_active_bitmap;
8736         u32 cu_bitmap_per_wgp, cu_active_bitmap;
8737
8738         wgp_active_bitmap = gfx_v10_0_get_wgp_active_bitmap_per_sh(adev);
8739         cu_active_bitmap = 0;
8740
8741         for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) {
8742                 /* if there is one WGP enabled, it means 2 CUs will be enabled */
8743                 cu_bitmap_per_wgp = 3 << (2 * wgp_idx);
8744                 if (wgp_active_bitmap & (1 << wgp_idx))
8745                         cu_active_bitmap |= cu_bitmap_per_wgp;
8746         }
8747
8748         return cu_active_bitmap;
8749 }
8750
8751 static int gfx_v10_0_get_cu_info(struct amdgpu_device *adev,
8752                                  struct amdgpu_cu_info *cu_info)
8753 {
8754         int i, j, k, counter, active_cu_number = 0;
8755         u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
8756         unsigned disable_masks[4 * 2];
8757
8758         if (!adev || !cu_info)
8759                 return -EINVAL;
8760
8761         amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);
8762
8763         mutex_lock(&adev->grbm_idx_mutex);
8764         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
8765                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
8766                         mask = 1;
8767                         ao_bitmap = 0;
8768                         counter = 0;
8769                         gfx_v10_0_select_se_sh(adev, i, j, 0xffffffff);
8770                         if (i < 4 && j < 2)
8771                                 gfx_v10_0_set_user_wgp_inactive_bitmap_per_sh(
8772                                         adev, disable_masks[i * 2 + j]);
8773                         bitmap = gfx_v10_0_get_cu_active_bitmap_per_sh(adev);
8774                         cu_info->bitmap[i][j] = bitmap;
8775
8776                         for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) {
8777                                 if (bitmap & mask) {
8778                                         if (counter < adev->gfx.config.max_cu_per_sh)
8779                                                 ao_bitmap |= mask;
8780                                         counter++;
8781                                 }
8782                                 mask <<= 1;
8783                         }
8784                         active_cu_number += counter;
8785                         if (i < 2 && j < 2)
8786                                 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
8787                         cu_info->ao_cu_bitmap[i][j] = ao_bitmap;
8788                 }
8789         }
8790         gfx_v10_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
8791         mutex_unlock(&adev->grbm_idx_mutex);
8792
8793         cu_info->number = active_cu_number;
8794         cu_info->ao_cu_mask = ao_cu_mask;
8795         cu_info->simd_per_cu = NUM_SIMD_PER_CU;
8796
8797         return 0;
8798 }
8799
8800 const struct amdgpu_ip_block_version gfx_v10_0_ip_block =
8801 {
8802         .type = AMD_IP_BLOCK_TYPE_GFX,
8803         .major = 10,
8804         .minor = 0,
8805         .rev = 0,
8806         .funcs = &gfx_v10_0_ip_funcs,
8807 };