drivers/gpu/drm/i915/intel_pm.c

   1 /*
   2  * Copyright © 2012 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <[email protected]>
  25  *
  26  */
  27
  28 #include <linux/cpufreq.h>
  29 #include "i915_drv.h"
  30 #include "intel_drv.h"
  31 #include "../../../platform/x86/intel_ips.h"
  32 #include <linux/module.h>
  33
  34 /**
  35  * RC6 is a special power stage which allows the GPU to enter an very
  36  * low-voltage mode when idle, using down to 0V while at this stage.  This
  37  * stage is entered automatically when the GPU is idle when RC6 support is
  38  * enabled, and as soon as new workload arises GPU wakes up automatically as well.
  39  *
  40  * There are different RC6 modes available in Intel GPU, which differentiate
  41  * among each other with the latency required to enter and leave RC6 and
  42  * voltage consumed by the GPU in different states.
  43  *
  44  * The combination of the following flags define which states GPU is allowed
  45  * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
  46  * RC6pp is deepest RC6. Their support by hardware varies according to the
  47  * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
  48  * which brings the most power savings; deeper states save more power, but
  49  * require higher latency to switch to and wake up.
  50  */
  51 #define INTEL_RC6_ENABLE                        (1<<0)
  52 #define INTEL_RC6p_ENABLE                       (1<<1)
  53 #define INTEL_RC6pp_ENABLE                      (1<<2)
  54
  55 static void bxt_init_clock_gating(struct drm_device *dev)
  56 {
  57         struct drm_i915_private *dev_priv = dev->dev_private;
  58
  59         /* WaDisableSDEUnitClockGating:bxt */
  60         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
  61                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
  62
  63         /*
  64          * FIXME:
  65          * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
  66          */
  67         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
  68                    GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
  69 }
  70
  71 static void i915_pineview_get_mem_freq(struct drm_device *dev)
  72 {
  73         struct drm_i915_private *dev_priv = dev->dev_private;
  74         u32 tmp;
  75
  76         tmp = I915_READ(CLKCFG);
  77
  78         switch (tmp & CLKCFG_FSB_MASK) {
  79         case CLKCFG_FSB_533:
  80                 dev_priv->fsb_freq = 533; /* 133*4 */
  81                 break;
  82         case CLKCFG_FSB_800:
  83                 dev_priv->fsb_freq = 800; /* 200*4 */
  84                 break;
  85         case CLKCFG_FSB_667:
  86                 dev_priv->fsb_freq =  667; /* 167*4 */
  87                 break;
  88         case CLKCFG_FSB_400:
  89                 dev_priv->fsb_freq = 400; /* 100*4 */
  90                 break;
  91         }
  92
  93         switch (tmp & CLKCFG_MEM_MASK) {
  94         case CLKCFG_MEM_533:
  95                 dev_priv->mem_freq = 533;
  96                 break;
  97         case CLKCFG_MEM_667:
  98                 dev_priv->mem_freq = 667;
  99                 break;
 100         case CLKCFG_MEM_800:
 101                 dev_priv->mem_freq = 800;
 102                 break;
 103         }
 104
 105         /* detect pineview DDR3 setting */
 106         tmp = I915_READ(CSHRDDR3CTL);
 107         dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
 108 }
 109
 110 static void i915_ironlake_get_mem_freq(struct drm_device *dev)
 111 {
 112         struct drm_i915_private *dev_priv = dev->dev_private;
 113         u16 ddrpll, csipll;
 114
 115         ddrpll = I915_READ16(DDRMPLL1);
 116         csipll = I915_READ16(CSIPLL0);
 117
 118         switch (ddrpll & 0xff) {
 119         case 0xc:
 120                 dev_priv->mem_freq = 800;
 121                 break;
 122         case 0x10:
 123                 dev_priv->mem_freq = 1066;
 124                 break;
 125         case 0x14:
 126                 dev_priv->mem_freq = 1333;
 127                 break;
 128         case 0x18:
 129                 dev_priv->mem_freq = 1600;
 130                 break;
 131         default:
 132                 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
 133                                  ddrpll & 0xff);
 134                 dev_priv->mem_freq = 0;
 135                 break;
 136         }
 137
 138         dev_priv->ips.r_t = dev_priv->mem_freq;
 139
 140         switch (csipll & 0x3ff) {
 141         case 0x00c:
 142                 dev_priv->fsb_freq = 3200;
 143                 break;
 144         case 0x00e:
 145                 dev_priv->fsb_freq = 3733;
 146                 break;
 147         case 0x010:
 148                 dev_priv->fsb_freq = 4266;
 149                 break;
 150         case 0x012:
 151                 dev_priv->fsb_freq = 4800;
 152                 break;
 153         case 0x014:
 154                 dev_priv->fsb_freq = 5333;
 155                 break;
 156         case 0x016:
 157                 dev_priv->fsb_freq = 5866;
 158                 break;
 159         case 0x018:
 160                 dev_priv->fsb_freq = 6400;
 161                 break;
 162         default:
 163                 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
 164                                  csipll & 0x3ff);
 165                 dev_priv->fsb_freq = 0;
 166                 break;
 167         }
 168
 169         if (dev_priv->fsb_freq == 3200) {
 170                 dev_priv->ips.c_m = 0;
 171         } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
 172                 dev_priv->ips.c_m = 1;
 173         } else {
 174                 dev_priv->ips.c_m = 2;
 175         }
 176 }
 177
 178 static const struct cxsr_latency cxsr_latency_table[] = {
 179         {1, 0, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
 180         {1, 0, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
 181         {1, 0, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
 182         {1, 1, 800, 667, 6420, 36420, 6873, 36873},    /* DDR3-667 SC */
 183         {1, 1, 800, 800, 5902, 35902, 6318, 36318},    /* DDR3-800 SC */
 184
 185         {1, 0, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
 186         {1, 0, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
 187         {1, 0, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
 188         {1, 1, 667, 667, 6438, 36438, 6911, 36911},    /* DDR3-667 SC */
 189         {1, 1, 667, 800, 5941, 35941, 6377, 36377},    /* DDR3-800 SC */
 190
 191         {1, 0, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
 192         {1, 0, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
 193         {1, 0, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
 194         {1, 1, 400, 667, 6509, 36509, 7062, 37062},    /* DDR3-667 SC */
 195         {1, 1, 400, 800, 5985, 35985, 6501, 36501},    /* DDR3-800 SC */
 196
 197         {0, 0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
 198         {0, 0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
 199         {0, 0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
 200         {0, 1, 800, 667, 6476, 36476, 6955, 36955},    /* DDR3-667 SC */
 201         {0, 1, 800, 800, 5958, 35958, 6400, 36400},    /* DDR3-800 SC */
 202
 203         {0, 0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
 204         {0, 0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
 205         {0, 0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
 206         {0, 1, 667, 667, 6494, 36494, 6993, 36993},    /* DDR3-667 SC */
 207         {0, 1, 667, 800, 5998, 35998, 6460, 36460},    /* DDR3-800 SC */
 208
 209         {0, 0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
 210         {0, 0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
 211         {0, 0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
 212         {0, 1, 400, 667, 6566, 36566, 7145, 37145},    /* DDR3-667 SC */
 213         {0, 1, 400, 800, 6042, 36042, 6584, 36584},    /* DDR3-800 SC */
 214 };
 215
 216 static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
 217                                                          int is_ddr3,
 218                                                          int fsb,
 219                                                          int mem)
 220 {
 221         const struct cxsr_latency *latency;
 222         int i;
 223
 224         if (fsb == 0 || mem == 0)
 225                 return NULL;
 226
 227         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
 228                 latency = &cxsr_latency_table[i];
 229                 if (is_desktop == latency->is_desktop &&
 230                     is_ddr3 == latency->is_ddr3 &&
 231                     fsb == latency->fsb_freq && mem == latency->mem_freq)
 232                         return latency;
 233         }
 234
 235         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
 236
 237         return NULL;
 238 }
 239
 240 static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable)
 241 {
 242         u32 val;
 243
 244         mutex_lock(&dev_priv->rps.hw_lock);
 245
 246         val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
 247         if (enable)
 248                 val &= ~FORCE_DDR_HIGH_FREQ;
 249         else
 250                 val |= FORCE_DDR_HIGH_FREQ;
 251         val &= ~FORCE_DDR_LOW_FREQ;
 252         val |= FORCE_DDR_FREQ_REQ_ACK;
 253         vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
 254
 255         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
 256                       FORCE_DDR_FREQ_REQ_ACK) == 0, 3))
 257                 DRM_ERROR("timed out waiting for Punit DDR DVFS request\n");
 258
 259         mutex_unlock(&dev_priv->rps.hw_lock);
 260 }
 261
 262 static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable)
 263 {
 264         u32 val;
 265
 266         mutex_lock(&dev_priv->rps.hw_lock);
 267
 268         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
 269         if (enable)
 270                 val |= DSP_MAXFIFO_PM5_ENABLE;
 271         else
 272                 val &= ~DSP_MAXFIFO_PM5_ENABLE;
 273         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
 274
 275         mutex_unlock(&dev_priv->rps.hw_lock);
 276 }
 277
 278 #define FW_WM(value, plane) \
 279         (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK)
 280
 281 void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
 282 {
 283         struct drm_device *dev = dev_priv->dev;
 284         u32 val;
 285
 286         if (IS_VALLEYVIEW(dev)) {
 287                 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
 288                 POSTING_READ(FW_BLC_SELF_VLV);
 289                 dev_priv->wm.vlv.cxsr = enable;
 290         } else if (IS_G4X(dev) || IS_CRESTLINE(dev)) {
 291                 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
 292                 POSTING_READ(FW_BLC_SELF);
 293         } else if (IS_PINEVIEW(dev)) {
 294                 val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN;
 295                 val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0;
 296                 I915_WRITE(DSPFW3, val);
 297                 POSTING_READ(DSPFW3);
 298         } else if (IS_I945G(dev) || IS_I945GM(dev)) {
 299                 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
 300                                _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
 301                 I915_WRITE(FW_BLC_SELF, val);
 302                 POSTING_READ(FW_BLC_SELF);
 303         } else if (IS_I915GM(dev)) {
 304                 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
 305                                _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
 306                 I915_WRITE(INSTPM, val);
 307                 POSTING_READ(INSTPM);
 308         } else {
 309                 return;
 310         }
 311
 312         DRM_DEBUG_KMS("memory self-refresh is %s\n",
 313                       enable ? "enabled" : "disabled");
 314 }
 315
 316
 317 /*
 318  * Latency for FIFO fetches is dependent on several factors:
 319  *   - memory configuration (speed, channels)
 320  *   - chipset
 321  *   - current MCH state
 322  * It can be fairly high in some situations, so here we assume a fairly
 323  * pessimal value.  It's a tradeoff between extra memory fetches (if we
 324  * set this value too high, the FIFO will fetch frequently to stay full)
 325  * and power consumption (set it too low to save power and we might see
 326  * FIFO underruns and display "flicker").
 327  *
 328  * A value of 5us seems to be a good balance; safe for very low end
 329  * platforms but not overly aggressive on lower latency configs.
 330  */
 331 static const int pessimal_latency_ns = 5000;
 332
 333 #define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
 334         ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
 335
 336 static int vlv_get_fifo_size(struct drm_device *dev,
 337                               enum pipe pipe, int plane)
 338 {
 339         struct drm_i915_private *dev_priv = dev->dev_private;
 340         int sprite0_start, sprite1_start, size;
 341
 342         switch (pipe) {
 343                 uint32_t dsparb, dsparb2, dsparb3;
 344         case PIPE_A:
 345                 dsparb = I915_READ(DSPARB);
 346                 dsparb2 = I915_READ(DSPARB2);
 347                 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0);
 348                 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4);
 349                 break;
 350         case PIPE_B:
 351                 dsparb = I915_READ(DSPARB);
 352                 dsparb2 = I915_READ(DSPARB2);
 353                 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8);
 354                 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12);
 355                 break;
 356         case PIPE_C:
 357                 dsparb2 = I915_READ(DSPARB2);
 358                 dsparb3 = I915_READ(DSPARB3);
 359                 sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16);
 360                 sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20);
 361                 break;
 362         default:
 363                 return 0;
 364         }
 365
 366         switch (plane) {
 367         case 0:
 368                 size = sprite0_start;
 369                 break;
 370         case 1:
 371                 size = sprite1_start - sprite0_start;
 372                 break;
 373         case 2:
 374                 size = 512 - 1 - sprite1_start;
 375                 break;
 376         default:
 377                 return 0;
 378         }
 379
 380         DRM_DEBUG_KMS("Pipe %c %s %c FIFO size: %d\n",
 381                       pipe_name(pipe), plane == 0 ? "primary" : "sprite",
 382                       plane == 0 ? plane_name(pipe) : sprite_name(pipe, plane - 1),
 383                       size);
 384
 385         return size;
 386 }
 387
 388 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
 389 {
 390         struct drm_i915_private *dev_priv = dev->dev_private;
 391         uint32_t dsparb = I915_READ(DSPARB);
 392         int size;
 393
 394         size = dsparb & 0x7f;
 395         if (plane)
 396                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
 397
 398         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 399                       plane ? "B" : "A", size);
 400
 401         return size;
 402 }
 403
 404 static int i830_get_fifo_size(struct drm_device *dev, int plane)
 405 {
 406         struct drm_i915_private *dev_priv = dev->dev_private;
 407         uint32_t dsparb = I915_READ(DSPARB);
 408         int size;
 409
 410         size = dsparb & 0x1ff;
 411         if (plane)
 412                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
 413         size >>= 1; /* Convert to cachelines */
 414
 415         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 416                       plane ? "B" : "A", size);
 417
 418         return size;
 419 }
 420
 421 static int i845_get_fifo_size(struct drm_device *dev, int plane)
 422 {
 423         struct drm_i915_private *dev_priv = dev->dev_private;
 424         uint32_t dsparb = I915_READ(DSPARB);
 425         int size;
 426
 427         size = dsparb & 0x7f;
 428         size >>= 2; /* Convert to cachelines */
 429
 430         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
 431                       plane ? "B" : "A",
 432                       size);
 433
 434         return size;
 435 }
 436
 437 /* Pineview has different values for various configs */
 438 static const struct intel_watermark_params pineview_display_wm = {
 439         .fifo_size = PINEVIEW_DISPLAY_FIFO,
 440         .max_wm = PINEVIEW_MAX_WM,
 441         .default_wm = PINEVIEW_DFT_WM,
 442         .guard_size = PINEVIEW_GUARD_WM,
 443         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 444 };
 445 static const struct intel_watermark_params pineview_display_hplloff_wm = {
 446         .fifo_size = PINEVIEW_DISPLAY_FIFO,
 447         .max_wm = PINEVIEW_MAX_WM,
 448         .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
 449         .guard_size = PINEVIEW_GUARD_WM,
 450         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 451 };
 452 static const struct intel_watermark_params pineview_cursor_wm = {
 453         .fifo_size = PINEVIEW_CURSOR_FIFO,
 454         .max_wm = PINEVIEW_CURSOR_MAX_WM,
 455         .default_wm = PINEVIEW_CURSOR_DFT_WM,
 456         .guard_size = PINEVIEW_CURSOR_GUARD_WM,
 457         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 458 };
 459 static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
 460         .fifo_size = PINEVIEW_CURSOR_FIFO,
 461         .max_wm = PINEVIEW_CURSOR_MAX_WM,
 462         .default_wm = PINEVIEW_CURSOR_DFT_WM,
 463         .guard_size = PINEVIEW_CURSOR_GUARD_WM,
 464         .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
 465 };
 466 static const struct intel_watermark_params g4x_wm_info = {
 467         .fifo_size = G4X_FIFO_SIZE,
 468         .max_wm = G4X_MAX_WM,
 469         .default_wm = G4X_MAX_WM,
 470         .guard_size = 2,
 471         .cacheline_size = G4X_FIFO_LINE_SIZE,
 472 };
 473 static const struct intel_watermark_params g4x_cursor_wm_info = {
 474         .fifo_size = I965_CURSOR_FIFO,
 475         .max_wm = I965_CURSOR_MAX_WM,
 476         .default_wm = I965_CURSOR_DFT_WM,
 477         .guard_size = 2,
 478         .cacheline_size = G4X_FIFO_LINE_SIZE,
 479 };
 480 static const struct intel_watermark_params valleyview_wm_info = {
 481         .fifo_size = VALLEYVIEW_FIFO_SIZE,
 482         .max_wm = VALLEYVIEW_MAX_WM,
 483         .default_wm = VALLEYVIEW_MAX_WM,
 484         .guard_size = 2,
 485         .cacheline_size = G4X_FIFO_LINE_SIZE,
 486 };
 487 static const struct intel_watermark_params valleyview_cursor_wm_info = {
 488         .fifo_size = I965_CURSOR_FIFO,
 489         .max_wm = VALLEYVIEW_CURSOR_MAX_WM,
 490         .default_wm = I965_CURSOR_DFT_WM,
 491         .guard_size = 2,
 492         .cacheline_size = G4X_FIFO_LINE_SIZE,
 493 };
 494 static const struct intel_watermark_params i965_cursor_wm_info = {
 495         .fifo_size = I965_CURSOR_FIFO,
 496         .max_wm = I965_CURSOR_MAX_WM,
 497         .default_wm = I965_CURSOR_DFT_WM,
 498         .guard_size = 2,
 499         .cacheline_size = I915_FIFO_LINE_SIZE,
 500 };
 501 static const struct intel_watermark_params i945_wm_info = {
 502         .fifo_size = I945_FIFO_SIZE,
 503         .max_wm = I915_MAX_WM,
 504         .default_wm = 1,
 505         .guard_size = 2,
 506         .cacheline_size = I915_FIFO_LINE_SIZE,
 507 };
 508 static const struct intel_watermark_params i915_wm_info = {
 509         .fifo_size = I915_FIFO_SIZE,
 510         .max_wm = I915_MAX_WM,
 511         .default_wm = 1,
 512         .guard_size = 2,
 513         .cacheline_size = I915_FIFO_LINE_SIZE,
 514 };
 515 static const struct intel_watermark_params i830_a_wm_info = {
 516         .fifo_size = I855GM_FIFO_SIZE,
 517         .max_wm = I915_MAX_WM,
 518         .default_wm = 1,
 519         .guard_size = 2,
 520         .cacheline_size = I830_FIFO_LINE_SIZE,
 521 };
 522 static const struct intel_watermark_params i830_bc_wm_info = {
 523         .fifo_size = I855GM_FIFO_SIZE,
 524         .max_wm = I915_MAX_WM/2,
 525         .default_wm = 1,
 526         .guard_size = 2,
 527         .cacheline_size = I830_FIFO_LINE_SIZE,
 528 };
 529 static const struct intel_watermark_params i845_wm_info = {
 530         .fifo_size = I830_FIFO_SIZE,
 531         .max_wm = I915_MAX_WM,
 532         .default_wm = 1,
 533         .guard_size = 2,
 534         .cacheline_size = I830_FIFO_LINE_SIZE,
 535 };
 536
 537 /**
 538  * intel_calculate_wm - calculate watermark level
 539  * @clock_in_khz: pixel clock
 540  * @wm: chip FIFO params
 541  * @pixel_size: display pixel size
 542  * @latency_ns: memory latency for the platform
 543  *
 544  * Calculate the watermark level (the level at which the display plane will
 545  * start fetching from memory again).  Each chip has a different display
 546  * FIFO size and allocation, so the caller needs to figure that out and pass
 547  * in the correct intel_watermark_params structure.
 548  *
 549  * As the pixel clock runs, the FIFO will be drained at a rate that depends
 550  * on the pixel size.  When it reaches the watermark level, it'll start
 551  * fetching FIFO line sized based chunks from memory until the FIFO fills
 552  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
 553  * will occur, and a display engine hang could result.
 554  */
 555 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
 556                                         const struct intel_watermark_params *wm,
 557                                         int fifo_size,
 558                                         int pixel_size,
 559                                         unsigned long latency_ns)
 560 {
 561         long entries_required, wm_size;
 562
 563         /*
 564          * Note: we need to make sure we don't overflow for various clock &
 565          * latency values.
 566          * clocks go from a few thousand to several hundred thousand.
 567          * latency is usually a few thousand
 568          */
 569         entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
 570                 1000;
 571         entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
 572
 573         DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
 574
 575         wm_size = fifo_size - (entries_required + wm->guard_size);
 576
 577         DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
 578
 579         /* Don't promote wm_size to unsigned... */
 580         if (wm_size > (long)wm->max_wm)
 581                 wm_size = wm->max_wm;
 582         if (wm_size <= 0)
 583                 wm_size = wm->default_wm;
 584
 585         /*
 586          * Bspec seems to indicate that the value shouldn't be lower than
 587          * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
 588          * Lets go for 8 which is the burst size since certain platforms
 589          * already use a hardcoded 8 (which is what the spec says should be
 590          * done).
 591          */
 592         if (wm_size <= 8)
 593                 wm_size = 8;
 594
 595         return wm_size;
 596 }
 597
 598 static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
 599 {
 600         struct drm_crtc *crtc, *enabled = NULL;
 601
 602         for_each_crtc(dev, crtc) {
 603                 if (intel_crtc_active(crtc)) {
 604                         if (enabled)
 605                                 return NULL;
 606                         enabled = crtc;
 607                 }
 608         }
 609
 610         return enabled;
 611 }
 612
 613 static void pineview_update_wm(struct drm_crtc *unused_crtc)
 614 {
 615         struct drm_device *dev = unused_crtc->dev;
 616         struct drm_i915_private *dev_priv = dev->dev_private;
 617         struct drm_crtc *crtc;
 618         const struct cxsr_latency *latency;
 619         u32 reg;
 620         unsigned long wm;
 621
 622         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
 623                                          dev_priv->fsb_freq, dev_priv->mem_freq);
 624         if (!latency) {
 625                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
 626                 intel_set_memory_cxsr(dev_priv, false);
 627                 return;
 628         }
 629
 630         crtc = single_enabled_crtc(dev);
 631         if (crtc) {
 632                 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
 633                 int pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
 634                 int clock = adjusted_mode->crtc_clock;
 635
 636                 /* Display SR */
 637                 wm = intel_calculate_wm(clock, &pineview_display_wm,
 638                                         pineview_display_wm.fifo_size,
 639                                         pixel_size, latency->display_sr);
 640                 reg = I915_READ(DSPFW1);
 641                 reg &= ~DSPFW_SR_MASK;
 642                 reg |= FW_WM(wm, SR);
 643                 I915_WRITE(DSPFW1, reg);
 644                 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
 645
 646                 /* cursor SR */
 647                 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
 648                                         pineview_display_wm.fifo_size,
 649                                         pixel_size, latency->cursor_sr);
 650                 reg = I915_READ(DSPFW3);
 651                 reg &= ~DSPFW_CURSOR_SR_MASK;
 652                 reg |= FW_WM(wm, CURSOR_SR);
 653                 I915_WRITE(DSPFW3, reg);
 654
 655                 /* Display HPLL off SR */
 656                 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
 657                                         pineview_display_hplloff_wm.fifo_size,
 658                                         pixel_size, latency->display_hpll_disable);
 659                 reg = I915_READ(DSPFW3);
 660                 reg &= ~DSPFW_HPLL_SR_MASK;
 661                 reg |= FW_WM(wm, HPLL_SR);
 662                 I915_WRITE(DSPFW3, reg);
 663
 664                 /* cursor HPLL off SR */
 665                 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
 666                                         pineview_display_hplloff_wm.fifo_size,
 667                                         pixel_size, latency->cursor_hpll_disable);
 668                 reg = I915_READ(DSPFW3);
 669                 reg &= ~DSPFW_HPLL_CURSOR_MASK;
 670                 reg |= FW_WM(wm, HPLL_CURSOR);
 671                 I915_WRITE(DSPFW3, reg);
 672                 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
 673
 674                 intel_set_memory_cxsr(dev_priv, true);
 675         } else {
 676                 intel_set_memory_cxsr(dev_priv, false);
 677         }
 678 }
 679
 680 static bool g4x_compute_wm0(struct drm_device *dev,
 681                             int plane,
 682                             const struct intel_watermark_params *display,
 683                             int display_latency_ns,
 684                             const struct intel_watermark_params *cursor,
 685                             int cursor_latency_ns,
 686                             int *plane_wm,
 687                             int *cursor_wm)
 688 {
 689         struct drm_crtc *crtc;
 690         const struct drm_display_mode *adjusted_mode;
 691         int htotal, hdisplay, clock, pixel_size;
 692         int line_time_us, line_count;
 693         int entries, tlb_miss;
 694
 695         crtc = intel_get_crtc_for_plane(dev, plane);
 696         if (!intel_crtc_active(crtc)) {
 697                 *cursor_wm = cursor->guard_size;
 698                 *plane_wm = display->guard_size;
 699                 return false;
 700         }
 701
 702         adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
 703         clock = adjusted_mode->crtc_clock;
 704         htotal = adjusted_mode->crtc_htotal;
 705         hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
 706         pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
 707
 708         /* Use the small buffer method to calculate plane watermark */
 709         entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
 710         tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
 711         if (tlb_miss > 0)
 712                 entries += tlb_miss;
 713         entries = DIV_ROUND_UP(entries, display->cacheline_size);
 714         *plane_wm = entries + display->guard_size;
 715         if (*plane_wm > (int)display->max_wm)
 716                 *plane_wm = display->max_wm;
 717
 718         /* Use the large buffer method to calculate cursor watermark */
 719         line_time_us = max(htotal * 1000 / clock, 1);
 720         line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
 721         entries = line_count * crtc->cursor->state->crtc_w * pixel_size;
 722         tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
 723         if (tlb_miss > 0)
 724                 entries += tlb_miss;
 725         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
 726         *cursor_wm = entries + cursor->guard_size;
 727         if (*cursor_wm > (int)cursor->max_wm)
 728                 *cursor_wm = (int)cursor->max_wm;
 729
 730         return true;
 731 }
 732
 733 /*
 734  * Check the wm result.
 735  *
 736  * If any calculated watermark values is larger than the maximum value that
 737  * can be programmed into the associated watermark register, that watermark
 738  * must be disabled.
 739  */
 740 static bool g4x_check_srwm(struct drm_device *dev,
 741                            int display_wm, int cursor_wm,
 742                            const struct intel_watermark_params *display,
 743                            const struct intel_watermark_params *cursor)
 744 {
 745         DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
 746                       display_wm, cursor_wm);
 747
 748         if (display_wm > display->max_wm) {
 749                 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
 750                               display_wm, display->max_wm);
 751                 return false;
 752         }
 753
 754         if (cursor_wm > cursor->max_wm) {
 755                 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
 756                               cursor_wm, cursor->max_wm);
 757                 return false;
 758         }
 759
 760         if (!(display_wm || cursor_wm)) {
 761                 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
 762                 return false;
 763         }
 764
 765         return true;
 766 }
 767
 768 static bool g4x_compute_srwm(struct drm_device *dev,
 769                              int plane,
 770                              int latency_ns,
 771                              const struct intel_watermark_params *display,
 772                              const struct intel_watermark_params *cursor,
 773                              int *display_wm, int *cursor_wm)
 774 {
 775         struct drm_crtc *crtc;
 776         const struct drm_display_mode *adjusted_mode;
 777         int hdisplay, htotal, pixel_size, clock;
 778         unsigned long line_time_us;
 779         int line_count, line_size;
 780         int small, large;
 781         int entries;
 782
 783         if (!latency_ns) {
 784                 *display_wm = *cursor_wm = 0;
 785                 return false;
 786         }
 787
 788         crtc = intel_get_crtc_for_plane(dev, plane);
 789         adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
 790         clock = adjusted_mode->crtc_clock;
 791         htotal = adjusted_mode->crtc_htotal;
 792         hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
 793         pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
 794
 795         line_time_us = max(htotal * 1000 / clock, 1);
 796         line_count = (latency_ns / line_time_us + 1000) / 1000;
 797         line_size = hdisplay * pixel_size;
 798
 799         /* Use the minimum of the small and large buffer method for primary */
 800         small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
 801         large = line_count * line_size;
 802
 803         entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
 804         *display_wm = entries + display->guard_size;
 805
 806         /* calculate the self-refresh watermark for display cursor */
 807         entries = line_count * pixel_size * crtc->cursor->state->crtc_w;
 808         entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
 809         *cursor_wm = entries + cursor->guard_size;
 810
 811         return g4x_check_srwm(dev,
 812                               *display_wm, *cursor_wm,
 813                               display, cursor);
 814 }
 815
 816 #define FW_WM_VLV(value, plane) \
 817         (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV)
 818
 819 static void vlv_write_wm_values(struct intel_crtc *crtc,
 820                                 const struct vlv_wm_values *wm)
 821 {
 822         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 823         enum pipe pipe = crtc->pipe;
 824
 825         I915_WRITE(VLV_DDL(pipe),
 826                    (wm->ddl[pipe].cursor << DDL_CURSOR_SHIFT) |
 827                    (wm->ddl[pipe].sprite[1] << DDL_SPRITE_SHIFT(1)) |
 828                    (wm->ddl[pipe].sprite[0] << DDL_SPRITE_SHIFT(0)) |
 829                    (wm->ddl[pipe].primary << DDL_PLANE_SHIFT));
 830
 831         I915_WRITE(DSPFW1,
 832                    FW_WM(wm->sr.plane, SR) |
 833                    FW_WM(wm->pipe[PIPE_B].cursor, CURSORB) |
 834                    FW_WM_VLV(wm->pipe[PIPE_B].primary, PLANEB) |
 835                    FW_WM_VLV(wm->pipe[PIPE_A].primary, PLANEA));
 836         I915_WRITE(DSPFW2,
 837                    FW_WM_VLV(wm->pipe[PIPE_A].sprite[1], SPRITEB) |
 838                    FW_WM(wm->pipe[PIPE_A].cursor, CURSORA) |
 839                    FW_WM_VLV(wm->pipe[PIPE_A].sprite[0], SPRITEA));
 840         I915_WRITE(DSPFW3,
 841                    FW_WM(wm->sr.cursor, CURSOR_SR));
 842
 843         if (IS_CHERRYVIEW(dev_priv)) {
 844                 I915_WRITE(DSPFW7_CHV,
 845                            FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
 846                            FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
 847                 I915_WRITE(DSPFW8_CHV,
 848                            FW_WM_VLV(wm->pipe[PIPE_C].sprite[1], SPRITEF) |
 849                            FW_WM_VLV(wm->pipe[PIPE_C].sprite[0], SPRITEE));
 850                 I915_WRITE(DSPFW9_CHV,
 851                            FW_WM_VLV(wm->pipe[PIPE_C].primary, PLANEC) |
 852                            FW_WM(wm->pipe[PIPE_C].cursor, CURSORC));
 853                 I915_WRITE(DSPHOWM,
 854                            FW_WM(wm->sr.plane >> 9, SR_HI) |
 855                            FW_WM(wm->pipe[PIPE_C].sprite[1] >> 8, SPRITEF_HI) |
 856                            FW_WM(wm->pipe[PIPE_C].sprite[0] >> 8, SPRITEE_HI) |
 857                            FW_WM(wm->pipe[PIPE_C].primary >> 8, PLANEC_HI) |
 858                            FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
 859                            FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
 860                            FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
 861                            FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
 862                            FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
 863                            FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
 864         } else {
 865                 I915_WRITE(DSPFW7,
 866                            FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
 867                            FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
 868                 I915_WRITE(DSPHOWM,
 869                            FW_WM(wm->sr.plane >> 9, SR_HI) |
 870                            FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
 871                            FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
 872                            FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
 873                            FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
 874                            FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
 875                            FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
 876         }
 877
 878         /* zero (unused) WM1 watermarks */
 879         I915_WRITE(DSPFW4, 0);
 880         I915_WRITE(DSPFW5, 0);
 881         I915_WRITE(DSPFW6, 0);
 882         I915_WRITE(DSPHOWM1, 0);
 883
 884         POSTING_READ(DSPFW1);
 885 }
 886
 887 #undef FW_WM_VLV
 888
 889 enum vlv_wm_level {
 890         VLV_WM_LEVEL_PM2,
 891         VLV_WM_LEVEL_PM5,
 892         VLV_WM_LEVEL_DDR_DVFS,
 893 };
 894
 895 /* latency must be in 0.1us units. */
 896 static unsigned int vlv_wm_method2(unsigned int pixel_rate,
 897                                    unsigned int pipe_htotal,
 898                                    unsigned int horiz_pixels,
 899                                    unsigned int bytes_per_pixel,
 900                                    unsigned int latency)
 901 {
 902         unsigned int ret;
 903
 904         ret = (latency * pixel_rate) / (pipe_htotal * 10000);
 905         ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
 906         ret = DIV_ROUND_UP(ret, 64);
 907
 908         return ret;
 909 }
 910
 911 static void vlv_setup_wm_latency(struct drm_device *dev)
 912 {
 913         struct drm_i915_private *dev_priv = dev->dev_private;
 914
 915         /* all latencies in usec */
 916         dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3;
 917
 918         dev_priv->wm.max_level = VLV_WM_LEVEL_PM2;
 919
 920         if (IS_CHERRYVIEW(dev_priv)) {
 921                 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12;
 922                 dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33;
 923
 924                 dev_priv->wm.max_level = VLV_WM_LEVEL_DDR_DVFS;
 925         }
 926 }
 927
 928 static uint16_t vlv_compute_wm_level(struct intel_plane *plane,
 929                                      struct intel_crtc *crtc,
 930                                      const struct intel_plane_state *state,
 931                                      int level)
 932 {
 933         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 934         int clock, htotal, pixel_size, width, wm;
 935
 936         if (dev_priv->wm.pri_latency[level] == 0)
 937                 return USHRT_MAX;
 938
 939         if (!state->visible)
 940                 return 0;
 941
 942         pixel_size = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
 943         clock = crtc->config->base.adjusted_mode.crtc_clock;
 944         htotal = crtc->config->base.adjusted_mode.crtc_htotal;
 945         width = crtc->config->pipe_src_w;
 946         if (WARN_ON(htotal == 0))
 947                 htotal = 1;
 948
 949         if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
 950                 /*
 951                  * FIXME the formula gives values that are
 952                  * too big for the cursor FIFO, and hence we
 953                  * would never be able to use cursors. For
 954                  * now just hardcode the watermark.
 955                  */
 956                 wm = 63;
 957         } else {
 958                 wm = vlv_wm_method2(clock, htotal, width, pixel_size,
 959                                     dev_priv->wm.pri_latency[level] * 10);
 960         }
 961
 962         return min_t(int, wm, USHRT_MAX);
 963 }
 964
 965 static void vlv_compute_fifo(struct intel_crtc *crtc)
 966 {
 967         struct drm_device *dev = crtc->base.dev;
 968         struct vlv_wm_state *wm_state = &crtc->wm_state;
 969         struct intel_plane *plane;
 970         unsigned int total_rate = 0;
 971         const int fifo_size = 512 - 1;
 972         int fifo_extra, fifo_left = fifo_size;
 973
 974         for_each_intel_plane_on_crtc(dev, crtc, plane) {
 975                 struct intel_plane_state *state =
 976                         to_intel_plane_state(plane->base.state);
 977
 978                 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
 979                         continue;
 980
 981                 if (state->visible) {
 982                         wm_state->num_active_planes++;
 983                         total_rate += drm_format_plane_cpp(state->base.fb->pixel_format, 0);
 984                 }
 985         }
 986
 987         for_each_intel_plane_on_crtc(dev, crtc, plane) {
 988                 struct intel_plane_state *state =
 989                         to_intel_plane_state(plane->base.state);
 990                 unsigned int rate;
 991
 992                 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
 993                         plane->wm.fifo_size = 63;
 994                         continue;
 995                 }
 996
 997                 if (!state->visible) {
 998                         plane->wm.fifo_size = 0;
 999                         continue;
1000                 }
1001
1002                 rate = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1003                 plane->wm.fifo_size = fifo_size * rate / total_rate;
1004                 fifo_left -= plane->wm.fifo_size;
1005         }
1006
1007         fifo_extra = DIV_ROUND_UP(fifo_left, wm_state->num_active_planes ?: 1);
1008
1009         /* spread the remainder evenly */
1010         for_each_intel_plane_on_crtc(dev, crtc, plane) {
1011                 int plane_extra;
1012
1013                 if (fifo_left == 0)
1014                         break;
1015
1016                 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1017                         continue;
1018
1019                 /* give it all to the first plane if none are active */
1020                 if (plane->wm.fifo_size == 0 &&
1021                     wm_state->num_active_planes)
1022                         continue;
1023
1024                 plane_extra = min(fifo_extra, fifo_left);
1025                 plane->wm.fifo_size += plane_extra;
1026                 fifo_left -= plane_extra;
1027         }
1028
1029         WARN_ON(fifo_left != 0);
1030 }
1031
1032 static void vlv_invert_wms(struct intel_crtc *crtc)
1033 {
1034         struct vlv_wm_state *wm_state = &crtc->wm_state;
1035         int level;
1036
1037         for (level = 0; level < wm_state->num_levels; level++) {
1038                 struct drm_device *dev = crtc->base.dev;
1039                 const int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1040                 struct intel_plane *plane;
1041
1042                 wm_state->sr[level].plane = sr_fifo_size - wm_state->sr[level].plane;
1043                 wm_state->sr[level].cursor = 63 - wm_state->sr[level].cursor;
1044
1045                 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1046                         switch (plane->base.type) {
1047                                 int sprite;
1048                         case DRM_PLANE_TYPE_CURSOR:
1049                                 wm_state->wm[level].cursor = plane->wm.fifo_size -
1050                                         wm_state->wm[level].cursor;
1051                                 break;
1052                         case DRM_PLANE_TYPE_PRIMARY:
1053                                 wm_state->wm[level].primary = plane->wm.fifo_size -
1054                                         wm_state->wm[level].primary;
1055                                 break;
1056                         case DRM_PLANE_TYPE_OVERLAY:
1057                                 sprite = plane->plane;
1058                                 wm_state->wm[level].sprite[sprite] = plane->wm.fifo_size -
1059                                         wm_state->wm[level].sprite[sprite];
1060                                 break;
1061                         }
1062                 }
1063         }
1064 }
1065
1066 static void vlv_compute_wm(struct intel_crtc *crtc)
1067 {
1068         struct drm_device *dev = crtc->base.dev;
1069         struct vlv_wm_state *wm_state = &crtc->wm_state;
1070         struct intel_plane *plane;
1071         int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1072         int level;
1073
1074         memset(wm_state, 0, sizeof(*wm_state));
1075
1076         wm_state->cxsr = crtc->pipe != PIPE_C && crtc->wm.cxsr_allowed;
1077         wm_state->num_levels = to_i915(dev)->wm.max_level + 1;
1078
1079         wm_state->num_active_planes = 0;
1080
1081         vlv_compute_fifo(crtc);
1082
1083         if (wm_state->num_active_planes != 1)
1084                 wm_state->cxsr = false;
1085
1086         if (wm_state->cxsr) {
1087                 for (level = 0; level < wm_state->num_levels; level++) {
1088                         wm_state->sr[level].plane = sr_fifo_size;
1089                         wm_state->sr[level].cursor = 63;
1090                 }
1091         }
1092
1093         for_each_intel_plane_on_crtc(dev, crtc, plane) {
1094                 struct intel_plane_state *state =
1095                         to_intel_plane_state(plane->base.state);
1096
1097                 if (!state->visible)
1098                         continue;
1099
1100                 /* normal watermarks */
1101                 for (level = 0; level < wm_state->num_levels; level++) {
1102                         int wm = vlv_compute_wm_level(plane, crtc, state, level);
1103                         int max_wm = plane->base.type == DRM_PLANE_TYPE_CURSOR ? 63 : 511;
1104
1105                         /* hack */
1106                         if (WARN_ON(level == 0 && wm > max_wm))
1107                                 wm = max_wm;
1108
1109                         if (wm > plane->wm.fifo_size)
1110                                 break;
1111
1112                         switch (plane->base.type) {
1113                                 int sprite;
1114                         case DRM_PLANE_TYPE_CURSOR:
1115                                 wm_state->wm[level].cursor = wm;
1116                                 break;
1117                         case DRM_PLANE_TYPE_PRIMARY:
1118                                 wm_state->wm[level].primary = wm;
1119                                 break;
1120                         case DRM_PLANE_TYPE_OVERLAY:
1121                                 sprite = plane->plane;
1122                                 wm_state->wm[level].sprite[sprite] = wm;
1123                                 break;
1124                         }
1125                 }
1126
1127                 wm_state->num_levels = level;
1128
1129                 if (!wm_state->cxsr)
1130                         continue;
1131
1132                 /* maxfifo watermarks */
1133                 switch (plane->base.type) {
1134                         int sprite, level;
1135                 case DRM_PLANE_TYPE_CURSOR:
1136                         for (level = 0; level < wm_state->num_levels; level++)
1137                                 wm_state->sr[level].cursor =
1138                                         wm_state->wm[level].cursor;
1139                         break;
1140                 case DRM_PLANE_TYPE_PRIMARY:
1141                         for (level = 0; level < wm_state->num_levels; level++)
1142                                 wm_state->sr[level].plane =
1143                                         min(wm_state->sr[level].plane,
1144                                             wm_state->wm[level].primary);
1145                         break;
1146                 case DRM_PLANE_TYPE_OVERLAY:
1147                         sprite = plane->plane;
1148                         for (level = 0; level < wm_state->num_levels; level++)
1149                                 wm_state->sr[level].plane =
1150                                         min(wm_state->sr[level].plane,
1151                                             wm_state->wm[level].sprite[sprite]);
1152                         break;
1153                 }
1154         }
1155
1156         /* clear any (partially) filled invalid levels */
1157         for (level = wm_state->num_levels; level < to_i915(dev)->wm.max_level + 1; level++) {
1158                 memset(&wm_state->wm[level], 0, sizeof(wm_state->wm[level]));
1159                 memset(&wm_state->sr[level], 0, sizeof(wm_state->sr[level]));
1160         }
1161
1162         vlv_invert_wms(crtc);
1163 }
1164
1165 #define VLV_FIFO(plane, value) \
1166         (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV)
1167
1168 static void vlv_pipe_set_fifo_size(struct intel_crtc *crtc)
1169 {
1170         struct drm_device *dev = crtc->base.dev;
1171         struct drm_i915_private *dev_priv = to_i915(dev);
1172         struct intel_plane *plane;
1173         int sprite0_start = 0, sprite1_start = 0, fifo_size = 0;
1174
1175         for_each_intel_plane_on_crtc(dev, crtc, plane) {
1176                 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1177                         WARN_ON(plane->wm.fifo_size != 63);
1178                         continue;
1179                 }
1180
1181                 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
1182                         sprite0_start = plane->wm.fifo_size;
1183                 else if (plane->plane == 0)
1184                         sprite1_start = sprite0_start + plane->wm.fifo_size;
1185                 else
1186                         fifo_size = sprite1_start + plane->wm.fifo_size;
1187         }
1188
1189         WARN_ON(fifo_size != 512 - 1);
1190
1191         DRM_DEBUG_KMS("Pipe %c FIFO split %d / %d / %d\n",
1192                       pipe_name(crtc->pipe), sprite0_start,
1193                       sprite1_start, fifo_size);
1194
1195         switch (crtc->pipe) {
1196                 uint32_t dsparb, dsparb2, dsparb3;
1197         case PIPE_A:
1198                 dsparb = I915_READ(DSPARB);
1199                 dsparb2 = I915_READ(DSPARB2);
1200
1201                 dsparb &= ~(VLV_FIFO(SPRITEA, 0xff) |
1202                             VLV_FIFO(SPRITEB, 0xff));
1203                 dsparb |= (VLV_FIFO(SPRITEA, sprite0_start) |
1204                            VLV_FIFO(SPRITEB, sprite1_start));
1205
1206                 dsparb2 &= ~(VLV_FIFO(SPRITEA_HI, 0x1) |
1207                              VLV_FIFO(SPRITEB_HI, 0x1));
1208                 dsparb2 |= (VLV_FIFO(SPRITEA_HI, sprite0_start >> 8) |
1209                            VLV_FIFO(SPRITEB_HI, sprite1_start >> 8));
1210
1211                 I915_WRITE(DSPARB, dsparb);
1212                 I915_WRITE(DSPARB2, dsparb2);
1213                 break;
1214         case PIPE_B:
1215                 dsparb = I915_READ(DSPARB);
1216                 dsparb2 = I915_READ(DSPARB2);
1217
1218                 dsparb &= ~(VLV_FIFO(SPRITEC, 0xff) |
1219                             VLV_FIFO(SPRITED, 0xff));
1220                 dsparb |= (VLV_FIFO(SPRITEC, sprite0_start) |
1221                            VLV_FIFO(SPRITED, sprite1_start));
1222
1223                 dsparb2 &= ~(VLV_FIFO(SPRITEC_HI, 0xff) |
1224                              VLV_FIFO(SPRITED_HI, 0xff));
1225                 dsparb2 |= (VLV_FIFO(SPRITEC_HI, sprite0_start >> 8) |
1226                            VLV_FIFO(SPRITED_HI, sprite1_start >> 8));
1227
1228                 I915_WRITE(DSPARB, dsparb);
1229                 I915_WRITE(DSPARB2, dsparb2);
1230                 break;
1231         case PIPE_C:
1232                 dsparb3 = I915_READ(DSPARB3);
1233                 dsparb2 = I915_READ(DSPARB2);
1234
1235                 dsparb3 &= ~(VLV_FIFO(SPRITEE, 0xff) |
1236                              VLV_FIFO(SPRITEF, 0xff));
1237                 dsparb3 |= (VLV_FIFO(SPRITEE, sprite0_start) |
1238                             VLV_FIFO(SPRITEF, sprite1_start));
1239
1240                 dsparb2 &= ~(VLV_FIFO(SPRITEE_HI, 0xff) |
1241                              VLV_FIFO(SPRITEF_HI, 0xff));
1242                 dsparb2 |= (VLV_FIFO(SPRITEE_HI, sprite0_start >> 8) |
1243                            VLV_FIFO(SPRITEF_HI, sprite1_start >> 8));
1244
1245                 I915_WRITE(DSPARB3, dsparb3);
1246                 I915_WRITE(DSPARB2, dsparb2);
1247                 break;
1248         default:
1249                 break;
1250         }
1251 }
1252
1253 #undef VLV_FIFO
1254
1255 static void vlv_merge_wm(struct drm_device *dev,
1256                          struct vlv_wm_values *wm)
1257 {
1258         struct intel_crtc *crtc;
1259         int num_active_crtcs = 0;
1260
1261         wm->level = to_i915(dev)->wm.max_level;
1262         wm->cxsr = true;
1263
1264         for_each_intel_crtc(dev, crtc) {
1265                 const struct vlv_wm_state *wm_state = &crtc->wm_state;
1266
1267                 if (!crtc->active)
1268                         continue;
1269
1270                 if (!wm_state->cxsr)
1271                         wm->cxsr = false;
1272
1273                 num_active_crtcs++;
1274                 wm->level = min_t(int, wm->level, wm_state->num_levels - 1);
1275         }
1276
1277         if (num_active_crtcs != 1)
1278                 wm->cxsr = false;
1279
1280         if (num_active_crtcs > 1)
1281                 wm->level = VLV_WM_LEVEL_PM2;
1282
1283         for_each_intel_crtc(dev, crtc) {
1284                 struct vlv_wm_state *wm_state = &crtc->wm_state;
1285                 enum pipe pipe = crtc->pipe;
1286
1287                 if (!crtc->active)
1288                         continue;
1289
1290                 wm->pipe[pipe] = wm_state->wm[wm->level];
1291                 if (wm->cxsr)
1292                         wm->sr = wm_state->sr[wm->level];
1293
1294                 wm->ddl[pipe].primary = DDL_PRECISION_HIGH | 2;
1295                 wm->ddl[pipe].sprite[0] = DDL_PRECISION_HIGH | 2;
1296                 wm->ddl[pipe].sprite[1] = DDL_PRECISION_HIGH | 2;
1297                 wm->ddl[pipe].cursor = DDL_PRECISION_HIGH | 2;
1298         }
1299 }
1300
1301 static void vlv_update_wm(struct drm_crtc *crtc)
1302 {
1303         struct drm_device *dev = crtc->dev;
1304         struct drm_i915_private *dev_priv = dev->dev_private;
1305         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1306         enum pipe pipe = intel_crtc->pipe;
1307         struct vlv_wm_values wm = {};
1308
1309         vlv_compute_wm(intel_crtc);
1310         vlv_merge_wm(dev, &wm);
1311
1312         if (memcmp(&dev_priv->wm.vlv, &wm, sizeof(wm)) == 0) {
1313                 /* FIXME should be part of crtc atomic commit */
1314                 vlv_pipe_set_fifo_size(intel_crtc);
1315                 return;
1316         }
1317
1318         if (wm.level < VLV_WM_LEVEL_DDR_DVFS &&
1319             dev_priv->wm.vlv.level >= VLV_WM_LEVEL_DDR_DVFS)
1320                 chv_set_memory_dvfs(dev_priv, false);
1321
1322         if (wm.level < VLV_WM_LEVEL_PM5 &&
1323             dev_priv->wm.vlv.level >= VLV_WM_LEVEL_PM5)
1324                 chv_set_memory_pm5(dev_priv, false);
1325
1326         if (!wm.cxsr && dev_priv->wm.vlv.cxsr)
1327                 intel_set_memory_cxsr(dev_priv, false);
1328
1329         /* FIXME should be part of crtc atomic commit */
1330         vlv_pipe_set_fifo_size(intel_crtc);
1331
1332         vlv_write_wm_values(intel_crtc, &wm);
1333
1334         DRM_DEBUG_KMS("Setting FIFO watermarks - %c: plane=%d, cursor=%d, "
1335                       "sprite0=%d, sprite1=%d, SR: plane=%d, cursor=%d level=%d cxsr=%d\n",
1336                       pipe_name(pipe), wm.pipe[pipe].primary, wm.pipe[pipe].cursor,
1337                       wm.pipe[pipe].sprite[0], wm.pipe[pipe].sprite[1],
1338                       wm.sr.plane, wm.sr.cursor, wm.level, wm.cxsr);
1339
1340         if (wm.cxsr && !dev_priv->wm.vlv.cxsr)
1341                 intel_set_memory_cxsr(dev_priv, true);
1342
1343         if (wm.level >= VLV_WM_LEVEL_PM5 &&
1344             dev_priv->wm.vlv.level < VLV_WM_LEVEL_PM5)
1345                 chv_set_memory_pm5(dev_priv, true);
1346
1347         if (wm.level >= VLV_WM_LEVEL_DDR_DVFS &&
1348             dev_priv->wm.vlv.level < VLV_WM_LEVEL_DDR_DVFS)
1349                 chv_set_memory_dvfs(dev_priv, true);
1350
1351         dev_priv->wm.vlv = wm;
1352 }
1353
1354 #define single_plane_enabled(mask) is_power_of_2(mask)
1355
1356 static void g4x_update_wm(struct drm_crtc *crtc)
1357 {
1358         struct drm_device *dev = crtc->dev;
1359         static const int sr_latency_ns = 12000;
1360         struct drm_i915_private *dev_priv = dev->dev_private;
1361         int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1362         int plane_sr, cursor_sr;
1363         unsigned int enabled = 0;
1364         bool cxsr_enabled;
1365
1366         if (g4x_compute_wm0(dev, PIPE_A,
1367                             &g4x_wm_info, pessimal_latency_ns,
1368                             &g4x_cursor_wm_info, pessimal_latency_ns,
1369                             &planea_wm, &cursora_wm))
1370                 enabled |= 1 << PIPE_A;
1371
1372         if (g4x_compute_wm0(dev, PIPE_B,
1373                             &g4x_wm_info, pessimal_latency_ns,
1374                             &g4x_cursor_wm_info, pessimal_latency_ns,
1375                             &planeb_wm, &cursorb_wm))
1376                 enabled |= 1 << PIPE_B;
1377
1378         if (single_plane_enabled(enabled) &&
1379             g4x_compute_srwm(dev, ffs(enabled) - 1,
1380                              sr_latency_ns,
1381                              &g4x_wm_info,
1382                              &g4x_cursor_wm_info,
1383                              &plane_sr, &cursor_sr)) {
1384                 cxsr_enabled = true;
1385         } else {
1386                 cxsr_enabled = false;
1387                 intel_set_memory_cxsr(dev_priv, false);
1388                 plane_sr = cursor_sr = 0;
1389         }
1390
1391         DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1392                       "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1393                       planea_wm, cursora_wm,
1394                       planeb_wm, cursorb_wm,
1395                       plane_sr, cursor_sr);
1396
1397         I915_WRITE(DSPFW1,
1398                    FW_WM(plane_sr, SR) |
1399                    FW_WM(cursorb_wm, CURSORB) |
1400                    FW_WM(planeb_wm, PLANEB) |
1401                    FW_WM(planea_wm, PLANEA));
1402         I915_WRITE(DSPFW2,
1403                    (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
1404                    FW_WM(cursora_wm, CURSORA));
1405         /* HPLL off in SR has some issues on G4x... disable it */
1406         I915_WRITE(DSPFW3,
1407                    (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
1408                    FW_WM(cursor_sr, CURSOR_SR));
1409
1410         if (cxsr_enabled)
1411                 intel_set_memory_cxsr(dev_priv, true);
1412 }
1413
1414 static void i965_update_wm(struct drm_crtc *unused_crtc)
1415 {
1416         struct drm_device *dev = unused_crtc->dev;
1417         struct drm_i915_private *dev_priv = dev->dev_private;
1418         struct drm_crtc *crtc;
1419         int srwm = 1;
1420         int cursor_sr = 16;
1421         bool cxsr_enabled;
1422
1423         /* Calc sr entries for one plane configs */
1424         crtc = single_enabled_crtc(dev);
1425         if (crtc) {
1426                 /* self-refresh has much higher latency */
1427                 static const int sr_latency_ns = 12000;
1428                 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1429                 int clock = adjusted_mode->crtc_clock;
1430                 int htotal = adjusted_mode->crtc_htotal;
1431                 int hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
1432                 int pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
1433                 unsigned long line_time_us;
1434                 int entries;
1435
1436                 line_time_us = max(htotal * 1000 / clock, 1);
1437
1438                 /* Use ns/us then divide to preserve precision */
1439                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1440                         pixel_size * hdisplay;
1441                 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1442                 srwm = I965_FIFO_SIZE - entries;
1443                 if (srwm < 0)
1444                         srwm = 1;
1445                 srwm &= 0x1ff;
1446                 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1447                               entries, srwm);
1448
1449                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1450                         pixel_size * crtc->cursor->state->crtc_w;
1451                 entries = DIV_ROUND_UP(entries,
1452                                           i965_cursor_wm_info.cacheline_size);
1453                 cursor_sr = i965_cursor_wm_info.fifo_size -
1454                         (entries + i965_cursor_wm_info.guard_size);
1455
1456                 if (cursor_sr > i965_cursor_wm_info.max_wm)
1457                         cursor_sr = i965_cursor_wm_info.max_wm;
1458
1459                 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1460                               "cursor %d\n", srwm, cursor_sr);
1461
1462                 cxsr_enabled = true;
1463         } else {
1464                 cxsr_enabled = false;
1465                 /* Turn off self refresh if both pipes are enabled */
1466                 intel_set_memory_cxsr(dev_priv, false);
1467         }
1468
1469         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1470                       srwm);
1471
1472         /* 965 has limitations... */
1473         I915_WRITE(DSPFW1, FW_WM(srwm, SR) |
1474                    FW_WM(8, CURSORB) |
1475                    FW_WM(8, PLANEB) |
1476                    FW_WM(8, PLANEA));
1477         I915_WRITE(DSPFW2, FW_WM(8, CURSORA) |
1478                    FW_WM(8, PLANEC_OLD));
1479         /* update cursor SR watermark */
1480         I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR));
1481
1482         if (cxsr_enabled)
1483                 intel_set_memory_cxsr(dev_priv, true);
1484 }
1485
1486 #undef FW_WM
1487
1488 static void i9xx_update_wm(struct drm_crtc *unused_crtc)
1489 {
1490         struct drm_device *dev = unused_crtc->dev;
1491         struct drm_i915_private *dev_priv = dev->dev_private;
1492         const struct intel_watermark_params *wm_info;
1493         uint32_t fwater_lo;
1494         uint32_t fwater_hi;
1495         int cwm, srwm = 1;
1496         int fifo_size;
1497         int planea_wm, planeb_wm;
1498         struct drm_crtc *crtc, *enabled = NULL;
1499
1500         if (IS_I945GM(dev))
1501                 wm_info = &i945_wm_info;
1502         else if (!IS_GEN2(dev))
1503                 wm_info = &i915_wm_info;
1504         else
1505                 wm_info = &i830_a_wm_info;
1506
1507         fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1508         crtc = intel_get_crtc_for_plane(dev, 0);
1509         if (intel_crtc_active(crtc)) {
1510                 const struct drm_display_mode *adjusted_mode;
1511                 int cpp = crtc->primary->state->fb->bits_per_pixel / 8;
1512                 if (IS_GEN2(dev))
1513                         cpp = 4;
1514
1515                 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1516                 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1517                                                wm_info, fifo_size, cpp,
1518                                                pessimal_latency_ns);
1519                 enabled = crtc;
1520         } else {
1521                 planea_wm = fifo_size - wm_info->guard_size;
1522                 if (planea_wm > (long)wm_info->max_wm)
1523                         planea_wm = wm_info->max_wm;
1524         }
1525
1526         if (IS_GEN2(dev))
1527                 wm_info = &i830_bc_wm_info;
1528
1529         fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1530         crtc = intel_get_crtc_for_plane(dev, 1);
1531         if (intel_crtc_active(crtc)) {
1532                 const struct drm_display_mode *adjusted_mode;
1533                 int cpp = crtc->primary->state->fb->bits_per_pixel / 8;
1534                 if (IS_GEN2(dev))
1535                         cpp = 4;
1536
1537                 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1538                 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1539                                                wm_info, fifo_size, cpp,
1540                                                pessimal_latency_ns);
1541                 if (enabled == NULL)
1542                         enabled = crtc;
1543                 else
1544                         enabled = NULL;
1545         } else {
1546                 planeb_wm = fifo_size - wm_info->guard_size;
1547                 if (planeb_wm > (long)wm_info->max_wm)
1548                         planeb_wm = wm_info->max_wm;
1549         }
1550
1551         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1552
1553         if (IS_I915GM(dev) && enabled) {
1554                 struct drm_i915_gem_object *obj;
1555
1556                 obj = intel_fb_obj(enabled->primary->state->fb);
1557
1558                 /* self-refresh seems busted with untiled */
1559                 if (obj->tiling_mode == I915_TILING_NONE)
1560                         enabled = NULL;
1561         }
1562
1563         /*
1564          * Overlay gets an aggressive default since video jitter is bad.
1565          */
1566         cwm = 2;
1567
1568         /* Play safe and disable self-refresh before adjusting watermarks. */
1569         intel_set_memory_cxsr(dev_priv, false);
1570
1571         /* Calc sr entries for one plane configs */
1572         if (HAS_FW_BLC(dev) && enabled) {
1573                 /* self-refresh has much higher latency */
1574                 static const int sr_latency_ns = 6000;
1575                 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(enabled)->config->base.adjusted_mode;
1576                 int clock = adjusted_mode->crtc_clock;
1577                 int htotal = adjusted_mode->crtc_htotal;
1578                 int hdisplay = to_intel_crtc(enabled)->config->pipe_src_w;
1579                 int pixel_size = enabled->primary->state->fb->bits_per_pixel / 8;
1580                 unsigned long line_time_us;
1581                 int entries;
1582
1583                 line_time_us = max(htotal * 1000 / clock, 1);
1584
1585                 /* Use ns/us then divide to preserve precision */
1586                 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1587                         pixel_size * hdisplay;
1588                 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1589                 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1590                 srwm = wm_info->fifo_size - entries;
1591                 if (srwm < 0)
1592                         srwm = 1;
1593
1594                 if (IS_I945G(dev) || IS_I945GM(dev))
1595                         I915_WRITE(FW_BLC_SELF,
1596                                    FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1597                 else if (IS_I915GM(dev))
1598                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1599         }
1600
1601         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1602                       planea_wm, planeb_wm, cwm, srwm);
1603
1604         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1605         fwater_hi = (cwm & 0x1f);
1606
1607         /* Set request length to 8 cachelines per fetch */
1608         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1609         fwater_hi = fwater_hi | (1 << 8);
1610
1611         I915_WRITE(FW_BLC, fwater_lo);
1612         I915_WRITE(FW_BLC2, fwater_hi);
1613
1614         if (enabled)
1615                 intel_set_memory_cxsr(dev_priv, true);
1616 }
1617
1618 static void i845_update_wm(struct drm_crtc *unused_crtc)
1619 {
1620         struct drm_device *dev = unused_crtc->dev;
1621         struct drm_i915_private *dev_priv = dev->dev_private;
1622         struct drm_crtc *crtc;
1623         const struct drm_display_mode *adjusted_mode;
1624         uint32_t fwater_lo;
1625         int planea_wm;
1626
1627         crtc = single_enabled_crtc(dev);
1628         if (crtc == NULL)
1629                 return;
1630
1631         adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
1632         planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
1633                                        &i845_wm_info,
1634                                        dev_priv->display.get_fifo_size(dev, 0),
1635                                        4, pessimal_latency_ns);
1636         fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1637         fwater_lo |= (3<<8) | planea_wm;
1638
1639         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1640
1641         I915_WRITE(FW_BLC, fwater_lo);
1642 }
1643
1644 uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
1645 {
1646         uint32_t pixel_rate;
1647
1648         pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
1649
1650         /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1651          * adjust the pixel_rate here. */
1652
1653         if (pipe_config->pch_pfit.enabled) {
1654                 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
1655                 uint32_t pfit_size = pipe_config->pch_pfit.size;
1656
1657                 pipe_w = pipe_config->pipe_src_w;
1658                 pipe_h = pipe_config->pipe_src_h;
1659
1660                 pfit_w = (pfit_size >> 16) & 0xFFFF;
1661                 pfit_h = pfit_size & 0xFFFF;
1662                 if (pipe_w < pfit_w)
1663                         pipe_w = pfit_w;
1664                 if (pipe_h < pfit_h)
1665                         pipe_h = pfit_h;
1666
1667                 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1668                                      pfit_w * pfit_h);
1669         }
1670
1671         return pixel_rate;
1672 }
1673
1674 /* latency must be in 0.1us units. */
1675 static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
1676                                uint32_t latency)
1677 {
1678         uint64_t ret;
1679
1680         if (WARN(latency == 0, "Latency value missing\n"))
1681                 return UINT_MAX;
1682
1683         ret = (uint64_t) pixel_rate * bytes_per_pixel * latency;
1684         ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1685
1686         return ret;
1687 }
1688
1689 /* latency must be in 0.1us units. */
1690 static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
1691                                uint32_t horiz_pixels, uint8_t bytes_per_pixel,
1692                                uint32_t latency)
1693 {
1694         uint32_t ret;
1695
1696         if (WARN(latency == 0, "Latency value missing\n"))
1697                 return UINT_MAX;
1698
1699         ret = (latency * pixel_rate) / (pipe_htotal * 10000);
1700         ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
1701         ret = DIV_ROUND_UP(ret, 64) + 2;
1702         return ret;
1703 }
1704
1705 static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
1706                            uint8_t bytes_per_pixel)
1707 {
1708         return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2;
1709 }
1710
1711 struct ilk_wm_maximums {
1712         uint16_t pri;
1713         uint16_t spr;
1714         uint16_t cur;
1715         uint16_t fbc;
1716 };
1717
1718 /*
1719  * For both WM_PIPE and WM_LP.
1720  * mem_value must be in 0.1us units.
1721  */
1722 static uint32_t ilk_compute_pri_wm(const struct intel_crtc_state *cstate,
1723                                    const struct intel_plane_state *pstate,
1724                                    uint32_t mem_value,
1725                                    bool is_lp)
1726 {
1727         int bpp = pstate->base.fb ? pstate->base.fb->bits_per_pixel / 8 : 0;
1728         uint32_t method1, method2;
1729
1730         if (!cstate->base.active || !pstate->visible)
1731                 return 0;
1732
1733         method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), bpp, mem_value);
1734
1735         if (!is_lp)
1736                 return method1;
1737
1738         method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1739                                  cstate->base.adjusted_mode.crtc_htotal,
1740                                  drm_rect_width(&pstate->dst),
1741                                  bpp,
1742                                  mem_value);
1743
1744         return min(method1, method2);
1745 }
1746
1747 /*
1748  * For both WM_PIPE and WM_LP.
1749  * mem_value must be in 0.1us units.
1750  */
1751 static uint32_t ilk_compute_spr_wm(const struct intel_crtc_state *cstate,
1752                                    const struct intel_plane_state *pstate,
1753                                    uint32_t mem_value)
1754 {
1755         int bpp = pstate->base.fb ? pstate->base.fb->bits_per_pixel / 8 : 0;
1756         uint32_t method1, method2;
1757
1758         if (!cstate->base.active || !pstate->visible)
1759                 return 0;
1760
1761         method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), bpp, mem_value);
1762         method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1763                                  cstate->base.adjusted_mode.crtc_htotal,
1764                                  drm_rect_width(&pstate->dst),
1765                                  bpp,
1766                                  mem_value);
1767         return min(method1, method2);
1768 }
1769
1770 /*
1771  * For both WM_PIPE and WM_LP.
1772  * mem_value must be in 0.1us units.
1773  */
1774 static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state *cstate,
1775                                    const struct intel_plane_state *pstate,
1776                                    uint32_t mem_value)
1777 {
1778         int bpp = pstate->base.fb ? pstate->base.fb->bits_per_pixel / 8 : 0;
1779
1780         if (!cstate->base.active || !pstate->visible)
1781                 return 0;
1782
1783         return ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1784                               cstate->base.adjusted_mode.crtc_htotal,
1785                               drm_rect_width(&pstate->dst),
1786                               bpp,
1787                               mem_value);
1788 }
1789
1790 /* Only for WM_LP. */
1791 static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state *cstate,
1792                                    const struct intel_plane_state *pstate,
1793                                    uint32_t pri_val)
1794 {
1795         int bpp = pstate->base.fb ? pstate->base.fb->bits_per_pixel / 8 : 0;
1796
1797         if (!cstate->base.active || !pstate->visible)
1798                 return 0;
1799
1800         return ilk_wm_fbc(pri_val, drm_rect_width(&pstate->dst), bpp);
1801 }
1802
1803 static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
1804 {
1805         if (INTEL_INFO(dev)->gen >= 8)
1806                 return 3072;
1807         else if (INTEL_INFO(dev)->gen >= 7)
1808                 return 768;
1809         else
1810                 return 512;
1811 }
1812
1813 static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev,
1814                                          int level, bool is_sprite)
1815 {
1816         if (INTEL_INFO(dev)->gen >= 8)
1817                 /* BDW primary/sprite plane watermarks */
1818                 return level == 0 ? 255 : 2047;
1819         else if (INTEL_INFO(dev)->gen >= 7)
1820                 /* IVB/HSW primary/sprite plane watermarks */
1821                 return level == 0 ? 127 : 1023;
1822         else if (!is_sprite)
1823                 /* ILK/SNB primary plane watermarks */
1824                 return level == 0 ? 127 : 511;
1825         else
1826                 /* ILK/SNB sprite plane watermarks */
1827                 return level == 0 ? 63 : 255;
1828 }
1829
1830 static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev,
1831                                           int level)
1832 {
1833         if (INTEL_INFO(dev)->gen >= 7)
1834                 return level == 0 ? 63 : 255;
1835         else
1836                 return level == 0 ? 31 : 63;
1837 }
1838
1839 static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev)
1840 {
1841         if (INTEL_INFO(dev)->gen >= 8)
1842                 return 31;
1843         else
1844                 return 15;
1845 }
1846
1847 /* Calculate the maximum primary/sprite plane watermark */
1848 static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
1849                                      int level,
1850                                      const struct intel_wm_config *config,
1851                                      enum intel_ddb_partitioning ddb_partitioning,
1852                                      bool is_sprite)
1853 {
1854         unsigned int fifo_size = ilk_display_fifo_size(dev);
1855
1856         /* if sprites aren't enabled, sprites get nothing */
1857         if (is_sprite && !config->sprites_enabled)
1858                 return 0;
1859
1860         /* HSW allows LP1+ watermarks even with multiple pipes */
1861         if (level == 0 || config->num_pipes_active > 1) {
1862                 fifo_size /= INTEL_INFO(dev)->num_pipes;
1863
1864                 /*
1865                  * For some reason the non self refresh
1866                  * FIFO size is only half of the self
1867                  * refresh FIFO size on ILK/SNB.
1868                  */
1869                 if (INTEL_INFO(dev)->gen <= 6)
1870                         fifo_size /= 2;
1871         }
1872
1873         if (config->sprites_enabled) {
1874                 /* level 0 is always calculated with 1:1 split */
1875                 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
1876                         if (is_sprite)
1877                                 fifo_size *= 5;
1878                         fifo_size /= 6;
1879                 } else {
1880                         fifo_size /= 2;
1881                 }
1882         }
1883
1884         /* clamp to max that the registers can hold */
1885         return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite));
1886 }
1887
1888 /* Calculate the maximum cursor plane watermark */
1889 static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
1890                                       int level,
1891                                       const struct intel_wm_config *config)
1892 {
1893         /* HSW LP1+ watermarks w/ multiple pipes */
1894         if (level > 0 && config->num_pipes_active > 1)
1895                 return 64;
1896
1897         /* otherwise just report max that registers can hold */
1898         return ilk_cursor_wm_reg_max(dev, level);
1899 }
1900
1901 static void ilk_compute_wm_maximums(const struct drm_device *dev,
1902                                     int level,
1903                                     const struct intel_wm_config *config,
1904                                     enum intel_ddb_partitioning ddb_partitioning,
1905                                     struct ilk_wm_maximums *max)
1906 {
1907         max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
1908         max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
1909         max->cur = ilk_cursor_wm_max(dev, level, config);
1910         max->fbc = ilk_fbc_wm_reg_max(dev);
1911 }
1912
1913 static void ilk_compute_wm_reg_maximums(struct drm_device *dev,
1914                                         int level,
1915                                         struct ilk_wm_maximums *max)
1916 {
1917         max->pri = ilk_plane_wm_reg_max(dev, level, false);
1918         max->spr = ilk_plane_wm_reg_max(dev, level, true);
1919         max->cur = ilk_cursor_wm_reg_max(dev, level);
1920         max->fbc = ilk_fbc_wm_reg_max(dev);
1921 }
1922
1923 static bool ilk_validate_wm_level(int level,
1924                                   const struct ilk_wm_maximums *max,
1925                                   struct intel_wm_level *result)
1926 {
1927         bool ret;
1928
1929         /* already determined to be invalid? */
1930         if (!result->enable)
1931                 return false;
1932
1933         result->enable = result->pri_val <= max->pri &&
1934                          result->spr_val <= max->spr &&
1935                          result->cur_val <= max->cur;
1936
1937         ret = result->enable;
1938
1939         /*
1940          * HACK until we can pre-compute everything,
1941          * and thus fail gracefully if LP0 watermarks
1942          * are exceeded...
1943          */
1944         if (level == 0 && !result->enable) {
1945                 if (result->pri_val > max->pri)
1946                         DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
1947                                       level, result->pri_val, max->pri);
1948                 if (result->spr_val > max->spr)
1949                         DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
1950                                       level, result->spr_val, max->spr);
1951                 if (result->cur_val > max->cur)
1952                         DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
1953                                       level, result->cur_val, max->cur);
1954
1955                 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
1956                 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
1957                 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
1958                 result->enable = true;
1959         }
1960
1961         return ret;
1962 }
1963
1964 static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
1965                                  const struct intel_crtc *intel_crtc,
1966                                  int level,
1967                                  struct intel_crtc_state *cstate,
1968                                  struct intel_plane_state *pristate,
1969                                  struct intel_plane_state *sprstate,
1970                                  struct intel_plane_state *curstate,
1971                                  struct intel_wm_level *result)
1972 {
1973         uint16_t pri_latency = dev_priv->wm.pri_latency[level];
1974         uint16_t spr_latency = dev_priv->wm.spr_latency[level];
1975         uint16_t cur_latency = dev_priv->wm.cur_latency[level];
1976
1977         /* WM1+ latency values stored in 0.5us units */
1978         if (level > 0) {
1979                 pri_latency *= 5;
1980                 spr_latency *= 5;
1981                 cur_latency *= 5;
1982         }
1983
1984         result->pri_val = ilk_compute_pri_wm(cstate, pristate,
1985                                              pri_latency, level);
1986         result->spr_val = ilk_compute_spr_wm(cstate, sprstate, spr_latency);
1987         result->cur_val = ilk_compute_cur_wm(cstate, curstate, cur_latency);
1988         result->fbc_val = ilk_compute_fbc_wm(cstate, pristate, result->pri_val);
1989         result->enable = true;
1990 }
1991
1992 static uint32_t
1993 hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
1994 {
1995         struct drm_i915_private *dev_priv = dev->dev_private;
1996         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1997         const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
1998         u32 linetime, ips_linetime;
1999
2000         if (!intel_crtc->active)
2001                 return 0;
2002
2003         /* The WM are computed with base on how long it takes to fill a single
2004          * row at the given clock rate, multiplied by 8.
2005          * */
2006         linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2007                                      adjusted_mode->crtc_clock);
2008         ips_linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2009                                          dev_priv->cdclk_freq);
2010
2011         return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2012                PIPE_WM_LINETIME_TIME(linetime);
2013 }
2014
2015 static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8])
2016 {
2017         struct drm_i915_private *dev_priv = dev->dev_private;
2018
2019         if (IS_GEN9(dev)) {
2020                 uint32_t val;
2021                 int ret, i;
2022                 int level, max_level = ilk_wm_max_level(dev);
2023
2024                 /* read the first set of memory latencies[0:3] */
2025                 val = 0; /* data0 to be programmed to 0 for first set */
2026                 mutex_lock(&dev_priv->rps.hw_lock);
2027                 ret = sandybridge_pcode_read(dev_priv,
2028                                              GEN9_PCODE_READ_MEM_LATENCY,
2029                                              &val);
2030                 mutex_unlock(&dev_priv->rps.hw_lock);
2031
2032                 if (ret) {
2033                         DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2034                         return;
2035                 }
2036
2037                 wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2038                 wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2039                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2040                 wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2041                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2042                 wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2043                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2044
2045                 /* read the second set of memory latencies[4:7] */
2046                 val = 1; /* data0 to be programmed to 1 for second set */
2047                 mutex_lock(&dev_priv->rps.hw_lock);
2048                 ret = sandybridge_pcode_read(dev_priv,
2049                                              GEN9_PCODE_READ_MEM_LATENCY,
2050                                              &val);
2051                 mutex_unlock(&dev_priv->rps.hw_lock);
2052                 if (ret) {
2053                         DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2054                         return;
2055                 }
2056
2057                 wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2058                 wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2059                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2060                 wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2061                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2062                 wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2063                                 GEN9_MEM_LATENCY_LEVEL_MASK;
2064
2065                 /*
2066                  * WaWmMemoryReadLatency:skl
2067                  *
2068                  * punit doesn't take into account the read latency so we need
2069                  * to add 2us to the various latency levels we retrieve from
2070                  * the punit.
2071                  *   - W0 is a bit special in that it's the only level that
2072                  *   can't be disabled if we want to have display working, so
2073                  *   we always add 2us there.
2074                  *   - For levels >=1, punit returns 0us latency when they are
2075                  *   disabled, so we respect that and don't add 2us then
2076                  *
2077                  * Additionally, if a level n (n > 1) has a 0us latency, all
2078                  * levels m (m >= n) need to be disabled. We make sure to
2079                  * sanitize the values out of the punit to satisfy this
2080                  * requirement.
2081                  */
2082                 wm[0] += 2;
2083                 for (level = 1; level <= max_level; level++)
2084                         if (wm[level] != 0)
2085                                 wm[level] += 2;
2086                         else {
2087                                 for (i = level + 1; i <= max_level; i++)
2088                                         wm[i] = 0;
2089
2090                                 break;
2091                         }
2092         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2093                 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2094
2095                 wm[0] = (sskpd >> 56) & 0xFF;
2096                 if (wm[0] == 0)
2097                         wm[0] = sskpd & 0xF;
2098                 wm[1] = (sskpd >> 4) & 0xFF;
2099                 wm[2] = (sskpd >> 12) & 0xFF;
2100                 wm[3] = (sskpd >> 20) & 0x1FF;
2101                 wm[4] = (sskpd >> 32) & 0x1FF;
2102         } else if (INTEL_INFO(dev)->gen >= 6) {
2103                 uint32_t sskpd = I915_READ(MCH_SSKPD);
2104
2105                 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2106                 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2107                 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2108                 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
2109         } else if (INTEL_INFO(dev)->gen >= 5) {
2110                 uint32_t mltr = I915_READ(MLTR_ILK);
2111
2112                 /* ILK primary LP0 latency is 700 ns */
2113                 wm[0] = 7;
2114                 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2115                 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
2116         }
2117 }
2118
2119 static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2120 {
2121         /* ILK sprite LP0 latency is 1300 ns */
2122         if (INTEL_INFO(dev)->gen == 5)
2123                 wm[0] = 13;
2124 }
2125
2126 static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2127 {
2128         /* ILK cursor LP0 latency is 1300 ns */
2129         if (INTEL_INFO(dev)->gen == 5)
2130                 wm[0] = 13;
2131
2132         /* WaDoubleCursorLP3Latency:ivb */
2133         if (IS_IVYBRIDGE(dev))
2134                 wm[3] *= 2;
2135 }
2136
2137 int ilk_wm_max_level(const struct drm_device *dev)
2138 {
2139         /* how many WM levels are we expecting */
2140         if (INTEL_INFO(dev)->gen >= 9)
2141                 return 7;
2142         else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2143                 return 4;
2144         else if (INTEL_INFO(dev)->gen >= 6)
2145                 return 3;
2146         else
2147                 return 2;
2148 }
2149
2150 static void intel_print_wm_latency(struct drm_device *dev,
2151                                    const char *name,
2152                                    const uint16_t wm[8])
2153 {
2154         int level, max_level = ilk_wm_max_level(dev);
2155
2156         for (level = 0; level <= max_level; level++) {
2157                 unsigned int latency = wm[level];
2158
2159                 if (latency == 0) {
2160                         DRM_ERROR("%s WM%d latency not provided\n",
2161                                   name, level);
2162                         continue;
2163                 }
2164
2165                 /*
2166                  * - latencies are in us on gen9.
2167                  * - before then, WM1+ latency values are in 0.5us units
2168                  */
2169                 if (IS_GEN9(dev))
2170                         latency *= 10;
2171                 else if (level > 0)
2172                         latency *= 5;
2173
2174                 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2175                               name, level, wm[level],
2176                               latency / 10, latency % 10);
2177         }
2178 }
2179
2180 static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
2181                                     uint16_t wm[5], uint16_t min)
2182 {
2183         int level, max_level = ilk_wm_max_level(dev_priv->dev);
2184
2185         if (wm[0] >= min)
2186                 return false;
2187
2188         wm[0] = max(wm[0], min);
2189         for (level = 1; level <= max_level; level++)
2190                 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
2191
2192         return true;
2193 }
2194
2195 static void snb_wm_latency_quirk(struct drm_device *dev)
2196 {
2197         struct drm_i915_private *dev_priv = dev->dev_private;
2198         bool changed;
2199
2200         /*
2201          * The BIOS provided WM memory latency values are often
2202          * inadequate for high resolution displays. Adjust them.
2203          */
2204         changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
2205                 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
2206                 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
2207
2208         if (!changed)
2209                 return;
2210
2211         DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2212         intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2213         intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2214         intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2215 }
2216
2217 static void ilk_setup_wm_latency(struct drm_device *dev)
2218 {
2219         struct drm_i915_private *dev_priv = dev->dev_private;
2220
2221         intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2222
2223         memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2224                sizeof(dev_priv->wm.pri_latency));
2225         memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2226                sizeof(dev_priv->wm.pri_latency));
2227
2228         intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2229         intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
2230
2231         intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2232         intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2233         intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2234
2235         if (IS_GEN6(dev))
2236                 snb_wm_latency_quirk(dev);
2237 }
2238
2239 static void skl_setup_wm_latency(struct drm_device *dev)
2240 {
2241         struct drm_i915_private *dev_priv = dev->dev_private;
2242
2243         intel_read_wm_latency(dev, dev_priv->wm.skl_latency);
2244         intel_print_wm_latency(dev, "Gen9 Plane", dev_priv->wm.skl_latency);
2245 }
2246
2247 /* Compute new watermarks for the pipe */
2248 static int ilk_compute_pipe_wm(struct intel_crtc *intel_crtc,
2249                                struct drm_atomic_state *state)
2250 {
2251         struct intel_pipe_wm *pipe_wm;
2252         struct drm_device *dev = intel_crtc->base.dev;
2253         const struct drm_i915_private *dev_priv = dev->dev_private;
2254         struct intel_crtc_state *cstate = NULL;
2255         struct intel_plane *intel_plane;
2256         struct drm_plane_state *ps;
2257         struct intel_plane_state *pristate = NULL;
2258         struct intel_plane_state *sprstate = NULL;
2259         struct intel_plane_state *curstate = NULL;
2260         int level, max_level = ilk_wm_max_level(dev);
2261         /* LP0 watermark maximums depend on this pipe alone */
2262         struct intel_wm_config config = {
2263                 .num_pipes_active = 1,
2264         };
2265         struct ilk_wm_maximums max;
2266
2267         cstate = intel_atomic_get_crtc_state(state, intel_crtc);
2268         if (IS_ERR(cstate))
2269                 return PTR_ERR(cstate);
2270
2271         pipe_wm = &cstate->wm.optimal.ilk;
2272
2273         for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
2274                 ps = drm_atomic_get_plane_state(state,
2275                                                 &intel_plane->base);
2276                 if (IS_ERR(ps))
2277                         return PTR_ERR(ps);
2278
2279                 if (intel_plane->base.type == DRM_PLANE_TYPE_PRIMARY)
2280                         pristate = to_intel_plane_state(ps);
2281                 else if (intel_plane->base.type == DRM_PLANE_TYPE_OVERLAY)
2282                         sprstate = to_intel_plane_state(ps);
2283                 else if (intel_plane->base.type == DRM_PLANE_TYPE_CURSOR)
2284                         curstate = to_intel_plane_state(ps);
2285         }
2286
2287         config.sprites_enabled = sprstate->visible;
2288         config.sprites_scaled = sprstate->visible &&
2289                 (drm_rect_width(&sprstate->dst) != drm_rect_width(&sprstate->src) >> 16 ||
2290                 drm_rect_height(&sprstate->dst) != drm_rect_height(&sprstate->src) >> 16);
2291
2292         pipe_wm->pipe_enabled = cstate->base.active;
2293         pipe_wm->sprites_enabled = config.sprites_enabled;
2294         pipe_wm->sprites_scaled = config.sprites_scaled;
2295
2296         /* ILK/SNB: LP2+ watermarks only w/o sprites */
2297         if (INTEL_INFO(dev)->gen <= 6 && sprstate->visible)
2298                 max_level = 1;
2299
2300         /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
2301         if (config.sprites_scaled)
2302                 max_level = 0;
2303
2304         ilk_compute_wm_level(dev_priv, intel_crtc, 0, cstate,
2305                              pristate, sprstate, curstate, &pipe_wm->wm[0]);
2306
2307         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2308                 pipe_wm->linetime = hsw_compute_linetime_wm(dev,
2309                                                             &intel_crtc->base);
2310
2311         /* LP0 watermarks always use 1/2 DDB partitioning */
2312         ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2313
2314         /* At least LP0 must be valid */
2315         if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0]))
2316                 return -EINVAL;
2317
2318         ilk_compute_wm_reg_maximums(dev, 1, &max);
2319
2320         for (level = 1; level <= max_level; level++) {
2321                 struct intel_wm_level wm = {};
2322
2323                 ilk_compute_wm_level(dev_priv, intel_crtc, level, cstate,
2324                                      pristate, sprstate, curstate, &wm);
2325
2326                 /*
2327                  * Disable any watermark level that exceeds the
2328                  * register maximums since such watermarks are
2329                  * always invalid.
2330                  */
2331                 if (!ilk_validate_wm_level(level, &max, &wm))
2332                         break;
2333
2334                 pipe_wm->wm[level] = wm;
2335         }
2336
2337         return 0;
2338 }
2339
2340 /*
2341  * Merge the watermarks from all active pipes for a specific level.
2342  */
2343 static void ilk_merge_wm_level(struct drm_device *dev,
2344                                int level,
2345                                struct intel_wm_level *ret_wm)
2346 {
2347         const struct intel_crtc *intel_crtc;
2348
2349         ret_wm->enable = true;
2350
2351         for_each_intel_crtc(dev, intel_crtc) {
2352                 const struct intel_crtc_state *cstate =
2353                         to_intel_crtc_state(intel_crtc->base.state);
2354                 const struct intel_pipe_wm *active = &cstate->wm.optimal.ilk;
2355                 const struct intel_wm_level *wm = &active->wm[level];
2356
2357                 if (!active->pipe_enabled)
2358                         continue;
2359
2360                 /*
2361                  * The watermark values may have been used in the past,
2362                  * so we must maintain them in the registers for some
2363                  * time even if the level is now disabled.
2364                  */
2365                 if (!wm->enable)
2366                         ret_wm->enable = false;
2367
2368                 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2369                 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2370                 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2371                 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2372         }
2373 }
2374
2375 /*
2376  * Merge all low power watermarks for all active pipes.
2377  */
2378 static void ilk_wm_merge(struct drm_device *dev,
2379                          const struct intel_wm_config *config,
2380                          const struct ilk_wm_maximums *max,
2381                          struct intel_pipe_wm *merged)
2382 {
2383         struct drm_i915_private *dev_priv = dev->dev_private;
2384         int level, max_level = ilk_wm_max_level(dev);
2385         int last_enabled_level = max_level;
2386
2387         /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2388         if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) &&
2389             config->num_pipes_active > 1)
2390                 return;
2391
2392         /* ILK: FBC WM must be disabled always */
2393         merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
2394
2395         /* merge each WM1+ level */
2396         for (level = 1; level <= max_level; level++) {
2397                 struct intel_wm_level *wm = &merged->wm[level];
2398
2399                 ilk_merge_wm_level(dev, level, wm);
2400
2401                 if (level > last_enabled_level)
2402                         wm->enable = false;
2403                 else if (!ilk_validate_wm_level(level, max, wm))
2404                         /* make sure all following levels get disabled */
2405                         last_enabled_level = level - 1;
2406
2407                 /*
2408                  * The spec says it is preferred to disable
2409                  * FBC WMs instead of disabling a WM level.
2410                  */
2411                 if (wm->fbc_val > max->fbc) {
2412                         if (wm->enable)
2413                                 merged->fbc_wm_enabled = false;
2414                         wm->fbc_val = 0;
2415                 }
2416         }
2417
2418         /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2419         /*
2420          * FIXME this is racy. FBC might get enabled later.
2421          * What we should check here is whether FBC can be
2422          * enabled sometime later.
2423          */
2424         if (IS_GEN5(dev) && !merged->fbc_wm_enabled &&
2425             intel_fbc_enabled(dev_priv)) {
2426                 for (level = 2; level <= max_level; level++) {
2427                         struct intel_wm_level *wm = &merged->wm[level];
2428
2429                         wm->enable = false;
2430                 }
2431         }
2432 }
2433
2434 static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2435 {
2436         /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2437         return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2438 }
2439
2440 /* The value we need to program into the WM_LPx latency field */
2441 static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2442 {
2443         struct drm_i915_private *dev_priv = dev->dev_private;
2444
2445         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
2446                 return 2 * level;
2447         else
2448                 return dev_priv->wm.pri_latency[level];
2449 }
2450
2451 static void ilk_compute_wm_results(struct drm_device *dev,
2452                                    const struct intel_pipe_wm *merged,
2453                                    enum intel_ddb_partitioning partitioning,
2454                                    struct ilk_wm_values *results)
2455 {
2456         struct intel_crtc *intel_crtc;
2457         int level, wm_lp;
2458
2459         results->enable_fbc_wm = merged->fbc_wm_enabled;
2460         results->partitioning = partitioning;
2461
2462         /* LP1+ register values */
2463         for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2464                 const struct intel_wm_level *r;
2465
2466                 level = ilk_wm_lp_to_level(wm_lp, merged);
2467
2468                 r = &merged->wm[level];
2469
2470                 /*
2471                  * Maintain the watermark values even if the level is
2472                  * disabled. Doing otherwise could cause underruns.
2473                  */
2474                 results->wm_lp[wm_lp - 1] =
2475                         (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
2476                         (r->pri_val << WM1_LP_SR_SHIFT) |
2477                         r->cur_val;
2478
2479                 if (r->enable)
2480                         results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
2481
2482                 if (INTEL_INFO(dev)->gen >= 8)
2483                         results->wm_lp[wm_lp - 1] |=
2484                                 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2485                 else
2486                         results->wm_lp[wm_lp - 1] |=
2487                                 r->fbc_val << WM1_LP_FBC_SHIFT;
2488
2489                 /*
2490                  * Always set WM1S_LP_EN when spr_val != 0, even if the
2491                  * level is disabled. Doing otherwise could cause underruns.
2492                  */
2493                 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2494                         WARN_ON(wm_lp != 1);
2495                         results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2496                 } else
2497                         results->wm_lp_spr[wm_lp - 1] = r->spr_val;
2498         }
2499
2500         /* LP0 register values */
2501         for_each_intel_crtc(dev, intel_crtc) {
2502                 const struct intel_crtc_state *cstate =
2503                         to_intel_crtc_state(intel_crtc->base.state);
2504                 enum pipe pipe = intel_crtc->pipe;
2505                 const struct intel_wm_level *r = &cstate->wm.optimal.ilk.wm[0];
2506
2507                 if (WARN_ON(!r->enable))
2508                         continue;
2509
2510                 results->wm_linetime[pipe] = cstate->wm.optimal.ilk.linetime;
2511
2512                 results->wm_pipe[pipe] =
2513                         (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2514                         (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2515                         r->cur_val;
2516         }
2517 }
2518
2519 /* Find the result with the highest level enabled. Check for enable_fbc_wm in
2520  * case both are at the same level. Prefer r1 in case they're the same. */
2521 static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
2522                                                   struct intel_pipe_wm *r1,
2523                                                   struct intel_pipe_wm *r2)
2524 {
2525         int level, max_level = ilk_wm_max_level(dev);
2526         int level1 = 0, level2 = 0;
2527
2528         for (level = 1; level <= max_level; level++) {
2529                 if (r1->wm[level].enable)
2530                         level1 = level;
2531                 if (r2->wm[level].enable)
2532                         level2 = level;
2533         }
2534
2535         if (level1 == level2) {
2536                 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
2537                         return r2;
2538                 else
2539                         return r1;
2540         } else if (level1 > level2) {
2541                 return r1;
2542         } else {
2543                 return r2;
2544         }
2545 }
2546
2547 /* dirty bits used to track which watermarks need changes */
2548 #define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2549 #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2550 #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2551 #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2552 #define WM_DIRTY_FBC (1 << 24)
2553 #define WM_DIRTY_DDB (1 << 25)
2554
2555 static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
2556                                          const struct ilk_wm_values *old,
2557                                          const struct ilk_wm_values *new)
2558 {
2559         unsigned int dirty = 0;
2560         enum pipe pipe;
2561         int wm_lp;
2562
2563         for_each_pipe(dev_priv, pipe) {
2564                 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2565                         dirty |= WM_DIRTY_LINETIME(pipe);
2566                         /* Must disable LP1+ watermarks too */
2567                         dirty |= WM_DIRTY_LP_ALL;
2568                 }
2569
2570                 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2571                         dirty |= WM_DIRTY_PIPE(pipe);
2572                         /* Must disable LP1+ watermarks too */
2573                         dirty |= WM_DIRTY_LP_ALL;
2574                 }
2575         }
2576
2577         if (old->enable_fbc_wm != new->enable_fbc_wm) {
2578                 dirty |= WM_DIRTY_FBC;
2579                 /* Must disable LP1+ watermarks too */
2580                 dirty |= WM_DIRTY_LP_ALL;
2581         }
2582
2583         if (old->partitioning != new->partitioning) {
2584                 dirty |= WM_DIRTY_DDB;
2585                 /* Must disable LP1+ watermarks too */
2586                 dirty |= WM_DIRTY_LP_ALL;
2587         }
2588
2589         /* LP1+ watermarks already deemed dirty, no need to continue */
2590         if (dirty & WM_DIRTY_LP_ALL)
2591                 return dirty;
2592
2593         /* Find the lowest numbered LP1+ watermark in need of an update... */
2594         for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2595                 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2596                     old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2597                         break;
2598         }
2599
2600         /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2601         for (; wm_lp <= 3; wm_lp++)
2602                 dirty |= WM_DIRTY_LP(wm_lp);
2603
2604         return dirty;
2605 }
2606
2607 static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2608                                unsigned int dirty)
2609 {
2610         struct ilk_wm_values *previous = &dev_priv->wm.hw;
2611         bool changed = false;
2612
2613         if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2614                 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2615                 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
2616                 changed = true;
2617         }
2618         if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2619                 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2620                 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
2621                 changed = true;
2622         }
2623         if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2624                 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2625                 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
2626                 changed = true;
2627         }
2628
2629         /*
2630          * Don't touch WM1S_LP_EN here.
2631          * Doing so could cause underruns.
2632          */
2633
2634         return changed;
2635 }
2636
2637 /*
2638  * The spec says we shouldn't write when we don't need, because every write
2639  * causes WMs to be re-evaluated, expending some power.
2640  */
2641 static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2642                                 struct ilk_wm_values *results)
2643 {
2644         struct drm_device *dev = dev_priv->dev;
2645         struct ilk_wm_values *previous = &dev_priv->wm.hw;
2646         unsigned int dirty;
2647         uint32_t val;
2648
2649         dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
2650         if (!dirty)
2651                 return;
2652
2653         _ilk_disable_lp_wm(dev_priv, dirty);
2654
2655         if (dirty & WM_DIRTY_PIPE(PIPE_A))
2656                 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
2657         if (dirty & WM_DIRTY_PIPE(PIPE_B))
2658                 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
2659         if (dirty & WM_DIRTY_PIPE(PIPE_C))
2660                 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2661
2662         if (dirty & WM_DIRTY_LINETIME(PIPE_A))
2663                 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
2664         if (dirty & WM_DIRTY_LINETIME(PIPE_B))
2665                 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
2666         if (dirty & WM_DIRTY_LINETIME(PIPE_C))
2667                 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2668
2669         if (dirty & WM_DIRTY_DDB) {
2670                 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
2671                         val = I915_READ(WM_MISC);
2672                         if (results->partitioning == INTEL_DDB_PART_1_2)
2673                                 val &= ~WM_MISC_DATA_PARTITION_5_6;
2674                         else
2675                                 val |= WM_MISC_DATA_PARTITION_5_6;
2676                         I915_WRITE(WM_MISC, val);
2677                 } else {
2678                         val = I915_READ(DISP_ARB_CTL2);
2679                         if (results->partitioning == INTEL_DDB_PART_1_2)
2680                                 val &= ~DISP_DATA_PARTITION_5_6;
2681                         else
2682                                 val |= DISP_DATA_PARTITION_5_6;
2683                         I915_WRITE(DISP_ARB_CTL2, val);
2684                 }
2685         }
2686
2687         if (dirty & WM_DIRTY_FBC) {
2688                 val = I915_READ(DISP_ARB_CTL);
2689                 if (results->enable_fbc_wm)
2690                         val &= ~DISP_FBC_WM_DIS;
2691                 else
2692                         val |= DISP_FBC_WM_DIS;
2693                 I915_WRITE(DISP_ARB_CTL, val);
2694         }
2695
2696         if (dirty & WM_DIRTY_LP(1) &&
2697             previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2698                 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2699
2700         if (INTEL_INFO(dev)->gen >= 7) {
2701                 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2702                         I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2703                 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2704                         I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2705         }
2706
2707         if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
2708                 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
2709         if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
2710                 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
2711         if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
2712                 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
2713
2714         dev_priv->wm.hw = *results;
2715 }
2716
2717 static bool ilk_disable_lp_wm(struct drm_device *dev)
2718 {
2719         struct drm_i915_private *dev_priv = dev->dev_private;
2720
2721         return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2722 }
2723
2724 /*
2725  * On gen9, we need to allocate Display Data Buffer (DDB) portions to the
2726  * different active planes.
2727  */
2728
2729 #define SKL_DDB_SIZE            896     /* in blocks */
2730 #define BXT_DDB_SIZE            512
2731
2732 /*
2733  * Return the index of a plane in the SKL DDB and wm result arrays.  Primary
2734  * plane is always in slot 0, cursor is always in slot I915_MAX_PLANES-1, and
2735  * other universal planes are in indices 1..n.  Note that this may leave unused
2736  * indices between the top "sprite" plane and the cursor.
2737  */
2738 static int
2739 skl_wm_plane_id(const struct intel_plane *plane)
2740 {
2741         switch (plane->base.type) {
2742         case DRM_PLANE_TYPE_PRIMARY:
2743                 return 0;
2744         case DRM_PLANE_TYPE_CURSOR:
2745                 return PLANE_CURSOR;
2746         case DRM_PLANE_TYPE_OVERLAY:
2747                 return plane->plane + 1;
2748         default:
2749                 MISSING_CASE(plane->base.type);
2750                 return plane->plane;
2751         }
2752 }
2753
2754 static void
2755 skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
2756                                    const struct intel_crtc_state *cstate,
2757                                    const struct intel_wm_config *config,
2758                                    struct skl_ddb_entry *alloc /* out */)
2759 {
2760         struct drm_crtc *for_crtc = cstate->base.crtc;
2761         struct drm_crtc *crtc;
2762         unsigned int pipe_size, ddb_size;
2763         int nth_active_pipe;
2764
2765         if (!cstate->base.active) {
2766                 alloc->start = 0;
2767                 alloc->end = 0;
2768                 return;
2769         }
2770
2771         if (IS_BROXTON(dev))
2772                 ddb_size = BXT_DDB_SIZE;
2773         else
2774                 ddb_size = SKL_DDB_SIZE;
2775
2776         ddb_size -= 4; /* 4 blocks for bypass path allocation */
2777
2778         nth_active_pipe = 0;
2779         for_each_crtc(dev, crtc) {
2780                 if (!to_intel_crtc(crtc)->active)
2781                         continue;
2782
2783                 if (crtc == for_crtc)
2784                         break;
2785
2786                 nth_active_pipe++;
2787         }
2788
2789         pipe_size = ddb_size / config->num_pipes_active;
2790         alloc->start = nth_active_pipe * ddb_size / config->num_pipes_active;
2791         alloc->end = alloc->start + pipe_size;
2792 }
2793
2794 static unsigned int skl_cursor_allocation(const struct intel_wm_config *config)
2795 {
2796         if (config->num_pipes_active == 1)
2797                 return 32;
2798
2799         return 8;
2800 }
2801
2802 static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
2803 {
2804         entry->start = reg & 0x3ff;
2805         entry->end = (reg >> 16) & 0x3ff;
2806         if (entry->end)
2807                 entry->end += 1;
2808 }
2809
2810 void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
2811                           struct skl_ddb_allocation *ddb /* out */)
2812 {
2813         enum pipe pipe;
2814         int plane;
2815         u32 val;
2816
2817         memset(ddb, 0, sizeof(*ddb));
2818
2819         for_each_pipe(dev_priv, pipe) {
2820                 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PIPE(pipe)))
2821                         continue;
2822
2823                 for_each_plane(dev_priv, pipe, plane) {
2824                         val = I915_READ(PLANE_BUF_CFG(pipe, plane));
2825                         skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane],
2826                                                    val);
2827                 }
2828
2829                 val = I915_READ(CUR_BUF_CFG(pipe));
2830                 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][PLANE_CURSOR],
2831                                            val);
2832         }
2833 }
2834
2835 static unsigned int
2836 skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
2837                              const struct drm_plane_state *pstate,
2838                              int y)
2839 {
2840         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
2841         struct drm_framebuffer *fb = pstate->fb;
2842
2843         /* for planar format */
2844         if (fb->pixel_format == DRM_FORMAT_NV12) {
2845                 if (y)  /* y-plane data rate */
2846                         return intel_crtc->config->pipe_src_w *
2847                                 intel_crtc->config->pipe_src_h *
2848                                 drm_format_plane_cpp(fb->pixel_format, 0);
2849                 else    /* uv-plane data rate */
2850                         return (intel_crtc->config->pipe_src_w/2) *
2851                                 (intel_crtc->config->pipe_src_h/2) *
2852                                 drm_format_plane_cpp(fb->pixel_format, 1);
2853         }
2854
2855         /* for packed formats */
2856         return intel_crtc->config->pipe_src_w *
2857                 intel_crtc->config->pipe_src_h *
2858                 drm_format_plane_cpp(fb->pixel_format, 0);
2859 }
2860
2861 /*
2862  * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching
2863  * a 8192x4096@32bpp framebuffer:
2864  *   3 * 4096 * 8192  * 4 < 2^32
2865  */
2866 static unsigned int
2867 skl_get_total_relative_data_rate(const struct intel_crtc_state *cstate)
2868 {
2869         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
2870         struct drm_device *dev = intel_crtc->base.dev;
2871         const struct intel_plane *intel_plane;
2872         unsigned int total_data_rate = 0;
2873
2874         for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
2875                 const struct drm_plane_state *pstate = intel_plane->base.state;
2876
2877                 if (pstate->fb == NULL)
2878                         continue;
2879
2880                 if (intel_plane->base.type == DRM_PLANE_TYPE_CURSOR)
2881                         continue;
2882
2883                 /* packed/uv */
2884                 total_data_rate += skl_plane_relative_data_rate(cstate,
2885                                                                 pstate,
2886                                                                 0);
2887
2888                 if (pstate->fb->pixel_format == DRM_FORMAT_NV12)
2889                         /* y-plane */
2890                         total_data_rate += skl_plane_relative_data_rate(cstate,
2891                                                                         pstate,
2892                                                                         1);
2893         }
2894
2895         return total_data_rate;
2896 }
2897
2898 static void
2899 skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
2900                       struct skl_ddb_allocation *ddb /* out */)
2901 {
2902         struct drm_crtc *crtc = cstate->base.crtc;
2903         struct drm_device *dev = crtc->dev;
2904         struct drm_i915_private *dev_priv = to_i915(dev);
2905         struct intel_wm_config *config = &dev_priv->wm.config;
2906         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2907         struct intel_plane *intel_plane;
2908         enum pipe pipe = intel_crtc->pipe;
2909         struct skl_ddb_entry *alloc = &ddb->pipe[pipe];
2910         uint16_t alloc_size, start, cursor_blocks;
2911         uint16_t minimum[I915_MAX_PLANES];
2912         uint16_t y_minimum[I915_MAX_PLANES];
2913         unsigned int total_data_rate;
2914
2915         skl_ddb_get_pipe_allocation_limits(dev, cstate, config, alloc);
2916         alloc_size = skl_ddb_entry_size(alloc);
2917         if (alloc_size == 0) {
2918                 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
2919                 memset(&ddb->plane[pipe][PLANE_CURSOR], 0,
2920                        sizeof(ddb->plane[pipe][PLANE_CURSOR]));
2921                 return;
2922         }
2923
2924         cursor_blocks = skl_cursor_allocation(config);
2925         ddb->plane[pipe][PLANE_CURSOR].start = alloc->end - cursor_blocks;
2926         ddb->plane[pipe][PLANE_CURSOR].end = alloc->end;
2927
2928         alloc_size -= cursor_blocks;
2929         alloc->end -= cursor_blocks;
2930
2931         /* 1. Allocate the mininum required blocks for each active plane */
2932         for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
2933                 struct drm_plane *plane = &intel_plane->base;
2934                 struct drm_framebuffer *fb = plane->state->fb;
2935                 int id = skl_wm_plane_id(intel_plane);
2936
2937                 if (fb == NULL)
2938                         continue;
2939                 if (plane->type == DRM_PLANE_TYPE_CURSOR)
2940                         continue;
2941
2942                 minimum[id] = 8;
2943                 alloc_size -= minimum[id];
2944                 y_minimum[id] = (fb->pixel_format == DRM_FORMAT_NV12) ? 8 : 0;
2945                 alloc_size -= y_minimum[id];
2946         }
2947
2948         /*
2949          * 2. Distribute the remaining space in proportion to the amount of
2950          * data each plane needs to fetch from memory.
2951          *
2952          * FIXME: we may not allocate every single block here.
2953          */
2954         total_data_rate = skl_get_total_relative_data_rate(cstate);
2955
2956         start = alloc->start;
2957         for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
2958                 struct drm_plane *plane = &intel_plane->base;
2959                 struct drm_plane_state *pstate = intel_plane->base.state;
2960                 unsigned int data_rate, y_data_rate;
2961                 uint16_t plane_blocks, y_plane_blocks = 0;
2962                 int id = skl_wm_plane_id(intel_plane);
2963
2964                 if (pstate->fb == NULL)
2965                         continue;
2966                 if (plane->type == DRM_PLANE_TYPE_CURSOR)
2967                         continue;
2968
2969                 data_rate = skl_plane_relative_data_rate(cstate, pstate, 0);
2970
2971                 /*
2972                  * allocation for (packed formats) or (uv-plane part of planar format):
2973                  * promote the expression to 64 bits to avoid overflowing, the
2974                  * result is < available as data_rate / total_data_rate < 1
2975                  */
2976                 plane_blocks = minimum[id];
2977                 plane_blocks += div_u64((uint64_t)alloc_size * data_rate,
2978                                         total_data_rate);
2979
2980                 ddb->plane[pipe][id].start = start;
2981                 ddb->plane[pipe][id].end = start + plane_blocks;
2982
2983                 start += plane_blocks;
2984
2985                 /*
2986                  * allocation for y_plane part of planar format:
2987                  */
2988                 if (pstate->fb->pixel_format == DRM_FORMAT_NV12) {
2989                         y_data_rate = skl_plane_relative_data_rate(cstate,
2990                                                                    pstate,
2991                                                                    1);
2992                         y_plane_blocks = y_minimum[id];
2993                         y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate,
2994                                                 total_data_rate);
2995
2996                         ddb->y_plane[pipe][id].start = start;
2997                         ddb->y_plane[pipe][id].end = start + y_plane_blocks;
2998
2999                         start += y_plane_blocks;
3000                 }
3001
3002         }
3003
3004 }
3005
3006 static uint32_t skl_pipe_pixel_rate(const struct intel_crtc_state *config)
3007 {
3008         /* TODO: Take into account the scalers once we support them */
3009         return config->base.adjusted_mode.crtc_clock;
3010 }
3011
3012 /*
3013  * The max latency should be 257 (max the punit can code is 255 and we add 2us
3014  * for the read latency) and bytes_per_pixel should always be <= 8, so that
3015  * should allow pixel_rate up to ~2 GHz which seems sufficient since max
3016  * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
3017 */
3018 static uint32_t skl_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
3019                                uint32_t latency)
3020 {
3021         uint32_t wm_intermediate_val, ret;
3022
3023         if (latency == 0)
3024                 return UINT_MAX;
3025
3026         wm_intermediate_val = latency * pixel_rate * bytes_per_pixel / 512;
3027         ret = DIV_ROUND_UP(wm_intermediate_val, 1000);
3028
3029         return ret;
3030 }
3031
3032 static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
3033                                uint32_t horiz_pixels, uint8_t bytes_per_pixel,
3034                                uint64_t tiling, uint32_t latency)
3035 {
3036         uint32_t ret;
3037         uint32_t plane_bytes_per_line, plane_blocks_per_line;
3038         uint32_t wm_intermediate_val;
3039
3040         if (latency == 0)
3041                 return UINT_MAX;
3042
3043         plane_bytes_per_line = horiz_pixels * bytes_per_pixel;
3044
3045         if (tiling == I915_FORMAT_MOD_Y_TILED ||
3046             tiling == I915_FORMAT_MOD_Yf_TILED) {
3047                 plane_bytes_per_line *= 4;
3048                 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3049                 plane_blocks_per_line /= 4;
3050         } else {
3051                 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3052         }
3053
3054         wm_intermediate_val = latency * pixel_rate;
3055         ret = DIV_ROUND_UP(wm_intermediate_val, pipe_htotal * 1000) *
3056                                 plane_blocks_per_line;
3057
3058         return ret;
3059 }
3060
3061 static bool skl_ddb_allocation_changed(const struct skl_ddb_allocation *new_ddb,
3062                                        const struct intel_crtc *intel_crtc)
3063 {
3064         struct drm_device *dev = intel_crtc->base.dev;
3065         struct drm_i915_private *dev_priv = dev->dev_private;
3066         const struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb;
3067
3068         /*
3069          * If ddb allocation of pipes changed, it may require recalculation of
3070          * watermarks
3071          */
3072         if (memcmp(new_ddb->pipe, cur_ddb->pipe, sizeof(new_ddb->pipe)))
3073                 return true;
3074
3075         return false;
3076 }
3077
3078 static bool skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
3079                                  struct intel_crtc_state *cstate,
3080                                  struct intel_plane *intel_plane,
3081                                  uint16_t ddb_allocation,
3082                                  int level,
3083                                  uint16_t *out_blocks, /* out */
3084                                  uint8_t *out_lines /* out */)
3085 {
3086         struct drm_plane *plane = &intel_plane->base;
3087         struct drm_framebuffer *fb = plane->state->fb;
3088         uint32_t latency = dev_priv->wm.skl_latency[level];
3089         uint32_t method1, method2;
3090         uint32_t plane_bytes_per_line, plane_blocks_per_line;
3091         uint32_t res_blocks, res_lines;
3092         uint32_t selected_result;
3093         uint8_t bytes_per_pixel;
3094
3095         if (latency == 0 || !cstate->base.active || !fb)
3096                 return false;
3097
3098         bytes_per_pixel = drm_format_plane_cpp(fb->pixel_format, 0);
3099         method1 = skl_wm_method1(skl_pipe_pixel_rate(cstate),
3100                                  bytes_per_pixel,
3101                                  latency);
3102         method2 = skl_wm_method2(skl_pipe_pixel_rate(cstate),
3103                                  cstate->base.adjusted_mode.crtc_htotal,
3104                                  cstate->pipe_src_w,
3105                                  bytes_per_pixel,
3106                                  fb->modifier[0],
3107                                  latency);
3108
3109         plane_bytes_per_line = cstate->pipe_src_w * bytes_per_pixel;
3110         plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3111
3112         if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3113             fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED) {
3114                 uint32_t min_scanlines = 4;
3115                 uint32_t y_tile_minimum;
3116                 if (intel_rotation_90_or_270(plane->state->rotation)) {
3117                         int bpp = (fb->pixel_format == DRM_FORMAT_NV12) ?
3118                                 drm_format_plane_cpp(fb->pixel_format, 1) :
3119                                 drm_format_plane_cpp(fb->pixel_format, 0);
3120
3121                         switch (bpp) {
3122                         case 1:
3123                                 min_scanlines = 16;
3124                                 break;
3125                         case 2:
3126                                 min_scanlines = 8;
3127                                 break;
3128                         case 8:
3129                                 WARN(1, "Unsupported pixel depth for rotation");
3130                         }
3131                 }
3132                 y_tile_minimum = plane_blocks_per_line * min_scanlines;
3133                 selected_result = max(method2, y_tile_minimum);
3134         } else {
3135                 if ((ddb_allocation / plane_blocks_per_line) >= 1)
3136                         selected_result = min(method1, method2);
3137                 else
3138                         selected_result = method1;
3139         }
3140
3141         res_blocks = selected_result + 1;
3142         res_lines = DIV_ROUND_UP(selected_result, plane_blocks_per_line);
3143
3144         if (level >= 1 && level <= 7) {
3145                 if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3146                     fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED)
3147                         res_lines += 4;
3148                 else
3149                         res_blocks++;
3150         }
3151
3152         if (res_blocks >= ddb_allocation || res_lines > 31)
3153                 return false;
3154
3155         *out_blocks = res_blocks;
3156         *out_lines = res_lines;
3157
3158         return true;
3159 }
3160
3161 static void skl_compute_wm_level(const struct drm_i915_private *dev_priv,
3162                                  struct skl_ddb_allocation *ddb,
3163                                  struct intel_crtc_state *cstate,
3164                                  int level,
3165                                  struct skl_wm_level *result)
3166 {
3167         struct drm_device *dev = dev_priv->dev;
3168         struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
3169         struct intel_plane *intel_plane;
3170         uint16_t ddb_blocks;
3171         enum pipe pipe = intel_crtc->pipe;
3172
3173         for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3174                 int i = skl_wm_plane_id(intel_plane);
3175
3176                 ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][i]);
3177
3178                 result->plane_en[i] = skl_compute_plane_wm(dev_priv,
3179                                                 cstate,
3180                                                 intel_plane,
3181                                                 ddb_blocks,
3182                                                 level,
3183                                                 &result->plane_res_b[i],
3184                                                 &result->plane_res_l[i]);
3185         }
3186 }
3187
3188 static uint32_t
3189 skl_compute_linetime_wm(struct intel_crtc_state *cstate)
3190 {
3191         if (!cstate->base.active)
3192                 return 0;
3193
3194         if (WARN_ON(skl_pipe_pixel_rate(cstate) == 0))
3195                 return 0;
3196
3197         return DIV_ROUND_UP(8 * cstate->base.adjusted_mode.crtc_htotal * 1000,
3198                             skl_pipe_pixel_rate(cstate));
3199 }
3200
3201 static void skl_compute_transition_wm(struct intel_crtc_state *cstate,
3202                                       struct skl_wm_level *trans_wm /* out */)
3203 {
3204         struct drm_crtc *crtc = cstate->base.crtc;
3205         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3206         struct intel_plane *intel_plane;
3207
3208         if (!cstate->base.active)
3209                 return;
3210
3211         /* Until we know more, just disable transition WMs */
3212         for_each_intel_plane_on_crtc(crtc->dev, intel_crtc, intel_plane) {
3213                 int i = skl_wm_plane_id(intel_plane);
3214
3215                 trans_wm->plane_en[i] = false;
3216         }
3217 }
3218
3219 static void skl_compute_pipe_wm(struct intel_crtc_state *cstate,
3220                                 struct skl_ddb_allocation *ddb,
3221                                 struct skl_pipe_wm *pipe_wm)
3222 {
3223         struct drm_device *dev = cstate->base.crtc->dev;
3224         const struct drm_i915_private *dev_priv = dev->dev_private;
3225         int level, max_level = ilk_wm_max_level(dev);
3226
3227         for (level = 0; level <= max_level; level++) {
3228                 skl_compute_wm_level(dev_priv, ddb, cstate,
3229                                      level, &pipe_wm->wm[level]);
3230         }
3231         pipe_wm->linetime = skl_compute_linetime_wm(cstate);
3232
3233         skl_compute_transition_wm(cstate, &pipe_wm->trans_wm);
3234 }
3235
3236 static void skl_compute_wm_results(struct drm_device *dev,
3237                                    struct skl_pipe_wm *p_wm,
3238                                    struct skl_wm_values *r,
3239                                    struct intel_crtc *intel_crtc)
3240 {
3241         int level, max_level = ilk_wm_max_level(dev);
3242         enum pipe pipe = intel_crtc->pipe;
3243         uint32_t temp;
3244         int i;
3245
3246         for (level = 0; level <= max_level; level++) {
3247                 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3248                         temp = 0;
3249
3250                         temp |= p_wm->wm[level].plane_res_l[i] <<
3251                                         PLANE_WM_LINES_SHIFT;
3252                         temp |= p_wm->wm[level].plane_res_b[i];
3253                         if (p_wm->wm[level].plane_en[i])
3254                                 temp |= PLANE_WM_EN;
3255
3256                         r->plane[pipe][i][level] = temp;
3257                 }
3258
3259                 temp = 0;
3260
3261                 temp |= p_wm->wm[level].plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT;
3262                 temp |= p_wm->wm[level].plane_res_b[PLANE_CURSOR];
3263
3264                 if (p_wm->wm[level].plane_en[PLANE_CURSOR])
3265                         temp |= PLANE_WM_EN;
3266
3267                 r->plane[pipe][PLANE_CURSOR][level] = temp;
3268
3269         }
3270
3271         /* transition WMs */
3272         for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3273                 temp = 0;
3274                 temp |= p_wm->trans_wm.plane_res_l[i] << PLANE_WM_LINES_SHIFT;
3275                 temp |= p_wm->trans_wm.plane_res_b[i];
3276                 if (p_wm->trans_wm.plane_en[i])
3277                         temp |= PLANE_WM_EN;
3278
3279                 r->plane_trans[pipe][i] = temp;
3280         }
3281
3282         temp = 0;
3283         temp |= p_wm->trans_wm.plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT;
3284         temp |= p_wm->trans_wm.plane_res_b[PLANE_CURSOR];
3285         if (p_wm->trans_wm.plane_en[PLANE_CURSOR])
3286                 temp |= PLANE_WM_EN;
3287
3288         r->plane_trans[pipe][PLANE_CURSOR] = temp;
3289
3290         r->wm_linetime[pipe] = p_wm->linetime;
3291 }
3292
3293 static void skl_ddb_entry_write(struct drm_i915_private *dev_priv,
3294                                 i915_reg_t reg,
3295                                 const struct skl_ddb_entry *entry)
3296 {
3297         if (entry->end)
3298                 I915_WRITE(reg, (entry->end - 1) << 16 | entry->start);
3299         else
3300                 I915_WRITE(reg, 0);
3301 }
3302
3303 static void skl_write_wm_values(struct drm_i915_private *dev_priv,
3304                                 const struct skl_wm_values *new)
3305 {
3306         struct drm_device *dev = dev_priv->dev;
3307         struct intel_crtc *crtc;
3308
3309         list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
3310                 int i, level, max_level = ilk_wm_max_level(dev);
3311                 enum pipe pipe = crtc->pipe;
3312
3313                 if (!new->dirty[pipe])
3314                         continue;
3315
3316                 I915_WRITE(PIPE_WM_LINETIME(pipe), new->wm_linetime[pipe]);
3317
3318                 for (level = 0; level <= max_level; level++) {
3319                         for (i = 0; i < intel_num_planes(crtc); i++)
3320                                 I915_WRITE(PLANE_WM(pipe, i, level),
3321                                            new->plane[pipe][i][level]);
3322                         I915_WRITE(CUR_WM(pipe, level),
3323                                    new->plane[pipe][PLANE_CURSOR][level]);
3324                 }
3325                 for (i = 0; i < intel_num_planes(crtc); i++)
3326                         I915_WRITE(PLANE_WM_TRANS(pipe, i),
3327                                    new->plane_trans[pipe][i]);
3328                 I915_WRITE(CUR_WM_TRANS(pipe),
3329                            new->plane_trans[pipe][PLANE_CURSOR]);
3330
3331                 for (i = 0; i < intel_num_planes(crtc); i++) {
3332                         skl_ddb_entry_write(dev_priv,
3333                                             PLANE_BUF_CFG(pipe, i),
3334                                             &new->ddb.plane[pipe][i]);
3335                         skl_ddb_entry_write(dev_priv,
3336                                             PLANE_NV12_BUF_CFG(pipe, i),
3337                                             &new->ddb.y_plane[pipe][i]);
3338                 }
3339
3340                 skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe),
3341                                     &new->ddb.plane[pipe][PLANE_CURSOR]);
3342         }
3343 }
3344
3345 /*
3346  * When setting up a new DDB allocation arrangement, we need to correctly
3347  * sequence the times at which the new allocations for the pipes are taken into
3348  * account or we'll have pipes fetching from space previously allocated to
3349  * another pipe.
3350  *
3351  * Roughly the sequence looks like:
3352  *  1. re-allocate the pipe(s) with the allocation being reduced and not
3353  *     overlapping with a previous light-up pipe (another way to put it is:
3354  *     pipes with their new allocation strickly included into their old ones).
3355  *  2. re-allocate the other pipes that get their allocation reduced
3356  *  3. allocate the pipes having their allocation increased
3357  *
3358  * Steps 1. and 2. are here to take care of the following case:
3359  * - Initially DDB looks like this:
3360  *     |   B    |   C    |
3361  * - enable pipe A.
3362  * - pipe B has a reduced DDB allocation that overlaps with the old pipe C
3363  *   allocation
3364  *     |  A  |  B  |  C  |
3365  *
3366  * We need to sequence the re-allocation: C, B, A (and not B, C, A).
3367  */
3368
3369 static void
3370 skl_wm_flush_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, int pass)
3371 {
3372         int plane;
3373
3374         DRM_DEBUG_KMS("flush pipe %c (pass %d)\n", pipe_name(pipe), pass);
3375
3376         for_each_plane(dev_priv, pipe, plane) {
3377                 I915_WRITE(PLANE_SURF(pipe, plane),
3378                            I915_READ(PLANE_SURF(pipe, plane)));
3379         }
3380         I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3381 }
3382
3383 static bool
3384 skl_ddb_allocation_included(const struct skl_ddb_allocation *old,
3385                             const struct skl_ddb_allocation *new,
3386                             enum pipe pipe)
3387 {
3388         uint16_t old_size, new_size;
3389
3390         old_size = skl_ddb_entry_size(&old->pipe[pipe]);
3391         new_size = skl_ddb_entry_size(&new->pipe[pipe]);
3392
3393         return old_size != new_size &&
3394                new->pipe[pipe].start >= old->pipe[pipe].start &&
3395                new->pipe[pipe].end <= old->pipe[pipe].end;
3396 }
3397
3398 static void skl_flush_wm_values(struct drm_i915_private *dev_priv,
3399                                 struct skl_wm_values *new_values)
3400 {
3401         struct drm_device *dev = dev_priv->dev;
3402         struct skl_ddb_allocation *cur_ddb, *new_ddb;
3403         bool reallocated[I915_MAX_PIPES] = {};
3404         struct intel_crtc *crtc;
3405         enum pipe pipe;
3406
3407         new_ddb = &new_values->ddb;
3408         cur_ddb = &dev_priv->wm.skl_hw.ddb;
3409
3410         /*
3411          * First pass: flush the pipes with the new allocation contained into
3412          * the old space.
3413          *
3414          * We'll wait for the vblank on those pipes to ensure we can safely
3415          * re-allocate the freed space without this pipe fetching from it.
3416          */
3417         for_each_intel_crtc(dev, crtc) {
3418                 if (!crtc->active)
3419                         continue;
3420
3421                 pipe = crtc->pipe;
3422
3423                 if (!skl_ddb_allocation_included(cur_ddb, new_ddb, pipe))
3424                         continue;
3425
3426                 skl_wm_flush_pipe(dev_priv, pipe, 1);
3427                 intel_wait_for_vblank(dev, pipe);
3428
3429                 reallocated[pipe] = true;
3430         }
3431
3432
3433         /*
3434          * Second pass: flush the pipes that are having their allocation
3435          * reduced, but overlapping with a previous allocation.
3436          *
3437          * Here as well we need to wait for the vblank to make sure the freed
3438          * space is not used anymore.
3439          */
3440         for_each_intel_crtc(dev, crtc) {
3441                 if (!crtc->active)
3442                         continue;
3443
3444                 pipe = crtc->pipe;
3445
3446                 if (reallocated[pipe])
3447                         continue;
3448
3449                 if (skl_ddb_entry_size(&new_ddb->pipe[pipe]) <
3450                     skl_ddb_entry_size(&cur_ddb->pipe[pipe])) {
3451                         skl_wm_flush_pipe(dev_priv, pipe, 2);
3452                         intel_wait_for_vblank(dev, pipe);
3453                         reallocated[pipe] = true;
3454                 }
3455         }
3456
3457         /*
3458          * Third pass: flush the pipes that got more space allocated.
3459          *
3460          * We don't need to actively wait for the update here, next vblank
3461          * will just get more DDB space with the correct WM values.
3462          */
3463         for_each_intel_crtc(dev, crtc) {
3464                 if (!crtc->active)
3465                         continue;
3466
3467                 pipe = crtc->pipe;
3468
3469                 /*
3470                  * At this point, only the pipes more space than before are
3471                  * left to re-allocate.
3472                  */
3473                 if (reallocated[pipe])
3474                         continue;
3475
3476                 skl_wm_flush_pipe(dev_priv, pipe, 3);
3477         }
3478 }
3479
3480 static bool skl_update_pipe_wm(struct drm_crtc *crtc,
3481                                struct skl_ddb_allocation *ddb, /* out */
3482                                struct skl_pipe_wm *pipe_wm /* out */)
3483 {
3484         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3485         struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
3486
3487         skl_allocate_pipe_ddb(cstate, ddb);
3488         skl_compute_pipe_wm(cstate, ddb, pipe_wm);
3489
3490         if (!memcmp(&intel_crtc->wm.active.skl, pipe_wm, sizeof(*pipe_wm)))
3491                 return false;
3492
3493         intel_crtc->wm.active.skl = *pipe_wm;
3494
3495         return true;
3496 }
3497
3498 static void skl_update_other_pipe_wm(struct drm_device *dev,
3499                                      struct drm_crtc *crtc,
3500                                      struct skl_wm_values *r)
3501 {
3502         struct intel_crtc *intel_crtc;
3503         struct intel_crtc *this_crtc = to_intel_crtc(crtc);
3504
3505         /*
3506          * If the WM update hasn't changed the allocation for this_crtc (the
3507          * crtc we are currently computing the new WM values for), other
3508          * enabled crtcs will keep the same allocation and we don't need to
3509          * recompute anything for them.
3510          */
3511         if (!skl_ddb_allocation_changed(&r->ddb, this_crtc))
3512                 return;
3513
3514         /*
3515          * Otherwise, because of this_crtc being freshly enabled/disabled, the
3516          * other active pipes need new DDB allocation and WM values.
3517          */
3518         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
3519                                 base.head) {
3520                 struct skl_pipe_wm pipe_wm = {};
3521                 bool wm_changed;
3522
3523                 if (this_crtc->pipe == intel_crtc->pipe)
3524                         continue;
3525
3526                 if (!intel_crtc->active)
3527                         continue;
3528
3529                 wm_changed = skl_update_pipe_wm(&intel_crtc->base,
3530                                                 &r->ddb, &pipe_wm);
3531
3532                 /*
3533                  * If we end up re-computing the other pipe WM values, it's
3534                  * because it was really needed, so we expect the WM values to
3535                  * be different.
3536                  */
3537                 WARN_ON(!wm_changed);
3538
3539                 skl_compute_wm_results(dev, &pipe_wm, r, intel_crtc);
3540                 r->dirty[intel_crtc->pipe] = true;
3541         }
3542 }
3543
3544 static void skl_clear_wm(struct skl_wm_values *watermarks, enum pipe pipe)
3545 {
3546         watermarks->wm_linetime[pipe] = 0;
3547         memset(watermarks->plane[pipe], 0,
3548                sizeof(uint32_t) * 8 * I915_MAX_PLANES);
3549         memset(watermarks->plane_trans[pipe],
3550                0, sizeof(uint32_t) * I915_MAX_PLANES);
3551         watermarks->plane_trans[pipe][PLANE_CURSOR] = 0;
3552
3553         /* Clear ddb entries for pipe */
3554         memset(&watermarks->ddb.pipe[pipe], 0, sizeof(struct skl_ddb_entry));
3555         memset(&watermarks->ddb.plane[pipe], 0,
3556                sizeof(struct skl_ddb_entry) * I915_MAX_PLANES);
3557         memset(&watermarks->ddb.y_plane[pipe], 0,
3558                sizeof(struct skl_ddb_entry) * I915_MAX_PLANES);
3559         memset(&watermarks->ddb.plane[pipe][PLANE_CURSOR], 0,
3560                sizeof(struct skl_ddb_entry));
3561
3562 }
3563
3564 static void skl_update_wm(struct drm_crtc *crtc)
3565 {
3566         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3567         struct drm_device *dev = crtc->dev;
3568         struct drm_i915_private *dev_priv = dev->dev_private;
3569         struct skl_wm_values *results = &dev_priv->wm.skl_results;
3570         struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
3571         struct skl_pipe_wm *pipe_wm = &cstate->wm.optimal.skl;
3572
3573
3574         /* Clear all dirty flags */
3575         memset(results->dirty, 0, sizeof(bool) * I915_MAX_PIPES);
3576
3577         skl_clear_wm(results, intel_crtc->pipe);
3578
3579         if (!skl_update_pipe_wm(crtc, &results->ddb, pipe_wm))
3580                 return;
3581
3582         skl_compute_wm_results(dev, pipe_wm, results, intel_crtc);
3583         results->dirty[intel_crtc->pipe] = true;
3584
3585         skl_update_other_pipe_wm(dev, crtc, results);
3586         skl_write_wm_values(dev_priv, results);
3587         skl_flush_wm_values(dev_priv, results);
3588
3589         /* store the new configuration */
3590         dev_priv->wm.skl_hw = *results;
3591 }
3592
3593 static void ilk_program_watermarks(struct drm_i915_private *dev_priv)
3594 {
3595         struct drm_device *dev = dev_priv->dev;
3596         struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
3597         struct ilk_wm_maximums max;
3598         struct intel_wm_config *config = &dev_priv->wm.config;
3599         struct ilk_wm_values results = {};
3600         enum intel_ddb_partitioning partitioning;
3601
3602         ilk_compute_wm_maximums(dev, 1, config, INTEL_DDB_PART_1_2, &max);
3603         ilk_wm_merge(dev, config, &max, &lp_wm_1_2);
3604
3605         /* 5/6 split only in single pipe config on IVB+ */
3606         if (INTEL_INFO(dev)->gen >= 7 &&
3607             config->num_pipes_active == 1 && config->sprites_enabled) {
3608                 ilk_compute_wm_maximums(dev, 1, config, INTEL_DDB_PART_5_6, &max);
3609                 ilk_wm_merge(dev, config, &max, &lp_wm_5_6);
3610
3611                 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
3612         } else {
3613                 best_lp_wm = &lp_wm_1_2;
3614         }
3615
3616         partitioning = (best_lp_wm == &lp_wm_1_2) ?
3617                        INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
3618
3619         ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
3620
3621         ilk_write_wm_values(dev_priv, &results);
3622 }
3623
3624 static void ilk_update_wm(struct drm_crtc *crtc)
3625 {
3626         struct drm_i915_private *dev_priv = to_i915(crtc->dev);
3627         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3628         struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
3629
3630         WARN_ON(cstate->base.active != intel_crtc->active);
3631
3632         /*
3633          * IVB workaround: must disable low power watermarks for at least
3634          * one frame before enabling scaling.  LP watermarks can be re-enabled
3635          * when scaling is disabled.
3636          *
3637          * WaCxSRDisabledForSpriteScaling:ivb
3638          */
3639         if (cstate->disable_lp_wm) {
3640                 ilk_disable_lp_wm(crtc->dev);
3641                 intel_wait_for_vblank(crtc->dev, intel_crtc->pipe);
3642         }
3643
3644         intel_crtc->wm.active.ilk = cstate->wm.optimal.ilk;
3645
3646         ilk_program_watermarks(dev_priv);
3647 }
3648
3649 static void skl_pipe_wm_active_state(uint32_t val,
3650                                      struct skl_pipe_wm *active,
3651                                      bool is_transwm,
3652                                      bool is_cursor,
3653                                      int i,
3654                                      int level)
3655 {
3656         bool is_enabled = (val & PLANE_WM_EN) != 0;
3657
3658         if (!is_transwm) {
3659                 if (!is_cursor) {
3660                         active->wm[level].plane_en[i] = is_enabled;
3661                         active->wm[level].plane_res_b[i] =
3662                                         val & PLANE_WM_BLOCKS_MASK;
3663                         active->wm[level].plane_res_l[i] =
3664                                         (val >> PLANE_WM_LINES_SHIFT) &
3665                                                 PLANE_WM_LINES_MASK;
3666                 } else {
3667                         active->wm[level].plane_en[PLANE_CURSOR] = is_enabled;
3668                         active->wm[level].plane_res_b[PLANE_CURSOR] =
3669                                         val & PLANE_WM_BLOCKS_MASK;
3670                         active->wm[level].plane_res_l[PLANE_CURSOR] =
3671                                         (val >> PLANE_WM_LINES_SHIFT) &
3672                                                 PLANE_WM_LINES_MASK;
3673                 }
3674         } else {
3675                 if (!is_cursor) {
3676                         active->trans_wm.plane_en[i] = is_enabled;
3677                         active->trans_wm.plane_res_b[i] =
3678                                         val & PLANE_WM_BLOCKS_MASK;
3679                         active->trans_wm.plane_res_l[i] =
3680                                         (val >> PLANE_WM_LINES_SHIFT) &
3681                                                 PLANE_WM_LINES_MASK;
3682                 } else {
3683                         active->trans_wm.plane_en[PLANE_CURSOR] = is_enabled;
3684                         active->trans_wm.plane_res_b[PLANE_CURSOR] =
3685                                         val & PLANE_WM_BLOCKS_MASK;
3686                         active->trans_wm.plane_res_l[PLANE_CURSOR] =
3687                                         (val >> PLANE_WM_LINES_SHIFT) &
3688                                                 PLANE_WM_LINES_MASK;
3689                 }
3690         }
3691 }
3692
3693 static void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3694 {
3695         struct drm_device *dev = crtc->dev;
3696         struct drm_i915_private *dev_priv = dev->dev_private;
3697         struct skl_wm_values *hw = &dev_priv->wm.skl_hw;
3698         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3699         struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
3700         struct skl_pipe_wm *active = &cstate->wm.optimal.skl;
3701         enum pipe pipe = intel_crtc->pipe;
3702         int level, i, max_level;
3703         uint32_t temp;
3704
3705         max_level = ilk_wm_max_level(dev);
3706
3707         hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
3708
3709         for (level = 0; level <= max_level; level++) {
3710                 for (i = 0; i < intel_num_planes(intel_crtc); i++)
3711                         hw->plane[pipe][i][level] =
3712                                         I915_READ(PLANE_WM(pipe, i, level));
3713                 hw->plane[pipe][PLANE_CURSOR][level] = I915_READ(CUR_WM(pipe, level));
3714         }
3715
3716         for (i = 0; i < intel_num_planes(intel_crtc); i++)
3717                 hw->plane_trans[pipe][i] = I915_READ(PLANE_WM_TRANS(pipe, i));
3718         hw->plane_trans[pipe][PLANE_CURSOR] = I915_READ(CUR_WM_TRANS(pipe));
3719
3720         if (!intel_crtc->active)
3721                 return;
3722
3723         hw->dirty[pipe] = true;
3724
3725         active->linetime = hw->wm_linetime[pipe];
3726
3727         for (level = 0; level <= max_level; level++) {
3728                 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3729                         temp = hw->plane[pipe][i][level];
3730                         skl_pipe_wm_active_state(temp, active, false,
3731                                                 false, i, level);
3732                 }
3733                 temp = hw->plane[pipe][PLANE_CURSOR][level];
3734                 skl_pipe_wm_active_state(temp, active, false, true, i, level);
3735         }
3736
3737         for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3738                 temp = hw->plane_trans[pipe][i];
3739                 skl_pipe_wm_active_state(temp, active, true, false, i, 0);
3740         }
3741
3742         temp = hw->plane_trans[pipe][PLANE_CURSOR];
3743         skl_pipe_wm_active_state(temp, active, true, true, i, 0);
3744
3745         intel_crtc->wm.active.skl = *active;
3746 }
3747
3748 void skl_wm_get_hw_state(struct drm_device *dev)
3749 {
3750         struct drm_i915_private *dev_priv = dev->dev_private;
3751         struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
3752         struct drm_crtc *crtc;
3753
3754         skl_ddb_get_hw_state(dev_priv, ddb);
3755         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
3756                 skl_pipe_wm_get_hw_state(crtc);
3757 }
3758
3759 static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3760 {
3761         struct drm_device *dev = crtc->dev;
3762         struct drm_i915_private *dev_priv = dev->dev_private;
3763         struct ilk_wm_values *hw = &dev_priv->wm.hw;
3764         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3765         struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
3766         struct intel_pipe_wm *active = &cstate->wm.optimal.ilk;
3767         enum pipe pipe = intel_crtc->pipe;
3768         static const i915_reg_t wm0_pipe_reg[] = {
3769                 [PIPE_A] = WM0_PIPEA_ILK,
3770                 [PIPE_B] = WM0_PIPEB_ILK,
3771                 [PIPE_C] = WM0_PIPEC_IVB,
3772         };
3773
3774         hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
3775         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
3776                 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
3777
3778         active->pipe_enabled = intel_crtc->active;
3779
3780         if (active->pipe_enabled) {
3781                 u32 tmp = hw->wm_pipe[pipe];
3782
3783                 /*
3784                  * For active pipes LP0 watermark is marked as
3785                  * enabled, and LP1+ watermaks as disabled since
3786                  * we can't really reverse compute them in case
3787                  * multiple pipes are active.
3788                  */
3789                 active->wm[0].enable = true;
3790                 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
3791                 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
3792                 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
3793                 active->linetime = hw->wm_linetime[pipe];
3794         } else {
3795                 int level, max_level = ilk_wm_max_level(dev);
3796
3797                 /*
3798                  * For inactive pipes, all watermark levels
3799                  * should be marked as enabled but zeroed,
3800                  * which is what we'd compute them to.
3801                  */
3802                 for (level = 0; level <= max_level; level++)
3803                         active->wm[level].enable = true;
3804         }
3805
3806         intel_crtc->wm.active.ilk = *active;
3807 }
3808
3809 #define _FW_WM(value, plane) \
3810         (((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT)
3811 #define _FW_WM_VLV(value, plane) \
3812         (((value) & DSPFW_ ## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT)
3813
3814 static void vlv_read_wm_values(struct drm_i915_private *dev_priv,
3815                                struct vlv_wm_values *wm)
3816 {
3817         enum pipe pipe;
3818         uint32_t tmp;
3819
3820         for_each_pipe(dev_priv, pipe) {
3821                 tmp = I915_READ(VLV_DDL(pipe));
3822
3823                 wm->ddl[pipe].primary =
3824                         (tmp >> DDL_PLANE_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3825                 wm->ddl[pipe].cursor =
3826                         (tmp >> DDL_CURSOR_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3827                 wm->ddl[pipe].sprite[0] =
3828                         (tmp >> DDL_SPRITE_SHIFT(0)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3829                 wm->ddl[pipe].sprite[1] =
3830                         (tmp >> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3831         }
3832
3833         tmp = I915_READ(DSPFW1);
3834         wm->sr.plane = _FW_WM(tmp, SR);
3835         wm->pipe[PIPE_B].cursor = _FW_WM(tmp, CURSORB);
3836         wm->pipe[PIPE_B].primary = _FW_WM_VLV(tmp, PLANEB);
3837         wm->pipe[PIPE_A].primary = _FW_WM_VLV(tmp, PLANEA);
3838
3839         tmp = I915_READ(DSPFW2);
3840         wm->pipe[PIPE_A].sprite[1] = _FW_WM_VLV(tmp, SPRITEB);
3841         wm->pipe[PIPE_A].cursor = _FW_WM(tmp, CURSORA);
3842         wm->pipe[PIPE_A].sprite[0] = _FW_WM_VLV(tmp, SPRITEA);
3843
3844         tmp = I915_READ(DSPFW3);
3845         wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
3846
3847         if (IS_CHERRYVIEW(dev_priv)) {
3848                 tmp = I915_READ(DSPFW7_CHV);
3849                 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
3850                 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
3851
3852                 tmp = I915_READ(DSPFW8_CHV);
3853                 wm->pipe[PIPE_C].sprite[1] = _FW_WM_VLV(tmp, SPRITEF);
3854                 wm->pipe[PIPE_C].sprite[0] = _FW_WM_VLV(tmp, SPRITEE);
3855
3856                 tmp = I915_READ(DSPFW9_CHV);
3857                 wm->pipe[PIPE_C].primary = _FW_WM_VLV(tmp, PLANEC);
3858                 wm->pipe[PIPE_C].cursor = _FW_WM(tmp, CURSORC);
3859
3860                 tmp = I915_READ(DSPHOWM);
3861                 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
3862                 wm->pipe[PIPE_C].sprite[1] |= _FW_WM(tmp, SPRITEF_HI) << 8;
3863                 wm->pipe[PIPE_C].sprite[0] |= _FW_WM(tmp, SPRITEE_HI) << 8;
3864                 wm->pipe[PIPE_C].primary |= _FW_WM(tmp, PLANEC_HI) << 8;
3865                 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
3866                 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
3867                 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
3868                 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
3869                 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
3870                 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
3871         } else {
3872                 tmp = I915_READ(DSPFW7);
3873                 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
3874                 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
3875
3876                 tmp = I915_READ(DSPHOWM);
3877                 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
3878                 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
3879                 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
3880                 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
3881                 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
3882                 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
3883                 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
3884         }
3885 }
3886
3887 #undef _FW_WM
3888 #undef _FW_WM_VLV
3889
3890 void vlv_wm_get_hw_state(struct drm_device *dev)
3891 {
3892         struct drm_i915_private *dev_priv = to_i915(dev);
3893         struct vlv_wm_values *wm = &dev_priv->wm.vlv;
3894         struct intel_plane *plane;
3895         enum pipe pipe;
3896         u32 val;
3897
3898         vlv_read_wm_values(dev_priv, wm);
3899
3900         for_each_intel_plane(dev, plane) {
3901                 switch (plane->base.type) {
3902                         int sprite;
3903                 case DRM_PLANE_TYPE_CURSOR:
3904                         plane->wm.fifo_size = 63;
3905                         break;
3906                 case DRM_PLANE_TYPE_PRIMARY:
3907                         plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, 0);
3908                         break;
3909                 case DRM_PLANE_TYPE_OVERLAY:
3910                         sprite = plane->plane;
3911                         plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, sprite + 1);
3912                         break;
3913                 }
3914         }
3915
3916         wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
3917         wm->level = VLV_WM_LEVEL_PM2;
3918
3919         if (IS_CHERRYVIEW(dev_priv)) {
3920                 mutex_lock(&dev_priv->rps.hw_lock);
3921
3922                 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
3923                 if (val & DSP_MAXFIFO_PM5_ENABLE)
3924                         wm->level = VLV_WM_LEVEL_PM5;
3925
3926                 /*
3927                  * If DDR DVFS is disabled in the BIOS, Punit
3928                  * will never ack the request. So if that happens
3929                  * assume we don't have to enable/disable DDR DVFS
3930                  * dynamically. To test that just set the REQ_ACK
3931                  * bit to poke the Punit, but don't change the
3932                  * HIGH/LOW bits so that we don't actually change
3933                  * the current state.
3934                  */
3935                 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
3936                 val |= FORCE_DDR_FREQ_REQ_ACK;
3937                 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
3938
3939                 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
3940                               FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) {
3941                         DRM_DEBUG_KMS("Punit not acking DDR DVFS request, "
3942                                       "assuming DDR DVFS is disabled\n");
3943                         dev_priv->wm.max_level = VLV_WM_LEVEL_PM5;
3944                 } else {
3945                         val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
3946                         if ((val & FORCE_DDR_HIGH_FREQ) == 0)
3947                                 wm->level = VLV_WM_LEVEL_DDR_DVFS;
3948                 }
3949
3950                 mutex_unlock(&dev_priv->rps.hw_lock);
3951         }
3952
3953         for_each_pipe(dev_priv, pipe)
3954                 DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n",
3955                               pipe_name(pipe), wm->pipe[pipe].primary, wm->pipe[pipe].cursor,
3956                               wm->pipe[pipe].sprite[0], wm->pipe[pipe].sprite[1]);
3957
3958         DRM_DEBUG_KMS("Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n",
3959                       wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr);
3960 }
3961
3962 void ilk_wm_get_hw_state(struct drm_device *dev)
3963 {
3964         struct drm_i915_private *dev_priv = dev->dev_private;
3965         struct ilk_wm_values *hw = &dev_priv->wm.hw;
3966         struct drm_crtc *crtc;
3967
3968         for_each_crtc(dev, crtc)
3969                 ilk_pipe_wm_get_hw_state(crtc);
3970
3971         hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
3972         hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
3973         hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
3974
3975         hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
3976         if (INTEL_INFO(dev)->gen >= 7) {
3977                 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
3978                 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
3979         }
3980
3981         if (IS_HASWELL(dev) || IS_BROADWELL(dev))
3982                 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
3983                         INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
3984         else if (IS_IVYBRIDGE(dev))
3985                 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
3986                         INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
3987
3988         hw->enable_fbc_wm =
3989                 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
3990 }
3991
3992 /**
3993  * intel_update_watermarks - update FIFO watermark values based on current modes
3994  *
3995  * Calculate watermark values for the various WM regs based on current mode
3996  * and plane configuration.
3997  *
3998  * There are several cases to deal with here:
3999  *   - normal (i.e. non-self-refresh)
4000  *   - self-refresh (SR) mode
4001  *   - lines are large relative to FIFO size (buffer can hold up to 2)
4002  *   - lines are small relative to FIFO size (buffer can hold more than 2
4003  *     lines), so need to account for TLB latency
4004  *
4005  *   The normal calculation is:
4006  *     watermark = dotclock * bytes per pixel * latency
4007  *   where latency is platform & configuration dependent (we assume pessimal
4008  *   values here).
4009  *
4010  *   The SR calculation is:
4011  *     watermark = (trunc(latency/line time)+1) * surface width *
4012  *       bytes per pixel
4013  *   where
4014  *     line time = htotal / dotclock
4015  *     surface width = hdisplay for normal plane and 64 for cursor
4016  *   and latency is assumed to be high, as above.
4017  *
4018  * The final value programmed to the register should always be rounded up,
4019  * and include an extra 2 entries to account for clock crossings.
4020  *
4021  * We don't use the sprite, so we can ignore that.  And on Crestline we have
4022  * to set the non-SR watermarks to 8.
4023  */
4024 void intel_update_watermarks(struct drm_crtc *crtc)
4025 {
4026         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
4027
4028         if (dev_priv->display.update_wm)
4029                 dev_priv->display.update_wm(crtc);
4030 }
4031
4032 /**
4033  * Lock protecting IPS related data structures
4034  */
4035 DEFINE_SPINLOCK(mchdev_lock);
4036
4037 /* Global for IPS driver to get at the current i915 device. Protected by
4038  * mchdev_lock. */
4039 static struct drm_i915_private *i915_mch_dev;
4040
4041 bool ironlake_set_drps(struct drm_device *dev, u8 val)
4042 {
4043         struct drm_i915_private *dev_priv = dev->dev_private;
4044         u16 rgvswctl;
4045
4046         assert_spin_locked(&mchdev_lock);
4047
4048         rgvswctl = I915_READ16(MEMSWCTL);
4049         if (rgvswctl & MEMCTL_CMD_STS) {
4050                 DRM_DEBUG("gpu busy, RCS change rejected\n");
4051                 return false; /* still busy with another command */
4052         }
4053
4054         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
4055                 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
4056         I915_WRITE16(MEMSWCTL, rgvswctl);
4057         POSTING_READ16(MEMSWCTL);
4058
4059         rgvswctl |= MEMCTL_CMD_STS;
4060         I915_WRITE16(MEMSWCTL, rgvswctl);
4061
4062         return true;
4063 }
4064
4065 static void ironlake_enable_drps(struct drm_device *dev)
4066 {
4067         struct drm_i915_private *dev_priv = dev->dev_private;
4068         u32 rgvmodectl = I915_READ(MEMMODECTL);
4069         u8 fmax, fmin, fstart, vstart;
4070
4071         spin_lock_irq(&mchdev_lock);
4072
4073         /* Enable temp reporting */
4074         I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
4075         I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
4076
4077         /* 100ms RC evaluation intervals */
4078         I915_WRITE(RCUPEI, 100000);
4079         I915_WRITE(RCDNEI, 100000);
4080
4081         /* Set max/min thresholds to 90ms and 80ms respectively */
4082         I915_WRITE(RCBMAXAVG, 90000);
4083         I915_WRITE(RCBMINAVG, 80000);
4084
4085         I915_WRITE(MEMIHYST, 1);
4086
4087         /* Set up min, max, and cur for interrupt handling */
4088         fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
4089         fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
4090         fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
4091                 MEMMODE_FSTART_SHIFT;
4092
4093         vstart = (I915_READ(PXVFREQ(fstart)) & PXVFREQ_PX_MASK) >>
4094                 PXVFREQ_PX_SHIFT;
4095
4096         dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
4097         dev_priv->ips.fstart = fstart;
4098
4099         dev_priv->ips.max_delay = fstart;
4100         dev_priv->ips.min_delay = fmin;
4101         dev_priv->ips.cur_delay = fstart;
4102
4103         DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
4104                          fmax, fmin, fstart);
4105
4106         I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
4107
4108         /*
4109          * Interrupts will be enabled in ironlake_irq_postinstall
4110          */
4111
4112         I915_WRITE(VIDSTART, vstart);
4113         POSTING_READ(VIDSTART);
4114
4115         rgvmodectl |= MEMMODE_SWMODE_EN;
4116         I915_WRITE(MEMMODECTL, rgvmodectl);
4117
4118         if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
4119                 DRM_ERROR("stuck trying to change perf mode\n");
4120         mdelay(1);
4121
4122         ironlake_set_drps(dev, fstart);
4123
4124         dev_priv->ips.last_count1 = I915_READ(DMIEC) +
4125                 I915_READ(DDREC) + I915_READ(CSIEC);
4126         dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
4127         dev_priv->ips.last_count2 = I915_READ(GFXEC);
4128         dev_priv->ips.last_time2 = ktime_get_raw_ns();
4129
4130         spin_unlock_irq(&mchdev_lock);
4131 }
4132
4133 static void ironlake_disable_drps(struct drm_device *dev)
4134 {
4135         struct drm_i915_private *dev_priv = dev->dev_private;
4136         u16 rgvswctl;
4137
4138         spin_lock_irq(&mchdev_lock);
4139
4140         rgvswctl = I915_READ16(MEMSWCTL);
4141
4142         /* Ack interrupts, disable EFC interrupt */
4143         I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
4144         I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
4145         I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
4146         I915_WRITE(DEIIR, DE_PCU_EVENT);
4147         I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
4148
4149         /* Go back to the starting frequency */
4150         ironlake_set_drps(dev, dev_priv->ips.fstart);
4151         mdelay(1);
4152         rgvswctl |= MEMCTL_CMD_STS;
4153         I915_WRITE(MEMSWCTL, rgvswctl);
4154         mdelay(1);
4155
4156         spin_unlock_irq(&mchdev_lock);
4157 }
4158
4159 /* There's a funny hw issue where the hw returns all 0 when reading from
4160  * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
4161  * ourselves, instead of doing a rmw cycle (which might result in us clearing
4162  * all limits and the gpu stuck at whatever frequency it is at atm).
4163  */
4164 static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val)
4165 {
4166         u32 limits;
4167
4168         /* Only set the down limit when we've reached the lowest level to avoid
4169          * getting more interrupts, otherwise leave this clear. This prevents a
4170          * race in the hw when coming out of rc6: There's a tiny window where
4171          * the hw runs at the minimal clock before selecting the desired
4172          * frequency, if the down threshold expires in that window we will not
4173          * receive a down interrupt. */
4174         if (IS_GEN9(dev_priv->dev)) {
4175                 limits = (dev_priv->rps.max_freq_softlimit) << 23;
4176                 if (val <= dev_priv->rps.min_freq_softlimit)
4177                         limits |= (dev_priv->rps.min_freq_softlimit) << 14;
4178         } else {
4179                 limits = dev_priv->rps.max_freq_softlimit << 24;
4180                 if (val <= dev_priv->rps.min_freq_softlimit)
4181                         limits |= dev_priv->rps.min_freq_softlimit << 16;
4182         }
4183
4184         return limits;
4185 }
4186
4187 static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
4188 {
4189         int new_power;
4190         u32 threshold_up = 0, threshold_down = 0; /* in % */
4191         u32 ei_up = 0, ei_down = 0;
4192
4193         new_power = dev_priv->rps.power;
4194         switch (dev_priv->rps.power) {
4195         case LOW_POWER:
4196                 if (val > dev_priv->rps.efficient_freq + 1 && val > dev_priv->rps.cur_freq)
4197                         new_power = BETWEEN;
4198                 break;
4199
4200         case BETWEEN:
4201                 if (val <= dev_priv->rps.efficient_freq && val < dev_priv->rps.cur_freq)
4202                         new_power = LOW_POWER;
4203                 else if (val >= dev_priv->rps.rp0_freq && val > dev_priv->rps.cur_freq)
4204                         new_power = HIGH_POWER;
4205                 break;
4206
4207         case HIGH_POWER:
4208                 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 && val < dev_priv->rps.cur_freq)
4209                         new_power = BETWEEN;
4210                 break;
4211         }
4212         /* Max/min bins are special */
4213         if (val <= dev_priv->rps.min_freq_softlimit)
4214                 new_power = LOW_POWER;
4215         if (val >= dev_priv->rps.max_freq_softlimit)
4216                 new_power = HIGH_POWER;
4217         if (new_power == dev_priv->rps.power)
4218                 return;
4219
4220         /* Note the units here are not exactly 1us, but 1280ns. */
4221         switch (new_power) {
4222         case LOW_POWER:
4223                 /* Upclock if more than 95% busy over 16ms */
4224                 ei_up = 16000;
4225                 threshold_up = 95;
4226
4227                 /* Downclock if less than 85% busy over 32ms */
4228                 ei_down = 32000;
4229                 threshold_down = 85;
4230                 break;
4231
4232         case BETWEEN:
4233                 /* Upclock if more than 90% busy over 13ms */
4234                 ei_up = 13000;
4235                 threshold_up = 90;
4236
4237                 /* Downclock if less than 75% busy over 32ms */
4238                 ei_down = 32000;
4239                 threshold_down = 75;
4240                 break;
4241
4242         case HIGH_POWER:
4243                 /* Upclock if more than 85% busy over 10ms */
4244                 ei_up = 10000;
4245                 threshold_up = 85;
4246
4247                 /* Downclock if less than 60% busy over 32ms */
4248                 ei_down = 32000;
4249                 threshold_down = 60;
4250                 break;
4251         }
4252
4253         I915_WRITE(GEN6_RP_UP_EI,
4254                 GT_INTERVAL_FROM_US(dev_priv, ei_up));
4255         I915_WRITE(GEN6_RP_UP_THRESHOLD,
4256                 GT_INTERVAL_FROM_US(dev_priv, (ei_up * threshold_up / 100)));
4257
4258         I915_WRITE(GEN6_RP_DOWN_EI,
4259                 GT_INTERVAL_FROM_US(dev_priv, ei_down));
4260         I915_WRITE(GEN6_RP_DOWN_THRESHOLD,
4261                 GT_INTERVAL_FROM_US(dev_priv, (ei_down * threshold_down / 100)));
4262
4263          I915_WRITE(GEN6_RP_CONTROL,
4264                     GEN6_RP_MEDIA_TURBO |
4265                     GEN6_RP_MEDIA_HW_NORMAL_MODE |
4266                     GEN6_RP_MEDIA_IS_GFX |
4267                     GEN6_RP_ENABLE |
4268                     GEN6_RP_UP_BUSY_AVG |
4269                     GEN6_RP_DOWN_IDLE_AVG);
4270
4271         dev_priv->rps.power = new_power;
4272         dev_priv->rps.up_threshold = threshold_up;
4273         dev_priv->rps.down_threshold = threshold_down;
4274         dev_priv->rps.last_adj = 0;
4275 }
4276
4277 static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
4278 {
4279         u32 mask = 0;
4280
4281         if (val > dev_priv->rps.min_freq_softlimit)
4282                 mask |= GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
4283         if (val < dev_priv->rps.max_freq_softlimit)
4284                 mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD;
4285
4286         mask &= dev_priv->pm_rps_events;
4287
4288         return gen6_sanitize_rps_pm_mask(dev_priv, ~mask);
4289 }
4290
4291 /* gen6_set_rps is called to update the frequency request, but should also be
4292  * called when the range (min_delay and max_delay) is modified so that we can
4293  * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
4294 static void gen6_set_rps(struct drm_device *dev, u8 val)
4295 {
4296         struct drm_i915_private *dev_priv = dev->dev_private;
4297
4298         /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
4299         if (IS_BXT_REVID(dev, 0, BXT_REVID_A1))
4300                 return;
4301
4302         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4303         WARN_ON(val > dev_priv->rps.max_freq);
4304         WARN_ON(val < dev_priv->rps.min_freq);
4305
4306         /* min/max delay may still have been modified so be sure to
4307          * write the limits value.
4308          */
4309         if (val != dev_priv->rps.cur_freq) {
4310                 gen6_set_rps_thresholds(dev_priv, val);
4311
4312                 if (IS_GEN9(dev))
4313                         I915_WRITE(GEN6_RPNSWREQ,
4314                                    GEN9_FREQUENCY(val));
4315                 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4316                         I915_WRITE(GEN6_RPNSWREQ,
4317                                    HSW_FREQUENCY(val));
4318                 else
4319                         I915_WRITE(GEN6_RPNSWREQ,
4320                                    GEN6_FREQUENCY(val) |
4321                                    GEN6_OFFSET(0) |
4322                                    GEN6_AGGRESSIVE_TURBO);
4323         }
4324
4325         /* Make sure we continue to get interrupts
4326          * until we hit the minimum or maximum frequencies.
4327          */
4328         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val));
4329         I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4330
4331         POSTING_READ(GEN6_RPNSWREQ);
4332
4333         dev_priv->rps.cur_freq = val;
4334         trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
4335 }
4336
4337 static void valleyview_set_rps(struct drm_device *dev, u8 val)
4338 {
4339         struct drm_i915_private *dev_priv = dev->dev_private;
4340
4341         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4342         WARN_ON(val > dev_priv->rps.max_freq);
4343         WARN_ON(val < dev_priv->rps.min_freq);
4344
4345         if (WARN_ONCE(IS_CHERRYVIEW(dev) && (val & 1),
4346                       "Odd GPU freq value\n"))
4347                 val &= ~1;
4348
4349         I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4350
4351         if (val != dev_priv->rps.cur_freq) {
4352                 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
4353                 if (!IS_CHERRYVIEW(dev_priv))
4354                         gen6_set_rps_thresholds(dev_priv, val);
4355         }
4356
4357         dev_priv->rps.cur_freq = val;
4358         trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
4359 }
4360
4361 /* vlv_set_rps_idle: Set the frequency to idle, if Gfx clocks are down
4362  *
4363  * * If Gfx is Idle, then
4364  * 1. Forcewake Media well.
4365  * 2. Request idle freq.
4366  * 3. Release Forcewake of Media well.
4367 */
4368 static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
4369 {
4370         u32 val = dev_priv->rps.idle_freq;
4371
4372         if (dev_priv->rps.cur_freq <= val)
4373                 return;
4374
4375         /* Wake up the media well, as that takes a lot less
4376          * power than the Render well. */
4377         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_MEDIA);
4378         valleyview_set_rps(dev_priv->dev, val);
4379         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA);
4380 }
4381
4382 void gen6_rps_busy(struct drm_i915_private *dev_priv)
4383 {
4384         mutex_lock(&dev_priv->rps.hw_lock);
4385         if (dev_priv->rps.enabled) {
4386                 if (dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED))
4387                         gen6_rps_reset_ei(dev_priv);
4388                 I915_WRITE(GEN6_PMINTRMSK,
4389                            gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
4390         }
4391         mutex_unlock(&dev_priv->rps.hw_lock);
4392 }
4393
4394 void gen6_rps_idle(struct drm_i915_private *dev_priv)
4395 {
4396         struct drm_device *dev = dev_priv->dev;
4397
4398         mutex_lock(&dev_priv->rps.hw_lock);
4399         if (dev_priv->rps.enabled) {
4400                 if (IS_VALLEYVIEW(dev))
4401                         vlv_set_rps_idle(dev_priv);
4402                 else
4403                         gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
4404                 dev_priv->rps.last_adj = 0;
4405                 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
4406         }
4407         mutex_unlock(&dev_priv->rps.hw_lock);
4408
4409         spin_lock(&dev_priv->rps.client_lock);
4410         while (!list_empty(&dev_priv->rps.clients))
4411                 list_del_init(dev_priv->rps.clients.next);
4412         spin_unlock(&dev_priv->rps.client_lock);
4413 }
4414
4415 void gen6_rps_boost(struct drm_i915_private *dev_priv,
4416                     struct intel_rps_client *rps,
4417                     unsigned long submitted)
4418 {
4419         /* This is intentionally racy! We peek at the state here, then
4420          * validate inside the RPS worker.
4421          */
4422         if (!(dev_priv->mm.busy &&
4423               dev_priv->rps.enabled &&
4424               dev_priv->rps.cur_freq < dev_priv->rps.max_freq_softlimit))
4425                 return;
4426
4427         /* Force a RPS boost (and don't count it against the client) if
4428          * the GPU is severely congested.
4429          */
4430         if (rps && time_after(jiffies, submitted + DRM_I915_THROTTLE_JIFFIES))
4431                 rps = NULL;
4432
4433         spin_lock(&dev_priv->rps.client_lock);
4434         if (rps == NULL || list_empty(&rps->link)) {
4435                 spin_lock_irq(&dev_priv->irq_lock);
4436                 if (dev_priv->rps.interrupts_enabled) {
4437                         dev_priv->rps.client_boost = true;
4438                         queue_work(dev_priv->wq, &dev_priv->rps.work);
4439                 }
4440                 spin_unlock_irq(&dev_priv->irq_lock);
4441
4442                 if (rps != NULL) {
4443                         list_add(&rps->link, &dev_priv->rps.clients);
4444                         rps->boosts++;
4445                 } else
4446                         dev_priv->rps.boosts++;
4447         }
4448         spin_unlock(&dev_priv->rps.client_lock);
4449 }
4450
4451 void intel_set_rps(struct drm_device *dev, u8 val)
4452 {
4453         if (IS_VALLEYVIEW(dev))
4454                 valleyview_set_rps(dev, val);
4455         else
4456                 gen6_set_rps(dev, val);
4457 }
4458
4459 static void gen9_disable_rps(struct drm_device *dev)
4460 {
4461         struct drm_i915_private *dev_priv = dev->dev_private;
4462
4463         I915_WRITE(GEN6_RC_CONTROL, 0);
4464         I915_WRITE(GEN9_PG_ENABLE, 0);
4465 }
4466
4467 static void gen6_disable_rps(struct drm_device *dev)
4468 {
4469         struct drm_i915_private *dev_priv = dev->dev_private;
4470
4471         I915_WRITE(GEN6_RC_CONTROL, 0);
4472         I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
4473 }
4474
4475 static void cherryview_disable_rps(struct drm_device *dev)
4476 {
4477         struct drm_i915_private *dev_priv = dev->dev_private;
4478
4479         I915_WRITE(GEN6_RC_CONTROL, 0);
4480 }
4481
4482 static void valleyview_disable_rps(struct drm_device *dev)
4483 {
4484         struct drm_i915_private *dev_priv = dev->dev_private;
4485
4486         /* we're doing forcewake before Disabling RC6,
4487          * This what the BIOS expects when going into suspend */
4488         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4489
4490         I915_WRITE(GEN6_RC_CONTROL, 0);
4491
4492         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4493 }
4494
4495 static void intel_print_rc6_info(struct drm_device *dev, u32 mode)
4496 {
4497         if (IS_VALLEYVIEW(dev)) {
4498                 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
4499                         mode = GEN6_RC_CTL_RC6_ENABLE;
4500                 else
4501                         mode = 0;
4502         }
4503         if (HAS_RC6p(dev))
4504                 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s RC6p %s RC6pp %s\n",
4505                               (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
4506                               (mode & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
4507                               (mode & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
4508
4509         else
4510                 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s\n",
4511                               (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off");
4512 }
4513
4514 static int sanitize_rc6_option(const struct drm_device *dev, int enable_rc6)
4515 {
4516         /* No RC6 before Ironlake and code is gone for ilk. */
4517         if (INTEL_INFO(dev)->gen < 6)
4518                 return 0;
4519
4520         /* Respect the kernel parameter if it is set */
4521         if (enable_rc6 >= 0) {
4522                 int mask;
4523
4524                 if (HAS_RC6p(dev))
4525                         mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
4526                                INTEL_RC6pp_ENABLE;
4527                 else
4528                         mask = INTEL_RC6_ENABLE;
4529
4530                 if ((enable_rc6 & mask) != enable_rc6)
4531                         DRM_DEBUG_KMS("Adjusting RC6 mask to %d (requested %d, valid %d)\n",
4532                                       enable_rc6 & mask, enable_rc6, mask);
4533
4534                 return enable_rc6 & mask;
4535         }
4536
4537         if (IS_IVYBRIDGE(dev))
4538                 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
4539
4540         return INTEL_RC6_ENABLE;
4541 }
4542
4543 int intel_enable_rc6(const struct drm_device *dev)
4544 {
4545         return i915.enable_rc6;
4546 }
4547
4548 static void gen6_init_rps_frequencies(struct drm_device *dev)
4549 {
4550         struct drm_i915_private *dev_priv = dev->dev_private;
4551         uint32_t rp_state_cap;
4552         u32 ddcc_status = 0;
4553         int ret;
4554
4555         /* All of these values are in units of 50MHz */
4556         dev_priv->rps.cur_freq          = 0;
4557         /* static values from HW: RP0 > RP1 > RPn (min_freq) */
4558         if (IS_BROXTON(dev)) {
4559                 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
4560                 dev_priv->rps.rp0_freq = (rp_state_cap >> 16) & 0xff;
4561                 dev_priv->rps.rp1_freq = (rp_state_cap >>  8) & 0xff;
4562                 dev_priv->rps.min_freq = (rp_state_cap >>  0) & 0xff;
4563         } else {
4564                 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
4565                 dev_priv->rps.rp0_freq = (rp_state_cap >>  0) & 0xff;
4566                 dev_priv->rps.rp1_freq = (rp_state_cap >>  8) & 0xff;
4567                 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
4568         }
4569
4570         /* hw_max = RP0 until we check for overclocking */
4571         dev_priv->rps.max_freq          = dev_priv->rps.rp0_freq;
4572
4573         dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
4574         if (IS_HASWELL(dev) || IS_BROADWELL(dev) ||
4575             IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
4576                 ret = sandybridge_pcode_read(dev_priv,
4577                                         HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
4578                                         &ddcc_status);
4579                 if (0 == ret)
4580                         dev_priv->rps.efficient_freq =
4581                                 clamp_t(u8,
4582                                         ((ddcc_status >> 8) & 0xff),
4583                                         dev_priv->rps.min_freq,
4584                                         dev_priv->rps.max_freq);
4585         }
4586
4587         if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
4588                 /* Store the frequency values in 16.66 MHZ units, which is
4589                    the natural hardware unit for SKL */
4590                 dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER;
4591                 dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER;
4592                 dev_priv->rps.min_freq *= GEN9_FREQ_SCALER;
4593                 dev_priv->rps.max_freq *= GEN9_FREQ_SCALER;
4594                 dev_priv->rps.efficient_freq *= GEN9_FREQ_SCALER;
4595         }
4596
4597         dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
4598
4599         /* Preserve min/max settings in case of re-init */
4600         if (dev_priv->rps.max_freq_softlimit == 0)
4601                 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
4602
4603         if (dev_priv->rps.min_freq_softlimit == 0) {
4604                 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4605                         dev_priv->rps.min_freq_softlimit =
4606                                 max_t(int, dev_priv->rps.efficient_freq,
4607                                       intel_freq_opcode(dev_priv, 450));
4608                 else
4609                         dev_priv->rps.min_freq_softlimit =
4610                                 dev_priv->rps.min_freq;
4611         }
4612 }
4613
4614 /* See the Gen9_GT_PM_Programming_Guide doc for the below */
4615 static void gen9_enable_rps(struct drm_device *dev)
4616 {
4617         struct drm_i915_private *dev_priv = dev->dev_private;
4618
4619         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4620
4621         gen6_init_rps_frequencies(dev);
4622
4623         /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
4624         if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
4625                 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4626                 return;
4627         }
4628
4629         /* Program defaults and thresholds for RPS*/
4630         I915_WRITE(GEN6_RC_VIDEO_FREQ,
4631                 GEN9_FREQUENCY(dev_priv->rps.rp1_freq));
4632
4633         /* 1 second timeout*/
4634         I915_WRITE(GEN6_RP_DOWN_TIMEOUT,
4635                 GT_INTERVAL_FROM_US(dev_priv, 1000000));
4636
4637         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa);
4638
4639         /* Leaning on the below call to gen6_set_rps to program/setup the
4640          * Up/Down EI & threshold registers, as well as the RP_CONTROL,
4641          * RP_INTERRUPT_LIMITS & RPNSWREQ registers */
4642         dev_priv->rps.power = HIGH_POWER; /* force a reset */
4643         gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
4644
4645         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4646 }
4647
4648 static void gen9_enable_rc6(struct drm_device *dev)
4649 {
4650         struct drm_i915_private *dev_priv = dev->dev_private;
4651         struct intel_engine_cs *ring;
4652         uint32_t rc6_mask = 0;
4653         int unused;
4654
4655         /* 1a: Software RC state - RC0 */
4656         I915_WRITE(GEN6_RC_STATE, 0);
4657
4658         /* 1b: Get forcewake during program sequence. Although the driver
4659          * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
4660         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4661
4662         /* 2a: Disable RC states. */
4663         I915_WRITE(GEN6_RC_CONTROL, 0);
4664
4665         /* 2b: Program RC6 thresholds.*/
4666
4667         /* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */
4668         if (IS_SKYLAKE(dev) && !((IS_SKL_GT3(dev) || IS_SKL_GT4(dev)) &&
4669                                  IS_SKL_REVID(dev, 0, SKL_REVID_E0)))
4670                 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16);
4671         else
4672                 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
4673         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4674         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4675         for_each_ring(ring, dev_priv, unused)
4676                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4677
4678         if (HAS_GUC_UCODE(dev))
4679                 I915_WRITE(GUC_MAX_IDLE_COUNT, 0xA);
4680
4681         I915_WRITE(GEN6_RC_SLEEP, 0);
4682
4683         /* 2c: Program Coarse Power Gating Policies. */
4684         I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25);
4685         I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25);
4686
4687         /* 3a: Enable RC6 */
4688         if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4689                 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
4690         DRM_INFO("RC6 %s\n", (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
4691                         "on" : "off");
4692         /* WaRsUseTimeoutMode */
4693         if (IS_SKL_REVID(dev, 0, SKL_REVID_D0) ||
4694             IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
4695                 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us */
4696                 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4697                            GEN7_RC_CTL_TO_MODE |
4698                            rc6_mask);
4699         } else {
4700                 I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
4701                 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4702                            GEN6_RC_CTL_EI_MODE(1) |
4703                            rc6_mask);
4704         }
4705
4706         /*
4707          * 3b: Enable Coarse Power Gating only when RC6 is enabled.
4708          * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6.
4709          */
4710         if (IS_BXT_REVID(dev, 0, BXT_REVID_A1) ||
4711             ((IS_SKL_GT3(dev) || IS_SKL_GT4(dev)) &&
4712              IS_SKL_REVID(dev, 0, SKL_REVID_E0)))
4713                 I915_WRITE(GEN9_PG_ENABLE, 0);
4714         else
4715                 I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
4716                                 (GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0);
4717
4718         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4719
4720 }
4721
4722 static void gen8_enable_rps(struct drm_device *dev)
4723 {
4724         struct drm_i915_private *dev_priv = dev->dev_private;
4725         struct intel_engine_cs *ring;
4726         uint32_t rc6_mask = 0;
4727         int unused;
4728
4729         /* 1a: Software RC state - RC0 */
4730         I915_WRITE(GEN6_RC_STATE, 0);
4731
4732         /* 1c & 1d: Get forcewake during program sequence. Although the driver
4733          * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
4734         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4735
4736         /* 2a: Disable RC states. */
4737         I915_WRITE(GEN6_RC_CONTROL, 0);
4738
4739         /* Initialize rps frequencies */
4740         gen6_init_rps_frequencies(dev);
4741
4742         /* 2b: Program RC6 thresholds.*/
4743         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
4744         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4745         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4746         for_each_ring(ring, dev_priv, unused)
4747                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4748         I915_WRITE(GEN6_RC_SLEEP, 0);
4749         if (IS_BROADWELL(dev))
4750                 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
4751         else
4752                 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
4753
4754         /* 3: Enable RC6 */
4755         if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4756                 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
4757         intel_print_rc6_info(dev, rc6_mask);
4758         if (IS_BROADWELL(dev))
4759                 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4760                                 GEN7_RC_CTL_TO_MODE |
4761                                 rc6_mask);
4762         else
4763                 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4764                                 GEN6_RC_CTL_EI_MODE(1) |
4765                                 rc6_mask);
4766
4767         /* 4 Program defaults and thresholds for RPS*/
4768         I915_WRITE(GEN6_RPNSWREQ,
4769                    HSW_FREQUENCY(dev_priv->rps.rp1_freq));
4770         I915_WRITE(GEN6_RC_VIDEO_FREQ,
4771                    HSW_FREQUENCY(dev_priv->rps.rp1_freq));
4772         /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
4773         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
4774
4775         /* Docs recommend 900MHz, and 300 MHz respectively */
4776         I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
4777                    dev_priv->rps.max_freq_softlimit << 24 |
4778                    dev_priv->rps.min_freq_softlimit << 16);
4779
4780         I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
4781         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
4782         I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
4783         I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
4784
4785         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
4786
4787         /* 5: Enable RPS */
4788         I915_WRITE(GEN6_RP_CONTROL,
4789                    GEN6_RP_MEDIA_TURBO |
4790                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
4791                    GEN6_RP_MEDIA_IS_GFX |
4792                    GEN6_RP_ENABLE |
4793                    GEN6_RP_UP_BUSY_AVG |
4794                    GEN6_RP_DOWN_IDLE_AVG);
4795
4796         /* 6: Ring frequency + overclocking (our driver does this later */
4797
4798         dev_priv->rps.power = HIGH_POWER; /* force a reset */
4799         gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
4800
4801         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4802 }
4803
4804 static void gen6_enable_rps(struct drm_device *dev)
4805 {
4806         struct drm_i915_private *dev_priv = dev->dev_private;
4807         struct intel_engine_cs *ring;
4808         u32 rc6vids, pcu_mbox = 0, rc6_mask = 0;
4809         u32 gtfifodbg;
4810         int rc6_mode;
4811         int i, ret;
4812
4813         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4814
4815         /* Here begins a magic sequence of register writes to enable
4816          * auto-downclocking.
4817          *
4818          * Perhaps there might be some value in exposing these to
4819          * userspace...
4820          */
4821         I915_WRITE(GEN6_RC_STATE, 0);
4822
4823         /* Clear the DBG now so we don't confuse earlier errors */
4824         if ((gtfifodbg = I915_READ(GTFIFODBG))) {
4825                 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
4826                 I915_WRITE(GTFIFODBG, gtfifodbg);
4827         }
4828
4829         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4830
4831         /* Initialize rps frequencies */
4832         gen6_init_rps_frequencies(dev);
4833
4834         /* disable the counters and set deterministic thresholds */
4835         I915_WRITE(GEN6_RC_CONTROL, 0);
4836
4837         I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
4838         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
4839         I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
4840         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
4841         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
4842
4843         for_each_ring(ring, dev_priv, i)
4844                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4845
4846         I915_WRITE(GEN6_RC_SLEEP, 0);
4847         I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
4848         if (IS_IVYBRIDGE(dev))
4849                 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
4850         else
4851                 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
4852         I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
4853         I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
4854
4855         /* Check if we are enabling RC6 */
4856         rc6_mode = intel_enable_rc6(dev_priv->dev);
4857         if (rc6_mode & INTEL_RC6_ENABLE)
4858                 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
4859
4860         /* We don't use those on Haswell */
4861         if (!IS_HASWELL(dev)) {
4862                 if (rc6_mode & INTEL_RC6p_ENABLE)
4863                         rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
4864
4865                 if (rc6_mode & INTEL_RC6pp_ENABLE)
4866                         rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
4867         }
4868
4869         intel_print_rc6_info(dev, rc6_mask);
4870
4871         I915_WRITE(GEN6_RC_CONTROL,
4872                    rc6_mask |
4873                    GEN6_RC_CTL_EI_MODE(1) |
4874                    GEN6_RC_CTL_HW_ENABLE);
4875
4876         /* Power down if completely idle for over 50ms */
4877         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
4878         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
4879
4880         ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
4881         if (ret)
4882                 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
4883
4884         ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
4885         if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
4886                 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
4887                                  (dev_priv->rps.max_freq_softlimit & 0xff) * 50,
4888                                  (pcu_mbox & 0xff) * 50);
4889                 dev_priv->rps.max_freq = pcu_mbox & 0xff;
4890         }
4891
4892         dev_priv->rps.power = HIGH_POWER; /* force a reset */
4893         gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
4894
4895         rc6vids = 0;
4896         ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
4897         if (IS_GEN6(dev) && ret) {
4898                 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
4899         } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
4900                 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
4901                           GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
4902                 rc6vids &= 0xffff00;
4903                 rc6vids |= GEN6_ENCODE_RC6_VID(450);
4904                 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
4905                 if (ret)
4906                         DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
4907         }
4908
4909         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4910 }
4911
4912 static void __gen6_update_ring_freq(struct drm_device *dev)
4913 {
4914         struct drm_i915_private *dev_priv = dev->dev_private;
4915         int min_freq = 15;
4916         unsigned int gpu_freq;
4917         unsigned int max_ia_freq, min_ring_freq;
4918         unsigned int max_gpu_freq, min_gpu_freq;
4919         int scaling_factor = 180;
4920         struct cpufreq_policy *policy;
4921
4922         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4923
4924         policy = cpufreq_cpu_get(0);
4925         if (policy) {
4926                 max_ia_freq = policy->cpuinfo.max_freq;
4927                 cpufreq_cpu_put(policy);
4928         } else {
4929                 /*
4930                  * Default to measured freq if none found, PCU will ensure we
4931                  * don't go over
4932                  */
4933                 max_ia_freq = tsc_khz;
4934         }
4935
4936         /* Convert from kHz to MHz */
4937         max_ia_freq /= 1000;
4938
4939         min_ring_freq = I915_READ(DCLK) & 0xf;
4940         /* convert DDR frequency from units of 266.6MHz to bandwidth */
4941         min_ring_freq = mult_frac(min_ring_freq, 8, 3);
4942
4943         if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
4944                 /* Convert GT frequency to 50 HZ units */
4945                 min_gpu_freq = dev_priv->rps.min_freq / GEN9_FREQ_SCALER;
4946                 max_gpu_freq = dev_priv->rps.max_freq / GEN9_FREQ_SCALER;
4947         } else {
4948                 min_gpu_freq = dev_priv->rps.min_freq;
4949                 max_gpu_freq = dev_priv->rps.max_freq;
4950         }
4951
4952         /*
4953          * For each potential GPU frequency, load a ring frequency we'd like
4954          * to use for memory access.  We do this by specifying the IA frequency
4955          * the PCU should use as a reference to determine the ring frequency.
4956          */
4957         for (gpu_freq = max_gpu_freq; gpu_freq >= min_gpu_freq; gpu_freq--) {
4958                 int diff = max_gpu_freq - gpu_freq;
4959                 unsigned int ia_freq = 0, ring_freq = 0;
4960
4961                 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
4962                         /*
4963                          * ring_freq = 2 * GT. ring_freq is in 100MHz units
4964                          * No floor required for ring frequency on SKL.
4965                          */
4966                         ring_freq = gpu_freq;
4967                 } else if (INTEL_INFO(dev)->gen >= 8) {
4968                         /* max(2 * GT, DDR). NB: GT is 50MHz units */
4969                         ring_freq = max(min_ring_freq, gpu_freq);
4970                 } else if (IS_HASWELL(dev)) {
4971                         ring_freq = mult_frac(gpu_freq, 5, 4);
4972                         ring_freq = max(min_ring_freq, ring_freq);
4973                         /* leave ia_freq as the default, chosen by cpufreq */
4974                 } else {
4975                         /* On older processors, there is no separate ring
4976                          * clock domain, so in order to boost the bandwidth
4977                          * of the ring, we need to upclock the CPU (ia_freq).
4978                          *
4979                          * For GPU frequencies less than 750MHz,
4980                          * just use the lowest ring freq.
4981                          */
4982                         if (gpu_freq < min_freq)
4983                                 ia_freq = 800;
4984                         else
4985                                 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
4986                         ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
4987                 }
4988
4989                 sandybridge_pcode_write(dev_priv,
4990                                         GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
4991                                         ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
4992                                         ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
4993                                         gpu_freq);
4994         }
4995 }
4996
4997 void gen6_update_ring_freq(struct drm_device *dev)
4998 {
4999         struct drm_i915_private *dev_priv = dev->dev_private;
5000
5001         if (!HAS_CORE_RING_FREQ(dev))
5002                 return;
5003
5004         mutex_lock(&dev_priv->rps.hw_lock);
5005         __gen6_update_ring_freq(dev);
5006         mutex_unlock(&dev_priv->rps.hw_lock);
5007 }
5008
5009 static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
5010 {
5011         struct drm_device *dev = dev_priv->dev;
5012         u32 val, rp0;
5013
5014         val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5015
5016         switch (INTEL_INFO(dev)->eu_total) {
5017         case 8:
5018                 /* (2 * 4) config */
5019                 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
5020                 break;
5021         case 12:
5022                 /* (2 * 6) config */
5023                 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT);
5024                 break;
5025         case 16:
5026                 /* (2 * 8) config */
5027         default:
5028                 /* Setting (2 * 8) Min RP0 for any other combination */
5029                 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT);
5030                 break;
5031         }
5032
5033         rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK);
5034
5035         return rp0;
5036 }
5037
5038 static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5039 {
5040         u32 val, rpe;
5041
5042         val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
5043         rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
5044
5045         return rpe;
5046 }
5047
5048 static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
5049 {
5050         u32 val, rp1;
5051
5052         val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5053         rp1 = (val & FB_GFX_FREQ_FUSE_MASK);
5054
5055         return rp1;
5056 }
5057
5058 static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
5059 {
5060         u32 val, rp1;
5061
5062         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5063
5064         rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
5065
5066         return rp1;
5067 }
5068
5069 static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
5070 {
5071         u32 val, rp0;
5072
5073         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5074
5075         rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
5076         /* Clamp to max */
5077         rp0 = min_t(u32, rp0, 0xea);
5078
5079         return rp0;
5080 }
5081
5082 static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5083 {
5084         u32 val, rpe;
5085
5086         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
5087         rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
5088         val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
5089         rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
5090
5091         return rpe;
5092 }
5093
5094 static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
5095 {
5096         return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
5097 }
5098
5099 /* Check that the pctx buffer wasn't move under us. */
5100 static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
5101 {
5102         unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5103
5104         WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
5105                              dev_priv->vlv_pctx->stolen->start);
5106 }
5107
5108
5109 /* Check that the pcbr address is not empty. */
5110 static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
5111 {
5112         unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5113
5114         WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
5115 }
5116
5117 static void cherryview_setup_pctx(struct drm_device *dev)
5118 {
5119         struct drm_i915_private *dev_priv = dev->dev_private;
5120         unsigned long pctx_paddr, paddr;
5121         struct i915_gtt *gtt = &dev_priv->gtt;
5122         u32 pcbr;
5123         int pctx_size = 32*1024;
5124
5125         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
5126
5127         pcbr = I915_READ(VLV_PCBR);
5128         if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
5129                 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5130                 paddr = (dev_priv->mm.stolen_base +
5131                          (gtt->stolen_size - pctx_size));
5132
5133                 pctx_paddr = (paddr & (~4095));
5134                 I915_WRITE(VLV_PCBR, pctx_paddr);
5135         }
5136
5137         DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
5138 }
5139
5140 static void valleyview_setup_pctx(struct drm_device *dev)
5141 {
5142         struct drm_i915_private *dev_priv = dev->dev_private;
5143         struct drm_i915_gem_object *pctx;
5144         unsigned long pctx_paddr;
5145         u32 pcbr;
5146         int pctx_size = 24*1024;
5147
5148         WARN_ON(!mutex_is_locked(&dev->struct_mutex));
5149
5150         pcbr = I915_READ(VLV_PCBR);
5151         if (pcbr) {
5152                 /* BIOS set it up already, grab the pre-alloc'd space */
5153                 int pcbr_offset;
5154
5155                 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
5156                 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
5157                                                                       pcbr_offset,
5158                                                                       I915_GTT_OFFSET_NONE,
5159                                                                       pctx_size);
5160                 goto out;
5161         }
5162
5163         DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5164
5165         /*
5166          * From the Gunit register HAS:
5167          * The Gfx driver is expected to program this register and ensure
5168          * proper allocation within Gfx stolen memory.  For example, this
5169          * register should be programmed such than the PCBR range does not
5170          * overlap with other ranges, such as the frame buffer, protected
5171          * memory, or any other relevant ranges.
5172          */
5173         pctx = i915_gem_object_create_stolen(dev, pctx_size);
5174         if (!pctx) {
5175                 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
5176                 return;
5177         }
5178
5179         pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
5180         I915_WRITE(VLV_PCBR, pctx_paddr);
5181
5182 out:
5183         DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
5184         dev_priv->vlv_pctx = pctx;
5185 }
5186
5187 static void valleyview_cleanup_pctx(struct drm_device *dev)
5188 {
5189         struct drm_i915_private *dev_priv = dev->dev_private;
5190
5191         if (WARN_ON(!dev_priv->vlv_pctx))
5192                 return;
5193
5194         drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
5195         dev_priv->vlv_pctx = NULL;
5196 }
5197
5198 static void valleyview_init_gt_powersave(struct drm_device *dev)
5199 {
5200         struct drm_i915_private *dev_priv = dev->dev_private;
5201         u32 val;
5202
5203         valleyview_setup_pctx(dev);
5204
5205         mutex_lock(&dev_priv->rps.hw_lock);
5206
5207         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5208         switch ((val >> 6) & 3) {
5209         case 0:
5210         case 1:
5211                 dev_priv->mem_freq = 800;
5212                 break;
5213         case 2:
5214                 dev_priv->mem_freq = 1066;
5215                 break;
5216         case 3:
5217                 dev_priv->mem_freq = 1333;
5218                 break;
5219         }
5220         DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
5221
5222         dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
5223         dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5224         DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
5225                          intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
5226                          dev_priv->rps.max_freq);
5227
5228         dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
5229         DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
5230                          intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5231                          dev_priv->rps.efficient_freq);
5232
5233         dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
5234         DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
5235                          intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
5236                          dev_priv->rps.rp1_freq);
5237
5238         dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
5239         DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
5240                          intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
5241                          dev_priv->rps.min_freq);
5242
5243         dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
5244
5245         /* Preserve min/max settings in case of re-init */
5246         if (dev_priv->rps.max_freq_softlimit == 0)
5247                 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
5248
5249         if (dev_priv->rps.min_freq_softlimit == 0)
5250                 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
5251
5252         mutex_unlock(&dev_priv->rps.hw_lock);
5253 }
5254
5255 static void cherryview_init_gt_powersave(struct drm_device *dev)
5256 {
5257         struct drm_i915_private *dev_priv = dev->dev_private;
5258         u32 val;
5259
5260         cherryview_setup_pctx(dev);
5261
5262         mutex_lock(&dev_priv->rps.hw_lock);
5263
5264         mutex_lock(&dev_priv->sb_lock);
5265         val = vlv_cck_read(dev_priv, CCK_FUSE_REG);
5266         mutex_unlock(&dev_priv->sb_lock);
5267
5268         switch ((val >> 2) & 0x7) {
5269         case 3:
5270                 dev_priv->mem_freq = 2000;
5271                 break;
5272         default:
5273                 dev_priv->mem_freq = 1600;
5274                 break;
5275         }
5276         DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
5277
5278         dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
5279         dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5280         DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
5281                          intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
5282                          dev_priv->rps.max_freq);
5283
5284         dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
5285         DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
5286                          intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5287                          dev_priv->rps.efficient_freq);
5288
5289         dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
5290         DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
5291                          intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
5292                          dev_priv->rps.rp1_freq);
5293
5294         /* PUnit validated range is only [RPe, RP0] */
5295         dev_priv->rps.min_freq = dev_priv->rps.efficient_freq;
5296         DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
5297                          intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
5298                          dev_priv->rps.min_freq);
5299
5300         WARN_ONCE((dev_priv->rps.max_freq |
5301                    dev_priv->rps.efficient_freq |
5302                    dev_priv->rps.rp1_freq |
5303                    dev_priv->rps.min_freq) & 1,
5304                   "Odd GPU freq values\n");
5305
5306         dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
5307
5308         /* Preserve min/max settings in case of re-init */
5309         if (dev_priv->rps.max_freq_softlimit == 0)
5310                 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
5311
5312         if (dev_priv->rps.min_freq_softlimit == 0)
5313                 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
5314
5315         mutex_unlock(&dev_priv->rps.hw_lock);
5316 }
5317
5318 static void valleyview_cleanup_gt_powersave(struct drm_device *dev)
5319 {
5320         valleyview_cleanup_pctx(dev);
5321 }
5322
5323 static void cherryview_enable_rps(struct drm_device *dev)
5324 {
5325         struct drm_i915_private *dev_priv = dev->dev_private;
5326         struct intel_engine_cs *ring;
5327         u32 gtfifodbg, val, rc6_mode = 0, pcbr;
5328         int i;
5329
5330         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5331
5332         gtfifodbg = I915_READ(GTFIFODBG);
5333         if (gtfifodbg) {
5334                 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5335                                  gtfifodbg);
5336                 I915_WRITE(GTFIFODBG, gtfifodbg);
5337         }
5338
5339         cherryview_check_pctx(dev_priv);
5340
5341         /* 1a & 1b: Get forcewake during program sequence. Although the driver
5342          * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
5343         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5344
5345         /*  Disable RC states. */
5346         I915_WRITE(GEN6_RC_CONTROL, 0);
5347
5348         /* 2a: Program RC6 thresholds.*/
5349         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
5350         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5351         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
5352
5353         for_each_ring(ring, dev_priv, i)
5354                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
5355         I915_WRITE(GEN6_RC_SLEEP, 0);
5356
5357         /* TO threshold set to 500 us ( 0x186 * 1.28 us) */
5358         I915_WRITE(GEN6_RC6_THRESHOLD, 0x186);
5359
5360         /* allows RC6 residency counter to work */
5361         I915_WRITE(VLV_COUNTER_CONTROL,
5362                    _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
5363                                       VLV_MEDIA_RC6_COUNT_EN |
5364                                       VLV_RENDER_RC6_COUNT_EN));
5365
5366         /* For now we assume BIOS is allocating and populating the PCBR  */
5367         pcbr = I915_READ(VLV_PCBR);
5368
5369         /* 3: Enable RC6 */
5370         if ((intel_enable_rc6(dev) & INTEL_RC6_ENABLE) &&
5371                                                 (pcbr >> VLV_PCBR_ADDR_SHIFT))
5372                 rc6_mode = GEN7_RC_CTL_TO_MODE;
5373
5374         I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
5375
5376         /* 4 Program defaults and thresholds for RPS*/
5377         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
5378         I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5379         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5380         I915_WRITE(GEN6_RP_UP_EI, 66000);
5381         I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5382
5383         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5384
5385         /* 5: Enable RPS */
5386         I915_WRITE(GEN6_RP_CONTROL,
5387                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
5388                    GEN6_RP_MEDIA_IS_GFX |
5389                    GEN6_RP_ENABLE |
5390                    GEN6_RP_UP_BUSY_AVG |
5391                    GEN6_RP_DOWN_IDLE_AVG);
5392
5393         /* Setting Fixed Bias */
5394         val = VLV_OVERRIDE_EN |
5395                   VLV_SOC_TDP_EN |
5396                   CHV_BIAS_CPU_50_SOC_50;
5397         vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
5398
5399         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5400
5401         /* RPS code assumes GPLL is used */
5402         WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
5403
5404         DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
5405         DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
5406
5407         dev_priv->rps.cur_freq = (val >> 8) & 0xff;
5408         DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
5409                          intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
5410                          dev_priv->rps.cur_freq);
5411
5412         DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
5413                          intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5414                          dev_priv->rps.efficient_freq);
5415
5416         valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
5417
5418         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5419 }
5420
5421 static void valleyview_enable_rps(struct drm_device *dev)
5422 {
5423         struct drm_i915_private *dev_priv = dev->dev_private;
5424         struct intel_engine_cs *ring;
5425         u32 gtfifodbg, val, rc6_mode = 0;
5426         int i;
5427
5428         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5429
5430         valleyview_check_pctx(dev_priv);
5431
5432         if ((gtfifodbg = I915_READ(GTFIFODBG))) {
5433                 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5434                                  gtfifodbg);
5435                 I915_WRITE(GTFIFODBG, gtfifodbg);
5436         }
5437
5438         /* If VLV, Forcewake all wells, else re-direct to regular path */
5439         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5440
5441         /*  Disable RC states. */
5442         I915_WRITE(GEN6_RC_CONTROL, 0);
5443
5444         I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
5445         I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5446         I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5447         I915_WRITE(GEN6_RP_UP_EI, 66000);
5448         I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5449
5450         I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5451
5452         I915_WRITE(GEN6_RP_CONTROL,
5453                    GEN6_RP_MEDIA_TURBO |
5454                    GEN6_RP_MEDIA_HW_NORMAL_MODE |
5455                    GEN6_RP_MEDIA_IS_GFX |
5456                    GEN6_RP_ENABLE |
5457                    GEN6_RP_UP_BUSY_AVG |
5458                    GEN6_RP_DOWN_IDLE_CONT);
5459
5460         I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
5461         I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
5462         I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
5463
5464         for_each_ring(ring, dev_priv, i)
5465                 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
5466
5467         I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
5468
5469         /* allows RC6 residency counter to work */
5470         I915_WRITE(VLV_COUNTER_CONTROL,
5471                    _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN |
5472                                       VLV_RENDER_RC0_COUNT_EN |
5473                                       VLV_MEDIA_RC6_COUNT_EN |
5474                                       VLV_RENDER_RC6_COUNT_EN));
5475
5476         if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
5477                 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
5478
5479         intel_print_rc6_info(dev, rc6_mode);
5480
5481         I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
5482
5483         /* Setting Fixed Bias */
5484         val = VLV_OVERRIDE_EN |
5485                   VLV_SOC_TDP_EN |
5486                   VLV_BIAS_CPU_125_SOC_875;
5487         vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
5488
5489         val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5490
5491         /* RPS code assumes GPLL is used */
5492         WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
5493
5494         DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
5495         DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
5496
5497         dev_priv->rps.cur_freq = (val >> 8) & 0xff;
5498         DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
5499                          intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
5500                          dev_priv->rps.cur_freq);
5501
5502         DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
5503                          intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
5504                          dev_priv->rps.efficient_freq);
5505
5506         valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
5507
5508         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5509 }
5510
5511 static unsigned long intel_pxfreq(u32 vidfreq)
5512 {
5513         unsigned long freq;
5514         int div = (vidfreq & 0x3f0000) >> 16;
5515         int post = (vidfreq & 0x3000) >> 12;
5516         int pre = (vidfreq & 0x7);
5517
5518         if (!pre)
5519                 return 0;
5520
5521         freq = ((div * 133333) / ((1<<post) * pre));
5522
5523         return freq;
5524 }
5525
5526 static const struct cparams {
5527         u16 i;
5528         u16 t;
5529         u16 m;
5530         u16 c;
5531 } cparams[] = {
5532         { 1, 1333, 301, 28664 },
5533         { 1, 1066, 294, 24460 },
5534         { 1, 800, 294, 25192 },
5535         { 0, 1333, 276, 27605 },
5536         { 0, 1066, 276, 27605 },
5537         { 0, 800, 231, 23784 },
5538 };
5539
5540 static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
5541 {
5542         u64 total_count, diff, ret;
5543         u32 count1, count2, count3, m = 0, c = 0;
5544         unsigned long now = jiffies_to_msecs(jiffies), diff1;
5545         int i;
5546
5547         assert_spin_locked(&mchdev_lock);
5548
5549         diff1 = now - dev_priv->ips.last_time1;
5550
5551         /* Prevent division-by-zero if we are asking too fast.
5552          * Also, we don't get interesting results if we are polling
5553          * faster than once in 10ms, so just return the saved value
5554          * in such cases.
5555          */
5556         if (diff1 <= 10)
5557                 return dev_priv->ips.chipset_power;
5558
5559         count1 = I915_READ(DMIEC);
5560         count2 = I915_READ(DDREC);
5561         count3 = I915_READ(CSIEC);
5562
5563         total_count = count1 + count2 + count3;
5564
5565         /* FIXME: handle per-counter overflow */
5566         if (total_count < dev_priv->ips.last_count1) {
5567                 diff = ~0UL - dev_priv->ips.last_count1;
5568                 diff += total_count;
5569         } else {
5570                 diff = total_count - dev_priv->ips.last_count1;
5571         }
5572
5573         for (i = 0; i < ARRAY_SIZE(cparams); i++) {
5574                 if (cparams[i].i == dev_priv->ips.c_m &&
5575                     cparams[i].t == dev_priv->ips.r_t) {
5576                         m = cparams[i].m;
5577                         c = cparams[i].c;
5578                         break;
5579                 }
5580         }
5581
5582         diff = div_u64(diff, diff1);
5583         ret = ((m * diff) + c);
5584         ret = div_u64(ret, 10);
5585
5586         dev_priv->ips.last_count1 = total_count;
5587         dev_priv->ips.last_time1 = now;
5588
5589         dev_priv->ips.chipset_power = ret;
5590
5591         return ret;
5592 }
5593
5594 unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
5595 {
5596         struct drm_device *dev = dev_priv->dev;
5597         unsigned long val;
5598
5599         if (INTEL_INFO(dev)->gen != 5)
5600                 return 0;
5601
5602         spin_lock_irq(&mchdev_lock);
5603
5604         val = __i915_chipset_val(dev_priv);
5605
5606         spin_unlock_irq(&mchdev_lock);
5607
5608         return val;
5609 }
5610
5611 unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
5612 {
5613         unsigned long m, x, b;
5614         u32 tsfs;
5615
5616         tsfs = I915_READ(TSFS);
5617
5618         m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
5619         x = I915_READ8(TR1);
5620
5621         b = tsfs & TSFS_INTR_MASK;
5622
5623         return ((m * x) / 127) - b;
5624 }
5625
5626 static int _pxvid_to_vd(u8 pxvid)
5627 {
5628         if (pxvid == 0)
5629                 return 0;
5630
5631         if (pxvid >= 8 && pxvid < 31)
5632                 pxvid = 31;
5633
5634         return (pxvid + 2) * 125;
5635 }
5636
5637 static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
5638 {
5639         struct drm_device *dev = dev_priv->dev;
5640         const int vd = _pxvid_to_vd(pxvid);
5641         const int vm = vd - 1125;
5642
5643         if (INTEL_INFO(dev)->is_mobile)
5644                 return vm > 0 ? vm : 0;
5645
5646         return vd;
5647 }
5648
5649 static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
5650 {
5651         u64 now, diff, diffms;
5652         u32 count;
5653
5654         assert_spin_locked(&mchdev_lock);
5655
5656         now = ktime_get_raw_ns();
5657         diffms = now - dev_priv->ips.last_time2;
5658         do_div(diffms, NSEC_PER_MSEC);
5659
5660         /* Don't divide by 0 */
5661         if (!diffms)
5662                 return;
5663
5664         count = I915_READ(GFXEC);
5665
5666         if (count < dev_priv->ips.last_count2) {
5667                 diff = ~0UL - dev_priv->ips.last_count2;
5668                 diff += count;
5669         } else {
5670                 diff = count - dev_priv->ips.last_count2;
5671         }
5672
5673         dev_priv->ips.last_count2 = count;
5674         dev_priv->ips.last_time2 = now;
5675
5676         /* More magic constants... */
5677         diff = diff * 1181;
5678         diff = div_u64(diff, diffms * 10);
5679         dev_priv->ips.gfx_power = diff;
5680 }
5681
5682 void i915_update_gfx_val(struct drm_i915_private *dev_priv)
5683 {
5684         struct drm_device *dev = dev_priv->dev;
5685
5686         if (INTEL_INFO(dev)->gen != 5)
5687                 return;
5688
5689         spin_lock_irq(&mchdev_lock);
5690
5691         __i915_update_gfx_val(dev_priv);
5692
5693         spin_unlock_irq(&mchdev_lock);
5694 }
5695
5696 static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
5697 {
5698         unsigned long t, corr, state1, corr2, state2;
5699         u32 pxvid, ext_v;
5700
5701         assert_spin_locked(&mchdev_lock);
5702
5703         pxvid = I915_READ(PXVFREQ(dev_priv->rps.cur_freq));
5704         pxvid = (pxvid >> 24) & 0x7f;
5705         ext_v = pvid_to_extvid(dev_priv, pxvid);
5706
5707         state1 = ext_v;
5708
5709         t = i915_mch_val(dev_priv);
5710
5711         /* Revel in the empirically derived constants */
5712
5713         /* Correction factor in 1/100000 units */
5714         if (t > 80)
5715                 corr = ((t * 2349) + 135940);
5716         else if (t >= 50)
5717                 corr = ((t * 964) + 29317);
5718         else /* < 50 */
5719                 corr = ((t * 301) + 1004);
5720
5721         corr = corr * ((150142 * state1) / 10000 - 78642);
5722         corr /= 100000;
5723         corr2 = (corr * dev_priv->ips.corr);
5724
5725         state2 = (corr2 * state1) / 10000;
5726         state2 /= 100; /* convert to mW */
5727
5728         __i915_update_gfx_val(dev_priv);
5729
5730         return dev_priv->ips.gfx_power + state2;
5731 }
5732
5733 unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
5734 {
5735         struct drm_device *dev = dev_priv->dev;
5736         unsigned long val;
5737
5738         if (INTEL_INFO(dev)->gen != 5)
5739                 return 0;
5740
5741         spin_lock_irq(&mchdev_lock);
5742
5743         val = __i915_gfx_val(dev_priv);
5744
5745         spin_unlock_irq(&mchdev_lock);
5746
5747         return val;
5748 }
5749
5750 /**
5751  * i915_read_mch_val - return value for IPS use
5752  *
5753  * Calculate and return a value for the IPS driver to use when deciding whether
5754  * we have thermal and power headroom to increase CPU or GPU power budget.
5755  */
5756 unsigned long i915_read_mch_val(void)
5757 {
5758         struct drm_i915_private *dev_priv;
5759         unsigned long chipset_val, graphics_val, ret = 0;
5760
5761         spin_lock_irq(&mchdev_lock);
5762         if (!i915_mch_dev)
5763                 goto out_unlock;
5764         dev_priv = i915_mch_dev;
5765
5766         chipset_val = __i915_chipset_val(dev_priv);
5767         graphics_val = __i915_gfx_val(dev_priv);
5768
5769         ret = chipset_val + graphics_val;
5770
5771 out_unlock:
5772         spin_unlock_irq(&mchdev_lock);
5773
5774         return ret;
5775 }
5776 EXPORT_SYMBOL_GPL(i915_read_mch_val);
5777
5778 /**
5779  * i915_gpu_raise - raise GPU frequency limit
5780  *
5781  * Raise the limit; IPS indicates we have thermal headroom.
5782  */
5783 bool i915_gpu_raise(void)
5784 {
5785         struct drm_i915_private *dev_priv;
5786         bool ret = true;
5787
5788         spin_lock_irq(&mchdev_lock);
5789         if (!i915_mch_dev) {
5790                 ret = false;
5791                 goto out_unlock;
5792         }
5793         dev_priv = i915_mch_dev;
5794
5795         if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
5796                 dev_priv->ips.max_delay--;
5797
5798 out_unlock:
5799         spin_unlock_irq(&mchdev_lock);
5800
5801         return ret;
5802 }
5803 EXPORT_SYMBOL_GPL(i915_gpu_raise);
5804
5805 /**
5806  * i915_gpu_lower - lower GPU frequency limit
5807  *
5808  * IPS indicates we're close to a thermal limit, so throttle back the GPU
5809  * frequency maximum.
5810  */
5811 bool i915_gpu_lower(void)
5812 {
5813         struct drm_i915_private *dev_priv;
5814         bool ret = true;
5815
5816         spin_lock_irq(&mchdev_lock);
5817         if (!i915_mch_dev) {
5818                 ret = false;
5819                 goto out_unlock;
5820         }
5821         dev_priv = i915_mch_dev;
5822
5823         if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
5824                 dev_priv->ips.max_delay++;
5825
5826 out_unlock:
5827         spin_unlock_irq(&mchdev_lock);
5828
5829         return ret;
5830 }
5831 EXPORT_SYMBOL_GPL(i915_gpu_lower);
5832
5833 /**
5834  * i915_gpu_busy - indicate GPU business to IPS
5835  *
5836  * Tell the IPS driver whether or not the GPU is busy.
5837  */
5838 bool i915_gpu_busy(void)
5839 {
5840         struct drm_i915_private *dev_priv;
5841         struct intel_engine_cs *ring;
5842         bool ret = false;
5843         int i;
5844
5845         spin_lock_irq(&mchdev_lock);
5846         if (!i915_mch_dev)
5847                 goto out_unlock;
5848         dev_priv = i915_mch_dev;
5849
5850         for_each_ring(ring, dev_priv, i)
5851                 ret |= !list_empty(&ring->request_list);
5852
5853 out_unlock:
5854         spin_unlock_irq(&mchdev_lock);
5855
5856         return ret;
5857 }
5858 EXPORT_SYMBOL_GPL(i915_gpu_busy);
5859
5860 /**
5861  * i915_gpu_turbo_disable - disable graphics turbo
5862  *
5863  * Disable graphics turbo by resetting the max frequency and setting the
5864  * current frequency to the default.
5865  */
5866 bool i915_gpu_turbo_disable(void)
5867 {
5868         struct drm_i915_private *dev_priv;
5869         bool ret = true;
5870
5871         spin_lock_irq(&mchdev_lock);
5872         if (!i915_mch_dev) {
5873                 ret = false;
5874                 goto out_unlock;
5875         }
5876         dev_priv = i915_mch_dev;
5877
5878         dev_priv->ips.max_delay = dev_priv->ips.fstart;
5879
5880         if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
5881                 ret = false;
5882
5883 out_unlock:
5884         spin_unlock_irq(&mchdev_lock);
5885
5886         return ret;
5887 }
5888 EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
5889
5890 /**
5891  * Tells the intel_ips driver that the i915 driver is now loaded, if
5892  * IPS got loaded first.
5893  *
5894  * This awkward dance is so that neither module has to depend on the
5895  * other in order for IPS to do the appropriate communication of
5896  * GPU turbo limits to i915.
5897  */
5898 static void
5899 ips_ping_for_i915_load(void)
5900 {
5901         void (*link)(void);
5902
5903         link = symbol_get(ips_link_to_i915_driver);
5904         if (link) {
5905                 link();
5906                 symbol_put(ips_link_to_i915_driver);
5907         }
5908 }
5909
5910 void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
5911 {
5912         /* We only register the i915 ips part with intel-ips once everything is
5913          * set up, to avoid intel-ips sneaking in and reading bogus values. */
5914         spin_lock_irq(&mchdev_lock);
5915         i915_mch_dev = dev_priv;
5916         spin_unlock_irq(&mchdev_lock);
5917
5918         ips_ping_for_i915_load();
5919 }
5920
5921 void intel_gpu_ips_teardown(void)
5922 {
5923         spin_lock_irq(&mchdev_lock);
5924         i915_mch_dev = NULL;
5925         spin_unlock_irq(&mchdev_lock);
5926 }
5927
5928 static void intel_init_emon(struct drm_device *dev)
5929 {
5930         struct drm_i915_private *dev_priv = dev->dev_private;
5931         u32 lcfuse;
5932         u8 pxw[16];
5933         int i;
5934
5935         /* Disable to program */
5936         I915_WRITE(ECR, 0);
5937         POSTING_READ(ECR);
5938
5939         /* Program energy weights for various events */
5940         I915_WRITE(SDEW, 0x15040d00);
5941         I915_WRITE(CSIEW0, 0x007f0000);
5942         I915_WRITE(CSIEW1, 0x1e220004);
5943         I915_WRITE(CSIEW2, 0x04000004);
5944
5945         for (i = 0; i < 5; i++)
5946                 I915_WRITE(PEW(i), 0);
5947         for (i = 0; i < 3; i++)
5948                 I915_WRITE(DEW(i), 0);
5949
5950         /* Program P-state weights to account for frequency power adjustment */
5951         for (i = 0; i < 16; i++) {
5952                 u32 pxvidfreq = I915_READ(PXVFREQ(i));
5953                 unsigned long freq = intel_pxfreq(pxvidfreq);
5954                 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
5955                         PXVFREQ_PX_SHIFT;
5956                 unsigned long val;
5957
5958                 val = vid * vid;
5959                 val *= (freq / 1000);
5960                 val *= 255;
5961                 val /= (127*127*900);
5962                 if (val > 0xff)
5963                         DRM_ERROR("bad pxval: %ld\n", val);
5964                 pxw[i] = val;
5965         }
5966         /* Render standby states get 0 weight */
5967         pxw[14] = 0;
5968         pxw[15] = 0;
5969
5970         for (i = 0; i < 4; i++) {
5971                 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
5972                         (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
5973                 I915_WRITE(PXW(i), val);
5974         }
5975
5976         /* Adjust magic regs to magic values (more experimental results) */
5977         I915_WRITE(OGW0, 0);
5978         I915_WRITE(OGW1, 0);
5979         I915_WRITE(EG0, 0x00007f00);
5980         I915_WRITE(EG1, 0x0000000e);
5981         I915_WRITE(EG2, 0x000e0000);
5982         I915_WRITE(EG3, 0x68000300);
5983         I915_WRITE(EG4, 0x42000000);
5984         I915_WRITE(EG5, 0x00140031);
5985         I915_WRITE(EG6, 0);
5986         I915_WRITE(EG7, 0);
5987
5988         for (i = 0; i < 8; i++)
5989                 I915_WRITE(PXWL(i), 0);
5990
5991         /* Enable PMON + select events */
5992         I915_WRITE(ECR, 0x80000019);
5993
5994         lcfuse = I915_READ(LCFUSE02);
5995
5996         dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
5997 }
5998
5999 void intel_init_gt_powersave(struct drm_device *dev)
6000 {
6001         i915.enable_rc6 = sanitize_rc6_option(dev, i915.enable_rc6);
6002
6003         if (IS_CHERRYVIEW(dev))
6004                 cherryview_init_gt_powersave(dev);
6005         else if (IS_VALLEYVIEW(dev))
6006                 valleyview_init_gt_powersave(dev);
6007 }
6008
6009 void intel_cleanup_gt_powersave(struct drm_device *dev)
6010 {
6011         if (IS_CHERRYVIEW(dev))
6012                 return;
6013         else if (IS_VALLEYVIEW(dev))
6014                 valleyview_cleanup_gt_powersave(dev);
6015 }
6016
6017 static void gen6_suspend_rps(struct drm_device *dev)
6018 {
6019         struct drm_i915_private *dev_priv = dev->dev_private;
6020
6021         flush_delayed_work(&dev_priv->rps.delayed_resume_work);
6022
6023         gen6_disable_rps_interrupts(dev);
6024 }
6025
6026 /**
6027  * intel_suspend_gt_powersave - suspend PM work and helper threads
6028  * @dev: drm device
6029  *
6030  * We don't want to disable RC6 or other features here, we just want
6031  * to make sure any work we've queued has finished and won't bother
6032  * us while we're suspended.
6033  */
6034 void intel_suspend_gt_powersave(struct drm_device *dev)
6035 {
6036         struct drm_i915_private *dev_priv = dev->dev_private;
6037
6038         if (INTEL_INFO(dev)->gen < 6)
6039                 return;
6040
6041         gen6_suspend_rps(dev);
6042
6043         /* Force GPU to min freq during suspend */
6044         gen6_rps_idle(dev_priv);
6045 }
6046
6047 void intel_disable_gt_powersave(struct drm_device *dev)
6048 {
6049         struct drm_i915_private *dev_priv = dev->dev_private;
6050
6051         if (IS_IRONLAKE_M(dev)) {
6052                 ironlake_disable_drps(dev);
6053         } else if (INTEL_INFO(dev)->gen >= 6) {
6054                 intel_suspend_gt_powersave(dev);
6055
6056                 mutex_lock(&dev_priv->rps.hw_lock);
6057                 if (INTEL_INFO(dev)->gen >= 9)
6058                         gen9_disable_rps(dev);
6059                 else if (IS_CHERRYVIEW(dev))
6060                         cherryview_disable_rps(dev);
6061                 else if (IS_VALLEYVIEW(dev))
6062                         valleyview_disable_rps(dev);
6063                 else
6064                         gen6_disable_rps(dev);
6065
6066                 dev_priv->rps.enabled = false;
6067                 mutex_unlock(&dev_priv->rps.hw_lock);
6068         }
6069 }
6070
6071 static void intel_gen6_powersave_work(struct work_struct *work)
6072 {
6073         struct drm_i915_private *dev_priv =
6074                 container_of(work, struct drm_i915_private,
6075                              rps.delayed_resume_work.work);
6076         struct drm_device *dev = dev_priv->dev;
6077
6078         mutex_lock(&dev_priv->rps.hw_lock);
6079
6080         gen6_reset_rps_interrupts(dev);
6081
6082         if (IS_CHERRYVIEW(dev)) {
6083                 cherryview_enable_rps(dev);
6084         } else if (IS_VALLEYVIEW(dev)) {
6085                 valleyview_enable_rps(dev);
6086         } else if (INTEL_INFO(dev)->gen >= 9) {
6087                 gen9_enable_rc6(dev);
6088                 gen9_enable_rps(dev);
6089                 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
6090                         __gen6_update_ring_freq(dev);
6091         } else if (IS_BROADWELL(dev)) {
6092                 gen8_enable_rps(dev);
6093                 __gen6_update_ring_freq(dev);
6094         } else {
6095                 gen6_enable_rps(dev);
6096                 __gen6_update_ring_freq(dev);
6097         }
6098
6099         WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq);
6100         WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq);
6101
6102         WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
6103         WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
6104
6105         dev_priv->rps.enabled = true;
6106
6107         gen6_enable_rps_interrupts(dev);
6108
6109         mutex_unlock(&dev_priv->rps.hw_lock);
6110
6111         intel_runtime_pm_put(dev_priv);
6112 }
6113
6114 void intel_enable_gt_powersave(struct drm_device *dev)
6115 {
6116         struct drm_i915_private *dev_priv = dev->dev_private;
6117
6118         /* Powersaving is controlled by the host when inside a VM */
6119         if (intel_vgpu_active(dev))
6120                 return;
6121
6122         if (IS_IRONLAKE_M(dev)) {
6123                 mutex_lock(&dev->struct_mutex);
6124                 ironlake_enable_drps(dev);
6125                 intel_init_emon(dev);
6126                 mutex_unlock(&dev->struct_mutex);
6127         } else if (INTEL_INFO(dev)->gen >= 6) {
6128                 /*
6129                  * PCU communication is slow and this doesn't need to be
6130                  * done at any specific time, so do this out of our fast path
6131                  * to make resume and init faster.
6132                  *
6133                  * We depend on the HW RC6 power context save/restore
6134                  * mechanism when entering D3 through runtime PM suspend. So
6135                  * disable RPM until RPS/RC6 is properly setup. We can only
6136                  * get here via the driver load/system resume/runtime resume
6137                  * paths, so the _noresume version is enough (and in case of
6138                  * runtime resume it's necessary).
6139                  */
6140                 if (schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
6141                                            round_jiffies_up_relative(HZ)))
6142                         intel_runtime_pm_get_noresume(dev_priv);
6143         }
6144 }
6145
6146 void intel_reset_gt_powersave(struct drm_device *dev)
6147 {
6148         struct drm_i915_private *dev_priv = dev->dev_private;
6149
6150         if (INTEL_INFO(dev)->gen < 6)
6151                 return;
6152
6153         gen6_suspend_rps(dev);
6154         dev_priv->rps.enabled = false;
6155 }
6156
6157 static void ibx_init_clock_gating(struct drm_device *dev)
6158 {
6159         struct drm_i915_private *dev_priv = dev->dev_private;
6160
6161         /*
6162          * On Ibex Peak and Cougar Point, we need to disable clock
6163          * gating for the panel power sequencer or it will fail to
6164          * start up when no ports are active.
6165          */
6166         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
6167 }
6168
6169 static void g4x_disable_trickle_feed(struct drm_device *dev)
6170 {
6171         struct drm_i915_private *dev_priv = dev->dev_private;
6172         enum pipe pipe;
6173
6174         for_each_pipe(dev_priv, pipe) {
6175                 I915_WRITE(DSPCNTR(pipe),
6176                            I915_READ(DSPCNTR(pipe)) |
6177                            DISPPLANE_TRICKLE_FEED_DISABLE);
6178
6179                 I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe)));
6180                 POSTING_READ(DSPSURF(pipe));
6181         }
6182 }
6183
6184 static void ilk_init_lp_watermarks(struct drm_device *dev)
6185 {
6186         struct drm_i915_private *dev_priv = dev->dev_private;
6187
6188         I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
6189         I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
6190         I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
6191
6192         /*
6193          * Don't touch WM1S_LP_EN here.
6194          * Doing so could cause underruns.
6195          */
6196 }
6197
6198 static void ironlake_init_clock_gating(struct drm_device *dev)
6199 {
6200         struct drm_i915_private *dev_priv = dev->dev_private;
6201         uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6202
6203         /*
6204          * Required for FBC
6205          * WaFbcDisableDpfcClockGating:ilk
6206          */
6207         dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
6208                    ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
6209                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6210
6211         I915_WRITE(PCH_3DCGDIS0,
6212                    MARIUNIT_CLOCK_GATE_DISABLE |
6213                    SVSMUNIT_CLOCK_GATE_DISABLE);
6214         I915_WRITE(PCH_3DCGDIS1,
6215                    VFMUNIT_CLOCK_GATE_DISABLE);
6216
6217         /*
6218          * According to the spec the following bits should be set in
6219          * order to enable memory self-refresh
6220          * The bit 22/21 of 0x42004
6221          * The bit 5 of 0x42020
6222          * The bit 15 of 0x45000
6223          */
6224         I915_WRITE(ILK_DISPLAY_CHICKEN2,
6225                    (I915_READ(ILK_DISPLAY_CHICKEN2) |
6226                     ILK_DPARB_GATE | ILK_VSDPFD_FULL));
6227         dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6228         I915_WRITE(DISP_ARB_CTL,
6229                    (I915_READ(DISP_ARB_CTL) |
6230                     DISP_FBC_WM_DIS));
6231
6232         ilk_init_lp_watermarks(dev);
6233
6234         /*
6235          * Based on the document from hardware guys the following bits
6236          * should be set unconditionally in order to enable FBC.
6237          * The bit 22 of 0x42000
6238          * The bit 22 of 0x42004
6239          * The bit 7,8,9 of 0x42020.
6240          */
6241         if (IS_IRONLAKE_M(dev)) {
6242                 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6243                 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6244                            I915_READ(ILK_DISPLAY_CHICKEN1) |
6245                            ILK_FBCQ_DIS);
6246                 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6247                            I915_READ(ILK_DISPLAY_CHICKEN2) |
6248                            ILK_DPARB_GATE);
6249         }
6250
6251         I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6252
6253         I915_WRITE(ILK_DISPLAY_CHICKEN2,
6254                    I915_READ(ILK_DISPLAY_CHICKEN2) |
6255                    ILK_ELPIN_409_SELECT);
6256         I915_WRITE(_3D_CHICKEN2,
6257                    _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
6258                    _3D_CHICKEN2_WM_READ_PIPELINED);
6259
6260         /* WaDisableRenderCachePipelinedFlush:ilk */
6261         I915_WRITE(CACHE_MODE_0,
6262                    _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
6263
6264         /* WaDisable_RenderCache_OperationalFlush:ilk */
6265         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6266
6267         g4x_disable_trickle_feed(dev);
6268
6269         ibx_init_clock_gating(dev);
6270 }
6271
6272 static void cpt_init_clock_gating(struct drm_device *dev)
6273 {
6274         struct drm_i915_private *dev_priv = dev->dev_private;
6275         int pipe;
6276         uint32_t val;
6277
6278         /*
6279          * On Ibex Peak and Cougar Point, we need to disable clock
6280          * gating for the panel power sequencer or it will fail to
6281          * start up when no ports are active.
6282          */
6283         I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
6284                    PCH_DPLUNIT_CLOCK_GATE_DISABLE |
6285                    PCH_CPUNIT_CLOCK_GATE_DISABLE);
6286         I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
6287                    DPLS_EDP_PPS_FIX_DIS);
6288         /* The below fixes the weird display corruption, a few pixels shifted
6289          * downward, on (only) LVDS of some HP laptops with IVY.
6290          */
6291         for_each_pipe(dev_priv, pipe) {
6292                 val = I915_READ(TRANS_CHICKEN2(pipe));
6293                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
6294                 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
6295                 if (dev_priv->vbt.fdi_rx_polarity_inverted)
6296                         val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
6297                 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
6298                 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
6299                 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
6300                 I915_WRITE(TRANS_CHICKEN2(pipe), val);
6301         }
6302         /* WADP0ClockGatingDisable */
6303         for_each_pipe(dev_priv, pipe) {
6304                 I915_WRITE(TRANS_CHICKEN1(pipe),
6305                            TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
6306         }
6307 }
6308
6309 static void gen6_check_mch_setup(struct drm_device *dev)
6310 {
6311         struct drm_i915_private *dev_priv = dev->dev_private;
6312         uint32_t tmp;
6313
6314         tmp = I915_READ(MCH_SSKPD);
6315         if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
6316                 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
6317                               tmp);
6318 }
6319
6320 static void gen6_init_clock_gating(struct drm_device *dev)
6321 {
6322         struct drm_i915_private *dev_priv = dev->dev_private;
6323         uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6324
6325         I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6326
6327         I915_WRITE(ILK_DISPLAY_CHICKEN2,
6328                    I915_READ(ILK_DISPLAY_CHICKEN2) |
6329                    ILK_ELPIN_409_SELECT);
6330
6331         /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
6332         I915_WRITE(_3D_CHICKEN,
6333                    _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
6334
6335         /* WaDisable_RenderCache_OperationalFlush:snb */
6336         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6337
6338         /*
6339          * BSpec recoomends 8x4 when MSAA is used,
6340          * however in practice 16x4 seems fastest.
6341          *
6342          * Note that PS/WM thread counts depend on the WIZ hashing
6343          * disable bit, which we don't touch here, but it's good
6344          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6345          */
6346         I915_WRITE(GEN6_GT_MODE,
6347                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6348
6349         ilk_init_lp_watermarks(dev);
6350
6351         I915_WRITE(CACHE_MODE_0,
6352                    _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
6353
6354         I915_WRITE(GEN6_UCGCTL1,
6355                    I915_READ(GEN6_UCGCTL1) |
6356                    GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
6357                    GEN6_CSUNIT_CLOCK_GATE_DISABLE);
6358
6359         /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
6360          * gating disable must be set.  Failure to set it results in
6361          * flickering pixels due to Z write ordering failures after
6362          * some amount of runtime in the Mesa "fire" demo, and Unigine
6363          * Sanctuary and Tropics, and apparently anything else with
6364          * alpha test or pixel discard.
6365          *
6366          * According to the spec, bit 11 (RCCUNIT) must also be set,
6367          * but we didn't debug actual testcases to find it out.
6368          *
6369          * WaDisableRCCUnitClockGating:snb
6370          * WaDisableRCPBUnitClockGating:snb
6371          */
6372         I915_WRITE(GEN6_UCGCTL2,
6373                    GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
6374                    GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
6375
6376         /* WaStripsFansDisableFastClipPerformanceFix:snb */
6377         I915_WRITE(_3D_CHICKEN3,
6378                    _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
6379
6380         /*
6381          * Bspec says:
6382          * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
6383          * 3DSTATE_SF number of SF output attributes is more than 16."
6384          */
6385         I915_WRITE(_3D_CHICKEN3,
6386                    _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
6387
6388         /*
6389          * According to the spec the following bits should be
6390          * set in order to enable memory self-refresh and fbc:
6391          * The bit21 and bit22 of 0x42000
6392          * The bit21 and bit22 of 0x42004
6393          * The bit5 and bit7 of 0x42020
6394          * The bit14 of 0x70180
6395          * The bit14 of 0x71180
6396          *
6397          * WaFbcAsynchFlipDisableFbcQueue:snb
6398          */
6399         I915_WRITE(ILK_DISPLAY_CHICKEN1,
6400                    I915_READ(ILK_DISPLAY_CHICKEN1) |
6401                    ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
6402         I915_WRITE(ILK_DISPLAY_CHICKEN2,
6403                    I915_READ(ILK_DISPLAY_CHICKEN2) |
6404                    ILK_DPARB_GATE | ILK_VSDPFD_FULL);
6405         I915_WRITE(ILK_DSPCLK_GATE_D,
6406                    I915_READ(ILK_DSPCLK_GATE_D) |
6407                    ILK_DPARBUNIT_CLOCK_GATE_ENABLE  |
6408                    ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
6409
6410         g4x_disable_trickle_feed(dev);
6411
6412         cpt_init_clock_gating(dev);
6413
6414         gen6_check_mch_setup(dev);
6415 }
6416
6417 static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
6418 {
6419         uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
6420
6421         /*
6422          * WaVSThreadDispatchOverride:ivb,vlv
6423          *
6424          * This actually overrides the dispatch
6425          * mode for all thread types.
6426          */
6427         reg &= ~GEN7_FF_SCHED_MASK;
6428         reg |= GEN7_FF_TS_SCHED_HW;
6429         reg |= GEN7_FF_VS_SCHED_HW;
6430         reg |= GEN7_FF_DS_SCHED_HW;
6431
6432         I915_WRITE(GEN7_FF_THREAD_MODE, reg);
6433 }
6434
6435 static void lpt_init_clock_gating(struct drm_device *dev)
6436 {
6437         struct drm_i915_private *dev_priv = dev->dev_private;
6438
6439         /*
6440          * TODO: this bit should only be enabled when really needed, then
6441          * disabled when not needed anymore in order to save power.
6442          */
6443         if (HAS_PCH_LPT_LP(dev))
6444                 I915_WRITE(SOUTH_DSPCLK_GATE_D,
6445                            I915_READ(SOUTH_DSPCLK_GATE_D) |
6446                            PCH_LP_PARTITION_LEVEL_DISABLE);
6447
6448         /* WADPOClockGatingDisable:hsw */
6449         I915_WRITE(TRANS_CHICKEN1(PIPE_A),
6450                    I915_READ(TRANS_CHICKEN1(PIPE_A)) |
6451                    TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
6452 }
6453
6454 static void lpt_suspend_hw(struct drm_device *dev)
6455 {
6456         struct drm_i915_private *dev_priv = dev->dev_private;
6457
6458         if (HAS_PCH_LPT_LP(dev)) {
6459                 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
6460
6461                 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6462                 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6463         }
6464 }
6465
6466 static void broadwell_init_clock_gating(struct drm_device *dev)
6467 {
6468         struct drm_i915_private *dev_priv = dev->dev_private;
6469         enum pipe pipe;
6470         uint32_t misccpctl;
6471
6472         ilk_init_lp_watermarks(dev);
6473
6474         /* WaSwitchSolVfFArbitrationPriority:bdw */
6475         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
6476
6477         /* WaPsrDPAMaskVBlankInSRD:bdw */
6478         I915_WRITE(CHICKEN_PAR1_1,
6479                    I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
6480
6481         /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
6482         for_each_pipe(dev_priv, pipe) {
6483                 I915_WRITE(CHICKEN_PIPESL_1(pipe),
6484                            I915_READ(CHICKEN_PIPESL_1(pipe)) |
6485                            BDW_DPRS_MASK_VBLANK_SRD);
6486         }
6487
6488         /* WaVSRefCountFullforceMissDisable:bdw */
6489         /* WaDSRefCountFullforceMissDisable:bdw */
6490         I915_WRITE(GEN7_FF_THREAD_MODE,
6491                    I915_READ(GEN7_FF_THREAD_MODE) &
6492                    ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
6493
6494         I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
6495                    _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
6496
6497         /* WaDisableSDEUnitClockGating:bdw */
6498         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
6499                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
6500
6501         /*
6502          * WaProgramL3SqcReg1Default:bdw
6503          * WaTempDisableDOPClkGating:bdw
6504          */
6505         misccpctl = I915_READ(GEN7_MISCCPCTL);
6506         I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
6507         I915_WRITE(GEN8_L3SQCREG1, BDW_WA_L3SQCREG1_DEFAULT);
6508         I915_WRITE(GEN7_MISCCPCTL, misccpctl);
6509
6510         /*
6511          * WaGttCachingOffByDefault:bdw
6512          * GTT cache may not work with big pages, so if those
6513          * are ever enabled GTT cache may need to be disabled.
6514          */
6515         I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
6516
6517         lpt_init_clock_gating(dev);
6518 }
6519
6520 static void haswell_init_clock_gating(struct drm_device *dev)
6521 {
6522         struct drm_i915_private *dev_priv = dev->dev_private;
6523
6524         ilk_init_lp_watermarks(dev);
6525
6526         /* L3 caching of data atomics doesn't work -- disable it. */
6527         I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
6528         I915_WRITE(HSW_ROW_CHICKEN3,
6529                    _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
6530
6531         /* This is required by WaCatErrorRejectionIssue:hsw */
6532         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6533                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6534                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6535
6536         /* WaVSRefCountFullforceMissDisable:hsw */
6537         I915_WRITE(GEN7_FF_THREAD_MODE,
6538                    I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
6539
6540         /* WaDisable_RenderCache_OperationalFlush:hsw */
6541         I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6542
6543         /* enable HiZ Raw Stall Optimization */
6544         I915_WRITE(CACHE_MODE_0_GEN7,
6545                    _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
6546
6547         /* WaDisable4x2SubspanOptimization:hsw */
6548         I915_WRITE(CACHE_MODE_1,
6549                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
6550
6551         /*
6552          * BSpec recommends 8x4 when MSAA is used,
6553          * however in practice 16x4 seems fastest.
6554          *
6555          * Note that PS/WM thread counts depend on the WIZ hashing
6556          * disable bit, which we don't touch here, but it's good
6557          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6558          */
6559         I915_WRITE(GEN7_GT_MODE,
6560                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6561
6562         /* WaSampleCChickenBitEnable:hsw */
6563         I915_WRITE(HALF_SLICE_CHICKEN3,
6564                    _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE));
6565
6566         /* WaSwitchSolVfFArbitrationPriority:hsw */
6567         I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
6568
6569         /* WaRsPkgCStateDisplayPMReq:hsw */
6570         I915_WRITE(CHICKEN_PAR1_1,
6571                    I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
6572
6573         lpt_init_clock_gating(dev);
6574 }
6575
6576 static void ivybridge_init_clock_gating(struct drm_device *dev)
6577 {
6578         struct drm_i915_private *dev_priv = dev->dev_private;
6579         uint32_t snpcr;
6580
6581         ilk_init_lp_watermarks(dev);
6582
6583         I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
6584
6585         /* WaDisableEarlyCull:ivb */
6586         I915_WRITE(_3D_CHICKEN3,
6587                    _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
6588
6589         /* WaDisableBackToBackFlipFix:ivb */
6590         I915_WRITE(IVB_CHICKEN3,
6591                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
6592                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
6593
6594         /* WaDisablePSDDualDispatchEnable:ivb */
6595         if (IS_IVB_GT1(dev))
6596                 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
6597                            _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
6598
6599         /* WaDisable_RenderCache_OperationalFlush:ivb */
6600         I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6601
6602         /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
6603         I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
6604                    GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
6605
6606         /* WaApplyL3ControlAndL3ChickenMode:ivb */
6607         I915_WRITE(GEN7_L3CNTLREG1,
6608                         GEN7_WA_FOR_GEN7_L3_CONTROL);
6609         I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
6610                    GEN7_WA_L3_CHICKEN_MODE);
6611         if (IS_IVB_GT1(dev))
6612                 I915_WRITE(GEN7_ROW_CHICKEN2,
6613                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6614         else {
6615                 /* must write both registers */
6616                 I915_WRITE(GEN7_ROW_CHICKEN2,
6617                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6618                 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
6619                            _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6620         }
6621
6622         /* WaForceL3Serialization:ivb */
6623         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
6624                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
6625
6626         /*
6627          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
6628          * This implements the WaDisableRCZUnitClockGating:ivb workaround.
6629          */
6630         I915_WRITE(GEN6_UCGCTL2,
6631                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
6632
6633         /* This is required by WaCatErrorRejectionIssue:ivb */
6634         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6635                         I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6636                         GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6637
6638         g4x_disable_trickle_feed(dev);
6639
6640         gen7_setup_fixed_func_scheduler(dev_priv);
6641
6642         if (0) { /* causes HiZ corruption on ivb:gt1 */
6643                 /* enable HiZ Raw Stall Optimization */
6644                 I915_WRITE(CACHE_MODE_0_GEN7,
6645                            _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
6646         }
6647
6648         /* WaDisable4x2SubspanOptimization:ivb */
6649         I915_WRITE(CACHE_MODE_1,
6650                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
6651
6652         /*
6653          * BSpec recommends 8x4 when MSAA is used,
6654          * however in practice 16x4 seems fastest.
6655          *
6656          * Note that PS/WM thread counts depend on the WIZ hashing
6657          * disable bit, which we don't touch here, but it's good
6658          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6659          */
6660         I915_WRITE(GEN7_GT_MODE,
6661                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6662
6663         snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
6664         snpcr &= ~GEN6_MBC_SNPCR_MASK;
6665         snpcr |= GEN6_MBC_SNPCR_MED;
6666         I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
6667
6668         if (!HAS_PCH_NOP(dev))
6669                 cpt_init_clock_gating(dev);
6670
6671         gen6_check_mch_setup(dev);
6672 }
6673
6674 static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv)
6675 {
6676         I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
6677
6678         /*
6679          * Disable trickle feed and enable pnd deadline calculation
6680          */
6681         I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
6682         I915_WRITE(CBR1_VLV, 0);
6683 }
6684
6685 static void valleyview_init_clock_gating(struct drm_device *dev)
6686 {
6687         struct drm_i915_private *dev_priv = dev->dev_private;
6688
6689         vlv_init_display_clock_gating(dev_priv);
6690
6691         /* WaDisableEarlyCull:vlv */
6692         I915_WRITE(_3D_CHICKEN3,
6693                    _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
6694
6695         /* WaDisableBackToBackFlipFix:vlv */
6696         I915_WRITE(IVB_CHICKEN3,
6697                    CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
6698                    CHICKEN3_DGMG_DONE_FIX_DISABLE);
6699
6700         /* WaPsdDispatchEnable:vlv */
6701         /* WaDisablePSDDualDispatchEnable:vlv */
6702         I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
6703                    _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
6704                                       GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
6705
6706         /* WaDisable_RenderCache_OperationalFlush:vlv */
6707         I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6708
6709         /* WaForceL3Serialization:vlv */
6710         I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
6711                    ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
6712
6713         /* WaDisableDopClockGating:vlv */
6714         I915_WRITE(GEN7_ROW_CHICKEN2,
6715                    _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6716
6717         /* This is required by WaCatErrorRejectionIssue:vlv */
6718         I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6719                    I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6720                    GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6721
6722         gen7_setup_fixed_func_scheduler(dev_priv);
6723
6724         /*
6725          * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
6726          * This implements the WaDisableRCZUnitClockGating:vlv workaround.
6727          */
6728         I915_WRITE(GEN6_UCGCTL2,
6729                    GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
6730
6731         /* WaDisableL3Bank2xClockGate:vlv
6732          * Disabling L3 clock gating- MMIO 940c[25] = 1
6733          * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
6734         I915_WRITE(GEN7_UCGCTL4,
6735                    I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
6736
6737         /*
6738          * BSpec says this must be set, even though
6739          * WaDisable4x2SubspanOptimization isn't listed for VLV.
6740          */
6741         I915_WRITE(CACHE_MODE_1,
6742                    _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
6743
6744         /*
6745          * BSpec recommends 8x4 when MSAA is used,
6746          * however in practice 16x4 seems fastest.
6747          *
6748          * Note that PS/WM thread counts depend on the WIZ hashing
6749          * disable bit, which we don't touch here, but it's good
6750          * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6751          */
6752         I915_WRITE(GEN7_GT_MODE,
6753                    _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6754
6755         /*
6756          * WaIncreaseL3CreditsForVLVB0:vlv
6757          * This is the hardware default actually.
6758          */
6759         I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
6760
6761         /*
6762          * WaDisableVLVClockGating_VBIIssue:vlv
6763          * Disable clock gating on th GCFG unit to prevent a delay
6764          * in the reporting of vblank events.
6765          */
6766         I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
6767 }
6768
6769 static void cherryview_init_clock_gating(struct drm_device *dev)
6770 {
6771         struct drm_i915_private *dev_priv = dev->dev_private;
6772
6773         vlv_init_display_clock_gating(dev_priv);
6774
6775         /* WaVSRefCountFullforceMissDisable:chv */
6776         /* WaDSRefCountFullforceMissDisable:chv */
6777         I915_WRITE(GEN7_FF_THREAD_MODE,
6778                    I915_READ(GEN7_FF_THREAD_MODE) &
6779                    ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
6780
6781         /* WaDisableSemaphoreAndSyncFlipWait:chv */
6782         I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
6783                    _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
6784
6785         /* WaDisableCSUnitClockGating:chv */
6786         I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
6787                    GEN6_CSUNIT_CLOCK_GATE_DISABLE);
6788
6789         /* WaDisableSDEUnitClockGating:chv */
6790         I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
6791                    GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
6792
6793         /*
6794          * GTT cache may not work with big pages, so if those
6795          * are ever enabled GTT cache may need to be disabled.
6796          */
6797         I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
6798 }
6799
6800 static void g4x_init_clock_gating(struct drm_device *dev)
6801 {
6802         struct drm_i915_private *dev_priv = dev->dev_private;
6803         uint32_t dspclk_gate;
6804
6805         I915_WRITE(RENCLK_GATE_D1, 0);
6806         I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
6807                    GS_UNIT_CLOCK_GATE_DISABLE |
6808                    CL_UNIT_CLOCK_GATE_DISABLE);
6809         I915_WRITE(RAMCLK_GATE_D, 0);
6810         dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
6811                 OVRUNIT_CLOCK_GATE_DISABLE |
6812                 OVCUNIT_CLOCK_GATE_DISABLE;
6813         if (IS_GM45(dev))
6814                 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
6815         I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
6816
6817         /* WaDisableRenderCachePipelinedFlush */
6818         I915_WRITE(CACHE_MODE_0,
6819                    _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
6820
6821         /* WaDisable_RenderCache_OperationalFlush:g4x */
6822         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6823
6824         g4x_disable_trickle_feed(dev);
6825 }
6826
6827 static void crestline_init_clock_gating(struct drm_device *dev)
6828 {
6829         struct drm_i915_private *dev_priv = dev->dev_private;
6830
6831         I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
6832         I915_WRITE(RENCLK_GATE_D2, 0);
6833         I915_WRITE(DSPCLK_GATE_D, 0);
6834         I915_WRITE(RAMCLK_GATE_D, 0);
6835         I915_WRITE16(DEUC, 0);
6836         I915_WRITE(MI_ARB_STATE,
6837                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6838
6839         /* WaDisable_RenderCache_OperationalFlush:gen4 */
6840         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6841 }
6842
6843 static void broadwater_init_clock_gating(struct drm_device *dev)
6844 {
6845         struct drm_i915_private *dev_priv = dev->dev_private;
6846
6847         I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
6848                    I965_RCC_CLOCK_GATE_DISABLE |
6849                    I965_RCPB_CLOCK_GATE_DISABLE |
6850                    I965_ISC_CLOCK_GATE_DISABLE |
6851                    I965_FBC_CLOCK_GATE_DISABLE);
6852         I915_WRITE(RENCLK_GATE_D2, 0);
6853         I915_WRITE(MI_ARB_STATE,
6854                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6855
6856         /* WaDisable_RenderCache_OperationalFlush:gen4 */
6857         I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6858 }
6859
6860 static void gen3_init_clock_gating(struct drm_device *dev)
6861 {
6862         struct drm_i915_private *dev_priv = dev->dev_private;
6863         u32 dstate = I915_READ(D_STATE);
6864
6865         dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
6866                 DSTATE_DOT_CLOCK_GATING;
6867         I915_WRITE(D_STATE, dstate);
6868
6869         if (IS_PINEVIEW(dev))
6870                 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
6871
6872         /* IIR "flip pending" means done if this bit is set */
6873         I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
6874
6875         /* interrupts should cause a wake up from C3 */
6876         I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
6877
6878         /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
6879         I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
6880
6881         I915_WRITE(MI_ARB_STATE,
6882                    _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6883 }
6884
6885 static void i85x_init_clock_gating(struct drm_device *dev)
6886 {
6887         struct drm_i915_private *dev_priv = dev->dev_private;
6888
6889         I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
6890
6891         /* interrupts should cause a wake up from C3 */
6892         I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
6893                    _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
6894
6895         I915_WRITE(MEM_MODE,
6896                    _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
6897 }
6898
6899 static void i830_init_clock_gating(struct drm_device *dev)
6900 {
6901         struct drm_i915_private *dev_priv = dev->dev_private;
6902
6903         I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
6904
6905         I915_WRITE(MEM_MODE,
6906                    _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
6907                    _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
6908 }
6909
6910 void intel_init_clock_gating(struct drm_device *dev)
6911 {
6912         struct drm_i915_private *dev_priv = dev->dev_private;
6913
6914         if (dev_priv->display.init_clock_gating)
6915                 dev_priv->display.init_clock_gating(dev);
6916 }
6917
6918 void intel_suspend_hw(struct drm_device *dev)
6919 {
6920         if (HAS_PCH_LPT(dev))
6921                 lpt_suspend_hw(dev);
6922 }
6923
6924 /* Set up chip specific power management-related functions */
6925 void intel_init_pm(struct drm_device *dev)
6926 {
6927         struct drm_i915_private *dev_priv = dev->dev_private;
6928
6929         intel_fbc_init(dev_priv);
6930
6931         /* For cxsr */
6932         if (IS_PINEVIEW(dev))
6933                 i915_pineview_get_mem_freq(dev);
6934         else if (IS_GEN5(dev))
6935                 i915_ironlake_get_mem_freq(dev);
6936
6937         /* For FIFO watermark updates */
6938         if (INTEL_INFO(dev)->gen >= 9) {
6939                 skl_setup_wm_latency(dev);
6940
6941                 if (IS_BROXTON(dev))
6942                         dev_priv->display.init_clock_gating =
6943                                 bxt_init_clock_gating;
6944                 dev_priv->display.update_wm = skl_update_wm;
6945         } else if (HAS_PCH_SPLIT(dev)) {
6946                 ilk_setup_wm_latency(dev);
6947
6948                 if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] &&
6949                      dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
6950                     (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] &&
6951                      dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
6952                         dev_priv->display.update_wm = ilk_update_wm;
6953                         dev_priv->display.compute_pipe_wm = ilk_compute_pipe_wm;
6954                 } else {
6955                         DRM_DEBUG_KMS("Failed to read display plane latency. "
6956                                       "Disable CxSR\n");
6957                 }
6958
6959                 if (IS_GEN5(dev))
6960                         dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
6961                 else if (IS_GEN6(dev))
6962                         dev_priv->display.init_clock_gating = gen6_init_clock_gating;
6963                 else if (IS_IVYBRIDGE(dev))
6964                         dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
6965                 else if (IS_HASWELL(dev))
6966                         dev_priv->display.init_clock_gating = haswell_init_clock_gating;
6967                 else if (INTEL_INFO(dev)->gen == 8)
6968                         dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
6969         } else if (IS_CHERRYVIEW(dev)) {
6970                 vlv_setup_wm_latency(dev);
6971
6972                 dev_priv->display.update_wm = vlv_update_wm;
6973                 dev_priv->display.init_clock_gating =
6974                         cherryview_init_clock_gating;
6975         } else if (IS_VALLEYVIEW(dev)) {
6976                 vlv_setup_wm_latency(dev);
6977
6978                 dev_priv->display.update_wm = vlv_update_wm;
6979                 dev_priv->display.init_clock_gating =
6980                         valleyview_init_clock_gating;
6981         } else if (IS_PINEVIEW(dev)) {
6982                 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
6983                                             dev_priv->is_ddr3,
6984                                             dev_priv->fsb_freq,
6985                                             dev_priv->mem_freq)) {
6986                         DRM_INFO("failed to find known CxSR latency "
6987                                  "(found ddr%s fsb freq %d, mem freq %d), "
6988                                  "disabling CxSR\n",
6989                                  (dev_priv->is_ddr3 == 1) ? "3" : "2",
6990                                  dev_priv->fsb_freq, dev_priv->mem_freq);
6991                         /* Disable CxSR and never update its watermark again */
6992                         intel_set_memory_cxsr(dev_priv, false);
6993                         dev_priv->display.update_wm = NULL;
6994                 } else
6995                         dev_priv->display.update_wm = pineview_update_wm;
6996                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
6997         } else if (IS_G4X(dev)) {
6998                 dev_priv->display.update_wm = g4x_update_wm;
6999                 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
7000         } else if (IS_GEN4(dev)) {
7001                 dev_priv->display.update_wm = i965_update_wm;
7002                 if (IS_CRESTLINE(dev))
7003                         dev_priv->display.init_clock_gating = crestline_init_clock_gating;
7004                 else if (IS_BROADWATER(dev))
7005                         dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
7006         } else if (IS_GEN3(dev)) {
7007                 dev_priv->display.update_wm = i9xx_update_wm;
7008                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
7009                 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7010         } else if (IS_GEN2(dev)) {
7011                 if (INTEL_INFO(dev)->num_pipes == 1) {
7012                         dev_priv->display.update_wm = i845_update_wm;
7013                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
7014                 } else {
7015                         dev_priv->display.update_wm = i9xx_update_wm;
7016                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
7017                 }
7018
7019                 if (IS_I85X(dev) || IS_I865G(dev))
7020                         dev_priv->display.init_clock_gating = i85x_init_clock_gating;
7021                 else
7022                         dev_priv->display.init_clock_gating = i830_init_clock_gating;
7023         } else {
7024                 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
7025         }
7026 }
7027
7028 int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val)
7029 {
7030         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
7031
7032         if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7033                 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
7034                 return -EAGAIN;
7035         }
7036
7037         I915_WRITE(GEN6_PCODE_DATA, *val);
7038         I915_WRITE(GEN6_PCODE_DATA1, 0);
7039         I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7040
7041         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7042                      500)) {
7043                 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
7044                 return -ETIMEDOUT;
7045         }
7046
7047         *val = I915_READ(GEN6_PCODE_DATA);
7048         I915_WRITE(GEN6_PCODE_DATA, 0);
7049
7050         return 0;
7051 }
7052
7053 int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val)
7054 {
7055         WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
7056
7057         if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7058                 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
7059                 return -EAGAIN;
7060         }
7061
7062         I915_WRITE(GEN6_PCODE_DATA, val);
7063         I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7064
7065         if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7066                      500)) {
7067                 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
7068                 return -ETIMEDOUT;
7069         }
7070
7071         I915_WRITE(GEN6_PCODE_DATA, 0);
7072
7073         return 0;
7074 }
7075
7076 static int vlv_gpu_freq_div(unsigned int czclk_freq)
7077 {
7078         switch (czclk_freq) {
7079         case 200:
7080                 return 10;
7081         case 267:
7082                 return 12;
7083         case 320:
7084         case 333:
7085                 return 16;
7086         case 400:
7087                 return 20;
7088         default:
7089                 return -1;
7090         }
7091 }
7092
7093 static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
7094 {
7095         int div, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000);
7096
7097         div = vlv_gpu_freq_div(czclk_freq);
7098         if (div < 0)
7099                 return div;
7100
7101         return DIV_ROUND_CLOSEST(czclk_freq * (val + 6 - 0xbd), div);
7102 }
7103
7104 static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
7105 {
7106         int mul, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000);
7107
7108         mul = vlv_gpu_freq_div(czclk_freq);
7109         if (mul < 0)
7110                 return mul;
7111
7112         return DIV_ROUND_CLOSEST(mul * val, czclk_freq) + 0xbd - 6;
7113 }
7114
7115 static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
7116 {
7117         int div, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000);
7118
7119         div = vlv_gpu_freq_div(czclk_freq) / 2;
7120         if (div < 0)
7121                 return div;
7122
7123         return DIV_ROUND_CLOSEST(czclk_freq * val, 2 * div) / 2;
7124 }
7125
7126 static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
7127 {
7128         int mul, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000);
7129
7130         mul = vlv_gpu_freq_div(czclk_freq) / 2;
7131         if (mul < 0)
7132                 return mul;
7133
7134         /* CHV needs even values */
7135         return DIV_ROUND_CLOSEST(val * 2 * mul, czclk_freq) * 2;
7136 }
7137
7138 int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
7139 {
7140         if (IS_GEN9(dev_priv->dev))
7141                 return DIV_ROUND_CLOSEST(val * GT_FREQUENCY_MULTIPLIER,
7142                                          GEN9_FREQ_SCALER);
7143         else if (IS_CHERRYVIEW(dev_priv->dev))
7144                 return chv_gpu_freq(dev_priv, val);
7145         else if (IS_VALLEYVIEW(dev_priv->dev))
7146                 return byt_gpu_freq(dev_priv, val);
7147         else
7148                 return val * GT_FREQUENCY_MULTIPLIER;
7149 }
7150
7151 int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
7152 {
7153         if (IS_GEN9(dev_priv->dev))
7154                 return DIV_ROUND_CLOSEST(val * GEN9_FREQ_SCALER,
7155                                          GT_FREQUENCY_MULTIPLIER);
7156         else if (IS_CHERRYVIEW(dev_priv->dev))
7157                 return chv_freq_opcode(dev_priv, val);
7158         else if (IS_VALLEYVIEW(dev_priv->dev))
7159                 return byt_freq_opcode(dev_priv, val);
7160         else
7161                 return DIV_ROUND_CLOSEST(val, GT_FREQUENCY_MULTIPLIER);
7162 }
7163
7164 struct request_boost {
7165         struct work_struct work;
7166         struct drm_i915_gem_request *req;
7167 };
7168
7169 static void __intel_rps_boost_work(struct work_struct *work)
7170 {
7171         struct request_boost *boost = container_of(work, struct request_boost, work);
7172         struct drm_i915_gem_request *req = boost->req;
7173
7174         if (!i915_gem_request_completed(req, true))
7175                 gen6_rps_boost(to_i915(req->ring->dev), NULL,
7176                                req->emitted_jiffies);
7177
7178         i915_gem_request_unreference__unlocked(req);
7179         kfree(boost);
7180 }
7181
7182 void intel_queue_rps_boost_for_request(struct drm_device *dev,
7183                                        struct drm_i915_gem_request *req)
7184 {
7185         struct request_boost *boost;
7186
7187         if (req == NULL || INTEL_INFO(dev)->gen < 6)
7188                 return;
7189
7190         if (i915_gem_request_completed(req, true))
7191                 return;
7192
7193         boost = kmalloc(sizeof(*boost), GFP_ATOMIC);
7194         if (boost == NULL)
7195                 return;
7196
7197         i915_gem_request_reference(req);
7198         boost->req = req;
7199
7200         INIT_WORK(&boost->work, __intel_rps_boost_work);
7201         queue_work(to_i915(dev)->wq, &boost->work);
7202 }
7203
7204 void intel_pm_setup(struct drm_device *dev)
7205 {
7206         struct drm_i915_private *dev_priv = dev->dev_private;
7207
7208         mutex_init(&dev_priv->rps.hw_lock);
7209         spin_lock_init(&dev_priv->rps.client_lock);
7210
7211         INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
7212                           intel_gen6_powersave_work);
7213         INIT_LIST_HEAD(&dev_priv->rps.clients);
7214         INIT_LIST_HEAD(&dev_priv->rps.semaphores.link);
7215         INIT_LIST_HEAD(&dev_priv->rps.mmioflips.link);
7216
7217         dev_priv->pm.suspended = false;
7218 }