drivers/tty/serial/omap-serial.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Driver for OMAP-UART controller.
   4  * Based on drivers/serial/8250.c
   5  *
   6  * Copyright (C) 2010 Texas Instruments.
   7  *
   8  * Authors:
   9  *      Govindraj R     <[email protected]>
  10  *      Thara Gopinath  <[email protected]>
  11  *
  12  * Note: This driver is made separate from 8250 driver as we cannot
  13  * over load 8250 driver with omap platform specific configuration for
  14  * features like DMA, it makes easier to implement features like DMA and
  15  * hardware flow control and software flow control configuration with
  16  * this driver as required for the omap-platform.
  17  */
  18
  19 #include <linux/module.h>
  20 #include <linux/init.h>
  21 #include <linux/console.h>
  22 #include <linux/serial.h>
  23 #include <linux/serial_reg.h>
  24 #include <linux/delay.h>
  25 #include <linux/slab.h>
  26 #include <linux/tty.h>
  27 #include <linux/tty_flip.h>
  28 #include <linux/platform_device.h>
  29 #include <linux/io.h>
  30 #include <linux/clk.h>
  31 #include <linux/serial_core.h>
  32 #include <linux/irq.h>
  33 #include <linux/pm_runtime.h>
  34 #include <linux/pm_wakeirq.h>
  35 #include <linux/of.h>
  36 #include <linux/of_irq.h>
  37 #include <linux/gpio/consumer.h>
  38 #include <linux/platform_data/serial-omap.h>
  39
  40 #define OMAP_MAX_HSUART_PORTS   10
  41
  42 #define UART_BUILD_REVISION(x, y)       (((x) << 8) | (y))
  43
  44 #define OMAP_UART_REV_42 0x0402
  45 #define OMAP_UART_REV_46 0x0406
  46 #define OMAP_UART_REV_52 0x0502
  47 #define OMAP_UART_REV_63 0x0603
  48
  49 #define OMAP_UART_TX_WAKEUP_EN          BIT(7)
  50
  51 /* Feature flags */
  52 #define OMAP_UART_WER_HAS_TX_WAKEUP     BIT(0)
  53
  54 #define UART_ERRATA_i202_MDR1_ACCESS    BIT(0)
  55 #define UART_ERRATA_i291_DMA_FORCEIDLE  BIT(1)
  56
  57 #define DEFAULT_CLK_SPEED 48000000 /* 48Mhz */
  58
  59 /* SCR register bitmasks */
  60 #define OMAP_UART_SCR_RX_TRIG_GRANU1_MASK               (1 << 7)
  61 #define OMAP_UART_SCR_TX_TRIG_GRANU1_MASK               (1 << 6)
  62 #define OMAP_UART_SCR_TX_EMPTY                  (1 << 3)
  63
  64 /* FCR register bitmasks */
  65 #define OMAP_UART_FCR_RX_FIFO_TRIG_MASK                 (0x3 << 6)
  66 #define OMAP_UART_FCR_TX_FIFO_TRIG_MASK                 (0x3 << 4)
  67
  68 /* MVR register bitmasks */
  69 #define OMAP_UART_MVR_SCHEME_SHIFT      30
  70
  71 #define OMAP_UART_LEGACY_MVR_MAJ_MASK   0xf0
  72 #define OMAP_UART_LEGACY_MVR_MAJ_SHIFT  4
  73 #define OMAP_UART_LEGACY_MVR_MIN_MASK   0x0f
  74
  75 #define OMAP_UART_MVR_MAJ_MASK          0x700
  76 #define OMAP_UART_MVR_MAJ_SHIFT         8
  77 #define OMAP_UART_MVR_MIN_MASK          0x3f
  78
  79 #define OMAP_UART_DMA_CH_FREE   -1
  80
  81 #define MSR_SAVE_FLAGS          UART_MSR_ANY_DELTA
  82 #define OMAP_MODE13X_SPEED      230400
  83
  84 /* WER = 0x7F
  85  * Enable module level wakeup in WER reg
  86  */
  87 #define OMAP_UART_WER_MOD_WKUP  0x7F
  88
  89 /* Enable XON/XOFF flow control on output */
  90 #define OMAP_UART_SW_TX         0x08
  91
  92 /* Enable XON/XOFF flow control on input */
  93 #define OMAP_UART_SW_RX         0x02
  94
  95 #define OMAP_UART_SW_CLR        0xF0
  96
  97 #define OMAP_UART_TCR_TRIG      0x0F
  98
  99 struct uart_omap_dma {
 100         u8                      uart_dma_tx;
 101         u8                      uart_dma_rx;
 102         int                     rx_dma_channel;
 103         int                     tx_dma_channel;
 104         dma_addr_t              rx_buf_dma_phys;
 105         dma_addr_t              tx_buf_dma_phys;
 106         unsigned int            uart_base;
 107         /*
 108          * Buffer for rx dma. It is not required for tx because the buffer
 109          * comes from port structure.
 110          */
 111         unsigned char           *rx_buf;
 112         unsigned int            prev_rx_dma_pos;
 113         int                     tx_buf_size;
 114         int                     tx_dma_used;
 115         int                     rx_dma_used;
 116         spinlock_t              tx_lock;
 117         spinlock_t              rx_lock;
 118         /* timer to poll activity on rx dma */
 119         struct timer_list       rx_timer;
 120         unsigned int            rx_buf_size;
 121         unsigned int            rx_poll_rate;
 122         unsigned int            rx_timeout;
 123 };
 124
 125 struct uart_omap_port {
 126         struct uart_port        port;
 127         struct uart_omap_dma    uart_dma;
 128         struct device           *dev;
 129         int                     wakeirq;
 130
 131         unsigned char           ier;
 132         unsigned char           lcr;
 133         unsigned char           mcr;
 134         unsigned char           fcr;
 135         unsigned char           efr;
 136         unsigned char           dll;
 137         unsigned char           dlh;
 138         unsigned char           mdr1;
 139         unsigned char           scr;
 140         unsigned char           wer;
 141
 142         int                     use_dma;
 143         /*
 144          * Some bits in registers are cleared on a read, so they must
 145          * be saved whenever the register is read, but the bits will not
 146          * be immediately processed.
 147          */
 148         unsigned int            lsr_break_flag;
 149         unsigned char           msr_saved_flags;
 150         char                    name[20];
 151         unsigned long           port_activity;
 152         int                     context_loss_cnt;
 153         u32                     errata;
 154         u32                     features;
 155
 156         struct gpio_desc        *rts_gpiod;
 157
 158         struct pm_qos_request   pm_qos_request;
 159         u32                     latency;
 160         u32                     calc_latency;
 161         struct work_struct      qos_work;
 162         bool                    is_suspending;
 163
 164         unsigned int            rs485_tx_filter_count;
 165 };
 166
 167 #define to_uart_omap_port(p) ((container_of((p), struct uart_omap_port, port)))
 168
 169 static struct uart_omap_port *ui[OMAP_MAX_HSUART_PORTS];
 170
 171 /* Forward declaration of functions */
 172 static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1);
 173
 174 static inline unsigned int serial_in(struct uart_omap_port *up, int offset)
 175 {
 176         offset <<= up->port.regshift;
 177         return readw(up->port.membase + offset);
 178 }
 179
 180 static inline void serial_out(struct uart_omap_port *up, int offset, int value)
 181 {
 182         offset <<= up->port.regshift;
 183         writew(value, up->port.membase + offset);
 184 }
 185
 186 static inline void serial_omap_clear_fifos(struct uart_omap_port *up)
 187 {
 188         serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO);
 189         serial_out(up, UART_FCR, UART_FCR_ENABLE_FIFO |
 190                        UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT);
 191         serial_out(up, UART_FCR, 0);
 192 }
 193
 194 #ifdef CONFIG_PM
 195 static int serial_omap_get_context_loss_count(struct uart_omap_port *up)
 196 {
 197         struct omap_uart_port_info *pdata = dev_get_platdata(up->dev);
 198
 199         if (!pdata || !pdata->get_context_loss_count)
 200                 return -EINVAL;
 201
 202         return pdata->get_context_loss_count(up->dev);
 203 }
 204
 205 /* REVISIT: Remove this when omap3 boots in device tree only mode */
 206 static void serial_omap_enable_wakeup(struct uart_omap_port *up, bool enable)
 207 {
 208         struct omap_uart_port_info *pdata = dev_get_platdata(up->dev);
 209
 210         if (!pdata || !pdata->enable_wakeup)
 211                 return;
 212
 213         pdata->enable_wakeup(up->dev, enable);
 214 }
 215 #endif /* CONFIG_PM */
 216
 217 /*
 218  * Calculate the absolute difference between the desired and actual baud
 219  * rate for the given mode.
 220  */
 221 static inline int calculate_baud_abs_diff(struct uart_port *port,
 222                                 unsigned int baud, unsigned int mode)
 223 {
 224         unsigned int n = port->uartclk / (mode * baud);
 225         int abs_diff;
 226
 227         if (n == 0)
 228                 n = 1;
 229
 230         abs_diff = baud - (port->uartclk / (mode * n));
 231         if (abs_diff < 0)
 232                 abs_diff = -abs_diff;
 233
 234         return abs_diff;
 235 }
 236
 237 /*
 238  * serial_omap_baud_is_mode16 - check if baud rate is MODE16X
 239  * @port: uart port info
 240  * @baud: baudrate for which mode needs to be determined
 241  *
 242  * Returns true if baud rate is MODE16X and false if MODE13X
 243  * Original table in OMAP TRM named "UART Mode Baud Rates, Divisor Values,
 244  * and Error Rates" determines modes not for all common baud rates.
 245  * E.g. for 1000000 baud rate mode must be 16x, but according to that
 246  * table it's determined as 13x.
 247  */
 248 static bool
 249 serial_omap_baud_is_mode16(struct uart_port *port, unsigned int baud)
 250 {
 251         int abs_diff_13 = calculate_baud_abs_diff(port, baud, 13);
 252         int abs_diff_16 = calculate_baud_abs_diff(port, baud, 16);
 253
 254         return (abs_diff_13 >= abs_diff_16);
 255 }
 256
 257 /*
 258  * serial_omap_get_divisor - calculate divisor value
 259  * @port: uart port info
 260  * @baud: baudrate for which divisor needs to be calculated.
 261  */
 262 static unsigned int
 263 serial_omap_get_divisor(struct uart_port *port, unsigned int baud)
 264 {
 265         unsigned int mode;
 266
 267         if (!serial_omap_baud_is_mode16(port, baud))
 268                 mode = 13;
 269         else
 270                 mode = 16;
 271         return port->uartclk/(mode * baud);
 272 }
 273
 274 static void serial_omap_enable_ms(struct uart_port *port)
 275 {
 276         struct uart_omap_port *up = to_uart_omap_port(port);
 277
 278         dev_dbg(up->port.dev, "serial_omap_enable_ms+%d\n", up->port.line);
 279
 280         up->ier |= UART_IER_MSI;
 281         serial_out(up, UART_IER, up->ier);
 282 }
 283
 284 static void serial_omap_stop_tx(struct uart_port *port)
 285 {
 286         struct uart_omap_port *up = to_uart_omap_port(port);
 287         int res;
 288
 289         /* Handle RS-485 */
 290         if (port->rs485.flags & SER_RS485_ENABLED) {
 291                 if (up->scr & OMAP_UART_SCR_TX_EMPTY) {
 292                         /* THR interrupt is fired when both TX FIFO and TX
 293                          * shift register are empty. This means there's nothing
 294                          * left to transmit now, so make sure the THR interrupt
 295                          * is fired when TX FIFO is below the trigger level,
 296                          * disable THR interrupts and toggle the RS-485 GPIO
 297                          * data direction pin if needed.
 298                          */
 299                         up->scr &= ~OMAP_UART_SCR_TX_EMPTY;
 300                         serial_out(up, UART_OMAP_SCR, up->scr);
 301                         res = (port->rs485.flags & SER_RS485_RTS_AFTER_SEND) ?
 302                                 1 : 0;
 303                         if (gpiod_get_value(up->rts_gpiod) != res) {
 304                                 if (port->rs485.delay_rts_after_send > 0)
 305                                         mdelay(
 306                                         port->rs485.delay_rts_after_send);
 307                                 gpiod_set_value(up->rts_gpiod, res);
 308                         }
 309                 } else {
 310                         /* We're asked to stop, but there's still stuff in the
 311                          * UART FIFO, so make sure the THR interrupt is fired
 312                          * when both TX FIFO and TX shift register are empty.
 313                          * The next THR interrupt (if no transmission is started
 314                          * in the meantime) will indicate the end of a
 315                          * transmission. Therefore we _don't_ disable THR
 316                          * interrupts in this situation.
 317                          */
 318                         up->scr |= OMAP_UART_SCR_TX_EMPTY;
 319                         serial_out(up, UART_OMAP_SCR, up->scr);
 320                         return;
 321                 }
 322         }
 323
 324         if (up->ier & UART_IER_THRI) {
 325                 up->ier &= ~UART_IER_THRI;
 326                 serial_out(up, UART_IER, up->ier);
 327         }
 328 }
 329
 330 static void serial_omap_stop_rx(struct uart_port *port)
 331 {
 332         struct uart_omap_port *up = to_uart_omap_port(port);
 333
 334         up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
 335         up->port.read_status_mask &= ~UART_LSR_DR;
 336         serial_out(up, UART_IER, up->ier);
 337 }
 338
 339 static void serial_omap_put_char(struct uart_omap_port *up, unsigned char ch)
 340 {
 341         serial_out(up, UART_TX, ch);
 342
 343         if ((up->port.rs485.flags & SER_RS485_ENABLED) &&
 344                         !(up->port.rs485.flags & SER_RS485_RX_DURING_TX))
 345                 up->rs485_tx_filter_count++;
 346 }
 347
 348 static void transmit_chars(struct uart_omap_port *up, unsigned int lsr)
 349 {
 350         struct circ_buf *xmit = &up->port.state->xmit;
 351         int count;
 352
 353         if (up->port.x_char) {
 354                 serial_omap_put_char(up, up->port.x_char);
 355                 up->port.icount.tx++;
 356                 up->port.x_char = 0;
 357                 return;
 358         }
 359         if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) {
 360                 serial_omap_stop_tx(&up->port);
 361                 return;
 362         }
 363         count = up->port.fifosize / 4;
 364         do {
 365                 serial_omap_put_char(up, xmit->buf[xmit->tail]);
 366                 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
 367                 up->port.icount.tx++;
 368
 369                 if (uart_circ_empty(xmit))
 370                         break;
 371         } while (--count > 0);
 372
 373         if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
 374                 uart_write_wakeup(&up->port);
 375
 376         if (uart_circ_empty(xmit))
 377                 serial_omap_stop_tx(&up->port);
 378 }
 379
 380 static inline void serial_omap_enable_ier_thri(struct uart_omap_port *up)
 381 {
 382         if (!(up->ier & UART_IER_THRI)) {
 383                 up->ier |= UART_IER_THRI;
 384                 serial_out(up, UART_IER, up->ier);
 385         }
 386 }
 387
 388 static void serial_omap_start_tx(struct uart_port *port)
 389 {
 390         struct uart_omap_port *up = to_uart_omap_port(port);
 391         int res;
 392
 393         /* Handle RS-485 */
 394         if (port->rs485.flags & SER_RS485_ENABLED) {
 395                 /* Fire THR interrupts when FIFO is below trigger level */
 396                 up->scr &= ~OMAP_UART_SCR_TX_EMPTY;
 397                 serial_out(up, UART_OMAP_SCR, up->scr);
 398
 399                 /* if rts not already enabled */
 400                 res = (port->rs485.flags & SER_RS485_RTS_ON_SEND) ? 1 : 0;
 401                 if (gpiod_get_value(up->rts_gpiod) != res) {
 402                         gpiod_set_value(up->rts_gpiod, res);
 403                         if (port->rs485.delay_rts_before_send > 0)
 404                                 mdelay(port->rs485.delay_rts_before_send);
 405                 }
 406         }
 407
 408         if ((port->rs485.flags & SER_RS485_ENABLED) &&
 409             !(port->rs485.flags & SER_RS485_RX_DURING_TX))
 410                 up->rs485_tx_filter_count = 0;
 411
 412         serial_omap_enable_ier_thri(up);
 413 }
 414
 415 static void serial_omap_throttle(struct uart_port *port)
 416 {
 417         struct uart_omap_port *up = to_uart_omap_port(port);
 418         unsigned long flags;
 419
 420         spin_lock_irqsave(&up->port.lock, flags);
 421         up->ier &= ~(UART_IER_RLSI | UART_IER_RDI);
 422         serial_out(up, UART_IER, up->ier);
 423         spin_unlock_irqrestore(&up->port.lock, flags);
 424 }
 425
 426 static void serial_omap_unthrottle(struct uart_port *port)
 427 {
 428         struct uart_omap_port *up = to_uart_omap_port(port);
 429         unsigned long flags;
 430
 431         spin_lock_irqsave(&up->port.lock, flags);
 432         up->ier |= UART_IER_RLSI | UART_IER_RDI;
 433         serial_out(up, UART_IER, up->ier);
 434         spin_unlock_irqrestore(&up->port.lock, flags);
 435 }
 436
 437 static unsigned int check_modem_status(struct uart_omap_port *up)
 438 {
 439         unsigned int status;
 440
 441         status = serial_in(up, UART_MSR);
 442         status |= up->msr_saved_flags;
 443         up->msr_saved_flags = 0;
 444         if ((status & UART_MSR_ANY_DELTA) == 0)
 445                 return status;
 446
 447         if (status & UART_MSR_ANY_DELTA && up->ier & UART_IER_MSI &&
 448             up->port.state != NULL) {
 449                 if (status & UART_MSR_TERI)
 450                         up->port.icount.rng++;
 451                 if (status & UART_MSR_DDSR)
 452                         up->port.icount.dsr++;
 453                 if (status & UART_MSR_DDCD)
 454                         uart_handle_dcd_change
 455                                 (&up->port, status & UART_MSR_DCD);
 456                 if (status & UART_MSR_DCTS)
 457                         uart_handle_cts_change
 458                                 (&up->port, status & UART_MSR_CTS);
 459                 wake_up_interruptible(&up->port.state->port.delta_msr_wait);
 460         }
 461
 462         return status;
 463 }
 464
 465 static void serial_omap_rlsi(struct uart_omap_port *up, unsigned int lsr)
 466 {
 467         unsigned int flag;
 468
 469         /*
 470          * Read one data character out to avoid stalling the receiver according
 471          * to the table 23-246 of the omap4 TRM.
 472          */
 473         if (likely(lsr & UART_LSR_DR)) {
 474                 serial_in(up, UART_RX);
 475                 if ((up->port.rs485.flags & SER_RS485_ENABLED) &&
 476                     !(up->port.rs485.flags & SER_RS485_RX_DURING_TX) &&
 477                     up->rs485_tx_filter_count)
 478                         up->rs485_tx_filter_count--;
 479         }
 480
 481         up->port.icount.rx++;
 482         flag = TTY_NORMAL;
 483
 484         if (lsr & UART_LSR_BI) {
 485                 flag = TTY_BREAK;
 486                 lsr &= ~(UART_LSR_FE | UART_LSR_PE);
 487                 up->port.icount.brk++;
 488                 /*
 489                  * We do the SysRQ and SAK checking
 490                  * here because otherwise the break
 491                  * may get masked by ignore_status_mask
 492                  * or read_status_mask.
 493                  */
 494                 if (uart_handle_break(&up->port))
 495                         return;
 496
 497         }
 498
 499         if (lsr & UART_LSR_PE) {
 500                 flag = TTY_PARITY;
 501                 up->port.icount.parity++;
 502         }
 503
 504         if (lsr & UART_LSR_FE) {
 505                 flag = TTY_FRAME;
 506                 up->port.icount.frame++;
 507         }
 508
 509         if (lsr & UART_LSR_OE)
 510                 up->port.icount.overrun++;
 511
 512 #ifdef CONFIG_SERIAL_OMAP_CONSOLE
 513         if (up->port.line == up->port.cons->index) {
 514                 /* Recover the break flag from console xmit */
 515                 lsr |= up->lsr_break_flag;
 516         }
 517 #endif
 518         uart_insert_char(&up->port, lsr, UART_LSR_OE, 0, flag);
 519 }
 520
 521 static void serial_omap_rdi(struct uart_omap_port *up, unsigned int lsr)
 522 {
 523         unsigned char ch = 0;
 524         unsigned int flag;
 525
 526         if (!(lsr & UART_LSR_DR))
 527                 return;
 528
 529         ch = serial_in(up, UART_RX);
 530         if ((up->port.rs485.flags & SER_RS485_ENABLED) &&
 531             !(up->port.rs485.flags & SER_RS485_RX_DURING_TX) &&
 532             up->rs485_tx_filter_count) {
 533                 up->rs485_tx_filter_count--;
 534                 return;
 535         }
 536
 537         flag = TTY_NORMAL;
 538         up->port.icount.rx++;
 539
 540         if (uart_handle_sysrq_char(&up->port, ch))
 541                 return;
 542
 543         uart_insert_char(&up->port, lsr, UART_LSR_OE, ch, flag);
 544 }
 545
 546 /**
 547  * serial_omap_irq() - This handles the interrupt from one port
 548  * @irq: uart port irq number
 549  * @dev_id: uart port info
 550  */
 551 static irqreturn_t serial_omap_irq(int irq, void *dev_id)
 552 {
 553         struct uart_omap_port *up = dev_id;
 554         unsigned int iir, lsr;
 555         unsigned int type;
 556         irqreturn_t ret = IRQ_NONE;
 557         int max_count = 256;
 558
 559         spin_lock(&up->port.lock);
 560
 561         do {
 562                 iir = serial_in(up, UART_IIR);
 563                 if (iir & UART_IIR_NO_INT)
 564                         break;
 565
 566                 ret = IRQ_HANDLED;
 567                 lsr = serial_in(up, UART_LSR);
 568
 569                 /* extract IRQ type from IIR register */
 570                 type = iir & 0x3e;
 571
 572                 switch (type) {
 573                 case UART_IIR_MSI:
 574                         check_modem_status(up);
 575                         break;
 576                 case UART_IIR_THRI:
 577                         transmit_chars(up, lsr);
 578                         break;
 579                 case UART_IIR_RX_TIMEOUT:
 580                 case UART_IIR_RDI:
 581                         serial_omap_rdi(up, lsr);
 582                         break;
 583                 case UART_IIR_RLSI:
 584                         serial_omap_rlsi(up, lsr);
 585                         break;
 586                 case UART_IIR_CTS_RTS_DSR:
 587                         /* simply try again */
 588                         break;
 589                 case UART_IIR_XOFF:
 590                 default:
 591                         break;
 592                 }
 593         } while (max_count--);
 594
 595         spin_unlock(&up->port.lock);
 596
 597         tty_flip_buffer_push(&up->port.state->port);
 598
 599         up->port_activity = jiffies;
 600
 601         return ret;
 602 }
 603
 604 static unsigned int serial_omap_tx_empty(struct uart_port *port)
 605 {
 606         struct uart_omap_port *up = to_uart_omap_port(port);
 607         unsigned long flags;
 608         unsigned int ret = 0;
 609
 610         dev_dbg(up->port.dev, "serial_omap_tx_empty+%d\n", up->port.line);
 611         spin_lock_irqsave(&up->port.lock, flags);
 612         ret = serial_in(up, UART_LSR) & UART_LSR_TEMT ? TIOCSER_TEMT : 0;
 613         spin_unlock_irqrestore(&up->port.lock, flags);
 614
 615         return ret;
 616 }
 617
 618 static unsigned int serial_omap_get_mctrl(struct uart_port *port)
 619 {
 620         struct uart_omap_port *up = to_uart_omap_port(port);
 621         unsigned int status;
 622         unsigned int ret = 0;
 623
 624         status = check_modem_status(up);
 625
 626         dev_dbg(up->port.dev, "serial_omap_get_mctrl+%d\n", up->port.line);
 627
 628         if (status & UART_MSR_DCD)
 629                 ret |= TIOCM_CAR;
 630         if (status & UART_MSR_RI)
 631                 ret |= TIOCM_RNG;
 632         if (status & UART_MSR_DSR)
 633                 ret |= TIOCM_DSR;
 634         if (status & UART_MSR_CTS)
 635                 ret |= TIOCM_CTS;
 636         return ret;
 637 }
 638
 639 static void serial_omap_set_mctrl(struct uart_port *port, unsigned int mctrl)
 640 {
 641         struct uart_omap_port *up = to_uart_omap_port(port);
 642         unsigned char mcr = 0, old_mcr, lcr;
 643
 644         dev_dbg(up->port.dev, "serial_omap_set_mctrl+%d\n", up->port.line);
 645         if (mctrl & TIOCM_RTS)
 646                 mcr |= UART_MCR_RTS;
 647         if (mctrl & TIOCM_DTR)
 648                 mcr |= UART_MCR_DTR;
 649         if (mctrl & TIOCM_OUT1)
 650                 mcr |= UART_MCR_OUT1;
 651         if (mctrl & TIOCM_OUT2)
 652                 mcr |= UART_MCR_OUT2;
 653         if (mctrl & TIOCM_LOOP)
 654                 mcr |= UART_MCR_LOOP;
 655
 656         old_mcr = serial_in(up, UART_MCR);
 657         old_mcr &= ~(UART_MCR_LOOP | UART_MCR_OUT2 | UART_MCR_OUT1 |
 658                      UART_MCR_DTR | UART_MCR_RTS);
 659         up->mcr = old_mcr | mcr;
 660         serial_out(up, UART_MCR, up->mcr);
 661
 662         /* Turn off autoRTS if RTS is lowered; restore autoRTS if RTS raised */
 663         lcr = serial_in(up, UART_LCR);
 664         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 665         if ((mctrl & TIOCM_RTS) && (port->status & UPSTAT_AUTORTS))
 666                 up->efr |= UART_EFR_RTS;
 667         else
 668                 up->efr &= ~UART_EFR_RTS;
 669         serial_out(up, UART_EFR, up->efr);
 670         serial_out(up, UART_LCR, lcr);
 671 }
 672
 673 static void serial_omap_break_ctl(struct uart_port *port, int break_state)
 674 {
 675         struct uart_omap_port *up = to_uart_omap_port(port);
 676         unsigned long flags;
 677
 678         dev_dbg(up->port.dev, "serial_omap_break_ctl+%d\n", up->port.line);
 679         spin_lock_irqsave(&up->port.lock, flags);
 680         if (break_state == -1)
 681                 up->lcr |= UART_LCR_SBC;
 682         else
 683                 up->lcr &= ~UART_LCR_SBC;
 684         serial_out(up, UART_LCR, up->lcr);
 685         spin_unlock_irqrestore(&up->port.lock, flags);
 686 }
 687
 688 static int serial_omap_startup(struct uart_port *port)
 689 {
 690         struct uart_omap_port *up = to_uart_omap_port(port);
 691         unsigned long flags;
 692         int retval;
 693
 694         /*
 695          * Allocate the IRQ
 696          */
 697         retval = request_irq(up->port.irq, serial_omap_irq, up->port.irqflags,
 698                                 up->name, up);
 699         if (retval)
 700                 return retval;
 701
 702         /* Optional wake-up IRQ */
 703         if (up->wakeirq) {
 704                 retval = dev_pm_set_dedicated_wake_irq(up->dev, up->wakeirq);
 705                 if (retval) {
 706                         free_irq(up->port.irq, up);
 707                         return retval;
 708                 }
 709         }
 710
 711         dev_dbg(up->port.dev, "serial_omap_startup+%d\n", up->port.line);
 712
 713         pm_runtime_get_sync(up->dev);
 714         /*
 715          * Clear the FIFO buffers and disable them.
 716          * (they will be reenabled in set_termios())
 717          */
 718         serial_omap_clear_fifos(up);
 719
 720         /*
 721          * Clear the interrupt registers.
 722          */
 723         (void) serial_in(up, UART_LSR);
 724         if (serial_in(up, UART_LSR) & UART_LSR_DR)
 725                 (void) serial_in(up, UART_RX);
 726         (void) serial_in(up, UART_IIR);
 727         (void) serial_in(up, UART_MSR);
 728
 729         /*
 730          * Now, initialize the UART
 731          */
 732         serial_out(up, UART_LCR, UART_LCR_WLEN8);
 733         spin_lock_irqsave(&up->port.lock, flags);
 734         /*
 735          * Most PC uarts need OUT2 raised to enable interrupts.
 736          */
 737         up->port.mctrl |= TIOCM_OUT2;
 738         serial_omap_set_mctrl(&up->port, up->port.mctrl);
 739         spin_unlock_irqrestore(&up->port.lock, flags);
 740
 741         up->msr_saved_flags = 0;
 742         /*
 743          * Finally, enable interrupts. Note: Modem status interrupts
 744          * are set via set_termios(), which will be occurring imminently
 745          * anyway, so we don't enable them here.
 746          */
 747         up->ier = UART_IER_RLSI | UART_IER_RDI;
 748         serial_out(up, UART_IER, up->ier);
 749
 750         /* Enable module level wake up */
 751         up->wer = OMAP_UART_WER_MOD_WKUP;
 752         if (up->features & OMAP_UART_WER_HAS_TX_WAKEUP)
 753                 up->wer |= OMAP_UART_TX_WAKEUP_EN;
 754
 755         serial_out(up, UART_OMAP_WER, up->wer);
 756
 757         up->port_activity = jiffies;
 758         return 0;
 759 }
 760
 761 static void serial_omap_shutdown(struct uart_port *port)
 762 {
 763         struct uart_omap_port *up = to_uart_omap_port(port);
 764         unsigned long flags;
 765
 766         dev_dbg(up->port.dev, "serial_omap_shutdown+%d\n", up->port.line);
 767
 768         /*
 769          * Disable interrupts from this port
 770          */
 771         up->ier = 0;
 772         serial_out(up, UART_IER, 0);
 773
 774         spin_lock_irqsave(&up->port.lock, flags);
 775         up->port.mctrl &= ~TIOCM_OUT2;
 776         serial_omap_set_mctrl(&up->port, up->port.mctrl);
 777         spin_unlock_irqrestore(&up->port.lock, flags);
 778
 779         /*
 780          * Disable break condition and FIFOs
 781          */
 782         serial_out(up, UART_LCR, serial_in(up, UART_LCR) & ~UART_LCR_SBC);
 783         serial_omap_clear_fifos(up);
 784
 785         /*
 786          * Read data port to reset things, and then free the irq
 787          */
 788         if (serial_in(up, UART_LSR) & UART_LSR_DR)
 789                 (void) serial_in(up, UART_RX);
 790
 791         pm_runtime_put_sync(up->dev);
 792         free_irq(up->port.irq, up);
 793         dev_pm_clear_wake_irq(up->dev);
 794 }
 795
 796 static void serial_omap_uart_qos_work(struct work_struct *work)
 797 {
 798         struct uart_omap_port *up = container_of(work, struct uart_omap_port,
 799                                                 qos_work);
 800
 801         cpu_latency_qos_update_request(&up->pm_qos_request, up->latency);
 802 }
 803
 804 static void
 805 serial_omap_set_termios(struct uart_port *port, struct ktermios *termios,
 806                         const struct ktermios *old)
 807 {
 808         struct uart_omap_port *up = to_uart_omap_port(port);
 809         unsigned char cval = 0;
 810         unsigned long flags;
 811         unsigned int baud, quot;
 812
 813         cval = UART_LCR_WLEN(tty_get_char_size(termios->c_cflag));
 814
 815         if (termios->c_cflag & CSTOPB)
 816                 cval |= UART_LCR_STOP;
 817         if (termios->c_cflag & PARENB)
 818                 cval |= UART_LCR_PARITY;
 819         if (!(termios->c_cflag & PARODD))
 820                 cval |= UART_LCR_EPAR;
 821         if (termios->c_cflag & CMSPAR)
 822                 cval |= UART_LCR_SPAR;
 823
 824         /*
 825          * Ask the core to calculate the divisor for us.
 826          */
 827
 828         baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/13);
 829         quot = serial_omap_get_divisor(port, baud);
 830
 831         /* calculate wakeup latency constraint */
 832         up->calc_latency = (USEC_PER_SEC * up->port.fifosize) / (baud / 8);
 833         up->latency = up->calc_latency;
 834         schedule_work(&up->qos_work);
 835
 836         up->dll = quot & 0xff;
 837         up->dlh = quot >> 8;
 838         up->mdr1 = UART_OMAP_MDR1_DISABLE;
 839
 840         up->fcr = UART_FCR_R_TRIG_01 | UART_FCR_T_TRIG_01 |
 841                         UART_FCR_ENABLE_FIFO;
 842
 843         /*
 844          * Ok, we're now changing the port state. Do it with
 845          * interrupts disabled.
 846          */
 847         spin_lock_irqsave(&up->port.lock, flags);
 848
 849         /*
 850          * Update the per-port timeout.
 851          */
 852         uart_update_timeout(port, termios->c_cflag, baud);
 853
 854         up->port.read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR;
 855         if (termios->c_iflag & INPCK)
 856                 up->port.read_status_mask |= UART_LSR_FE | UART_LSR_PE;
 857         if (termios->c_iflag & (BRKINT | PARMRK))
 858                 up->port.read_status_mask |= UART_LSR_BI;
 859
 860         /*
 861          * Characters to ignore
 862          */
 863         up->port.ignore_status_mask = 0;
 864         if (termios->c_iflag & IGNPAR)
 865                 up->port.ignore_status_mask |= UART_LSR_PE | UART_LSR_FE;
 866         if (termios->c_iflag & IGNBRK) {
 867                 up->port.ignore_status_mask |= UART_LSR_BI;
 868                 /*
 869                  * If we're ignoring parity and break indicators,
 870                  * ignore overruns too (for real raw support).
 871                  */
 872                 if (termios->c_iflag & IGNPAR)
 873                         up->port.ignore_status_mask |= UART_LSR_OE;
 874         }
 875
 876         /*
 877          * ignore all characters if CREAD is not set
 878          */
 879         if ((termios->c_cflag & CREAD) == 0)
 880                 up->port.ignore_status_mask |= UART_LSR_DR;
 881
 882         /*
 883          * Modem status interrupts
 884          */
 885         up->ier &= ~UART_IER_MSI;
 886         if (UART_ENABLE_MS(&up->port, termios->c_cflag))
 887                 up->ier |= UART_IER_MSI;
 888         serial_out(up, UART_IER, up->ier);
 889         serial_out(up, UART_LCR, cval);         /* reset DLAB */
 890         up->lcr = cval;
 891         up->scr = 0;
 892
 893         /* FIFOs and DMA Settings */
 894
 895         /* FCR can be changed only when the
 896          * baud clock is not running
 897          * DLL_REG and DLH_REG set to 0.
 898          */
 899         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
 900         serial_out(up, UART_DLL, 0);
 901         serial_out(up, UART_DLM, 0);
 902         serial_out(up, UART_LCR, 0);
 903
 904         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 905
 906         up->efr = serial_in(up, UART_EFR) & ~UART_EFR_ECB;
 907         up->efr &= ~UART_EFR_SCD;
 908         serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
 909
 910         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
 911         up->mcr = serial_in(up, UART_MCR) & ~UART_MCR_TCRTLR;
 912         serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
 913         /* FIFO ENABLE, DMA MODE */
 914
 915         up->scr |= OMAP_UART_SCR_RX_TRIG_GRANU1_MASK;
 916         /*
 917          * NOTE: Setting OMAP_UART_SCR_RX_TRIG_GRANU1_MASK
 918          * sets Enables the granularity of 1 for TRIGGER RX
 919          * level. Along with setting RX FIFO trigger level
 920          * to 1 (as noted below, 16 characters) and TLR[3:0]
 921          * to zero this will result RX FIFO threshold level
 922          * to 1 character, instead of 16 as noted in comment
 923          * below.
 924          */
 925
 926         /* Set receive FIFO threshold to 16 characters and
 927          * transmit FIFO threshold to 32 spaces
 928          */
 929         up->fcr &= ~OMAP_UART_FCR_RX_FIFO_TRIG_MASK;
 930         up->fcr &= ~OMAP_UART_FCR_TX_FIFO_TRIG_MASK;
 931         up->fcr |= UART_FCR6_R_TRIGGER_16 | UART_FCR6_T_TRIGGER_24 |
 932                 UART_FCR_ENABLE_FIFO;
 933
 934         serial_out(up, UART_FCR, up->fcr);
 935         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 936
 937         serial_out(up, UART_OMAP_SCR, up->scr);
 938
 939         /* Reset UART_MCR_TCRTLR: this must be done with the EFR_ECB bit set */
 940         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
 941         serial_out(up, UART_MCR, up->mcr);
 942         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 943         serial_out(up, UART_EFR, up->efr);
 944         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
 945
 946         /* Protocol, Baud Rate, and Interrupt Settings */
 947
 948         if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
 949                 serial_omap_mdr1_errataset(up, up->mdr1);
 950         else
 951                 serial_out(up, UART_OMAP_MDR1, up->mdr1);
 952
 953         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 954         serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
 955
 956         serial_out(up, UART_LCR, 0);
 957         serial_out(up, UART_IER, 0);
 958         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 959
 960         serial_out(up, UART_DLL, up->dll);      /* LS of divisor */
 961         serial_out(up, UART_DLM, up->dlh);      /* MS of divisor */
 962
 963         serial_out(up, UART_LCR, 0);
 964         serial_out(up, UART_IER, up->ier);
 965         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 966
 967         serial_out(up, UART_EFR, up->efr);
 968         serial_out(up, UART_LCR, cval);
 969
 970         if (!serial_omap_baud_is_mode16(port, baud))
 971                 up->mdr1 = UART_OMAP_MDR1_13X_MODE;
 972         else
 973                 up->mdr1 = UART_OMAP_MDR1_16X_MODE;
 974
 975         if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
 976                 serial_omap_mdr1_errataset(up, up->mdr1);
 977         else
 978                 serial_out(up, UART_OMAP_MDR1, up->mdr1);
 979
 980         /* Configure flow control */
 981         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
 982
 983         /* XON1/XOFF1 accessible mode B, TCRTLR=0, ECB=0 */
 984         serial_out(up, UART_XON1, termios->c_cc[VSTART]);
 985         serial_out(up, UART_XOFF1, termios->c_cc[VSTOP]);
 986
 987         /* Enable access to TCR/TLR */
 988         serial_out(up, UART_EFR, up->efr | UART_EFR_ECB);
 989         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
 990         serial_out(up, UART_MCR, up->mcr | UART_MCR_TCRTLR);
 991
 992         serial_out(up, UART_TI752_TCR, OMAP_UART_TCR_TRIG);
 993
 994         up->port.status &= ~(UPSTAT_AUTOCTS | UPSTAT_AUTORTS | UPSTAT_AUTOXOFF);
 995
 996         if (termios->c_cflag & CRTSCTS && up->port.flags & UPF_HARD_FLOW) {
 997                 /* Enable AUTOCTS (autoRTS is enabled when RTS is raised) */
 998                 up->port.status |= UPSTAT_AUTOCTS | UPSTAT_AUTORTS;
 999                 up->efr |= UART_EFR_CTS;
1000         } else {
1001                 /* Disable AUTORTS and AUTOCTS */
1002                 up->efr &= ~(UART_EFR_CTS | UART_EFR_RTS);
1003         }
1004
1005         if (up->port.flags & UPF_SOFT_FLOW) {
1006                 /* clear SW control mode bits */
1007                 up->efr &= OMAP_UART_SW_CLR;
1008
1009                 /*
1010                  * IXON Flag:
1011                  * Enable XON/XOFF flow control on input.
1012                  * Receiver compares XON1, XOFF1.
1013                  */
1014                 if (termios->c_iflag & IXON)
1015                         up->efr |= OMAP_UART_SW_RX;
1016
1017                 /*
1018                  * IXOFF Flag:
1019                  * Enable XON/XOFF flow control on output.
1020                  * Transmit XON1, XOFF1
1021                  */
1022                 if (termios->c_iflag & IXOFF) {
1023                         up->port.status |= UPSTAT_AUTOXOFF;
1024                         up->efr |= OMAP_UART_SW_TX;
1025                 }
1026
1027                 /*
1028                  * IXANY Flag:
1029                  * Enable any character to restart output.
1030                  * Operation resumes after receiving any
1031                  * character after recognition of the XOFF character
1032                  */
1033                 if (termios->c_iflag & IXANY)
1034                         up->mcr |= UART_MCR_XONANY;
1035                 else
1036                         up->mcr &= ~UART_MCR_XONANY;
1037         }
1038         serial_out(up, UART_MCR, up->mcr);
1039         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1040         serial_out(up, UART_EFR, up->efr);
1041         serial_out(up, UART_LCR, up->lcr);
1042
1043         serial_omap_set_mctrl(&up->port, up->port.mctrl);
1044
1045         spin_unlock_irqrestore(&up->port.lock, flags);
1046         dev_dbg(up->port.dev, "serial_omap_set_termios+%d\n", up->port.line);
1047 }
1048
1049 static void
1050 serial_omap_pm(struct uart_port *port, unsigned int state,
1051                unsigned int oldstate)
1052 {
1053         struct uart_omap_port *up = to_uart_omap_port(port);
1054         unsigned char efr;
1055
1056         dev_dbg(up->port.dev, "serial_omap_pm+%d\n", up->port.line);
1057
1058         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1059         efr = serial_in(up, UART_EFR);
1060         serial_out(up, UART_EFR, efr | UART_EFR_ECB);
1061         serial_out(up, UART_LCR, 0);
1062
1063         serial_out(up, UART_IER, (state != 0) ? UART_IERX_SLEEP : 0);
1064         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B);
1065         serial_out(up, UART_EFR, efr);
1066         serial_out(up, UART_LCR, 0);
1067 }
1068
1069 static void serial_omap_release_port(struct uart_port *port)
1070 {
1071         dev_dbg(port->dev, "serial_omap_release_port+\n");
1072 }
1073
1074 static int serial_omap_request_port(struct uart_port *port)
1075 {
1076         dev_dbg(port->dev, "serial_omap_request_port+\n");
1077         return 0;
1078 }
1079
1080 static void serial_omap_config_port(struct uart_port *port, int flags)
1081 {
1082         struct uart_omap_port *up = to_uart_omap_port(port);
1083
1084         dev_dbg(up->port.dev, "serial_omap_config_port+%d\n",
1085                                                         up->port.line);
1086         up->port.type = PORT_OMAP;
1087         up->port.flags |= UPF_SOFT_FLOW | UPF_HARD_FLOW;
1088 }
1089
1090 static int
1091 serial_omap_verify_port(struct uart_port *port, struct serial_struct *ser)
1092 {
1093         /* we don't want the core code to modify any port params */
1094         dev_dbg(port->dev, "serial_omap_verify_port+\n");
1095         return -EINVAL;
1096 }
1097
1098 static const char *
1099 serial_omap_type(struct uart_port *port)
1100 {
1101         struct uart_omap_port *up = to_uart_omap_port(port);
1102
1103         dev_dbg(up->port.dev, "serial_omap_type+%d\n", up->port.line);
1104         return up->name;
1105 }
1106
1107 static void __maybe_unused wait_for_xmitr(struct uart_omap_port *up)
1108 {
1109         unsigned int status, tmout = 10000;
1110
1111         /* Wait up to 10ms for the character(s) to be sent. */
1112         do {
1113                 status = serial_in(up, UART_LSR);
1114
1115                 if (status & UART_LSR_BI)
1116                         up->lsr_break_flag = UART_LSR_BI;
1117
1118                 if (--tmout == 0)
1119                         break;
1120                 udelay(1);
1121         } while (!uart_lsr_tx_empty(status));
1122
1123         /* Wait up to 1s for flow control if necessary */
1124         if (up->port.flags & UPF_CONS_FLOW) {
1125                 tmout = 1000000;
1126                 for (tmout = 1000000; tmout; tmout--) {
1127                         unsigned int msr = serial_in(up, UART_MSR);
1128
1129                         up->msr_saved_flags |= msr & MSR_SAVE_FLAGS;
1130                         if (msr & UART_MSR_CTS)
1131                                 break;
1132
1133                         udelay(1);
1134                 }
1135         }
1136 }
1137
1138 #ifdef CONFIG_CONSOLE_POLL
1139
1140 static void serial_omap_poll_put_char(struct uart_port *port, unsigned char ch)
1141 {
1142         struct uart_omap_port *up = to_uart_omap_port(port);
1143
1144         wait_for_xmitr(up);
1145         serial_out(up, UART_TX, ch);
1146 }
1147
1148 static int serial_omap_poll_get_char(struct uart_port *port)
1149 {
1150         struct uart_omap_port *up = to_uart_omap_port(port);
1151         unsigned int status;
1152
1153         status = serial_in(up, UART_LSR);
1154         if (!(status & UART_LSR_DR)) {
1155                 status = NO_POLL_CHAR;
1156                 goto out;
1157         }
1158
1159         status = serial_in(up, UART_RX);
1160
1161 out:
1162         return status;
1163 }
1164
1165 #endif /* CONFIG_CONSOLE_POLL */
1166
1167 #ifdef CONFIG_SERIAL_OMAP_CONSOLE
1168
1169 #ifdef CONFIG_SERIAL_EARLYCON
1170 static unsigned int omap_serial_early_in(struct uart_port *port, int offset)
1171 {
1172         offset <<= port->regshift;
1173         return readw(port->membase + offset);
1174 }
1175
1176 static void omap_serial_early_out(struct uart_port *port, int offset,
1177                                   int value)
1178 {
1179         offset <<= port->regshift;
1180         writew(value, port->membase + offset);
1181 }
1182
1183 static void omap_serial_early_putc(struct uart_port *port, unsigned char c)
1184 {
1185         unsigned int status;
1186
1187         for (;;) {
1188                 status = omap_serial_early_in(port, UART_LSR);
1189                 if (uart_lsr_tx_empty(status))
1190                         break;
1191                 cpu_relax();
1192         }
1193         omap_serial_early_out(port, UART_TX, c);
1194 }
1195
1196 static void early_omap_serial_write(struct console *console, const char *s,
1197                                     unsigned int count)
1198 {
1199         struct earlycon_device *device = console->data;
1200         struct uart_port *port = &device->port;
1201
1202         uart_console_write(port, s, count, omap_serial_early_putc);
1203 }
1204
1205 static int __init early_omap_serial_setup(struct earlycon_device *device,
1206                                           const char *options)
1207 {
1208         struct uart_port *port = &device->port;
1209
1210         if (!(device->port.membase || device->port.iobase))
1211                 return -ENODEV;
1212
1213         port->regshift = 2;
1214         device->con->write = early_omap_serial_write;
1215         return 0;
1216 }
1217
1218 OF_EARLYCON_DECLARE(omapserial, "ti,omap2-uart", early_omap_serial_setup);
1219 OF_EARLYCON_DECLARE(omapserial, "ti,omap3-uart", early_omap_serial_setup);
1220 OF_EARLYCON_DECLARE(omapserial, "ti,omap4-uart", early_omap_serial_setup);
1221 #endif /* CONFIG_SERIAL_EARLYCON */
1222
1223 static struct uart_omap_port *serial_omap_console_ports[OMAP_MAX_HSUART_PORTS];
1224
1225 static struct uart_driver serial_omap_reg;
1226
1227 static void serial_omap_console_putchar(struct uart_port *port, unsigned char ch)
1228 {
1229         struct uart_omap_port *up = to_uart_omap_port(port);
1230
1231         wait_for_xmitr(up);
1232         serial_out(up, UART_TX, ch);
1233 }
1234
1235 static void
1236 serial_omap_console_write(struct console *co, const char *s,
1237                 unsigned int count)
1238 {
1239         struct uart_omap_port *up = serial_omap_console_ports[co->index];
1240         unsigned long flags;
1241         unsigned int ier;
1242         int locked = 1;
1243
1244         local_irq_save(flags);
1245         if (up->port.sysrq)
1246                 locked = 0;
1247         else if (oops_in_progress)
1248                 locked = spin_trylock(&up->port.lock);
1249         else
1250                 spin_lock(&up->port.lock);
1251
1252         /*
1253          * First save the IER then disable the interrupts
1254          */
1255         ier = serial_in(up, UART_IER);
1256         serial_out(up, UART_IER, 0);
1257
1258         uart_console_write(&up->port, s, count, serial_omap_console_putchar);
1259
1260         /*
1261          * Finally, wait for transmitter to become empty
1262          * and restore the IER
1263          */
1264         wait_for_xmitr(up);
1265         serial_out(up, UART_IER, ier);
1266         /*
1267          * The receive handling will happen properly because the
1268          * receive ready bit will still be set; it is not cleared
1269          * on read.  However, modem control will not, we must
1270          * call it if we have saved something in the saved flags
1271          * while processing with interrupts off.
1272          */
1273         if (up->msr_saved_flags)
1274                 check_modem_status(up);
1275
1276         if (locked)
1277                 spin_unlock(&up->port.lock);
1278         local_irq_restore(flags);
1279 }
1280
1281 static int __init
1282 serial_omap_console_setup(struct console *co, char *options)
1283 {
1284         struct uart_omap_port *up;
1285         int baud = 115200;
1286         int bits = 8;
1287         int parity = 'n';
1288         int flow = 'n';
1289
1290         if (serial_omap_console_ports[co->index] == NULL)
1291                 return -ENODEV;
1292         up = serial_omap_console_ports[co->index];
1293
1294         if (options)
1295                 uart_parse_options(options, &baud, &parity, &bits, &flow);
1296
1297         return uart_set_options(&up->port, co, baud, parity, bits, flow);
1298 }
1299
1300 static struct console serial_omap_console = {
1301         .name           = OMAP_SERIAL_NAME,
1302         .write          = serial_omap_console_write,
1303         .device         = uart_console_device,
1304         .setup          = serial_omap_console_setup,
1305         .flags          = CON_PRINTBUFFER,
1306         .index          = -1,
1307         .data           = &serial_omap_reg,
1308 };
1309
1310 static void serial_omap_add_console_port(struct uart_omap_port *up)
1311 {
1312         serial_omap_console_ports[up->port.line] = up;
1313 }
1314
1315 #define OMAP_CONSOLE    (&serial_omap_console)
1316
1317 #else
1318
1319 #define OMAP_CONSOLE    NULL
1320
1321 static inline void serial_omap_add_console_port(struct uart_omap_port *up)
1322 {}
1323
1324 #endif
1325
1326 /* Enable or disable the rs485 support */
1327 static int
1328 serial_omap_config_rs485(struct uart_port *port, struct ktermios *termios,
1329                          struct serial_rs485 *rs485)
1330 {
1331         struct uart_omap_port *up = to_uart_omap_port(port);
1332         unsigned int mode;
1333         int val;
1334
1335         /* Disable interrupts from this port */
1336         mode = up->ier;
1337         up->ier = 0;
1338         serial_out(up, UART_IER, 0);
1339
1340         /* enable / disable rts */
1341         val = (rs485->flags & SER_RS485_ENABLED) ?
1342               SER_RS485_RTS_AFTER_SEND : SER_RS485_RTS_ON_SEND;
1343         val = (rs485->flags & val) ? 1 : 0;
1344         gpiod_set_value(up->rts_gpiod, val);
1345
1346         /* Enable interrupts */
1347         up->ier = mode;
1348         serial_out(up, UART_IER, up->ier);
1349
1350         /* If RS-485 is disabled, make sure the THR interrupt is fired when
1351          * TX FIFO is below the trigger level.
1352          */
1353         if (!(rs485->flags & SER_RS485_ENABLED) &&
1354             (up->scr & OMAP_UART_SCR_TX_EMPTY)) {
1355                 up->scr &= ~OMAP_UART_SCR_TX_EMPTY;
1356                 serial_out(up, UART_OMAP_SCR, up->scr);
1357         }
1358
1359         return 0;
1360 }
1361
1362 static const struct uart_ops serial_omap_pops = {
1363         .tx_empty       = serial_omap_tx_empty,
1364         .set_mctrl      = serial_omap_set_mctrl,
1365         .get_mctrl      = serial_omap_get_mctrl,
1366         .stop_tx        = serial_omap_stop_tx,
1367         .start_tx       = serial_omap_start_tx,
1368         .throttle       = serial_omap_throttle,
1369         .unthrottle     = serial_omap_unthrottle,
1370         .stop_rx        = serial_omap_stop_rx,
1371         .enable_ms      = serial_omap_enable_ms,
1372         .break_ctl      = serial_omap_break_ctl,
1373         .startup        = serial_omap_startup,
1374         .shutdown       = serial_omap_shutdown,
1375         .set_termios    = serial_omap_set_termios,
1376         .pm             = serial_omap_pm,
1377         .type           = serial_omap_type,
1378         .release_port   = serial_omap_release_port,
1379         .request_port   = serial_omap_request_port,
1380         .config_port    = serial_omap_config_port,
1381         .verify_port    = serial_omap_verify_port,
1382 #ifdef CONFIG_CONSOLE_POLL
1383         .poll_put_char  = serial_omap_poll_put_char,
1384         .poll_get_char  = serial_omap_poll_get_char,
1385 #endif
1386 };
1387
1388 static struct uart_driver serial_omap_reg = {
1389         .owner          = THIS_MODULE,
1390         .driver_name    = "OMAP-SERIAL",
1391         .dev_name       = OMAP_SERIAL_NAME,
1392         .nr             = OMAP_MAX_HSUART_PORTS,
1393         .cons           = OMAP_CONSOLE,
1394 };
1395
1396 #ifdef CONFIG_PM_SLEEP
1397 static int serial_omap_prepare(struct device *dev)
1398 {
1399         struct uart_omap_port *up = dev_get_drvdata(dev);
1400
1401         up->is_suspending = true;
1402
1403         return 0;
1404 }
1405
1406 static void serial_omap_complete(struct device *dev)
1407 {
1408         struct uart_omap_port *up = dev_get_drvdata(dev);
1409
1410         up->is_suspending = false;
1411 }
1412
1413 static int serial_omap_suspend(struct device *dev)
1414 {
1415         struct uart_omap_port *up = dev_get_drvdata(dev);
1416
1417         uart_suspend_port(&serial_omap_reg, &up->port);
1418         flush_work(&up->qos_work);
1419
1420         if (device_may_wakeup(dev))
1421                 serial_omap_enable_wakeup(up, true);
1422         else
1423                 serial_omap_enable_wakeup(up, false);
1424
1425         return 0;
1426 }
1427
1428 static int serial_omap_resume(struct device *dev)
1429 {
1430         struct uart_omap_port *up = dev_get_drvdata(dev);
1431
1432         if (device_may_wakeup(dev))
1433                 serial_omap_enable_wakeup(up, false);
1434
1435         uart_resume_port(&serial_omap_reg, &up->port);
1436
1437         return 0;
1438 }
1439 #else
1440 #define serial_omap_prepare NULL
1441 #define serial_omap_complete NULL
1442 #endif /* CONFIG_PM_SLEEP */
1443
1444 static void omap_serial_fill_features_erratas(struct uart_omap_port *up)
1445 {
1446         u32 mvr, scheme;
1447         u16 revision, major, minor;
1448
1449         mvr = readl(up->port.membase + (UART_OMAP_MVER << up->port.regshift));
1450
1451         /* Check revision register scheme */
1452         scheme = mvr >> OMAP_UART_MVR_SCHEME_SHIFT;
1453
1454         switch (scheme) {
1455         case 0: /* Legacy Scheme: OMAP2/3 */
1456                 /* MINOR_REV[0:4], MAJOR_REV[4:7] */
1457                 major = (mvr & OMAP_UART_LEGACY_MVR_MAJ_MASK) >>
1458                                         OMAP_UART_LEGACY_MVR_MAJ_SHIFT;
1459                 minor = (mvr & OMAP_UART_LEGACY_MVR_MIN_MASK);
1460                 break;
1461         case 1:
1462                 /* New Scheme: OMAP4+ */
1463                 /* MINOR_REV[0:5], MAJOR_REV[8:10] */
1464                 major = (mvr & OMAP_UART_MVR_MAJ_MASK) >>
1465                                         OMAP_UART_MVR_MAJ_SHIFT;
1466                 minor = (mvr & OMAP_UART_MVR_MIN_MASK);
1467                 break;
1468         default:
1469                 dev_warn(up->dev,
1470                         "Unknown %s revision, defaulting to highest\n",
1471                         up->name);
1472                 /* highest possible revision */
1473                 major = 0xff;
1474                 minor = 0xff;
1475         }
1476
1477         /* normalize revision for the driver */
1478         revision = UART_BUILD_REVISION(major, minor);
1479
1480         switch (revision) {
1481         case OMAP_UART_REV_46:
1482                 up->errata |= (UART_ERRATA_i202_MDR1_ACCESS |
1483                                 UART_ERRATA_i291_DMA_FORCEIDLE);
1484                 break;
1485         case OMAP_UART_REV_52:
1486                 up->errata |= (UART_ERRATA_i202_MDR1_ACCESS |
1487                                 UART_ERRATA_i291_DMA_FORCEIDLE);
1488                 up->features |= OMAP_UART_WER_HAS_TX_WAKEUP;
1489                 break;
1490         case OMAP_UART_REV_63:
1491                 up->errata |= UART_ERRATA_i202_MDR1_ACCESS;
1492                 up->features |= OMAP_UART_WER_HAS_TX_WAKEUP;
1493                 break;
1494         default:
1495                 break;
1496         }
1497 }
1498
1499 static struct omap_uart_port_info *of_get_uart_port_info(struct device *dev)
1500 {
1501         struct omap_uart_port_info *omap_up_info;
1502
1503         omap_up_info = devm_kzalloc(dev, sizeof(*omap_up_info), GFP_KERNEL);
1504         if (!omap_up_info)
1505                 return NULL; /* out of memory */
1506
1507         of_property_read_u32(dev->of_node, "clock-frequency",
1508                                          &omap_up_info->uartclk);
1509
1510         omap_up_info->flags = UPF_BOOT_AUTOCONF;
1511
1512         return omap_up_info;
1513 }
1514
1515 static int serial_omap_probe_rs485(struct uart_omap_port *up,
1516                                    struct device *dev)
1517 {
1518         struct serial_rs485 *rs485conf = &up->port.rs485;
1519         struct device_node *np = dev->of_node;
1520         enum gpiod_flags gflags;
1521         int ret;
1522
1523         rs485conf->flags = 0;
1524         up->rts_gpiod = NULL;
1525
1526         if (!np)
1527                 return 0;
1528
1529         ret = uart_get_rs485_mode(&up->port);
1530         if (ret)
1531                 return ret;
1532
1533         if (of_property_read_bool(np, "rs485-rts-active-high")) {
1534                 rs485conf->flags |= SER_RS485_RTS_ON_SEND;
1535                 rs485conf->flags &= ~SER_RS485_RTS_AFTER_SEND;
1536         } else {
1537                 rs485conf->flags &= ~SER_RS485_RTS_ON_SEND;
1538                 rs485conf->flags |= SER_RS485_RTS_AFTER_SEND;
1539         }
1540
1541         /* check for tx enable gpio */
1542         gflags = rs485conf->flags & SER_RS485_RTS_AFTER_SEND ?
1543                 GPIOD_OUT_HIGH : GPIOD_OUT_LOW;
1544         up->rts_gpiod = devm_gpiod_get_optional(dev, "rts", gflags);
1545         if (IS_ERR(up->rts_gpiod)) {
1546                 ret = PTR_ERR(up->rts_gpiod);
1547                 if (ret == -EPROBE_DEFER)
1548                         return ret;
1549
1550                 up->rts_gpiod = NULL;
1551                 up->port.rs485_supported = (const struct serial_rs485) { };
1552                 if (rs485conf->flags & SER_RS485_ENABLED) {
1553                         dev_err(dev, "disabling RS-485 (rts-gpio missing in device tree)\n");
1554                         memset(rs485conf, 0, sizeof(*rs485conf));
1555                 }
1556         } else {
1557                 gpiod_set_consumer_name(up->rts_gpiod, "omap-serial");
1558         }
1559
1560         return 0;
1561 }
1562
1563 static const struct serial_rs485 serial_omap_rs485_supported = {
1564         .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND | SER_RS485_RTS_AFTER_SEND |
1565                  SER_RS485_RX_DURING_TX,
1566         .delay_rts_before_send = 1,
1567         .delay_rts_after_send = 1,
1568 };
1569
1570 static int serial_omap_probe(struct platform_device *pdev)
1571 {
1572         struct omap_uart_port_info *omap_up_info = dev_get_platdata(&pdev->dev);
1573         struct uart_omap_port *up;
1574         struct resource *mem;
1575         void __iomem *base;
1576         int uartirq = 0;
1577         int wakeirq = 0;
1578         int ret;
1579
1580         /* The optional wakeirq may be specified in the board dts file */
1581         if (pdev->dev.of_node) {
1582                 uartirq = irq_of_parse_and_map(pdev->dev.of_node, 0);
1583                 if (!uartirq)
1584                         return -EPROBE_DEFER;
1585                 wakeirq = irq_of_parse_and_map(pdev->dev.of_node, 1);
1586                 omap_up_info = of_get_uart_port_info(&pdev->dev);
1587                 pdev->dev.platform_data = omap_up_info;
1588         } else {
1589                 uartirq = platform_get_irq(pdev, 0);
1590                 if (uartirq < 0)
1591                         return -EPROBE_DEFER;
1592         }
1593
1594         up = devm_kzalloc(&pdev->dev, sizeof(*up), GFP_KERNEL);
1595         if (!up)
1596                 return -ENOMEM;
1597
1598         mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1599         base = devm_ioremap_resource(&pdev->dev, mem);
1600         if (IS_ERR(base))
1601                 return PTR_ERR(base);
1602
1603         up->dev = &pdev->dev;
1604         up->port.dev = &pdev->dev;
1605         up->port.type = PORT_OMAP;
1606         up->port.iotype = UPIO_MEM;
1607         up->port.irq = uartirq;
1608         up->port.regshift = 2;
1609         up->port.fifosize = 64;
1610         up->port.ops = &serial_omap_pops;
1611         up->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_OMAP_CONSOLE);
1612
1613         if (pdev->dev.of_node)
1614                 ret = of_alias_get_id(pdev->dev.of_node, "serial");
1615         else
1616                 ret = pdev->id;
1617
1618         if (ret < 0) {
1619                 dev_err(&pdev->dev, "failed to get alias/pdev id, errno %d\n",
1620                         ret);
1621                 goto err_port_line;
1622         }
1623         up->port.line = ret;
1624
1625         if (up->port.line >= OMAP_MAX_HSUART_PORTS) {
1626                 dev_err(&pdev->dev, "uart ID %d >  MAX %d.\n", up->port.line,
1627                         OMAP_MAX_HSUART_PORTS);
1628                 ret = -ENXIO;
1629                 goto err_port_line;
1630         }
1631
1632         up->wakeirq = wakeirq;
1633         if (!up->wakeirq)
1634                 dev_info(up->port.dev, "no wakeirq for uart%d\n",
1635                          up->port.line);
1636
1637         ret = serial_omap_probe_rs485(up, &pdev->dev);
1638         if (ret < 0)
1639                 goto err_rs485;
1640
1641         sprintf(up->name, "OMAP UART%d", up->port.line);
1642         up->port.mapbase = mem->start;
1643         up->port.membase = base;
1644         up->port.flags = omap_up_info->flags;
1645         up->port.uartclk = omap_up_info->uartclk;
1646         up->port.rs485_config = serial_omap_config_rs485;
1647         up->port.rs485_supported = serial_omap_rs485_supported;
1648         if (!up->port.uartclk) {
1649                 up->port.uartclk = DEFAULT_CLK_SPEED;
1650                 dev_warn(&pdev->dev,
1651                          "No clock speed specified: using default: %d\n",
1652                          DEFAULT_CLK_SPEED);
1653         }
1654
1655         up->latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE;
1656         up->calc_latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE;
1657         cpu_latency_qos_add_request(&up->pm_qos_request, up->latency);
1658         INIT_WORK(&up->qos_work, serial_omap_uart_qos_work);
1659
1660         platform_set_drvdata(pdev, up);
1661         if (omap_up_info->autosuspend_timeout == 0)
1662                 omap_up_info->autosuspend_timeout = -1;
1663
1664         device_init_wakeup(up->dev, true);
1665
1666         pm_runtime_enable(&pdev->dev);
1667
1668         pm_runtime_get_sync(&pdev->dev);
1669
1670         omap_serial_fill_features_erratas(up);
1671
1672         ui[up->port.line] = up;
1673         serial_omap_add_console_port(up);
1674
1675         ret = uart_add_one_port(&serial_omap_reg, &up->port);
1676         if (ret != 0)
1677                 goto err_add_port;
1678
1679         return 0;
1680
1681 err_add_port:
1682         pm_runtime_put_sync(&pdev->dev);
1683         pm_runtime_disable(&pdev->dev);
1684         cpu_latency_qos_remove_request(&up->pm_qos_request);
1685         device_init_wakeup(up->dev, false);
1686 err_rs485:
1687 err_port_line:
1688         return ret;
1689 }
1690
1691 static int serial_omap_remove(struct platform_device *dev)
1692 {
1693         struct uart_omap_port *up = platform_get_drvdata(dev);
1694
1695         pm_runtime_get_sync(up->dev);
1696
1697         uart_remove_one_port(&serial_omap_reg, &up->port);
1698
1699         pm_runtime_put_sync(up->dev);
1700         pm_runtime_disable(up->dev);
1701         cpu_latency_qos_remove_request(&up->pm_qos_request);
1702         device_init_wakeup(&dev->dev, false);
1703
1704         return 0;
1705 }
1706
1707 /*
1708  * Work Around for Errata i202 (2430, 3430, 3630, 4430 and 4460)
1709  * The access to uart register after MDR1 Access
1710  * causes UART to corrupt data.
1711  *
1712  * Need a delay =
1713  * 5 L4 clock cycles + 5 UART functional clock cycle (@48MHz = ~0.2uS)
1714  * give 10 times as much
1715  */
1716 static void serial_omap_mdr1_errataset(struct uart_omap_port *up, u8 mdr1)
1717 {
1718         u8 timeout = 255;
1719
1720         serial_out(up, UART_OMAP_MDR1, mdr1);
1721         udelay(2);
1722         serial_out(up, UART_FCR, up->fcr | UART_FCR_CLEAR_XMIT |
1723                         UART_FCR_CLEAR_RCVR);
1724         /*
1725          * Wait for FIFO to empty: when empty, RX_FIFO_E bit is 0 and
1726          * TX_FIFO_E bit is 1.
1727          */
1728         while (UART_LSR_THRE != (serial_in(up, UART_LSR) &
1729                                 (UART_LSR_THRE | UART_LSR_DR))) {
1730                 timeout--;
1731                 if (!timeout) {
1732                         /* Should *never* happen. we warn and carry on */
1733                         dev_crit(up->dev, "Errata i202: timedout %x\n",
1734                                                 serial_in(up, UART_LSR));
1735                         break;
1736                 }
1737                 udelay(1);
1738         }
1739 }
1740
1741 #ifdef CONFIG_PM
1742 static void serial_omap_restore_context(struct uart_omap_port *up)
1743 {
1744         if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1745                 serial_omap_mdr1_errataset(up, UART_OMAP_MDR1_DISABLE);
1746         else
1747                 serial_out(up, UART_OMAP_MDR1, UART_OMAP_MDR1_DISABLE);
1748
1749         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1750         serial_out(up, UART_EFR, UART_EFR_ECB);
1751         serial_out(up, UART_LCR, 0x0); /* Operational mode */
1752         serial_out(up, UART_IER, 0x0);
1753         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1754         serial_out(up, UART_DLL, up->dll);
1755         serial_out(up, UART_DLM, up->dlh);
1756         serial_out(up, UART_LCR, 0x0); /* Operational mode */
1757         serial_out(up, UART_IER, up->ier);
1758         serial_out(up, UART_FCR, up->fcr);
1759         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_A);
1760         serial_out(up, UART_MCR, up->mcr);
1761         serial_out(up, UART_LCR, UART_LCR_CONF_MODE_B); /* Config B mode */
1762         serial_out(up, UART_OMAP_SCR, up->scr);
1763         serial_out(up, UART_EFR, up->efr);
1764         serial_out(up, UART_LCR, up->lcr);
1765         if (up->errata & UART_ERRATA_i202_MDR1_ACCESS)
1766                 serial_omap_mdr1_errataset(up, up->mdr1);
1767         else
1768                 serial_out(up, UART_OMAP_MDR1, up->mdr1);
1769         serial_out(up, UART_OMAP_WER, up->wer);
1770 }
1771
1772 static int serial_omap_runtime_suspend(struct device *dev)
1773 {
1774         struct uart_omap_port *up = dev_get_drvdata(dev);
1775
1776         if (!up)
1777                 return -EINVAL;
1778
1779         /*
1780         * When using 'no_console_suspend', the console UART must not be
1781         * suspended. Since driver suspend is managed by runtime suspend,
1782         * preventing runtime suspend (by returning error) will keep device
1783         * active during suspend.
1784         */
1785         if (up->is_suspending && !console_suspend_enabled &&
1786             uart_console(&up->port))
1787                 return -EBUSY;
1788
1789         up->context_loss_cnt = serial_omap_get_context_loss_count(up);
1790
1791         serial_omap_enable_wakeup(up, true);
1792
1793         up->latency = PM_QOS_CPU_LATENCY_DEFAULT_VALUE;
1794         schedule_work(&up->qos_work);
1795
1796         return 0;
1797 }
1798
1799 static int serial_omap_runtime_resume(struct device *dev)
1800 {
1801         struct uart_omap_port *up = dev_get_drvdata(dev);
1802
1803         int loss_cnt = serial_omap_get_context_loss_count(up);
1804
1805         serial_omap_enable_wakeup(up, false);
1806
1807         if (loss_cnt < 0) {
1808                 dev_dbg(dev, "serial_omap_get_context_loss_count failed : %d\n",
1809                         loss_cnt);
1810                 serial_omap_restore_context(up);
1811         } else if (up->context_loss_cnt != loss_cnt) {
1812                 serial_omap_restore_context(up);
1813         }
1814         up->latency = up->calc_latency;
1815         schedule_work(&up->qos_work);
1816
1817         return 0;
1818 }
1819 #endif
1820
1821 static const struct dev_pm_ops serial_omap_dev_pm_ops = {
1822         SET_SYSTEM_SLEEP_PM_OPS(serial_omap_suspend, serial_omap_resume)
1823         SET_RUNTIME_PM_OPS(serial_omap_runtime_suspend,
1824                                 serial_omap_runtime_resume, NULL)
1825         .prepare        = serial_omap_prepare,
1826         .complete       = serial_omap_complete,
1827 };
1828
1829 #if defined(CONFIG_OF)
1830 static const struct of_device_id omap_serial_of_match[] = {
1831         { .compatible = "ti,omap2-uart" },
1832         { .compatible = "ti,omap3-uart" },
1833         { .compatible = "ti,omap4-uart" },
1834         {},
1835 };
1836 MODULE_DEVICE_TABLE(of, omap_serial_of_match);
1837 #endif
1838
1839 static struct platform_driver serial_omap_driver = {
1840         .probe          = serial_omap_probe,
1841         .remove         = serial_omap_remove,
1842         .driver         = {
1843                 .name   = OMAP_SERIAL_DRIVER_NAME,
1844                 .pm     = &serial_omap_dev_pm_ops,
1845                 .of_match_table = of_match_ptr(omap_serial_of_match),
1846         },
1847 };
1848
1849 static int __init serial_omap_init(void)
1850 {
1851         int ret;
1852
1853         ret = uart_register_driver(&serial_omap_reg);
1854         if (ret != 0)
1855                 return ret;
1856         ret = platform_driver_register(&serial_omap_driver);
1857         if (ret != 0)
1858                 uart_unregister_driver(&serial_omap_reg);
1859         return ret;
1860 }
1861
1862 static void __exit serial_omap_exit(void)
1863 {
1864         platform_driver_unregister(&serial_omap_driver);
1865         uart_unregister_driver(&serial_omap_reg);
1866 }
1867
1868 module_init(serial_omap_init);
1869 module_exit(serial_omap_exit);
1870
1871 MODULE_DESCRIPTION("OMAP High Speed UART driver");
1872 MODULE_LICENSE("GPL");
1873 MODULE_AUTHOR("Texas Instruments Inc");