drivers/net/usb/asix_devices.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /*
   3  * ASIX AX8817X based USB 2.0 Ethernet Devices
   4  * Copyright (C) 2003-2006 David Hollis <[email protected]>
   5  * Copyright (C) 2005 Phil Chang <[email protected]>
   6  * Copyright (C) 2006 James Painter <[email protected]>
   7  * Copyright (c) 2002-2003 TiVo Inc.
   8  */
   9
  10 #include "asix.h"
  11
  12 #define PHY_MODE_MARVELL        0x0000
  13 #define MII_MARVELL_LED_CTRL    0x0018
  14 #define MII_MARVELL_STATUS      0x001b
  15 #define MII_MARVELL_CTRL        0x0014
  16
  17 #define MARVELL_LED_MANUAL      0x0019
  18
  19 #define MARVELL_STATUS_HWCFG    0x0004
  20
  21 #define MARVELL_CTRL_TXDELAY    0x0002
  22 #define MARVELL_CTRL_RXDELAY    0x0080
  23
  24 #define PHY_MODE_RTL8211CL      0x000C
  25
  26 #define AX88772A_PHY14H         0x14
  27 #define AX88772A_PHY14H_DEFAULT 0x442C
  28
  29 #define AX88772A_PHY15H         0x15
  30 #define AX88772A_PHY15H_DEFAULT 0x03C8
  31
  32 #define AX88772A_PHY16H         0x16
  33 #define AX88772A_PHY16H_DEFAULT 0x4044
  34
  35 struct ax88172_int_data {
  36         __le16 res1;
  37         u8 link;
  38         __le16 res2;
  39         u8 status;
  40         __le16 res3;
  41 } __packed;
  42
  43 static void asix_status(struct usbnet *dev, struct urb *urb)
  44 {
  45         struct ax88172_int_data *event;
  46         int link;
  47
  48         if (urb->actual_length < 8)
  49                 return;
  50
  51         event = urb->transfer_buffer;
  52         link = event->link & 0x01;
  53         if (netif_carrier_ok(dev->net) != link) {
  54                 usbnet_link_change(dev, link, 1);
  55                 netdev_dbg(dev->net, "Link Status is: %d\n", link);
  56         }
  57 }
  58
  59 static void asix_set_netdev_dev_addr(struct usbnet *dev, u8 *addr)
  60 {
  61         if (is_valid_ether_addr(addr)) {
  62                 eth_hw_addr_set(dev->net, addr);
  63         } else {
  64                 netdev_info(dev->net, "invalid hw address, using random\n");
  65                 eth_hw_addr_random(dev->net);
  66         }
  67 }
  68
  69 /* Get the PHY Identifier from the PHYSID1 & PHYSID2 MII registers */
  70 static u32 asix_get_phyid(struct usbnet *dev)
  71 {
  72         int phy_reg;
  73         u32 phy_id;
  74         int i;
  75
  76         /* Poll for the rare case the FW or phy isn't ready yet.  */
  77         for (i = 0; i < 100; i++) {
  78                 phy_reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_PHYSID1);
  79                 if (phy_reg < 0)
  80                         return 0;
  81                 if (phy_reg != 0 && phy_reg != 0xFFFF)
  82                         break;
  83                 mdelay(1);
  84         }
  85
  86         if (phy_reg <= 0 || phy_reg == 0xFFFF)
  87                 return 0;
  88
  89         phy_id = (phy_reg & 0xffff) << 16;
  90
  91         phy_reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_PHYSID2);
  92         if (phy_reg < 0)
  93                 return 0;
  94
  95         phy_id |= (phy_reg & 0xffff);
  96
  97         return phy_id;
  98 }
  99
 100 static u32 asix_get_link(struct net_device *net)
 101 {
 102         struct usbnet *dev = netdev_priv(net);
 103
 104         return mii_link_ok(&dev->mii);
 105 }
 106
 107 static int asix_ioctl (struct net_device *net, struct ifreq *rq, int cmd)
 108 {
 109         struct usbnet *dev = netdev_priv(net);
 110
 111         return generic_mii_ioctl(&dev->mii, if_mii(rq), cmd, NULL);
 112 }
 113
 114 /* We need to override some ethtool_ops so we require our
 115    own structure so we don't interfere with other usbnet
 116    devices that may be connected at the same time. */
 117 static const struct ethtool_ops ax88172_ethtool_ops = {
 118         .get_drvinfo            = asix_get_drvinfo,
 119         .get_link               = asix_get_link,
 120         .get_msglevel           = usbnet_get_msglevel,
 121         .set_msglevel           = usbnet_set_msglevel,
 122         .get_wol                = asix_get_wol,
 123         .set_wol                = asix_set_wol,
 124         .get_eeprom_len         = asix_get_eeprom_len,
 125         .get_eeprom             = asix_get_eeprom,
 126         .set_eeprom             = asix_set_eeprom,
 127         .nway_reset             = usbnet_nway_reset,
 128         .get_link_ksettings     = usbnet_get_link_ksettings_mii,
 129         .set_link_ksettings     = usbnet_set_link_ksettings_mii,
 130 };
 131
 132 static void ax88172_set_multicast(struct net_device *net)
 133 {
 134         struct usbnet *dev = netdev_priv(net);
 135         struct asix_data *data = (struct asix_data *)&dev->data;
 136         u8 rx_ctl = 0x8c;
 137
 138         if (net->flags & IFF_PROMISC) {
 139                 rx_ctl |= 0x01;
 140         } else if (net->flags & IFF_ALLMULTI ||
 141                    netdev_mc_count(net) > AX_MAX_MCAST) {
 142                 rx_ctl |= 0x02;
 143         } else if (netdev_mc_empty(net)) {
 144                 /* just broadcast and directed */
 145         } else {
 146                 /* We use the 20 byte dev->data
 147                  * for our 8 byte filter buffer
 148                  * to avoid allocating memory that
 149                  * is tricky to free later */
 150                 struct netdev_hw_addr *ha;
 151                 u32 crc_bits;
 152
 153                 memset(data->multi_filter, 0, AX_MCAST_FILTER_SIZE);
 154
 155                 /* Build the multicast hash filter. */
 156                 netdev_for_each_mc_addr(ha, net) {
 157                         crc_bits = ether_crc(ETH_ALEN, ha->addr) >> 26;
 158                         data->multi_filter[crc_bits >> 3] |=
 159                             1 << (crc_bits & 7);
 160                 }
 161
 162                 asix_write_cmd_async(dev, AX_CMD_WRITE_MULTI_FILTER, 0, 0,
 163                                    AX_MCAST_FILTER_SIZE, data->multi_filter);
 164
 165                 rx_ctl |= 0x10;
 166         }
 167
 168         asix_write_cmd_async(dev, AX_CMD_WRITE_RX_CTL, rx_ctl, 0, 0, NULL);
 169 }
 170
 171 static int ax88172_link_reset(struct usbnet *dev)
 172 {
 173         u8 mode;
 174         struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET };
 175
 176         mii_check_media(&dev->mii, 1, 1);
 177         mii_ethtool_gset(&dev->mii, &ecmd);
 178         mode = AX88172_MEDIUM_DEFAULT;
 179
 180         if (ecmd.duplex != DUPLEX_FULL)
 181                 mode |= ~AX88172_MEDIUM_FD;
 182
 183         netdev_dbg(dev->net, "ax88172_link_reset() speed: %u duplex: %d setting mode to 0x%04x\n",
 184                    ethtool_cmd_speed(&ecmd), ecmd.duplex, mode);
 185
 186         asix_write_medium_mode(dev, mode, 0);
 187
 188         return 0;
 189 }
 190
 191 static const struct net_device_ops ax88172_netdev_ops = {
 192         .ndo_open               = usbnet_open,
 193         .ndo_stop               = usbnet_stop,
 194         .ndo_start_xmit         = usbnet_start_xmit,
 195         .ndo_tx_timeout         = usbnet_tx_timeout,
 196         .ndo_change_mtu         = usbnet_change_mtu,
 197         .ndo_get_stats64        = dev_get_tstats64,
 198         .ndo_set_mac_address    = eth_mac_addr,
 199         .ndo_validate_addr      = eth_validate_addr,
 200         .ndo_eth_ioctl          = asix_ioctl,
 201         .ndo_set_rx_mode        = ax88172_set_multicast,
 202 };
 203
 204 static void asix_phy_reset(struct usbnet *dev, unsigned int reset_bits)
 205 {
 206         unsigned int timeout = 5000;
 207
 208         asix_mdio_write(dev->net, dev->mii.phy_id, MII_BMCR, reset_bits);
 209
 210         /* give phy_id a chance to process reset */
 211         udelay(500);
 212
 213         /* See IEEE 802.3 "22.2.4.1.1 Reset": 500ms max */
 214         while (timeout--) {
 215                 if (asix_mdio_read(dev->net, dev->mii.phy_id, MII_BMCR)
 216                                                         & BMCR_RESET)
 217                         udelay(100);
 218                 else
 219                         return;
 220         }
 221
 222         netdev_err(dev->net, "BMCR_RESET timeout on phy_id %d\n",
 223                    dev->mii.phy_id);
 224 }
 225
 226 static int ax88172_bind(struct usbnet *dev, struct usb_interface *intf)
 227 {
 228         int ret = 0;
 229         u8 buf[ETH_ALEN] = {0};
 230         int i;
 231         unsigned long gpio_bits = dev->driver_info->data;
 232
 233         usbnet_get_endpoints(dev,intf);
 234
 235         /* Toggle the GPIOs in a manufacturer/model specific way */
 236         for (i = 2; i >= 0; i--) {
 237                 ret = asix_write_cmd(dev, AX_CMD_WRITE_GPIOS,
 238                                 (gpio_bits >> (i * 8)) & 0xff, 0, 0, NULL, 0);
 239                 if (ret < 0)
 240                         goto out;
 241                 msleep(5);
 242         }
 243
 244         ret = asix_write_rx_ctl(dev, 0x80, 0);
 245         if (ret < 0)
 246                 goto out;
 247
 248         /* Get the MAC address */
 249         ret = asix_read_cmd(dev, AX88172_CMD_READ_NODE_ID,
 250                             0, 0, ETH_ALEN, buf, 0);
 251         if (ret < 0) {
 252                 netdev_dbg(dev->net, "read AX_CMD_READ_NODE_ID failed: %d\n",
 253                            ret);
 254                 goto out;
 255         }
 256
 257         asix_set_netdev_dev_addr(dev, buf);
 258
 259         /* Initialize MII structure */
 260         dev->mii.dev = dev->net;
 261         dev->mii.mdio_read = asix_mdio_read;
 262         dev->mii.mdio_write = asix_mdio_write;
 263         dev->mii.phy_id_mask = 0x3f;
 264         dev->mii.reg_num_mask = 0x1f;
 265
 266         dev->mii.phy_id = asix_read_phy_addr(dev, true);
 267         if (dev->mii.phy_id < 0)
 268                 return dev->mii.phy_id;
 269
 270         dev->net->netdev_ops = &ax88172_netdev_ops;
 271         dev->net->ethtool_ops = &ax88172_ethtool_ops;
 272         dev->net->needed_headroom = 4; /* cf asix_tx_fixup() */
 273         dev->net->needed_tailroom = 4; /* cf asix_tx_fixup() */
 274
 275         asix_phy_reset(dev, BMCR_RESET);
 276         asix_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE,
 277                 ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
 278         mii_nway_restart(&dev->mii);
 279
 280         return 0;
 281
 282 out:
 283         return ret;
 284 }
 285
 286 static void ax88772_ethtool_get_strings(struct net_device *netdev, u32 sset,
 287                                         u8 *data)
 288 {
 289         switch (sset) {
 290         case ETH_SS_TEST:
 291                 net_selftest_get_strings(data);
 292                 break;
 293         }
 294 }
 295
 296 static int ax88772_ethtool_get_sset_count(struct net_device *ndev, int sset)
 297 {
 298         switch (sset) {
 299         case ETH_SS_TEST:
 300                 return net_selftest_get_count();
 301         default:
 302                 return -EOPNOTSUPP;
 303         }
 304 }
 305
 306 static void ax88772_ethtool_get_pauseparam(struct net_device *ndev,
 307                                           struct ethtool_pauseparam *pause)
 308 {
 309         struct usbnet *dev = netdev_priv(ndev);
 310         struct asix_common_private *priv = dev->driver_priv;
 311
 312         phylink_ethtool_get_pauseparam(priv->phylink, pause);
 313 }
 314
 315 static int ax88772_ethtool_set_pauseparam(struct net_device *ndev,
 316                                          struct ethtool_pauseparam *pause)
 317 {
 318         struct usbnet *dev = netdev_priv(ndev);
 319         struct asix_common_private *priv = dev->driver_priv;
 320
 321         return phylink_ethtool_set_pauseparam(priv->phylink, pause);
 322 }
 323
 324 static const struct ethtool_ops ax88772_ethtool_ops = {
 325         .get_drvinfo            = asix_get_drvinfo,
 326         .get_link               = usbnet_get_link,
 327         .get_msglevel           = usbnet_get_msglevel,
 328         .set_msglevel           = usbnet_set_msglevel,
 329         .get_wol                = asix_get_wol,
 330         .set_wol                = asix_set_wol,
 331         .get_eeprom_len         = asix_get_eeprom_len,
 332         .get_eeprom             = asix_get_eeprom,
 333         .set_eeprom             = asix_set_eeprom,
 334         .nway_reset             = phy_ethtool_nway_reset,
 335         .get_link_ksettings     = phy_ethtool_get_link_ksettings,
 336         .set_link_ksettings     = phy_ethtool_set_link_ksettings,
 337         .self_test              = net_selftest,
 338         .get_strings            = ax88772_ethtool_get_strings,
 339         .get_sset_count         = ax88772_ethtool_get_sset_count,
 340         .get_pauseparam         = ax88772_ethtool_get_pauseparam,
 341         .set_pauseparam         = ax88772_ethtool_set_pauseparam,
 342 };
 343
 344 static int ax88772_reset(struct usbnet *dev)
 345 {
 346         struct asix_data *data = (struct asix_data *)&dev->data;
 347         struct asix_common_private *priv = dev->driver_priv;
 348         int ret;
 349
 350         /* Rewrite MAC address */
 351         ether_addr_copy(data->mac_addr, dev->net->dev_addr);
 352         ret = asix_write_cmd(dev, AX_CMD_WRITE_NODE_ID, 0, 0,
 353                              ETH_ALEN, data->mac_addr, 0);
 354         if (ret < 0)
 355                 goto out;
 356
 357         /* Set RX_CTL to default values with 2k buffer, and enable cactus */
 358         ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL, 0);
 359         if (ret < 0)
 360                 goto out;
 361
 362         ret = asix_write_medium_mode(dev, AX88772_MEDIUM_DEFAULT, 0);
 363         if (ret < 0)
 364                 goto out;
 365
 366         phylink_start(priv->phylink);
 367
 368         return 0;
 369
 370 out:
 371         return ret;
 372 }
 373
 374 static int ax88772_hw_reset(struct usbnet *dev, int in_pm)
 375 {
 376         struct asix_data *data = (struct asix_data *)&dev->data;
 377         struct asix_common_private *priv = dev->driver_priv;
 378         u16 rx_ctl;
 379         int ret;
 380
 381         ret = asix_write_gpio(dev, AX_GPIO_RSE | AX_GPIO_GPO_2 |
 382                               AX_GPIO_GPO2EN, 5, in_pm);
 383         if (ret < 0)
 384                 goto out;
 385
 386         ret = asix_write_cmd(dev, AX_CMD_SW_PHY_SELECT, priv->embd_phy,
 387                              0, 0, NULL, in_pm);
 388         if (ret < 0) {
 389                 netdev_dbg(dev->net, "Select PHY #1 failed: %d\n", ret);
 390                 goto out;
 391         }
 392
 393         if (priv->embd_phy) {
 394                 ret = asix_sw_reset(dev, AX_SWRESET_IPPD, in_pm);
 395                 if (ret < 0)
 396                         goto out;
 397
 398                 usleep_range(10000, 11000);
 399
 400                 ret = asix_sw_reset(dev, AX_SWRESET_CLEAR, in_pm);
 401                 if (ret < 0)
 402                         goto out;
 403
 404                 msleep(60);
 405
 406                 ret = asix_sw_reset(dev, AX_SWRESET_IPRL | AX_SWRESET_PRL,
 407                                     in_pm);
 408                 if (ret < 0)
 409                         goto out;
 410         } else {
 411                 ret = asix_sw_reset(dev, AX_SWRESET_IPPD | AX_SWRESET_PRL,
 412                                     in_pm);
 413                 if (ret < 0)
 414                         goto out;
 415         }
 416
 417         msleep(150);
 418
 419         if (in_pm && (!asix_mdio_read_nopm(dev->net, dev->mii.phy_id,
 420                                            MII_PHYSID1))){
 421                 ret = -EIO;
 422                 goto out;
 423         }
 424
 425         ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL, in_pm);
 426         if (ret < 0)
 427                 goto out;
 428
 429         ret = asix_write_medium_mode(dev, AX88772_MEDIUM_DEFAULT, in_pm);
 430         if (ret < 0)
 431                 goto out;
 432
 433         ret = asix_write_cmd(dev, AX_CMD_WRITE_IPG0,
 434                              AX88772_IPG0_DEFAULT | AX88772_IPG1_DEFAULT,
 435                              AX88772_IPG2_DEFAULT, 0, NULL, in_pm);
 436         if (ret < 0) {
 437                 netdev_dbg(dev->net, "Write IPG,IPG1,IPG2 failed: %d\n", ret);
 438                 goto out;
 439         }
 440
 441         /* Rewrite MAC address */
 442         ether_addr_copy(data->mac_addr, dev->net->dev_addr);
 443         ret = asix_write_cmd(dev, AX_CMD_WRITE_NODE_ID, 0, 0,
 444                              ETH_ALEN, data->mac_addr, in_pm);
 445         if (ret < 0)
 446                 goto out;
 447
 448         /* Set RX_CTL to default values with 2k buffer, and enable cactus */
 449         ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL, in_pm);
 450         if (ret < 0)
 451                 goto out;
 452
 453         rx_ctl = asix_read_rx_ctl(dev, in_pm);
 454         netdev_dbg(dev->net, "RX_CTL is 0x%04x after all initializations\n",
 455                    rx_ctl);
 456
 457         rx_ctl = asix_read_medium_status(dev, in_pm);
 458         netdev_dbg(dev->net,
 459                    "Medium Status is 0x%04x after all initializations\n",
 460                    rx_ctl);
 461
 462         return 0;
 463
 464 out:
 465         return ret;
 466 }
 467
 468 static int ax88772a_hw_reset(struct usbnet *dev, int in_pm)
 469 {
 470         struct asix_data *data = (struct asix_data *)&dev->data;
 471         struct asix_common_private *priv = dev->driver_priv;
 472         u16 rx_ctl, phy14h, phy15h, phy16h;
 473         int ret;
 474
 475         ret = asix_write_gpio(dev, AX_GPIO_RSE, 5, in_pm);
 476         if (ret < 0)
 477                 goto out;
 478
 479         ret = asix_write_cmd(dev, AX_CMD_SW_PHY_SELECT, priv->embd_phy |
 480                              AX_PHYSEL_SSEN, 0, 0, NULL, in_pm);
 481         if (ret < 0) {
 482                 netdev_dbg(dev->net, "Select PHY #1 failed: %d\n", ret);
 483                 goto out;
 484         }
 485         usleep_range(10000, 11000);
 486
 487         ret = asix_sw_reset(dev, AX_SWRESET_IPPD | AX_SWRESET_IPRL, in_pm);
 488         if (ret < 0)
 489                 goto out;
 490
 491         usleep_range(10000, 11000);
 492
 493         ret = asix_sw_reset(dev, AX_SWRESET_IPRL, in_pm);
 494         if (ret < 0)
 495                 goto out;
 496
 497         msleep(160);
 498
 499         ret = asix_sw_reset(dev, AX_SWRESET_CLEAR, in_pm);
 500         if (ret < 0)
 501                 goto out;
 502
 503         ret = asix_sw_reset(dev, AX_SWRESET_IPRL, in_pm);
 504         if (ret < 0)
 505                 goto out;
 506
 507         msleep(200);
 508
 509         if (in_pm && (!asix_mdio_read_nopm(dev->net, dev->mii.phy_id,
 510                                            MII_PHYSID1))) {
 511                 ret = -1;
 512                 goto out;
 513         }
 514
 515         if (priv->chipcode == AX_AX88772B_CHIPCODE) {
 516                 ret = asix_write_cmd(dev, AX_QCTCTRL, 0x8000, 0x8001,
 517                                      0, NULL, in_pm);
 518                 if (ret < 0) {
 519                         netdev_dbg(dev->net, "Write BQ setting failed: %d\n",
 520                                    ret);
 521                         goto out;
 522                 }
 523         } else if (priv->chipcode == AX_AX88772A_CHIPCODE) {
 524                 /* Check if the PHY registers have default settings */
 525                 phy14h = asix_mdio_read_nopm(dev->net, dev->mii.phy_id,
 526                                              AX88772A_PHY14H);
 527                 phy15h = asix_mdio_read_nopm(dev->net, dev->mii.phy_id,
 528                                              AX88772A_PHY15H);
 529                 phy16h = asix_mdio_read_nopm(dev->net, dev->mii.phy_id,
 530                                              AX88772A_PHY16H);
 531
 532                 netdev_dbg(dev->net,
 533                            "772a_hw_reset: MR20=0x%x MR21=0x%x MR22=0x%x\n",
 534                            phy14h, phy15h, phy16h);
 535
 536                 /* Restore PHY registers default setting if not */
 537                 if (phy14h != AX88772A_PHY14H_DEFAULT)
 538                         asix_mdio_write_nopm(dev->net, dev->mii.phy_id,
 539                                              AX88772A_PHY14H,
 540                                              AX88772A_PHY14H_DEFAULT);
 541                 if (phy15h != AX88772A_PHY15H_DEFAULT)
 542                         asix_mdio_write_nopm(dev->net, dev->mii.phy_id,
 543                                              AX88772A_PHY15H,
 544                                              AX88772A_PHY15H_DEFAULT);
 545                 if (phy16h != AX88772A_PHY16H_DEFAULT)
 546                         asix_mdio_write_nopm(dev->net, dev->mii.phy_id,
 547                                              AX88772A_PHY16H,
 548                                              AX88772A_PHY16H_DEFAULT);
 549         }
 550
 551         ret = asix_write_cmd(dev, AX_CMD_WRITE_IPG0,
 552                                 AX88772_IPG0_DEFAULT | AX88772_IPG1_DEFAULT,
 553                                 AX88772_IPG2_DEFAULT, 0, NULL, in_pm);
 554         if (ret < 0) {
 555                 netdev_dbg(dev->net, "Write IPG,IPG1,IPG2 failed: %d\n", ret);
 556                 goto out;
 557         }
 558
 559         /* Rewrite MAC address */
 560         memcpy(data->mac_addr, dev->net->dev_addr, ETH_ALEN);
 561         ret = asix_write_cmd(dev, AX_CMD_WRITE_NODE_ID, 0, 0, ETH_ALEN,
 562                                                         data->mac_addr, in_pm);
 563         if (ret < 0)
 564                 goto out;
 565
 566         /* Set RX_CTL to default values with 2k buffer, and enable cactus */
 567         ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL, in_pm);
 568         if (ret < 0)
 569                 goto out;
 570
 571         ret = asix_write_medium_mode(dev, AX88772_MEDIUM_DEFAULT, in_pm);
 572         if (ret < 0)
 573                 return ret;
 574
 575         /* Set RX_CTL to default values with 2k buffer, and enable cactus */
 576         ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL, in_pm);
 577         if (ret < 0)
 578                 goto out;
 579
 580         rx_ctl = asix_read_rx_ctl(dev, in_pm);
 581         netdev_dbg(dev->net, "RX_CTL is 0x%04x after all initializations\n",
 582                    rx_ctl);
 583
 584         rx_ctl = asix_read_medium_status(dev, in_pm);
 585         netdev_dbg(dev->net,
 586                    "Medium Status is 0x%04x after all initializations\n",
 587                    rx_ctl);
 588
 589         return 0;
 590
 591 out:
 592         return ret;
 593 }
 594
 595 static const struct net_device_ops ax88772_netdev_ops = {
 596         .ndo_open               = usbnet_open,
 597         .ndo_stop               = usbnet_stop,
 598         .ndo_start_xmit         = usbnet_start_xmit,
 599         .ndo_tx_timeout         = usbnet_tx_timeout,
 600         .ndo_change_mtu         = usbnet_change_mtu,
 601         .ndo_get_stats64        = dev_get_tstats64,
 602         .ndo_set_mac_address    = asix_set_mac_address,
 603         .ndo_validate_addr      = eth_validate_addr,
 604         .ndo_eth_ioctl          = phy_do_ioctl_running,
 605         .ndo_set_rx_mode        = asix_set_multicast,
 606 };
 607
 608 static void ax88772_suspend(struct usbnet *dev)
 609 {
 610         struct asix_common_private *priv = dev->driver_priv;
 611         u16 medium;
 612
 613         if (netif_running(dev->net)) {
 614                 rtnl_lock();
 615                 phylink_suspend(priv->phylink, false);
 616                 rtnl_unlock();
 617         }
 618
 619         /* Stop MAC operation */
 620         medium = asix_read_medium_status(dev, 1);
 621         medium &= ~AX_MEDIUM_RE;
 622         asix_write_medium_mode(dev, medium, 1);
 623
 624         netdev_dbg(dev->net, "ax88772_suspend: medium=0x%04x\n",
 625                    asix_read_medium_status(dev, 1));
 626 }
 627
 628 static int asix_suspend(struct usb_interface *intf, pm_message_t message)
 629 {
 630         struct usbnet *dev = usb_get_intfdata(intf);
 631         struct asix_common_private *priv = dev->driver_priv;
 632
 633         if (priv && priv->suspend)
 634                 priv->suspend(dev);
 635
 636         return usbnet_suspend(intf, message);
 637 }
 638
 639 static void ax88772_resume(struct usbnet *dev)
 640 {
 641         struct asix_common_private *priv = dev->driver_priv;
 642         int i;
 643
 644         for (i = 0; i < 3; i++)
 645                 if (!priv->reset(dev, 1))
 646                         break;
 647
 648         if (netif_running(dev->net)) {
 649                 rtnl_lock();
 650                 phylink_resume(priv->phylink);
 651                 rtnl_unlock();
 652         }
 653 }
 654
 655 static int asix_resume(struct usb_interface *intf)
 656 {
 657         struct usbnet *dev = usb_get_intfdata(intf);
 658         struct asix_common_private *priv = dev->driver_priv;
 659
 660         if (priv && priv->resume)
 661                 priv->resume(dev);
 662
 663         return usbnet_resume(intf);
 664 }
 665
 666 static int ax88772_init_mdio(struct usbnet *dev)
 667 {
 668         struct asix_common_private *priv = dev->driver_priv;
 669
 670         priv->mdio = devm_mdiobus_alloc(&dev->udev->dev);
 671         if (!priv->mdio)
 672                 return -ENOMEM;
 673
 674         priv->mdio->priv = dev;
 675         priv->mdio->read = &asix_mdio_bus_read;
 676         priv->mdio->write = &asix_mdio_bus_write;
 677         priv->mdio->name = "Asix MDIO Bus";
 678         /* mii bus name is usb-<usb bus number>-<usb device number> */
 679         snprintf(priv->mdio->id, MII_BUS_ID_SIZE, "usb-%03d:%03d",
 680                  dev->udev->bus->busnum, dev->udev->devnum);
 681
 682         return devm_mdiobus_register(&dev->udev->dev, priv->mdio);
 683 }
 684
 685 static int ax88772_init_phy(struct usbnet *dev)
 686 {
 687         struct asix_common_private *priv = dev->driver_priv;
 688         int ret;
 689
 690         priv->phydev = mdiobus_get_phy(priv->mdio, priv->phy_addr);
 691         if (!priv->phydev) {
 692                 netdev_err(dev->net, "Could not find PHY\n");
 693                 return -ENODEV;
 694         }
 695
 696         ret = phylink_connect_phy(priv->phylink, priv->phydev);
 697         if (ret) {
 698                 netdev_err(dev->net, "Could not connect PHY\n");
 699                 return ret;
 700         }
 701
 702         phy_suspend(priv->phydev);
 703         priv->phydev->mac_managed_pm = 1;
 704
 705         phy_attached_info(priv->phydev);
 706
 707         if (priv->embd_phy)
 708                 return 0;
 709
 710         /* In case main PHY is not the embedded PHY and MAC is RMII clock
 711          * provider, we need to suspend embedded PHY by keeping PLL enabled
 712          * (AX_SWRESET_IPPD == 0).
 713          */
 714         priv->phydev_int = mdiobus_get_phy(priv->mdio, AX_EMBD_PHY_ADDR);
 715         if (!priv->phydev_int) {
 716                 rtnl_lock();
 717                 phylink_disconnect_phy(priv->phylink);
 718                 rtnl_unlock();
 719                 netdev_err(dev->net, "Could not find internal PHY\n");
 720                 return -ENODEV;
 721         }
 722
 723         priv->phydev_int->mac_managed_pm = 1;
 724         phy_suspend(priv->phydev_int);
 725
 726         return 0;
 727 }
 728
 729 static void ax88772_mac_config(struct phylink_config *config, unsigned int mode,
 730                               const struct phylink_link_state *state)
 731 {
 732         /* Nothing to do */
 733 }
 734
 735 static void ax88772_mac_link_down(struct phylink_config *config,
 736                                  unsigned int mode, phy_interface_t interface)
 737 {
 738         struct usbnet *dev = netdev_priv(to_net_dev(config->dev));
 739
 740         asix_write_medium_mode(dev, 0, 0);
 741         usbnet_link_change(dev, false, false);
 742 }
 743
 744 static void ax88772_mac_link_up(struct phylink_config *config,
 745                                struct phy_device *phy,
 746                                unsigned int mode, phy_interface_t interface,
 747                                int speed, int duplex,
 748                                bool tx_pause, bool rx_pause)
 749 {
 750         struct usbnet *dev = netdev_priv(to_net_dev(config->dev));
 751         u16 m = AX_MEDIUM_AC | AX_MEDIUM_RE;
 752
 753         m |= duplex ? AX_MEDIUM_FD : 0;
 754
 755         switch (speed) {
 756         case SPEED_100:
 757                 m |= AX_MEDIUM_PS;
 758                 break;
 759         case SPEED_10:
 760                 break;
 761         default:
 762                 return;
 763         }
 764
 765         if (tx_pause)
 766                 m |= AX_MEDIUM_TFC;
 767
 768         if (rx_pause)
 769                 m |= AX_MEDIUM_RFC;
 770
 771         asix_write_medium_mode(dev, m, 0);
 772         usbnet_link_change(dev, true, false);
 773 }
 774
 775 static const struct phylink_mac_ops ax88772_phylink_mac_ops = {
 776         .validate = phylink_generic_validate,
 777         .mac_config = ax88772_mac_config,
 778         .mac_link_down = ax88772_mac_link_down,
 779         .mac_link_up = ax88772_mac_link_up,
 780 };
 781
 782 static int ax88772_phylink_setup(struct usbnet *dev)
 783 {
 784         struct asix_common_private *priv = dev->driver_priv;
 785         phy_interface_t phy_if_mode;
 786         struct phylink *phylink;
 787
 788         priv->phylink_config.dev = &dev->net->dev;
 789         priv->phylink_config.type = PHYLINK_NETDEV;
 790         priv->phylink_config.mac_capabilities = MAC_SYM_PAUSE | MAC_ASYM_PAUSE |
 791                 MAC_10 | MAC_100;
 792
 793         __set_bit(PHY_INTERFACE_MODE_INTERNAL,
 794                   priv->phylink_config.supported_interfaces);
 795         __set_bit(PHY_INTERFACE_MODE_RMII,
 796                   priv->phylink_config.supported_interfaces);
 797
 798         if (priv->embd_phy)
 799                 phy_if_mode = PHY_INTERFACE_MODE_INTERNAL;
 800         else
 801                 phy_if_mode = PHY_INTERFACE_MODE_RMII;
 802
 803         phylink = phylink_create(&priv->phylink_config, dev->net->dev.fwnode,
 804                                  phy_if_mode, &ax88772_phylink_mac_ops);
 805         if (IS_ERR(phylink))
 806                 return PTR_ERR(phylink);
 807
 808         priv->phylink = phylink;
 809         return 0;
 810 }
 811
 812 static int ax88772_bind(struct usbnet *dev, struct usb_interface *intf)
 813 {
 814         struct asix_common_private *priv;
 815         u8 buf[ETH_ALEN] = {0};
 816         int ret, i;
 817
 818         priv = devm_kzalloc(&dev->udev->dev, sizeof(*priv), GFP_KERNEL);
 819         if (!priv)
 820                 return -ENOMEM;
 821
 822         dev->driver_priv = priv;
 823
 824         usbnet_get_endpoints(dev, intf);
 825
 826         /* Maybe the boot loader passed the MAC address via device tree */
 827         if (!eth_platform_get_mac_address(&dev->udev->dev, buf)) {
 828                 netif_dbg(dev, ifup, dev->net,
 829                           "MAC address read from device tree");
 830         } else {
 831                 /* Try getting the MAC address from EEPROM */
 832                 if (dev->driver_info->data & FLAG_EEPROM_MAC) {
 833                         for (i = 0; i < (ETH_ALEN >> 1); i++) {
 834                                 ret = asix_read_cmd(dev, AX_CMD_READ_EEPROM,
 835                                                     0x04 + i, 0, 2, buf + i * 2,
 836                                                     0);
 837                                 if (ret < 0)
 838                                         break;
 839                         }
 840                 } else {
 841                         ret = asix_read_cmd(dev, AX_CMD_READ_NODE_ID,
 842                                             0, 0, ETH_ALEN, buf, 0);
 843                 }
 844
 845                 if (ret < 0) {
 846                         netdev_dbg(dev->net, "Failed to read MAC address: %d\n",
 847                                    ret);
 848                         return ret;
 849                 }
 850         }
 851
 852         asix_set_netdev_dev_addr(dev, buf);
 853
 854         dev->net->netdev_ops = &ax88772_netdev_ops;
 855         dev->net->ethtool_ops = &ax88772_ethtool_ops;
 856         dev->net->needed_headroom = 4; /* cf asix_tx_fixup() */
 857         dev->net->needed_tailroom = 4; /* cf asix_tx_fixup() */
 858
 859         ret = asix_read_phy_addr(dev, true);
 860         if (ret < 0)
 861                 return ret;
 862
 863         priv->phy_addr = ret;
 864         priv->embd_phy = ((priv->phy_addr & 0x1f) == AX_EMBD_PHY_ADDR);
 865
 866         ret = asix_read_cmd(dev, AX_CMD_STATMNGSTS_REG, 0, 0, 1,
 867                             &priv->chipcode, 0);
 868         if (ret < 0) {
 869                 netdev_dbg(dev->net, "Failed to read STATMNGSTS_REG: %d\n", ret);
 870                 return ret;
 871         }
 872
 873         priv->chipcode &= AX_CHIPCODE_MASK;
 874
 875         priv->resume = ax88772_resume;
 876         priv->suspend = ax88772_suspend;
 877         if (priv->chipcode == AX_AX88772_CHIPCODE)
 878                 priv->reset = ax88772_hw_reset;
 879         else
 880                 priv->reset = ax88772a_hw_reset;
 881
 882         ret = priv->reset(dev, 0);
 883         if (ret < 0) {
 884                 netdev_dbg(dev->net, "Failed to reset AX88772: %d\n", ret);
 885                 return ret;
 886         }
 887
 888         /* Asix framing packs multiple eth frames into a 2K usb bulk transfer */
 889         if (dev->driver_info->flags & FLAG_FRAMING_AX) {
 890                 /* hard_mtu  is still the default - the device does not support
 891                    jumbo eth frames */
 892                 dev->rx_urb_size = 2048;
 893         }
 894
 895         priv->presvd_phy_bmcr = 0;
 896         priv->presvd_phy_advertise = 0;
 897
 898         ret = ax88772_init_mdio(dev);
 899         if (ret)
 900                 return ret;
 901
 902         ret = ax88772_phylink_setup(dev);
 903         if (ret)
 904                 return ret;
 905
 906         ret = ax88772_init_phy(dev);
 907         if (ret)
 908                 phylink_destroy(priv->phylink);
 909
 910         return ret;
 911 }
 912
 913 static int ax88772_stop(struct usbnet *dev)
 914 {
 915         struct asix_common_private *priv = dev->driver_priv;
 916
 917         phylink_stop(priv->phylink);
 918
 919         return 0;
 920 }
 921
 922 static void ax88772_unbind(struct usbnet *dev, struct usb_interface *intf)
 923 {
 924         struct asix_common_private *priv = dev->driver_priv;
 925
 926         rtnl_lock();
 927         phylink_disconnect_phy(priv->phylink);
 928         rtnl_unlock();
 929         phylink_destroy(priv->phylink);
 930         asix_rx_fixup_common_free(dev->driver_priv);
 931 }
 932
 933 static void ax88178_unbind(struct usbnet *dev, struct usb_interface *intf)
 934 {
 935         asix_rx_fixup_common_free(dev->driver_priv);
 936         kfree(dev->driver_priv);
 937 }
 938
 939 static const struct ethtool_ops ax88178_ethtool_ops = {
 940         .get_drvinfo            = asix_get_drvinfo,
 941         .get_link               = asix_get_link,
 942         .get_msglevel           = usbnet_get_msglevel,
 943         .set_msglevel           = usbnet_set_msglevel,
 944         .get_wol                = asix_get_wol,
 945         .set_wol                = asix_set_wol,
 946         .get_eeprom_len         = asix_get_eeprom_len,
 947         .get_eeprom             = asix_get_eeprom,
 948         .set_eeprom             = asix_set_eeprom,
 949         .nway_reset             = usbnet_nway_reset,
 950         .get_link_ksettings     = usbnet_get_link_ksettings_mii,
 951         .set_link_ksettings     = usbnet_set_link_ksettings_mii,
 952 };
 953
 954 static int marvell_phy_init(struct usbnet *dev)
 955 {
 956         struct asix_data *data = (struct asix_data *)&dev->data;
 957         u16 reg;
 958
 959         netdev_dbg(dev->net, "marvell_phy_init()\n");
 960
 961         reg = asix_mdio_read(dev->net, dev->mii.phy_id, MII_MARVELL_STATUS);
 962         netdev_dbg(dev->net, "MII_MARVELL_STATUS = 0x%04x\n", reg);
 963
 964         asix_mdio_write(dev->net, dev->mii.phy_id, MII_MARVELL_CTRL,
 965                         MARVELL_CTRL_RXDELAY | MARVELL_CTRL_TXDELAY);
 966
 967         if (data->ledmode) {
 968                 reg = asix_mdio_read(dev->net, dev->mii.phy_id,
 969                         MII_MARVELL_LED_CTRL);
 970                 netdev_dbg(dev->net, "MII_MARVELL_LED_CTRL (1) = 0x%04x\n", reg);
 971
 972                 reg &= 0xf8ff;
 973                 reg |= (1 + 0x0100);
 974                 asix_mdio_write(dev->net, dev->mii.phy_id,
 975                         MII_MARVELL_LED_CTRL, reg);
 976
 977                 reg = asix_mdio_read(dev->net, dev->mii.phy_id,
 978                         MII_MARVELL_LED_CTRL);
 979                 netdev_dbg(dev->net, "MII_MARVELL_LED_CTRL (2) = 0x%04x\n", reg);
 980         }
 981
 982         return 0;
 983 }
 984
 985 static int rtl8211cl_phy_init(struct usbnet *dev)
 986 {
 987         struct asix_data *data = (struct asix_data *)&dev->data;
 988
 989         netdev_dbg(dev->net, "rtl8211cl_phy_init()\n");
 990
 991         asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0x0005);
 992         asix_mdio_write (dev->net, dev->mii.phy_id, 0x0c, 0);
 993         asix_mdio_write (dev->net, dev->mii.phy_id, 0x01,
 994                 asix_mdio_read (dev->net, dev->mii.phy_id, 0x01) | 0x0080);
 995         asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0);
 996
 997         if (data->ledmode == 12) {
 998                 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0x0002);
 999                 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1a, 0x00cb);
1000                 asix_mdio_write (dev->net, dev->mii.phy_id, 0x1f, 0);
1001         }
1002
1003         return 0;
1004 }
1005
1006 static int marvell_led_status(struct usbnet *dev, u16 speed)
1007 {
1008         u16 reg = asix_mdio_read(dev->net, dev->mii.phy_id, MARVELL_LED_MANUAL);
1009
1010         netdev_dbg(dev->net, "marvell_led_status() read 0x%04x\n", reg);
1011
1012         /* Clear out the center LED bits - 0x03F0 */
1013         reg &= 0xfc0f;
1014
1015         switch (speed) {
1016                 case SPEED_1000:
1017                         reg |= 0x03e0;
1018                         break;
1019                 case SPEED_100:
1020                         reg |= 0x03b0;
1021                         break;
1022                 default:
1023                         reg |= 0x02f0;
1024         }
1025
1026         netdev_dbg(dev->net, "marvell_led_status() writing 0x%04x\n", reg);
1027         asix_mdio_write(dev->net, dev->mii.phy_id, MARVELL_LED_MANUAL, reg);
1028
1029         return 0;
1030 }
1031
1032 static int ax88178_reset(struct usbnet *dev)
1033 {
1034         struct asix_data *data = (struct asix_data *)&dev->data;
1035         int ret;
1036         __le16 eeprom;
1037         u8 status;
1038         int gpio0 = 0;
1039         u32 phyid;
1040
1041         ret = asix_read_cmd(dev, AX_CMD_READ_GPIOS, 0, 0, 1, &status, 0);
1042         if (ret < 0) {
1043                 netdev_dbg(dev->net, "Failed to read GPIOS: %d\n", ret);
1044                 return ret;
1045         }
1046
1047         netdev_dbg(dev->net, "GPIO Status: 0x%04x\n", status);
1048
1049         asix_write_cmd(dev, AX_CMD_WRITE_ENABLE, 0, 0, 0, NULL, 0);
1050         ret = asix_read_cmd(dev, AX_CMD_READ_EEPROM, 0x0017, 0, 2, &eeprom, 0);
1051         if (ret < 0) {
1052                 netdev_dbg(dev->net, "Failed to read EEPROM: %d\n", ret);
1053                 return ret;
1054         }
1055
1056         asix_write_cmd(dev, AX_CMD_WRITE_DISABLE, 0, 0, 0, NULL, 0);
1057
1058         netdev_dbg(dev->net, "EEPROM index 0x17 is 0x%04x\n", eeprom);
1059
1060         if (eeprom == cpu_to_le16(0xffff)) {
1061                 data->phymode = PHY_MODE_MARVELL;
1062                 data->ledmode = 0;
1063                 gpio0 = 1;
1064         } else {
1065                 data->phymode = le16_to_cpu(eeprom) & 0x7F;
1066                 data->ledmode = le16_to_cpu(eeprom) >> 8;
1067                 gpio0 = (le16_to_cpu(eeprom) & 0x80) ? 0 : 1;
1068         }
1069         netdev_dbg(dev->net, "GPIO0: %d, PhyMode: %d\n", gpio0, data->phymode);
1070
1071         /* Power up external GigaPHY through AX88178 GPIO pin */
1072         asix_write_gpio(dev, AX_GPIO_RSE | AX_GPIO_GPO_1 |
1073                         AX_GPIO_GPO1EN, 40, 0);
1074         if ((le16_to_cpu(eeprom) >> 8) != 1) {
1075                 asix_write_gpio(dev, 0x003c, 30, 0);
1076                 asix_write_gpio(dev, 0x001c, 300, 0);
1077                 asix_write_gpio(dev, 0x003c, 30, 0);
1078         } else {
1079                 netdev_dbg(dev->net, "gpio phymode == 1 path\n");
1080                 asix_write_gpio(dev, AX_GPIO_GPO1EN, 30, 0);
1081                 asix_write_gpio(dev, AX_GPIO_GPO1EN | AX_GPIO_GPO_1, 30, 0);
1082         }
1083
1084         /* Read PHYID register *AFTER* powering up PHY */
1085         phyid = asix_get_phyid(dev);
1086         netdev_dbg(dev->net, "PHYID=0x%08x\n", phyid);
1087
1088         /* Set AX88178 to enable MII/GMII/RGMII interface for external PHY */
1089         asix_write_cmd(dev, AX_CMD_SW_PHY_SELECT, 0, 0, 0, NULL, 0);
1090
1091         asix_sw_reset(dev, 0, 0);
1092         msleep(150);
1093
1094         asix_sw_reset(dev, AX_SWRESET_PRL | AX_SWRESET_IPPD, 0);
1095         msleep(150);
1096
1097         asix_write_rx_ctl(dev, 0, 0);
1098
1099         if (data->phymode == PHY_MODE_MARVELL) {
1100                 marvell_phy_init(dev);
1101                 msleep(60);
1102         } else if (data->phymode == PHY_MODE_RTL8211CL)
1103                 rtl8211cl_phy_init(dev);
1104
1105         asix_phy_reset(dev, BMCR_RESET | BMCR_ANENABLE);
1106         asix_mdio_write(dev->net, dev->mii.phy_id, MII_ADVERTISE,
1107                         ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP);
1108         asix_mdio_write(dev->net, dev->mii.phy_id, MII_CTRL1000,
1109                         ADVERTISE_1000FULL);
1110
1111         asix_write_medium_mode(dev, AX88178_MEDIUM_DEFAULT, 0);
1112         mii_nway_restart(&dev->mii);
1113
1114         /* Rewrite MAC address */
1115         memcpy(data->mac_addr, dev->net->dev_addr, ETH_ALEN);
1116         ret = asix_write_cmd(dev, AX_CMD_WRITE_NODE_ID, 0, 0, ETH_ALEN,
1117                                                         data->mac_addr, 0);
1118         if (ret < 0)
1119                 return ret;
1120
1121         ret = asix_write_rx_ctl(dev, AX_DEFAULT_RX_CTL, 0);
1122         if (ret < 0)
1123                 return ret;
1124
1125         return 0;
1126 }
1127
1128 static int ax88178_link_reset(struct usbnet *dev)
1129 {
1130         u16 mode;
1131         struct ethtool_cmd ecmd = { .cmd = ETHTOOL_GSET };
1132         struct asix_data *data = (struct asix_data *)&dev->data;
1133         u32 speed;
1134
1135         netdev_dbg(dev->net, "ax88178_link_reset()\n");
1136
1137         mii_check_media(&dev->mii, 1, 1);
1138         mii_ethtool_gset(&dev->mii, &ecmd);
1139         mode = AX88178_MEDIUM_DEFAULT;
1140         speed = ethtool_cmd_speed(&ecmd);
1141
1142         if (speed == SPEED_1000)
1143                 mode |= AX_MEDIUM_GM;
1144         else if (speed == SPEED_100)
1145                 mode |= AX_MEDIUM_PS;
1146         else
1147                 mode &= ~(AX_MEDIUM_PS | AX_MEDIUM_GM);
1148
1149         mode |= AX_MEDIUM_ENCK;
1150
1151         if (ecmd.duplex == DUPLEX_FULL)
1152                 mode |= AX_MEDIUM_FD;
1153         else
1154                 mode &= ~AX_MEDIUM_FD;
1155
1156         netdev_dbg(dev->net, "ax88178_link_reset() speed: %u duplex: %d setting mode to 0x%04x\n",
1157                    speed, ecmd.duplex, mode);
1158
1159         asix_write_medium_mode(dev, mode, 0);
1160
1161         if (data->phymode == PHY_MODE_MARVELL && data->ledmode)
1162                 marvell_led_status(dev, speed);
1163
1164         return 0;
1165 }
1166
1167 static void ax88178_set_mfb(struct usbnet *dev)
1168 {
1169         u16 mfb = AX_RX_CTL_MFB_16384;
1170         u16 rxctl;
1171         u16 medium;
1172         int old_rx_urb_size = dev->rx_urb_size;
1173
1174         if (dev->hard_mtu < 2048) {
1175                 dev->rx_urb_size = 2048;
1176                 mfb = AX_RX_CTL_MFB_2048;
1177         } else if (dev->hard_mtu < 4096) {
1178                 dev->rx_urb_size = 4096;
1179                 mfb = AX_RX_CTL_MFB_4096;
1180         } else if (dev->hard_mtu < 8192) {
1181                 dev->rx_urb_size = 8192;
1182                 mfb = AX_RX_CTL_MFB_8192;
1183         } else if (dev->hard_mtu < 16384) {
1184                 dev->rx_urb_size = 16384;
1185                 mfb = AX_RX_CTL_MFB_16384;
1186         }
1187
1188         rxctl = asix_read_rx_ctl(dev, 0);
1189         asix_write_rx_ctl(dev, (rxctl & ~AX_RX_CTL_MFB_16384) | mfb, 0);
1190
1191         medium = asix_read_medium_status(dev, 0);
1192         if (dev->net->mtu > 1500)
1193                 medium |= AX_MEDIUM_JFE;
1194         else
1195                 medium &= ~AX_MEDIUM_JFE;
1196         asix_write_medium_mode(dev, medium, 0);
1197
1198         if (dev->rx_urb_size > old_rx_urb_size)
1199                 usbnet_unlink_rx_urbs(dev);
1200 }
1201
1202 static int ax88178_change_mtu(struct net_device *net, int new_mtu)
1203 {
1204         struct usbnet *dev = netdev_priv(net);
1205         int ll_mtu = new_mtu + net->hard_header_len + 4;
1206
1207         netdev_dbg(dev->net, "ax88178_change_mtu() new_mtu=%d\n", new_mtu);
1208
1209         if ((ll_mtu % dev->maxpacket) == 0)
1210                 return -EDOM;
1211
1212         net->mtu = new_mtu;
1213         dev->hard_mtu = net->mtu + net->hard_header_len;
1214         ax88178_set_mfb(dev);
1215
1216         /* max qlen depend on hard_mtu and rx_urb_size */
1217         usbnet_update_max_qlen(dev);
1218
1219         return 0;
1220 }
1221
1222 static const struct net_device_ops ax88178_netdev_ops = {
1223         .ndo_open               = usbnet_open,
1224         .ndo_stop               = usbnet_stop,
1225         .ndo_start_xmit         = usbnet_start_xmit,
1226         .ndo_tx_timeout         = usbnet_tx_timeout,
1227         .ndo_get_stats64        = dev_get_tstats64,
1228         .ndo_set_mac_address    = asix_set_mac_address,
1229         .ndo_validate_addr      = eth_validate_addr,
1230         .ndo_set_rx_mode        = asix_set_multicast,
1231         .ndo_eth_ioctl          = asix_ioctl,
1232         .ndo_change_mtu         = ax88178_change_mtu,
1233 };
1234
1235 static int ax88178_bind(struct usbnet *dev, struct usb_interface *intf)
1236 {
1237         int ret;
1238         u8 buf[ETH_ALEN] = {0};
1239
1240         usbnet_get_endpoints(dev,intf);
1241
1242         /* Get the MAC address */
1243         ret = asix_read_cmd(dev, AX_CMD_READ_NODE_ID, 0, 0, ETH_ALEN, buf, 0);
1244         if (ret < 0) {
1245                 netdev_dbg(dev->net, "Failed to read MAC address: %d\n", ret);
1246                 return ret;
1247         }
1248
1249         asix_set_netdev_dev_addr(dev, buf);
1250
1251         /* Initialize MII structure */
1252         dev->mii.dev = dev->net;
1253         dev->mii.mdio_read = asix_mdio_read;
1254         dev->mii.mdio_write = asix_mdio_write;
1255         dev->mii.phy_id_mask = 0x1f;
1256         dev->mii.reg_num_mask = 0xff;
1257         dev->mii.supports_gmii = 1;
1258
1259         dev->mii.phy_id = asix_read_phy_addr(dev, true);
1260         if (dev->mii.phy_id < 0)
1261                 return dev->mii.phy_id;
1262
1263         dev->net->netdev_ops = &ax88178_netdev_ops;
1264         dev->net->ethtool_ops = &ax88178_ethtool_ops;
1265         dev->net->max_mtu = 16384 - (dev->net->hard_header_len + 4);
1266
1267         /* Blink LEDS so users know driver saw dongle */
1268         asix_sw_reset(dev, 0, 0);
1269         msleep(150);
1270
1271         asix_sw_reset(dev, AX_SWRESET_PRL | AX_SWRESET_IPPD, 0);
1272         msleep(150);
1273
1274         /* Asix framing packs multiple eth frames into a 2K usb bulk transfer */
1275         if (dev->driver_info->flags & FLAG_FRAMING_AX) {
1276                 /* hard_mtu  is still the default - the device does not support
1277                    jumbo eth frames */
1278                 dev->rx_urb_size = 2048;
1279         }
1280
1281         dev->driver_priv = kzalloc(sizeof(struct asix_common_private), GFP_KERNEL);
1282         if (!dev->driver_priv)
1283                         return -ENOMEM;
1284
1285         return 0;
1286 }
1287
1288 static const struct driver_info ax8817x_info = {
1289         .description = "ASIX AX8817x USB 2.0 Ethernet",
1290         .bind = ax88172_bind,
1291         .status = asix_status,
1292         .link_reset = ax88172_link_reset,
1293         .reset = ax88172_link_reset,
1294         .flags =  FLAG_ETHER | FLAG_LINK_INTR,
1295         .data = 0x00130103,
1296 };
1297
1298 static const struct driver_info dlink_dub_e100_info = {
1299         .description = "DLink DUB-E100 USB Ethernet",
1300         .bind = ax88172_bind,
1301         .status = asix_status,
1302         .link_reset = ax88172_link_reset,
1303         .reset = ax88172_link_reset,
1304         .flags =  FLAG_ETHER | FLAG_LINK_INTR,
1305         .data = 0x009f9d9f,
1306 };
1307
1308 static const struct driver_info netgear_fa120_info = {
1309         .description = "Netgear FA-120 USB Ethernet",
1310         .bind = ax88172_bind,
1311         .status = asix_status,
1312         .link_reset = ax88172_link_reset,
1313         .reset = ax88172_link_reset,
1314         .flags =  FLAG_ETHER | FLAG_LINK_INTR,
1315         .data = 0x00130103,
1316 };
1317
1318 static const struct driver_info hawking_uf200_info = {
1319         .description = "Hawking UF200 USB Ethernet",
1320         .bind = ax88172_bind,
1321         .status = asix_status,
1322         .link_reset = ax88172_link_reset,
1323         .reset = ax88172_link_reset,
1324         .flags =  FLAG_ETHER | FLAG_LINK_INTR,
1325         .data = 0x001f1d1f,
1326 };
1327
1328 static const struct driver_info ax88772_info = {
1329         .description = "ASIX AX88772 USB 2.0 Ethernet",
1330         .bind = ax88772_bind,
1331         .unbind = ax88772_unbind,
1332         .status = asix_status,
1333         .reset = ax88772_reset,
1334         .stop = ax88772_stop,
1335         .flags = FLAG_ETHER | FLAG_FRAMING_AX | FLAG_LINK_INTR | FLAG_MULTI_PACKET,
1336         .rx_fixup = asix_rx_fixup_common,
1337         .tx_fixup = asix_tx_fixup,
1338 };
1339
1340 static const struct driver_info ax88772b_info = {
1341         .description = "ASIX AX88772B USB 2.0 Ethernet",
1342         .bind = ax88772_bind,
1343         .unbind = ax88772_unbind,
1344         .status = asix_status,
1345         .reset = ax88772_reset,
1346         .stop = ax88772_stop,
1347         .flags = FLAG_ETHER | FLAG_FRAMING_AX | FLAG_LINK_INTR |
1348                  FLAG_MULTI_PACKET,
1349         .rx_fixup = asix_rx_fixup_common,
1350         .tx_fixup = asix_tx_fixup,
1351         .data = FLAG_EEPROM_MAC,
1352 };
1353
1354 static const struct driver_info ax88178_info = {
1355         .description = "ASIX AX88178 USB 2.0 Ethernet",
1356         .bind = ax88178_bind,
1357         .unbind = ax88178_unbind,
1358         .status = asix_status,
1359         .link_reset = ax88178_link_reset,
1360         .reset = ax88178_reset,
1361         .flags = FLAG_ETHER | FLAG_FRAMING_AX | FLAG_LINK_INTR |
1362                  FLAG_MULTI_PACKET,
1363         .rx_fixup = asix_rx_fixup_common,
1364         .tx_fixup = asix_tx_fixup,
1365 };
1366
1367 /*
1368  * USBLINK 20F9 "USB 2.0 LAN" USB ethernet adapter, typically found in
1369  * no-name packaging.
1370  * USB device strings are:
1371  *   1: Manufacturer: USBLINK
1372  *   2: Product: HG20F9 USB2.0
1373  *   3: Serial: 000003
1374  * Appears to be compatible with Asix 88772B.
1375  */
1376 static const struct driver_info hg20f9_info = {
1377         .description = "HG20F9 USB 2.0 Ethernet",
1378         .bind = ax88772_bind,
1379         .unbind = ax88772_unbind,
1380         .status = asix_status,
1381         .reset = ax88772_reset,
1382         .flags = FLAG_ETHER | FLAG_FRAMING_AX | FLAG_LINK_INTR |
1383                  FLAG_MULTI_PACKET,
1384         .rx_fixup = asix_rx_fixup_common,
1385         .tx_fixup = asix_tx_fixup,
1386         .data = FLAG_EEPROM_MAC,
1387 };
1388
1389 static const struct usb_device_id       products [] = {
1390 {
1391         // Linksys USB200M
1392         USB_DEVICE (0x077b, 0x2226),
1393         .driver_info =  (unsigned long) &ax8817x_info,
1394 }, {
1395         // Netgear FA120
1396         USB_DEVICE (0x0846, 0x1040),
1397         .driver_info =  (unsigned long) &netgear_fa120_info,
1398 }, {
1399         // DLink DUB-E100
1400         USB_DEVICE (0x2001, 0x1a00),
1401         .driver_info =  (unsigned long) &dlink_dub_e100_info,
1402 }, {
1403         // Intellinet, ST Lab USB Ethernet
1404         USB_DEVICE (0x0b95, 0x1720),
1405         .driver_info =  (unsigned long) &ax8817x_info,
1406 }, {
1407         // Hawking UF200, TrendNet TU2-ET100
1408         USB_DEVICE (0x07b8, 0x420a),
1409         .driver_info =  (unsigned long) &hawking_uf200_info,
1410 }, {
1411         // Billionton Systems, USB2AR
1412         USB_DEVICE (0x08dd, 0x90ff),
1413         .driver_info =  (unsigned long) &ax8817x_info,
1414 }, {
1415         // Billionton Systems, GUSB2AM-1G-B
1416         USB_DEVICE(0x08dd, 0x0114),
1417         .driver_info =  (unsigned long) &ax88178_info,
1418 }, {
1419         // ATEN UC210T
1420         USB_DEVICE (0x0557, 0x2009),
1421         .driver_info =  (unsigned long) &ax8817x_info,
1422 }, {
1423         // Buffalo LUA-U2-KTX
1424         USB_DEVICE (0x0411, 0x003d),
1425         .driver_info =  (unsigned long) &ax8817x_info,
1426 }, {
1427         // Buffalo LUA-U2-GT 10/100/1000
1428         USB_DEVICE (0x0411, 0x006e),
1429         .driver_info =  (unsigned long) &ax88178_info,
1430 }, {
1431         // Sitecom LN-029 "USB 2.0 10/100 Ethernet adapter"
1432         USB_DEVICE (0x6189, 0x182d),
1433         .driver_info =  (unsigned long) &ax8817x_info,
1434 }, {
1435         // Sitecom LN-031 "USB 2.0 10/100/1000 Ethernet adapter"
1436         USB_DEVICE (0x0df6, 0x0056),
1437         .driver_info =  (unsigned long) &ax88178_info,
1438 }, {
1439         // Sitecom LN-028 "USB 2.0 10/100/1000 Ethernet adapter"
1440         USB_DEVICE (0x0df6, 0x061c),
1441         .driver_info =  (unsigned long) &ax88178_info,
1442 }, {
1443         // corega FEther USB2-TX
1444         USB_DEVICE (0x07aa, 0x0017),
1445         .driver_info =  (unsigned long) &ax8817x_info,
1446 }, {
1447         // Surecom EP-1427X-2
1448         USB_DEVICE (0x1189, 0x0893),
1449         .driver_info = (unsigned long) &ax8817x_info,
1450 }, {
1451         // goodway corp usb gwusb2e
1452         USB_DEVICE (0x1631, 0x6200),
1453         .driver_info = (unsigned long) &ax8817x_info,
1454 }, {
1455         // JVC MP-PRX1 Port Replicator
1456         USB_DEVICE (0x04f1, 0x3008),
1457         .driver_info = (unsigned long) &ax8817x_info,
1458 }, {
1459         // Lenovo U2L100P 10/100
1460         USB_DEVICE (0x17ef, 0x7203),
1461         .driver_info = (unsigned long)&ax88772b_info,
1462 }, {
1463         // ASIX AX88772B 10/100
1464         USB_DEVICE (0x0b95, 0x772b),
1465         .driver_info = (unsigned long) &ax88772b_info,
1466 }, {
1467         // ASIX AX88772 10/100
1468         USB_DEVICE (0x0b95, 0x7720),
1469         .driver_info = (unsigned long) &ax88772_info,
1470 }, {
1471         // ASIX AX88178 10/100/1000
1472         USB_DEVICE (0x0b95, 0x1780),
1473         .driver_info = (unsigned long) &ax88178_info,
1474 }, {
1475         // Logitec LAN-GTJ/U2A
1476         USB_DEVICE (0x0789, 0x0160),
1477         .driver_info = (unsigned long) &ax88178_info,
1478 }, {
1479         // Linksys USB200M Rev 2
1480         USB_DEVICE (0x13b1, 0x0018),
1481         .driver_info = (unsigned long) &ax88772_info,
1482 }, {
1483         // 0Q0 cable ethernet
1484         USB_DEVICE (0x1557, 0x7720),
1485         .driver_info = (unsigned long) &ax88772_info,
1486 }, {
1487         // DLink DUB-E100 H/W Ver B1
1488         USB_DEVICE (0x07d1, 0x3c05),
1489         .driver_info = (unsigned long) &ax88772_info,
1490 }, {
1491         // DLink DUB-E100 H/W Ver B1 Alternate
1492         USB_DEVICE (0x2001, 0x3c05),
1493         .driver_info = (unsigned long) &ax88772_info,
1494 }, {
1495        // DLink DUB-E100 H/W Ver C1
1496        USB_DEVICE (0x2001, 0x1a02),
1497        .driver_info = (unsigned long) &ax88772_info,
1498 }, {
1499         // Linksys USB1000
1500         USB_DEVICE (0x1737, 0x0039),
1501         .driver_info = (unsigned long) &ax88178_info,
1502 }, {
1503         // IO-DATA ETG-US2
1504         USB_DEVICE (0x04bb, 0x0930),
1505         .driver_info = (unsigned long) &ax88178_info,
1506 }, {
1507         // Belkin F5D5055
1508         USB_DEVICE(0x050d, 0x5055),
1509         .driver_info = (unsigned long) &ax88178_info,
1510 }, {
1511         // Apple USB Ethernet Adapter
1512         USB_DEVICE(0x05ac, 0x1402),
1513         .driver_info = (unsigned long) &ax88772_info,
1514 }, {
1515         // Cables-to-Go USB Ethernet Adapter
1516         USB_DEVICE(0x0b95, 0x772a),
1517         .driver_info = (unsigned long) &ax88772_info,
1518 }, {
1519         // ABOCOM for pci
1520         USB_DEVICE(0x14ea, 0xab11),
1521         .driver_info = (unsigned long) &ax88178_info,
1522 }, {
1523         // ASIX 88772a
1524         USB_DEVICE(0x0db0, 0xa877),
1525         .driver_info = (unsigned long) &ax88772_info,
1526 }, {
1527         // Asus USB Ethernet Adapter
1528         USB_DEVICE (0x0b95, 0x7e2b),
1529         .driver_info = (unsigned long)&ax88772b_info,
1530 }, {
1531         /* ASIX 88172a demo board */
1532         USB_DEVICE(0x0b95, 0x172a),
1533         .driver_info = (unsigned long) &ax88172a_info,
1534 }, {
1535         /*
1536          * USBLINK HG20F9 "USB 2.0 LAN"
1537          * Appears to have gazumped Linksys's manufacturer ID but
1538          * doesn't (yet) conflict with any known Linksys product.
1539          */
1540         USB_DEVICE(0x066b, 0x20f9),
1541         .driver_info = (unsigned long) &hg20f9_info,
1542 },
1543         { },            // END
1544 };
1545 MODULE_DEVICE_TABLE(usb, products);
1546
1547 static struct usb_driver asix_driver = {
1548         .name =         DRIVER_NAME,
1549         .id_table =     products,
1550         .probe =        usbnet_probe,
1551         .suspend =      asix_suspend,
1552         .resume =       asix_resume,
1553         .reset_resume = asix_resume,
1554         .disconnect =   usbnet_disconnect,
1555         .supports_autosuspend = 1,
1556         .disable_hub_initiated_lpm = 1,
1557 };
1558
1559 module_usb_driver(asix_driver);
1560
1561 MODULE_AUTHOR("David Hollis");
1562 MODULE_VERSION(DRIVER_VERSION);
1563 MODULE_DESCRIPTION("ASIX AX8817X based USB 2.0 Ethernet Devices");
1564 MODULE_LICENSE("GPL");
1565