drivers/usb/dwc3/core.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /**
   3  * core.c - DesignWare USB3 DRD Controller Core file
   4  *
   5  * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com
   6  *
   7  * Authors: Felipe Balbi <[email protected]>,
   8  *          Sebastian Andrzej Siewior <[email protected]>
   9  */
  10
  11 #include <linux/clk.h>
  12 #include <linux/version.h>
  13 #include <linux/module.h>
  14 #include <linux/kernel.h>
  15 #include <linux/slab.h>
  16 #include <linux/spinlock.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/pm_runtime.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/ioport.h>
  21 #include <linux/io.h>
  22 #include <linux/list.h>
  23 #include <linux/delay.h>
  24 #include <linux/dma-mapping.h>
  25 #include <linux/of.h>
  26 #include <linux/acpi.h>
  27 #include <linux/pinctrl/consumer.h>
  28 #include <linux/reset.h>
  29
  30 #include <linux/usb/ch9.h>
  31 #include <linux/usb/gadget.h>
  32 #include <linux/usb/of.h>
  33 #include <linux/usb/otg.h>
  34
  35 #include "core.h"
  36 #include "gadget.h"
  37 #include "io.h"
  38
  39 #include "debug.h"
  40
  41 #define DWC3_DEFAULT_AUTOSUSPEND_DELAY  5000 /* ms */
  42
  43 /**
  44  * dwc3_get_dr_mode - Validates and sets dr_mode
  45  * @dwc: pointer to our context structure
  46  */
  47 static int dwc3_get_dr_mode(struct dwc3 *dwc)
  48 {
  49         enum usb_dr_mode mode;
  50         struct device *dev = dwc->dev;
  51         unsigned int hw_mode;
  52
  53         if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)
  54                 dwc->dr_mode = USB_DR_MODE_OTG;
  55
  56         mode = dwc->dr_mode;
  57         hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
  58
  59         switch (hw_mode) {
  60         case DWC3_GHWPARAMS0_MODE_GADGET:
  61                 if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) {
  62                         dev_err(dev,
  63                                 "Controller does not support host mode.\n");
  64                         return -EINVAL;
  65                 }
  66                 mode = USB_DR_MODE_PERIPHERAL;
  67                 break;
  68         case DWC3_GHWPARAMS0_MODE_HOST:
  69                 if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) {
  70                         dev_err(dev,
  71                                 "Controller does not support device mode.\n");
  72                         return -EINVAL;
  73                 }
  74                 mode = USB_DR_MODE_HOST;
  75                 break;
  76         default:
  77                 if (IS_ENABLED(CONFIG_USB_DWC3_HOST))
  78                         mode = USB_DR_MODE_HOST;
  79                 else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET))
  80                         mode = USB_DR_MODE_PERIPHERAL;
  81
  82                 /*
  83                  * DWC_usb31 and DWC_usb3 v3.30a and higher do not support OTG
  84                  * mode. If the controller supports DRD but the dr_mode is not
  85                  * specified or set to OTG, then set the mode to peripheral.
  86                  */
  87                 if (mode == USB_DR_MODE_OTG &&
  88                     dwc->revision >= DWC3_REVISION_330A)
  89                         mode = USB_DR_MODE_PERIPHERAL;
  90         }
  91
  92         if (mode != dwc->dr_mode) {
  93                 dev_warn(dev,
  94                          "Configuration mismatch. dr_mode forced to %s\n",
  95                          mode == USB_DR_MODE_HOST ? "host" : "gadget");
  96
  97                 dwc->dr_mode = mode;
  98         }
  99
 100         return 0;
 101 }
 102
 103 void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode)
 104 {
 105         u32 reg;
 106
 107         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
 108         reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
 109         reg |= DWC3_GCTL_PRTCAPDIR(mode);
 110         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
 111
 112         dwc->current_dr_role = mode;
 113 }
 114
 115 static void __dwc3_set_mode(struct work_struct *work)
 116 {
 117         struct dwc3 *dwc = work_to_dwc(work);
 118         unsigned long flags;
 119         int ret;
 120
 121         if (dwc->dr_mode != USB_DR_MODE_OTG)
 122                 return;
 123
 124         if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_OTG)
 125                 dwc3_otg_update(dwc, 0);
 126
 127         if (!dwc->desired_dr_role)
 128                 return;
 129
 130         if (dwc->desired_dr_role == dwc->current_dr_role)
 131                 return;
 132
 133         if (dwc->desired_dr_role == DWC3_GCTL_PRTCAP_OTG && dwc->edev)
 134                 return;
 135
 136         switch (dwc->current_dr_role) {
 137         case DWC3_GCTL_PRTCAP_HOST:
 138                 dwc3_host_exit(dwc);
 139                 break;
 140         case DWC3_GCTL_PRTCAP_DEVICE:
 141                 dwc3_gadget_exit(dwc);
 142                 dwc3_event_buffers_cleanup(dwc);
 143                 break;
 144         case DWC3_GCTL_PRTCAP_OTG:
 145                 dwc3_otg_exit(dwc);
 146                 spin_lock_irqsave(&dwc->lock, flags);
 147                 dwc->desired_otg_role = DWC3_OTG_ROLE_IDLE;
 148                 spin_unlock_irqrestore(&dwc->lock, flags);
 149                 dwc3_otg_update(dwc, 1);
 150                 break;
 151         default:
 152                 break;
 153         }
 154
 155         spin_lock_irqsave(&dwc->lock, flags);
 156
 157         dwc3_set_prtcap(dwc, dwc->desired_dr_role);
 158
 159         spin_unlock_irqrestore(&dwc->lock, flags);
 160
 161         switch (dwc->desired_dr_role) {
 162         case DWC3_GCTL_PRTCAP_HOST:
 163                 ret = dwc3_host_init(dwc);
 164                 if (ret) {
 165                         dev_err(dwc->dev, "failed to initialize host\n");
 166                 } else {
 167                         if (dwc->usb2_phy)
 168                                 otg_set_vbus(dwc->usb2_phy->otg, true);
 169                         phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
 170                         phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
 171                 }
 172                 break;
 173         case DWC3_GCTL_PRTCAP_DEVICE:
 174                 dwc3_event_buffers_setup(dwc);
 175
 176                 if (dwc->usb2_phy)
 177                         otg_set_vbus(dwc->usb2_phy->otg, false);
 178                 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
 179                 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE);
 180
 181                 ret = dwc3_gadget_init(dwc);
 182                 if (ret)
 183                         dev_err(dwc->dev, "failed to initialize peripheral\n");
 184                 break;
 185         case DWC3_GCTL_PRTCAP_OTG:
 186                 dwc3_otg_init(dwc);
 187                 dwc3_otg_update(dwc, 0);
 188                 break;
 189         default:
 190                 break;
 191         }
 192
 193 }
 194
 195 void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
 196 {
 197         unsigned long flags;
 198
 199         spin_lock_irqsave(&dwc->lock, flags);
 200         dwc->desired_dr_role = mode;
 201         spin_unlock_irqrestore(&dwc->lock, flags);
 202
 203         queue_work(system_freezable_wq, &dwc->drd_work);
 204 }
 205
 206 u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type)
 207 {
 208         struct dwc3             *dwc = dep->dwc;
 209         u32                     reg;
 210
 211         dwc3_writel(dwc->regs, DWC3_GDBGFIFOSPACE,
 212                         DWC3_GDBGFIFOSPACE_NUM(dep->number) |
 213                         DWC3_GDBGFIFOSPACE_TYPE(type));
 214
 215         reg = dwc3_readl(dwc->regs, DWC3_GDBGFIFOSPACE);
 216
 217         return DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(reg);
 218 }
 219
 220 /**
 221  * dwc3_core_soft_reset - Issues core soft reset and PHY reset
 222  * @dwc: pointer to our context structure
 223  */
 224 static int dwc3_core_soft_reset(struct dwc3 *dwc)
 225 {
 226         u32             reg;
 227         int             retries = 1000;
 228         int             ret;
 229
 230         usb_phy_init(dwc->usb2_phy);
 231         usb_phy_init(dwc->usb3_phy);
 232         ret = phy_init(dwc->usb2_generic_phy);
 233         if (ret < 0)
 234                 return ret;
 235
 236         ret = phy_init(dwc->usb3_generic_phy);
 237         if (ret < 0) {
 238                 phy_exit(dwc->usb2_generic_phy);
 239                 return ret;
 240         }
 241
 242         /*
 243          * We're resetting only the device side because, if we're in host mode,
 244          * XHCI driver will reset the host block. If dwc3 was configured for
 245          * host-only mode, then we can return early.
 246          */
 247         if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST)
 248                 return 0;
 249
 250         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 251         reg |= DWC3_DCTL_CSFTRST;
 252         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 253
 254         /*
 255          * For DWC_usb31 controller 1.90a and later, the DCTL.CSFRST bit
 256          * is cleared only after all the clocks are synchronized. This can
 257          * take a little more than 50ms. Set the polling rate at 20ms
 258          * for 10 times instead.
 259          */
 260         if (dwc3_is_usb31(dwc) && dwc->revision >= DWC3_USB31_REVISION_190A)
 261                 retries = 10;
 262
 263         do {
 264                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 265                 if (!(reg & DWC3_DCTL_CSFTRST))
 266                         goto done;
 267
 268                 if (dwc3_is_usb31(dwc) &&
 269                     dwc->revision >= DWC3_USB31_REVISION_190A)
 270                         msleep(20);
 271                 else
 272                         udelay(1);
 273         } while (--retries);
 274
 275         phy_exit(dwc->usb3_generic_phy);
 276         phy_exit(dwc->usb2_generic_phy);
 277
 278         return -ETIMEDOUT;
 279
 280 done:
 281         /*
 282          * For DWC_usb31 controller 1.80a and prior, once DCTL.CSFRST bit
 283          * is cleared, we must wait at least 50ms before accessing the PHY
 284          * domain (synchronization delay).
 285          */
 286         if (dwc3_is_usb31(dwc) && dwc->revision <= DWC3_USB31_REVISION_180A)
 287                 msleep(50);
 288
 289         return 0;
 290 }
 291
 292 static const struct clk_bulk_data dwc3_core_clks[] = {
 293         { .id = "ref" },
 294         { .id = "bus_early" },
 295         { .id = "suspend" },
 296 };
 297
 298 /*
 299  * dwc3_frame_length_adjustment - Adjusts frame length if required
 300  * @dwc3: Pointer to our controller context structure
 301  */
 302 static void dwc3_frame_length_adjustment(struct dwc3 *dwc)
 303 {
 304         u32 reg;
 305         u32 dft;
 306
 307         if (dwc->revision < DWC3_REVISION_250A)
 308                 return;
 309
 310         if (dwc->fladj == 0)
 311                 return;
 312
 313         reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
 314         dft = reg & DWC3_GFLADJ_30MHZ_MASK;
 315         if (dft != dwc->fladj) {
 316                 reg &= ~DWC3_GFLADJ_30MHZ_MASK;
 317                 reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | dwc->fladj;
 318                 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
 319         }
 320 }
 321
 322 /**
 323  * dwc3_free_one_event_buffer - Frees one event buffer
 324  * @dwc: Pointer to our controller context structure
 325  * @evt: Pointer to event buffer to be freed
 326  */
 327 static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
 328                 struct dwc3_event_buffer *evt)
 329 {
 330         dma_free_coherent(dwc->sysdev, evt->length, evt->buf, evt->dma);
 331 }
 332
 333 /**
 334  * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
 335  * @dwc: Pointer to our controller context structure
 336  * @length: size of the event buffer
 337  *
 338  * Returns a pointer to the allocated event buffer structure on success
 339  * otherwise ERR_PTR(errno).
 340  */
 341 static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc,
 342                 unsigned length)
 343 {
 344         struct dwc3_event_buffer        *evt;
 345
 346         evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL);
 347         if (!evt)
 348                 return ERR_PTR(-ENOMEM);
 349
 350         evt->dwc        = dwc;
 351         evt->length     = length;
 352         evt->cache      = devm_kzalloc(dwc->dev, length, GFP_KERNEL);
 353         if (!evt->cache)
 354                 return ERR_PTR(-ENOMEM);
 355
 356         evt->buf        = dma_alloc_coherent(dwc->sysdev, length,
 357                         &evt->dma, GFP_KERNEL);
 358         if (!evt->buf)
 359                 return ERR_PTR(-ENOMEM);
 360
 361         return evt;
 362 }
 363
 364 /**
 365  * dwc3_free_event_buffers - frees all allocated event buffers
 366  * @dwc: Pointer to our controller context structure
 367  */
 368 static void dwc3_free_event_buffers(struct dwc3 *dwc)
 369 {
 370         struct dwc3_event_buffer        *evt;
 371
 372         evt = dwc->ev_buf;
 373         if (evt)
 374                 dwc3_free_one_event_buffer(dwc, evt);
 375 }
 376
 377 /**
 378  * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
 379  * @dwc: pointer to our controller context structure
 380  * @length: size of event buffer
 381  *
 382  * Returns 0 on success otherwise negative errno. In the error case, dwc
 383  * may contain some buffers allocated but not all which were requested.
 384  */
 385 static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
 386 {
 387         struct dwc3_event_buffer *evt;
 388
 389         evt = dwc3_alloc_one_event_buffer(dwc, length);
 390         if (IS_ERR(evt)) {
 391                 dev_err(dwc->dev, "can't allocate event buffer\n");
 392                 return PTR_ERR(evt);
 393         }
 394         dwc->ev_buf = evt;
 395
 396         return 0;
 397 }
 398
 399 /**
 400  * dwc3_event_buffers_setup - setup our allocated event buffers
 401  * @dwc: pointer to our controller context structure
 402  *
 403  * Returns 0 on success otherwise negative errno.
 404  */
 405 int dwc3_event_buffers_setup(struct dwc3 *dwc)
 406 {
 407         struct dwc3_event_buffer        *evt;
 408
 409         evt = dwc->ev_buf;
 410         evt->lpos = 0;
 411         dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0),
 412                         lower_32_bits(evt->dma));
 413         dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0),
 414                         upper_32_bits(evt->dma));
 415         dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0),
 416                         DWC3_GEVNTSIZ_SIZE(evt->length));
 417         dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
 418
 419         return 0;
 420 }
 421
 422 void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
 423 {
 424         struct dwc3_event_buffer        *evt;
 425
 426         evt = dwc->ev_buf;
 427
 428         evt->lpos = 0;
 429
 430         dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 0);
 431         dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 0);
 432         dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), DWC3_GEVNTSIZ_INTMASK
 433                         | DWC3_GEVNTSIZ_SIZE(0));
 434         dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
 435 }
 436
 437 static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc)
 438 {
 439         if (!dwc->has_hibernation)
 440                 return 0;
 441
 442         if (!dwc->nr_scratch)
 443                 return 0;
 444
 445         dwc->scratchbuf = kmalloc_array(dwc->nr_scratch,
 446                         DWC3_SCRATCHBUF_SIZE, GFP_KERNEL);
 447         if (!dwc->scratchbuf)
 448                 return -ENOMEM;
 449
 450         return 0;
 451 }
 452
 453 static int dwc3_setup_scratch_buffers(struct dwc3 *dwc)
 454 {
 455         dma_addr_t scratch_addr;
 456         u32 param;
 457         int ret;
 458
 459         if (!dwc->has_hibernation)
 460                 return 0;
 461
 462         if (!dwc->nr_scratch)
 463                 return 0;
 464
 465          /* should never fall here */
 466         if (!WARN_ON(dwc->scratchbuf))
 467                 return 0;
 468
 469         scratch_addr = dma_map_single(dwc->sysdev, dwc->scratchbuf,
 470                         dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE,
 471                         DMA_BIDIRECTIONAL);
 472         if (dma_mapping_error(dwc->sysdev, scratch_addr)) {
 473                 dev_err(dwc->sysdev, "failed to map scratch buffer\n");
 474                 ret = -EFAULT;
 475                 goto err0;
 476         }
 477
 478         dwc->scratch_addr = scratch_addr;
 479
 480         param = lower_32_bits(scratch_addr);
 481
 482         ret = dwc3_send_gadget_generic_command(dwc,
 483                         DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param);
 484         if (ret < 0)
 485                 goto err1;
 486
 487         param = upper_32_bits(scratch_addr);
 488
 489         ret = dwc3_send_gadget_generic_command(dwc,
 490                         DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param);
 491         if (ret < 0)
 492                 goto err1;
 493
 494         return 0;
 495
 496 err1:
 497         dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch *
 498                         DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
 499
 500 err0:
 501         return ret;
 502 }
 503
 504 static void dwc3_free_scratch_buffers(struct dwc3 *dwc)
 505 {
 506         if (!dwc->has_hibernation)
 507                 return;
 508
 509         if (!dwc->nr_scratch)
 510                 return;
 511
 512          /* should never fall here */
 513         if (!WARN_ON(dwc->scratchbuf))
 514                 return;
 515
 516         dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch *
 517                         DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
 518         kfree(dwc->scratchbuf);
 519 }
 520
 521 static void dwc3_core_num_eps(struct dwc3 *dwc)
 522 {
 523         struct dwc3_hwparams    *parms = &dwc->hwparams;
 524
 525         dwc->num_eps = DWC3_NUM_EPS(parms);
 526 }
 527
 528 static void dwc3_cache_hwparams(struct dwc3 *dwc)
 529 {
 530         struct dwc3_hwparams    *parms = &dwc->hwparams;
 531
 532         parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
 533         parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
 534         parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
 535         parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
 536         parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
 537         parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
 538         parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
 539         parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
 540         parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
 541 }
 542
 543 static int dwc3_core_ulpi_init(struct dwc3 *dwc)
 544 {
 545         int intf;
 546         int ret = 0;
 547
 548         intf = DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3);
 549
 550         if (intf == DWC3_GHWPARAMS3_HSPHY_IFC_ULPI ||
 551             (intf == DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI &&
 552              dwc->hsphy_interface &&
 553              !strncmp(dwc->hsphy_interface, "ulpi", 4)))
 554                 ret = dwc3_ulpi_init(dwc);
 555
 556         return ret;
 557 }
 558
 559 /**
 560  * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
 561  * @dwc: Pointer to our controller context structure
 562  *
 563  * Returns 0 on success. The USB PHY interfaces are configured but not
 564  * initialized. The PHY interfaces and the PHYs get initialized together with
 565  * the core in dwc3_core_init.
 566  */
 567 static int dwc3_phy_setup(struct dwc3 *dwc)
 568 {
 569         u32 reg;
 570
 571         reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
 572
 573         /*
 574          * Make sure UX_EXIT_PX is cleared as that causes issues with some
 575          * PHYs. Also, this bit is not supposed to be used in normal operation.
 576          */
 577         reg &= ~DWC3_GUSB3PIPECTL_UX_EXIT_PX;
 578
 579         /*
 580          * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY
 581          * to '0' during coreConsultant configuration. So default value
 582          * will be '0' when the core is reset. Application needs to set it
 583          * to '1' after the core initialization is completed.
 584          */
 585         if (dwc->revision > DWC3_REVISION_194A)
 586                 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
 587
 588         if (dwc->u2ss_inp3_quirk)
 589                 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK;
 590
 591         if (dwc->dis_rxdet_inp3_quirk)
 592                 reg |= DWC3_GUSB3PIPECTL_DISRXDETINP3;
 593
 594         if (dwc->req_p1p2p3_quirk)
 595                 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3;
 596
 597         if (dwc->del_p1p2p3_quirk)
 598                 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN;
 599
 600         if (dwc->del_phy_power_chg_quirk)
 601                 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE;
 602
 603         if (dwc->lfps_filter_quirk)
 604                 reg |= DWC3_GUSB3PIPECTL_LFPSFILT;
 605
 606         if (dwc->rx_detect_poll_quirk)
 607                 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL;
 608
 609         if (dwc->tx_de_emphasis_quirk)
 610                 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis);
 611
 612         if (dwc->dis_u3_susphy_quirk)
 613                 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
 614
 615         if (dwc->dis_del_phy_power_chg_quirk)
 616                 reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE;
 617
 618         dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
 619
 620         reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
 621
 622         /* Select the HS PHY interface */
 623         switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) {
 624         case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI:
 625                 if (dwc->hsphy_interface &&
 626                                 !strncmp(dwc->hsphy_interface, "utmi", 4)) {
 627                         reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI;
 628                         break;
 629                 } else if (dwc->hsphy_interface &&
 630                                 !strncmp(dwc->hsphy_interface, "ulpi", 4)) {
 631                         reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI;
 632                         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 633                 } else {
 634                         /* Relying on default value. */
 635                         if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI))
 636                                 break;
 637                 }
 638                 /* FALLTHROUGH */
 639         case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI:
 640                 /* FALLTHROUGH */
 641         default:
 642                 break;
 643         }
 644
 645         switch (dwc->hsphy_mode) {
 646         case USBPHY_INTERFACE_MODE_UTMI:
 647                 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
 648                        DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
 649                 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) |
 650                        DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT);
 651                 break;
 652         case USBPHY_INTERFACE_MODE_UTMIW:
 653                 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
 654                        DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
 655                 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) |
 656                        DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT);
 657                 break;
 658         default:
 659                 break;
 660         }
 661
 662         /*
 663          * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to
 664          * '0' during coreConsultant configuration. So default value will
 665          * be '0' when the core is reset. Application needs to set it to
 666          * '1' after the core initialization is completed.
 667          */
 668         if (dwc->revision > DWC3_REVISION_194A)
 669                 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
 670
 671         if (dwc->dis_u2_susphy_quirk)
 672                 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
 673
 674         if (dwc->dis_enblslpm_quirk)
 675                 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
 676         else
 677                 reg |= DWC3_GUSB2PHYCFG_ENBLSLPM;
 678
 679         if (dwc->dis_u2_freeclk_exists_quirk)
 680                 reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;
 681
 682         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 683
 684         return 0;
 685 }
 686
 687 static void dwc3_core_exit(struct dwc3 *dwc)
 688 {
 689         dwc3_event_buffers_cleanup(dwc);
 690
 691         usb_phy_shutdown(dwc->usb2_phy);
 692         usb_phy_shutdown(dwc->usb3_phy);
 693         phy_exit(dwc->usb2_generic_phy);
 694         phy_exit(dwc->usb3_generic_phy);
 695
 696         usb_phy_set_suspend(dwc->usb2_phy, 1);
 697         usb_phy_set_suspend(dwc->usb3_phy, 1);
 698         phy_power_off(dwc->usb2_generic_phy);
 699         phy_power_off(dwc->usb3_generic_phy);
 700         clk_bulk_disable_unprepare(dwc->num_clks, dwc->clks);
 701         reset_control_assert(dwc->reset);
 702 }
 703
 704 static bool dwc3_core_is_valid(struct dwc3 *dwc)
 705 {
 706         u32 reg;
 707
 708         reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
 709
 710         /* This should read as U3 followed by revision number */
 711         if ((reg & DWC3_GSNPSID_MASK) == 0x55330000) {
 712                 /* Detected DWC_usb3 IP */
 713                 dwc->revision = reg;
 714         } else if ((reg & DWC3_GSNPSID_MASK) == 0x33310000) {
 715                 /* Detected DWC_usb31 IP */
 716                 dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER);
 717                 dwc->revision |= DWC3_REVISION_IS_DWC31;
 718                 dwc->version_type = dwc3_readl(dwc->regs, DWC3_VER_TYPE);
 719         } else {
 720                 return false;
 721         }
 722
 723         return true;
 724 }
 725
 726 static void dwc3_core_setup_global_control(struct dwc3 *dwc)
 727 {
 728         u32 hwparams4 = dwc->hwparams.hwparams4;
 729         u32 reg;
 730
 731         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
 732         reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
 733
 734         switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
 735         case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
 736                 /**
 737                  * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an
 738                  * issue which would cause xHCI compliance tests to fail.
 739                  *
 740                  * Because of that we cannot enable clock gating on such
 741                  * configurations.
 742                  *
 743                  * Refers to:
 744                  *
 745                  * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based
 746                  * SOF/ITP Mode Used
 747                  */
 748                 if ((dwc->dr_mode == USB_DR_MODE_HOST ||
 749                                 dwc->dr_mode == USB_DR_MODE_OTG) &&
 750                                 (dwc->revision >= DWC3_REVISION_210A &&
 751                                 dwc->revision <= DWC3_REVISION_250A))
 752                         reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC;
 753                 else
 754                         reg &= ~DWC3_GCTL_DSBLCLKGTNG;
 755                 break;
 756         case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
 757                 /* enable hibernation here */
 758                 dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4);
 759
 760                 /*
 761                  * REVISIT Enabling this bit so that host-mode hibernation
 762                  * will work. Device-mode hibernation is not yet implemented.
 763                  */
 764                 reg |= DWC3_GCTL_GBLHIBERNATIONEN;
 765                 break;
 766         default:
 767                 /* nothing */
 768                 break;
 769         }
 770
 771         /* check if current dwc3 is on simulation board */
 772         if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) {
 773                 dev_info(dwc->dev, "Running with FPGA optimizations\n");
 774                 dwc->is_fpga = true;
 775         }
 776
 777         WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga,
 778                         "disable_scramble cannot be used on non-FPGA builds\n");
 779
 780         if (dwc->disable_scramble_quirk && dwc->is_fpga)
 781                 reg |= DWC3_GCTL_DISSCRAMBLE;
 782         else
 783                 reg &= ~DWC3_GCTL_DISSCRAMBLE;
 784
 785         if (dwc->u2exit_lfps_quirk)
 786                 reg |= DWC3_GCTL_U2EXIT_LFPS;
 787
 788         /*
 789          * WORKAROUND: DWC3 revisions <1.90a have a bug
 790          * where the device can fail to connect at SuperSpeed
 791          * and falls back to high-speed mode which causes
 792          * the device to enter a Connect/Disconnect loop
 793          */
 794         if (dwc->revision < DWC3_REVISION_190A)
 795                 reg |= DWC3_GCTL_U2RSTECN;
 796
 797         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
 798 }
 799
 800 static int dwc3_core_get_phy(struct dwc3 *dwc);
 801 static int dwc3_core_ulpi_init(struct dwc3 *dwc);
 802
 803 /* set global incr burst type configuration registers */
 804 static void dwc3_set_incr_burst_type(struct dwc3 *dwc)
 805 {
 806         struct device *dev = dwc->dev;
 807         /* incrx_mode : for INCR burst type. */
 808         bool incrx_mode;
 809         /* incrx_size : for size of INCRX burst. */
 810         u32 incrx_size;
 811         u32 *vals;
 812         u32 cfg;
 813         int ntype;
 814         int ret;
 815         int i;
 816
 817         cfg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0);
 818
 819         /*
 820          * Handle property "snps,incr-burst-type-adjustment".
 821          * Get the number of value from this property:
 822          * result <= 0, means this property is not supported.
 823          * result = 1, means INCRx burst mode supported.
 824          * result > 1, means undefined length burst mode supported.
 825          */
 826         ntype = device_property_count_u32(dev, "snps,incr-burst-type-adjustment");
 827         if (ntype <= 0)
 828                 return;
 829
 830         vals = kcalloc(ntype, sizeof(u32), GFP_KERNEL);
 831         if (!vals) {
 832                 dev_err(dev, "Error to get memory\n");
 833                 return;
 834         }
 835
 836         /* Get INCR burst type, and parse it */
 837         ret = device_property_read_u32_array(dev,
 838                         "snps,incr-burst-type-adjustment", vals, ntype);
 839         if (ret) {
 840                 kfree(vals);
 841                 dev_err(dev, "Error to get property\n");
 842                 return;
 843         }
 844
 845         incrx_size = *vals;
 846
 847         if (ntype > 1) {
 848                 /* INCRX (undefined length) burst mode */
 849                 incrx_mode = INCRX_UNDEF_LENGTH_BURST_MODE;
 850                 for (i = 1; i < ntype; i++) {
 851                         if (vals[i] > incrx_size)
 852                                 incrx_size = vals[i];
 853                 }
 854         } else {
 855                 /* INCRX burst mode */
 856                 incrx_mode = INCRX_BURST_MODE;
 857         }
 858
 859         kfree(vals);
 860
 861         /* Enable Undefined Length INCR Burst and Enable INCRx Burst */
 862         cfg &= ~DWC3_GSBUSCFG0_INCRBRST_MASK;
 863         if (incrx_mode)
 864                 cfg |= DWC3_GSBUSCFG0_INCRBRSTENA;
 865         switch (incrx_size) {
 866         case 256:
 867                 cfg |= DWC3_GSBUSCFG0_INCR256BRSTENA;
 868                 break;
 869         case 128:
 870                 cfg |= DWC3_GSBUSCFG0_INCR128BRSTENA;
 871                 break;
 872         case 64:
 873                 cfg |= DWC3_GSBUSCFG0_INCR64BRSTENA;
 874                 break;
 875         case 32:
 876                 cfg |= DWC3_GSBUSCFG0_INCR32BRSTENA;
 877                 break;
 878         case 16:
 879                 cfg |= DWC3_GSBUSCFG0_INCR16BRSTENA;
 880                 break;
 881         case 8:
 882                 cfg |= DWC3_GSBUSCFG0_INCR8BRSTENA;
 883                 break;
 884         case 4:
 885                 cfg |= DWC3_GSBUSCFG0_INCR4BRSTENA;
 886                 break;
 887         case 1:
 888                 break;
 889         default:
 890                 dev_err(dev, "Invalid property\n");
 891                 break;
 892         }
 893
 894         dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, cfg);
 895 }
 896
 897 /**
 898  * dwc3_core_init - Low-level initialization of DWC3 Core
 899  * @dwc: Pointer to our controller context structure
 900  *
 901  * Returns 0 on success otherwise negative errno.
 902  */
 903 static int dwc3_core_init(struct dwc3 *dwc)
 904 {
 905         u32                     reg;
 906         int                     ret;
 907
 908         /*
 909          * Write Linux Version Code to our GUID register so it's easy to figure
 910          * out which kernel version a bug was found.
 911          */
 912         dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE);
 913
 914         /* Handle USB2.0-only core configuration */
 915         if (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) ==
 916                         DWC3_GHWPARAMS3_SSPHY_IFC_DIS) {
 917                 if (dwc->maximum_speed == USB_SPEED_SUPER)
 918                         dwc->maximum_speed = USB_SPEED_HIGH;
 919         }
 920
 921         ret = dwc3_phy_setup(dwc);
 922         if (ret)
 923                 goto err0;
 924
 925         if (!dwc->ulpi_ready) {
 926                 ret = dwc3_core_ulpi_init(dwc);
 927                 if (ret)
 928                         goto err0;
 929                 dwc->ulpi_ready = true;
 930         }
 931
 932         if (!dwc->phys_ready) {
 933                 ret = dwc3_core_get_phy(dwc);
 934                 if (ret)
 935                         goto err0a;
 936                 dwc->phys_ready = true;
 937         }
 938
 939         ret = dwc3_core_soft_reset(dwc);
 940         if (ret)
 941                 goto err0a;
 942
 943         dwc3_core_setup_global_control(dwc);
 944         dwc3_core_num_eps(dwc);
 945
 946         ret = dwc3_setup_scratch_buffers(dwc);
 947         if (ret)
 948                 goto err1;
 949
 950         /* Adjust Frame Length */
 951         dwc3_frame_length_adjustment(dwc);
 952
 953         dwc3_set_incr_burst_type(dwc);
 954
 955         usb_phy_set_suspend(dwc->usb2_phy, 0);
 956         usb_phy_set_suspend(dwc->usb3_phy, 0);
 957         ret = phy_power_on(dwc->usb2_generic_phy);
 958         if (ret < 0)
 959                 goto err2;
 960
 961         ret = phy_power_on(dwc->usb3_generic_phy);
 962         if (ret < 0)
 963                 goto err3;
 964
 965         ret = dwc3_event_buffers_setup(dwc);
 966         if (ret) {
 967                 dev_err(dwc->dev, "failed to setup event buffers\n");
 968                 goto err4;
 969         }
 970
 971         /*
 972          * ENDXFER polling is available on version 3.10a and later of
 973          * the DWC_usb3 controller. It is NOT available in the
 974          * DWC_usb31 controller.
 975          */
 976         if (!dwc3_is_usb31(dwc) && dwc->revision >= DWC3_REVISION_310A) {
 977                 reg = dwc3_readl(dwc->regs, DWC3_GUCTL2);
 978                 reg |= DWC3_GUCTL2_RST_ACTBITLATER;
 979                 dwc3_writel(dwc->regs, DWC3_GUCTL2, reg);
 980         }
 981
 982         if (dwc->revision >= DWC3_REVISION_250A) {
 983                 reg = dwc3_readl(dwc->regs, DWC3_GUCTL1);
 984
 985                 /*
 986                  * Enable hardware control of sending remote wakeup
 987                  * in HS when the device is in the L1 state.
 988                  */
 989                 if (dwc->revision >= DWC3_REVISION_290A)
 990                         reg |= DWC3_GUCTL1_DEV_L1_EXIT_BY_HW;
 991
 992                 if (dwc->dis_tx_ipgap_linecheck_quirk)
 993                         reg |= DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS;
 994
 995                 dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
 996         }
 997
 998         if (dwc->dr_mode == USB_DR_MODE_HOST ||
 999             dwc->dr_mode == USB_DR_MODE_OTG) {
1000                 reg = dwc3_readl(dwc->regs, DWC3_GUCTL);
1001
1002                 /*
1003                  * Enable Auto retry Feature to make the controller operating in
1004                  * Host mode on seeing transaction errors(CRC errors or internal
1005                  * overrun scenerios) on IN transfers to reply to the device
1006                  * with a non-terminating retry ACK (i.e, an ACK transcation
1007                  * packet with Retry=1 & Nump != 0)
1008                  */
1009                 reg |= DWC3_GUCTL_HSTINAUTORETRY;
1010
1011                 dwc3_writel(dwc->regs, DWC3_GUCTL, reg);
1012         }
1013
1014         /*
1015          * Must config both number of packets and max burst settings to enable
1016          * RX and/or TX threshold.
1017          */
1018         if (dwc3_is_usb31(dwc) && dwc->dr_mode == USB_DR_MODE_HOST) {
1019                 u8 rx_thr_num = dwc->rx_thr_num_pkt_prd;
1020                 u8 rx_maxburst = dwc->rx_max_burst_prd;
1021                 u8 tx_thr_num = dwc->tx_thr_num_pkt_prd;
1022                 u8 tx_maxburst = dwc->tx_max_burst_prd;
1023
1024                 if (rx_thr_num && rx_maxburst) {
1025                         reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
1026                         reg |= DWC31_RXTHRNUMPKTSEL_PRD;
1027
1028                         reg &= ~DWC31_RXTHRNUMPKT_PRD(~0);
1029                         reg |= DWC31_RXTHRNUMPKT_PRD(rx_thr_num);
1030
1031                         reg &= ~DWC31_MAXRXBURSTSIZE_PRD(~0);
1032                         reg |= DWC31_MAXRXBURSTSIZE_PRD(rx_maxburst);
1033
1034                         dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
1035                 }
1036
1037                 if (tx_thr_num && tx_maxburst) {
1038                         reg = dwc3_readl(dwc->regs, DWC3_GTXTHRCFG);
1039                         reg |= DWC31_TXTHRNUMPKTSEL_PRD;
1040
1041                         reg &= ~DWC31_TXTHRNUMPKT_PRD(~0);
1042                         reg |= DWC31_TXTHRNUMPKT_PRD(tx_thr_num);
1043
1044                         reg &= ~DWC31_MAXTXBURSTSIZE_PRD(~0);
1045                         reg |= DWC31_MAXTXBURSTSIZE_PRD(tx_maxburst);
1046
1047                         dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg);
1048                 }
1049         }
1050
1051         return 0;
1052
1053 err4:
1054         phy_power_off(dwc->usb3_generic_phy);
1055
1056 err3:
1057         phy_power_off(dwc->usb2_generic_phy);
1058
1059 err2:
1060         usb_phy_set_suspend(dwc->usb2_phy, 1);
1061         usb_phy_set_suspend(dwc->usb3_phy, 1);
1062
1063 err1:
1064         usb_phy_shutdown(dwc->usb2_phy);
1065         usb_phy_shutdown(dwc->usb3_phy);
1066         phy_exit(dwc->usb2_generic_phy);
1067         phy_exit(dwc->usb3_generic_phy);
1068
1069 err0a:
1070         dwc3_ulpi_exit(dwc);
1071
1072 err0:
1073         return ret;
1074 }
1075
1076 static int dwc3_core_get_phy(struct dwc3 *dwc)
1077 {
1078         struct device           *dev = dwc->dev;
1079         struct device_node      *node = dev->of_node;
1080         int ret;
1081
1082         if (node) {
1083                 dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0);
1084                 dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1);
1085         } else {
1086                 dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
1087                 dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3);
1088         }
1089
1090         if (IS_ERR(dwc->usb2_phy)) {
1091                 ret = PTR_ERR(dwc->usb2_phy);
1092                 if (ret == -ENXIO || ret == -ENODEV) {
1093                         dwc->usb2_phy = NULL;
1094                 } else if (ret == -EPROBE_DEFER) {
1095                         return ret;
1096                 } else {
1097                         dev_err(dev, "no usb2 phy configured\n");
1098                         return ret;
1099                 }
1100         }
1101
1102         if (IS_ERR(dwc->usb3_phy)) {
1103                 ret = PTR_ERR(dwc->usb3_phy);
1104                 if (ret == -ENXIO || ret == -ENODEV) {
1105                         dwc->usb3_phy = NULL;
1106                 } else if (ret == -EPROBE_DEFER) {
1107                         return ret;
1108                 } else {
1109                         dev_err(dev, "no usb3 phy configured\n");
1110                         return ret;
1111                 }
1112         }
1113
1114         dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy");
1115         if (IS_ERR(dwc->usb2_generic_phy)) {
1116                 ret = PTR_ERR(dwc->usb2_generic_phy);
1117                 if (ret == -ENOSYS || ret == -ENODEV) {
1118                         dwc->usb2_generic_phy = NULL;
1119                 } else if (ret == -EPROBE_DEFER) {
1120                         return ret;
1121                 } else {
1122                         dev_err(dev, "no usb2 phy configured\n");
1123                         return ret;
1124                 }
1125         }
1126
1127         dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy");
1128         if (IS_ERR(dwc->usb3_generic_phy)) {
1129                 ret = PTR_ERR(dwc->usb3_generic_phy);
1130                 if (ret == -ENOSYS || ret == -ENODEV) {
1131                         dwc->usb3_generic_phy = NULL;
1132                 } else if (ret == -EPROBE_DEFER) {
1133                         return ret;
1134                 } else {
1135                         dev_err(dev, "no usb3 phy configured\n");
1136                         return ret;
1137                 }
1138         }
1139
1140         return 0;
1141 }
1142
1143 static int dwc3_core_init_mode(struct dwc3 *dwc)
1144 {
1145         struct device *dev = dwc->dev;
1146         int ret;
1147
1148         switch (dwc->dr_mode) {
1149         case USB_DR_MODE_PERIPHERAL:
1150                 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
1151
1152                 if (dwc->usb2_phy)
1153                         otg_set_vbus(dwc->usb2_phy->otg, false);
1154                 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
1155                 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE);
1156
1157                 ret = dwc3_gadget_init(dwc);
1158                 if (ret) {
1159                         if (ret != -EPROBE_DEFER)
1160                                 dev_err(dev, "failed to initialize gadget\n");
1161                         return ret;
1162                 }
1163                 break;
1164         case USB_DR_MODE_HOST:
1165                 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST);
1166
1167                 if (dwc->usb2_phy)
1168                         otg_set_vbus(dwc->usb2_phy->otg, true);
1169                 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
1170                 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
1171
1172                 ret = dwc3_host_init(dwc);
1173                 if (ret) {
1174                         if (ret != -EPROBE_DEFER)
1175                                 dev_err(dev, "failed to initialize host\n");
1176                         return ret;
1177                 }
1178                 break;
1179         case USB_DR_MODE_OTG:
1180                 INIT_WORK(&dwc->drd_work, __dwc3_set_mode);
1181                 ret = dwc3_drd_init(dwc);
1182                 if (ret) {
1183                         if (ret != -EPROBE_DEFER)
1184                                 dev_err(dev, "failed to initialize dual-role\n");
1185                         return ret;
1186                 }
1187                 break;
1188         default:
1189                 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode);
1190                 return -EINVAL;
1191         }
1192
1193         return 0;
1194 }
1195
1196 static void dwc3_core_exit_mode(struct dwc3 *dwc)
1197 {
1198         switch (dwc->dr_mode) {
1199         case USB_DR_MODE_PERIPHERAL:
1200                 dwc3_gadget_exit(dwc);
1201                 break;
1202         case USB_DR_MODE_HOST:
1203                 dwc3_host_exit(dwc);
1204                 break;
1205         case USB_DR_MODE_OTG:
1206                 dwc3_drd_exit(dwc);
1207                 break;
1208         default:
1209                 /* do nothing */
1210                 break;
1211         }
1212 }
1213
1214 static void dwc3_get_properties(struct dwc3 *dwc)
1215 {
1216         struct device           *dev = dwc->dev;
1217         u8                      lpm_nyet_threshold;
1218         u8                      tx_de_emphasis;
1219         u8                      hird_threshold;
1220         u8                      rx_thr_num_pkt_prd;
1221         u8                      rx_max_burst_prd;
1222         u8                      tx_thr_num_pkt_prd;
1223         u8                      tx_max_burst_prd;
1224
1225         /* default to highest possible threshold */
1226         lpm_nyet_threshold = 0xf;
1227
1228         /* default to -3.5dB de-emphasis */
1229         tx_de_emphasis = 1;
1230
1231         /*
1232          * default to assert utmi_sleep_n and use maximum allowed HIRD
1233          * threshold value of 0b1100
1234          */
1235         hird_threshold = 12;
1236
1237         dwc->maximum_speed = usb_get_maximum_speed(dev);
1238         dwc->dr_mode = usb_get_dr_mode(dev);
1239         dwc->hsphy_mode = of_usb_get_phy_mode(dev->of_node);
1240
1241         dwc->sysdev_is_parent = device_property_read_bool(dev,
1242                                 "linux,sysdev_is_parent");
1243         if (dwc->sysdev_is_parent)
1244                 dwc->sysdev = dwc->dev->parent;
1245         else
1246                 dwc->sysdev = dwc->dev;
1247
1248         dwc->has_lpm_erratum = device_property_read_bool(dev,
1249                                 "snps,has-lpm-erratum");
1250         device_property_read_u8(dev, "snps,lpm-nyet-threshold",
1251                                 &lpm_nyet_threshold);
1252         dwc->is_utmi_l1_suspend = device_property_read_bool(dev,
1253                                 "snps,is-utmi-l1-suspend");
1254         device_property_read_u8(dev, "snps,hird-threshold",
1255                                 &hird_threshold);
1256         dwc->dis_start_transfer_quirk = device_property_read_bool(dev,
1257                                 "snps,dis-start-transfer-quirk");
1258         dwc->usb3_lpm_capable = device_property_read_bool(dev,
1259                                 "snps,usb3_lpm_capable");
1260         dwc->usb2_lpm_disable = device_property_read_bool(dev,
1261                                 "snps,usb2-lpm-disable");
1262         device_property_read_u8(dev, "snps,rx-thr-num-pkt-prd",
1263                                 &rx_thr_num_pkt_prd);
1264         device_property_read_u8(dev, "snps,rx-max-burst-prd",
1265                                 &rx_max_burst_prd);
1266         device_property_read_u8(dev, "snps,tx-thr-num-pkt-prd",
1267                                 &tx_thr_num_pkt_prd);
1268         device_property_read_u8(dev, "snps,tx-max-burst-prd",
1269                                 &tx_max_burst_prd);
1270
1271         dwc->disable_scramble_quirk = device_property_read_bool(dev,
1272                                 "snps,disable_scramble_quirk");
1273         dwc->u2exit_lfps_quirk = device_property_read_bool(dev,
1274                                 "snps,u2exit_lfps_quirk");
1275         dwc->u2ss_inp3_quirk = device_property_read_bool(dev,
1276                                 "snps,u2ss_inp3_quirk");
1277         dwc->req_p1p2p3_quirk = device_property_read_bool(dev,
1278                                 "snps,req_p1p2p3_quirk");
1279         dwc->del_p1p2p3_quirk = device_property_read_bool(dev,
1280                                 "snps,del_p1p2p3_quirk");
1281         dwc->del_phy_power_chg_quirk = device_property_read_bool(dev,
1282                                 "snps,del_phy_power_chg_quirk");
1283         dwc->lfps_filter_quirk = device_property_read_bool(dev,
1284                                 "snps,lfps_filter_quirk");
1285         dwc->rx_detect_poll_quirk = device_property_read_bool(dev,
1286                                 "snps,rx_detect_poll_quirk");
1287         dwc->dis_u3_susphy_quirk = device_property_read_bool(dev,
1288                                 "snps,dis_u3_susphy_quirk");
1289         dwc->dis_u2_susphy_quirk = device_property_read_bool(dev,
1290                                 "snps,dis_u2_susphy_quirk");
1291         dwc->dis_enblslpm_quirk = device_property_read_bool(dev,
1292                                 "snps,dis_enblslpm_quirk");
1293         dwc->dis_u1_entry_quirk = device_property_read_bool(dev,
1294                                 "snps,dis-u1-entry-quirk");
1295         dwc->dis_u2_entry_quirk = device_property_read_bool(dev,
1296                                 "snps,dis-u2-entry-quirk");
1297         dwc->dis_rxdet_inp3_quirk = device_property_read_bool(dev,
1298                                 "snps,dis_rxdet_inp3_quirk");
1299         dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev,
1300                                 "snps,dis-u2-freeclk-exists-quirk");
1301         dwc->dis_del_phy_power_chg_quirk = device_property_read_bool(dev,
1302                                 "snps,dis-del-phy-power-chg-quirk");
1303         dwc->dis_tx_ipgap_linecheck_quirk = device_property_read_bool(dev,
1304                                 "snps,dis-tx-ipgap-linecheck-quirk");
1305
1306         dwc->tx_de_emphasis_quirk = device_property_read_bool(dev,
1307                                 "snps,tx_de_emphasis_quirk");
1308         device_property_read_u8(dev, "snps,tx_de_emphasis",
1309                                 &tx_de_emphasis);
1310         device_property_read_string(dev, "snps,hsphy_interface",
1311                                     &dwc->hsphy_interface);
1312         device_property_read_u32(dev, "snps,quirk-frame-length-adjustment",
1313                                  &dwc->fladj);
1314
1315         dwc->dis_metastability_quirk = device_property_read_bool(dev,
1316                                 "snps,dis_metastability_quirk");
1317
1318         dwc->lpm_nyet_threshold = lpm_nyet_threshold;
1319         dwc->tx_de_emphasis = tx_de_emphasis;
1320
1321         dwc->hird_threshold = hird_threshold;
1322
1323         dwc->rx_thr_num_pkt_prd = rx_thr_num_pkt_prd;
1324         dwc->rx_max_burst_prd = rx_max_burst_prd;
1325
1326         dwc->tx_thr_num_pkt_prd = tx_thr_num_pkt_prd;
1327         dwc->tx_max_burst_prd = tx_max_burst_prd;
1328
1329         dwc->imod_interval = 0;
1330 }
1331
1332 /* check whether the core supports IMOD */
1333 bool dwc3_has_imod(struct dwc3 *dwc)
1334 {
1335         return ((dwc3_is_usb3(dwc) &&
1336                  dwc->revision >= DWC3_REVISION_300A) ||
1337                 (dwc3_is_usb31(dwc) &&
1338                  dwc->revision >= DWC3_USB31_REVISION_120A));
1339 }
1340
1341 static void dwc3_check_params(struct dwc3 *dwc)
1342 {
1343         struct device *dev = dwc->dev;
1344
1345         /* Check for proper value of imod_interval */
1346         if (dwc->imod_interval && !dwc3_has_imod(dwc)) {
1347                 dev_warn(dwc->dev, "Interrupt moderation not supported\n");
1348                 dwc->imod_interval = 0;
1349         }
1350
1351         /*
1352          * Workaround for STAR 9000961433 which affects only version
1353          * 3.00a of the DWC_usb3 core. This prevents the controller
1354          * interrupt from being masked while handling events. IMOD
1355          * allows us to work around this issue. Enable it for the
1356          * affected version.
1357          */
1358         if (!dwc->imod_interval &&
1359             (dwc->revision == DWC3_REVISION_300A))
1360                 dwc->imod_interval = 1;
1361
1362         /* Check the maximum_speed parameter */
1363         switch (dwc->maximum_speed) {
1364         case USB_SPEED_LOW:
1365         case USB_SPEED_FULL:
1366         case USB_SPEED_HIGH:
1367         case USB_SPEED_SUPER:
1368         case USB_SPEED_SUPER_PLUS:
1369                 break;
1370         default:
1371                 dev_err(dev, "invalid maximum_speed parameter %d\n",
1372                         dwc->maximum_speed);
1373                 /* fall through */
1374         case USB_SPEED_UNKNOWN:
1375                 /* default to superspeed */
1376                 dwc->maximum_speed = USB_SPEED_SUPER;
1377
1378                 /*
1379                  * default to superspeed plus if we are capable.
1380                  */
1381                 if (dwc3_is_usb31(dwc) &&
1382                     (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) ==
1383                      DWC3_GHWPARAMS3_SSPHY_IFC_GEN2))
1384                         dwc->maximum_speed = USB_SPEED_SUPER_PLUS;
1385
1386                 break;
1387         }
1388 }
1389
1390 static int dwc3_probe(struct platform_device *pdev)
1391 {
1392         struct device           *dev = &pdev->dev;
1393         struct resource         *res, dwc_res;
1394         struct dwc3             *dwc;
1395
1396         int                     ret;
1397
1398         void __iomem            *regs;
1399
1400         dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL);
1401         if (!dwc)
1402                 return -ENOMEM;
1403
1404         dwc->clks = devm_kmemdup(dev, dwc3_core_clks, sizeof(dwc3_core_clks),
1405                                  GFP_KERNEL);
1406         if (!dwc->clks)
1407                 return -ENOMEM;
1408
1409         dwc->dev = dev;
1410
1411         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1412         if (!res) {
1413                 dev_err(dev, "missing memory resource\n");
1414                 return -ENODEV;
1415         }
1416
1417         dwc->xhci_resources[0].start = res->start;
1418         dwc->xhci_resources[0].end = dwc->xhci_resources[0].start +
1419                                         DWC3_XHCI_REGS_END;
1420         dwc->xhci_resources[0].flags = res->flags;
1421         dwc->xhci_resources[0].name = res->name;
1422
1423         /*
1424          * Request memory region but exclude xHCI regs,
1425          * since it will be requested by the xhci-plat driver.
1426          */
1427         dwc_res = *res;
1428         dwc_res.start += DWC3_GLOBALS_REGS_START;
1429
1430         regs = devm_ioremap_resource(dev, &dwc_res);
1431         if (IS_ERR(regs))
1432                 return PTR_ERR(regs);
1433
1434         dwc->regs       = regs;
1435         dwc->regs_size  = resource_size(&dwc_res);
1436
1437         dwc3_get_properties(dwc);
1438
1439         dwc->reset = devm_reset_control_get_optional_shared(dev, NULL);
1440         if (IS_ERR(dwc->reset))
1441                 return PTR_ERR(dwc->reset);
1442
1443         if (dev->of_node) {
1444                 dwc->num_clks = ARRAY_SIZE(dwc3_core_clks);
1445
1446                 ret = devm_clk_bulk_get(dev, dwc->num_clks, dwc->clks);
1447                 if (ret == -EPROBE_DEFER)
1448                         return ret;
1449                 /*
1450                  * Clocks are optional, but new DT platforms should support all
1451                  * clocks as required by the DT-binding.
1452                  */
1453                 if (ret)
1454                         dwc->num_clks = 0;
1455         }
1456
1457         ret = reset_control_deassert(dwc->reset);
1458         if (ret)
1459                 return ret;
1460
1461         ret = clk_bulk_prepare_enable(dwc->num_clks, dwc->clks);
1462         if (ret)
1463                 goto assert_reset;
1464
1465         if (!dwc3_core_is_valid(dwc)) {
1466                 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
1467                 ret = -ENODEV;
1468                 goto disable_clks;
1469         }
1470
1471         platform_set_drvdata(pdev, dwc);
1472         dwc3_cache_hwparams(dwc);
1473
1474         spin_lock_init(&dwc->lock);
1475
1476         pm_runtime_set_active(dev);
1477         pm_runtime_use_autosuspend(dev);
1478         pm_runtime_set_autosuspend_delay(dev, DWC3_DEFAULT_AUTOSUSPEND_DELAY);
1479         pm_runtime_enable(dev);
1480         ret = pm_runtime_get_sync(dev);
1481         if (ret < 0)
1482                 goto err1;
1483
1484         pm_runtime_forbid(dev);
1485
1486         ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
1487         if (ret) {
1488                 dev_err(dwc->dev, "failed to allocate event buffers\n");
1489                 ret = -ENOMEM;
1490                 goto err2;
1491         }
1492
1493         ret = dwc3_get_dr_mode(dwc);
1494         if (ret)
1495                 goto err3;
1496
1497         ret = dwc3_alloc_scratch_buffers(dwc);
1498         if (ret)
1499                 goto err3;
1500
1501         ret = dwc3_core_init(dwc);
1502         if (ret) {
1503                 if (ret != -EPROBE_DEFER)
1504                         dev_err(dev, "failed to initialize core: %d\n", ret);
1505                 goto err4;
1506         }
1507
1508         dwc3_check_params(dwc);
1509
1510         ret = dwc3_core_init_mode(dwc);
1511         if (ret)
1512                 goto err5;
1513
1514         dwc3_debugfs_init(dwc);
1515         pm_runtime_put(dev);
1516
1517         return 0;
1518
1519 err5:
1520         dwc3_event_buffers_cleanup(dwc);
1521         dwc3_ulpi_exit(dwc);
1522
1523 err4:
1524         dwc3_free_scratch_buffers(dwc);
1525
1526 err3:
1527         dwc3_free_event_buffers(dwc);
1528
1529 err2:
1530         pm_runtime_allow(&pdev->dev);
1531
1532 err1:
1533         pm_runtime_put_sync(&pdev->dev);
1534         pm_runtime_disable(&pdev->dev);
1535
1536 disable_clks:
1537         clk_bulk_disable_unprepare(dwc->num_clks, dwc->clks);
1538 assert_reset:
1539         reset_control_assert(dwc->reset);
1540
1541         return ret;
1542 }
1543
1544 static int dwc3_remove(struct platform_device *pdev)
1545 {
1546         struct dwc3     *dwc = platform_get_drvdata(pdev);
1547
1548         pm_runtime_get_sync(&pdev->dev);
1549
1550         dwc3_debugfs_exit(dwc);
1551         dwc3_core_exit_mode(dwc);
1552
1553         dwc3_core_exit(dwc);
1554         dwc3_ulpi_exit(dwc);
1555
1556         pm_runtime_put_sync(&pdev->dev);
1557         pm_runtime_allow(&pdev->dev);
1558         pm_runtime_disable(&pdev->dev);
1559
1560         dwc3_free_event_buffers(dwc);
1561         dwc3_free_scratch_buffers(dwc);
1562
1563         return 0;
1564 }
1565
1566 #ifdef CONFIG_PM
1567 static int dwc3_core_init_for_resume(struct dwc3 *dwc)
1568 {
1569         int ret;
1570
1571         ret = reset_control_deassert(dwc->reset);
1572         if (ret)
1573                 return ret;
1574
1575         ret = clk_bulk_prepare_enable(dwc->num_clks, dwc->clks);
1576         if (ret)
1577                 goto assert_reset;
1578
1579         ret = dwc3_core_init(dwc);
1580         if (ret)
1581                 goto disable_clks;
1582
1583         return 0;
1584
1585 disable_clks:
1586         clk_bulk_disable_unprepare(dwc->num_clks, dwc->clks);
1587 assert_reset:
1588         reset_control_assert(dwc->reset);
1589
1590         return ret;
1591 }
1592
1593 static int dwc3_suspend_common(struct dwc3 *dwc, pm_message_t msg)
1594 {
1595         unsigned long   flags;
1596         u32 reg;
1597
1598         switch (dwc->current_dr_role) {
1599         case DWC3_GCTL_PRTCAP_DEVICE:
1600                 spin_lock_irqsave(&dwc->lock, flags);
1601                 dwc3_gadget_suspend(dwc);
1602                 spin_unlock_irqrestore(&dwc->lock, flags);
1603                 synchronize_irq(dwc->irq_gadget);
1604                 dwc3_core_exit(dwc);
1605                 break;
1606         case DWC3_GCTL_PRTCAP_HOST:
1607                 if (!PMSG_IS_AUTO(msg)) {
1608                         dwc3_core_exit(dwc);
1609                         break;
1610                 }
1611
1612                 /* Let controller to suspend HSPHY before PHY driver suspends */
1613                 if (dwc->dis_u2_susphy_quirk ||
1614                     dwc->dis_enblslpm_quirk) {
1615                         reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
1616                         reg |=  DWC3_GUSB2PHYCFG_ENBLSLPM |
1617                                 DWC3_GUSB2PHYCFG_SUSPHY;
1618                         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
1619
1620                         /* Give some time for USB2 PHY to suspend */
1621                         usleep_range(5000, 6000);
1622                 }
1623
1624                 phy_pm_runtime_put_sync(dwc->usb2_generic_phy);
1625                 phy_pm_runtime_put_sync(dwc->usb3_generic_phy);
1626                 break;
1627         case DWC3_GCTL_PRTCAP_OTG:
1628                 /* do nothing during runtime_suspend */
1629                 if (PMSG_IS_AUTO(msg))
1630                         break;
1631
1632                 if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) {
1633                         spin_lock_irqsave(&dwc->lock, flags);
1634                         dwc3_gadget_suspend(dwc);
1635                         spin_unlock_irqrestore(&dwc->lock, flags);
1636                         synchronize_irq(dwc->irq_gadget);
1637                 }
1638
1639                 dwc3_otg_exit(dwc);
1640                 dwc3_core_exit(dwc);
1641                 break;
1642         default:
1643                 /* do nothing */
1644                 break;
1645         }
1646
1647         return 0;
1648 }
1649
1650 static int dwc3_resume_common(struct dwc3 *dwc, pm_message_t msg)
1651 {
1652         unsigned long   flags;
1653         int             ret;
1654         u32             reg;
1655
1656         switch (dwc->current_dr_role) {
1657         case DWC3_GCTL_PRTCAP_DEVICE:
1658                 ret = dwc3_core_init_for_resume(dwc);
1659                 if (ret)
1660                         return ret;
1661
1662                 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
1663                 spin_lock_irqsave(&dwc->lock, flags);
1664                 dwc3_gadget_resume(dwc);
1665                 spin_unlock_irqrestore(&dwc->lock, flags);
1666                 break;
1667         case DWC3_GCTL_PRTCAP_HOST:
1668                 if (!PMSG_IS_AUTO(msg)) {
1669                         ret = dwc3_core_init_for_resume(dwc);
1670                         if (ret)
1671                                 return ret;
1672                         dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST);
1673                         break;
1674                 }
1675                 /* Restore GUSB2PHYCFG bits that were modified in suspend */
1676                 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
1677                 if (dwc->dis_u2_susphy_quirk)
1678                         reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
1679
1680                 if (dwc->dis_enblslpm_quirk)
1681                         reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
1682
1683                 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
1684
1685                 phy_pm_runtime_get_sync(dwc->usb2_generic_phy);
1686                 phy_pm_runtime_get_sync(dwc->usb3_generic_phy);
1687                 break;
1688         case DWC3_GCTL_PRTCAP_OTG:
1689                 /* nothing to do on runtime_resume */
1690                 if (PMSG_IS_AUTO(msg))
1691                         break;
1692
1693                 ret = dwc3_core_init(dwc);
1694                 if (ret)
1695                         return ret;
1696
1697                 dwc3_set_prtcap(dwc, dwc->current_dr_role);
1698
1699                 dwc3_otg_init(dwc);
1700                 if (dwc->current_otg_role == DWC3_OTG_ROLE_HOST) {
1701                         dwc3_otg_host_init(dwc);
1702                 } else if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) {
1703                         spin_lock_irqsave(&dwc->lock, flags);
1704                         dwc3_gadget_resume(dwc);
1705                         spin_unlock_irqrestore(&dwc->lock, flags);
1706                 }
1707
1708                 break;
1709         default:
1710                 /* do nothing */
1711                 break;
1712         }
1713
1714         return 0;
1715 }
1716
1717 static int dwc3_runtime_checks(struct dwc3 *dwc)
1718 {
1719         switch (dwc->current_dr_role) {
1720         case DWC3_GCTL_PRTCAP_DEVICE:
1721                 if (dwc->connected)
1722                         return -EBUSY;
1723                 break;
1724         case DWC3_GCTL_PRTCAP_HOST:
1725         default:
1726                 /* do nothing */
1727                 break;
1728         }
1729
1730         return 0;
1731 }
1732
1733 static int dwc3_runtime_suspend(struct device *dev)
1734 {
1735         struct dwc3     *dwc = dev_get_drvdata(dev);
1736         int             ret;
1737
1738         if (dwc3_runtime_checks(dwc))
1739                 return -EBUSY;
1740
1741         ret = dwc3_suspend_common(dwc, PMSG_AUTO_SUSPEND);
1742         if (ret)
1743                 return ret;
1744
1745         device_init_wakeup(dev, true);
1746
1747         return 0;
1748 }
1749
1750 static int dwc3_runtime_resume(struct device *dev)
1751 {
1752         struct dwc3     *dwc = dev_get_drvdata(dev);
1753         int             ret;
1754
1755         device_init_wakeup(dev, false);
1756
1757         ret = dwc3_resume_common(dwc, PMSG_AUTO_RESUME);
1758         if (ret)
1759                 return ret;
1760
1761         switch (dwc->current_dr_role) {
1762         case DWC3_GCTL_PRTCAP_DEVICE:
1763                 dwc3_gadget_process_pending_events(dwc);
1764                 break;
1765         case DWC3_GCTL_PRTCAP_HOST:
1766         default:
1767                 /* do nothing */
1768                 break;
1769         }
1770
1771         pm_runtime_mark_last_busy(dev);
1772
1773         return 0;
1774 }
1775
1776 static int dwc3_runtime_idle(struct device *dev)
1777 {
1778         struct dwc3     *dwc = dev_get_drvdata(dev);
1779
1780         switch (dwc->current_dr_role) {
1781         case DWC3_GCTL_PRTCAP_DEVICE:
1782                 if (dwc3_runtime_checks(dwc))
1783                         return -EBUSY;
1784                 break;
1785         case DWC3_GCTL_PRTCAP_HOST:
1786         default:
1787                 /* do nothing */
1788                 break;
1789         }
1790
1791         pm_runtime_mark_last_busy(dev);
1792         pm_runtime_autosuspend(dev);
1793
1794         return 0;
1795 }
1796 #endif /* CONFIG_PM */
1797
1798 #ifdef CONFIG_PM_SLEEP
1799 static int dwc3_suspend(struct device *dev)
1800 {
1801         struct dwc3     *dwc = dev_get_drvdata(dev);
1802         int             ret;
1803
1804         ret = dwc3_suspend_common(dwc, PMSG_SUSPEND);
1805         if (ret)
1806                 return ret;
1807
1808         pinctrl_pm_select_sleep_state(dev);
1809
1810         return 0;
1811 }
1812
1813 static int dwc3_resume(struct device *dev)
1814 {
1815         struct dwc3     *dwc = dev_get_drvdata(dev);
1816         int             ret;
1817
1818         pinctrl_pm_select_default_state(dev);
1819
1820         ret = dwc3_resume_common(dwc, PMSG_RESUME);
1821         if (ret)
1822                 return ret;
1823
1824         pm_runtime_disable(dev);
1825         pm_runtime_set_active(dev);
1826         pm_runtime_enable(dev);
1827
1828         return 0;
1829 }
1830 #endif /* CONFIG_PM_SLEEP */
1831
1832 static const struct dev_pm_ops dwc3_dev_pm_ops = {
1833         SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume)
1834         SET_RUNTIME_PM_OPS(dwc3_runtime_suspend, dwc3_runtime_resume,
1835                         dwc3_runtime_idle)
1836 };
1837
1838 #ifdef CONFIG_OF
1839 static const struct of_device_id of_dwc3_match[] = {
1840         {
1841                 .compatible = "snps,dwc3"
1842         },
1843         {
1844                 .compatible = "synopsys,dwc3"
1845         },
1846         { },
1847 };
1848 MODULE_DEVICE_TABLE(of, of_dwc3_match);
1849 #endif
1850
1851 #ifdef CONFIG_ACPI
1852
1853 #define ACPI_ID_INTEL_BSW       "808622B7"
1854
1855 static const struct acpi_device_id dwc3_acpi_match[] = {
1856         { ACPI_ID_INTEL_BSW, 0 },
1857         { },
1858 };
1859 MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match);
1860 #endif
1861
1862 static struct platform_driver dwc3_driver = {
1863         .probe          = dwc3_probe,
1864         .remove         = dwc3_remove,
1865         .driver         = {
1866                 .name   = "dwc3",
1867                 .of_match_table = of_match_ptr(of_dwc3_match),
1868                 .acpi_match_table = ACPI_PTR(dwc3_acpi_match),
1869                 .pm     = &dwc3_dev_pm_ops,
1870         },
1871 };
1872
1873 module_platform_driver(dwc3_driver);
1874
1875 MODULE_ALIAS("platform:dwc3");
1876 MODULE_AUTHOR("Felipe Balbi <[email protected]>");
1877 MODULE_LICENSE("GPL v2");
1878 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");