drivers/gpu/drm/i915/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <[email protected]>
  25  *
  26  */
  27
  28 #include <linux/i2c.h>
  29 #include <linux/slab.h>
  30 #include <linux/export.h>
  31 #include <linux/types.h>
  32 #include <linux/notifier.h>
  33 #include <linux/reboot.h>
  34 #include <asm/byteorder.h>
  35 #include <drm/drmP.h>
  36 #include <drm/drm_atomic_helper.h>
  37 #include <drm/drm_crtc.h>
  38 #include <drm/drm_crtc_helper.h>
  39 #include <drm/drm_edid.h>
  40 #include "intel_drv.h"
  41 #include <drm/i915_drm.h>
  42 #include "i915_drv.h"
  43
  44 #define DP_LINK_CHECK_TIMEOUT   (10 * 1000)
  45
  46 /* Compliance test status bits  */
  47 #define INTEL_DP_RESOLUTION_SHIFT_MASK  0
  48 #define INTEL_DP_RESOLUTION_PREFERRED   (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  49 #define INTEL_DP_RESOLUTION_STANDARD    (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  50 #define INTEL_DP_RESOLUTION_FAILSAFE    (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  51
  52 struct dp_link_dpll {
  53         int clock;
  54         struct dpll dpll;
  55 };
  56
  57 static const struct dp_link_dpll gen4_dpll[] = {
  58         { 162000,
  59                 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
  60         { 270000,
  61                 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
  62 };
  63
  64 static const struct dp_link_dpll pch_dpll[] = {
  65         { 162000,
  66                 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
  67         { 270000,
  68                 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
  69 };
  70
  71 static const struct dp_link_dpll vlv_dpll[] = {
  72         { 162000,
  73                 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
  74         { 270000,
  75                 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
  76 };
  77
  78 /*
  79  * CHV supports eDP 1.4 that have  more link rates.
  80  * Below only provides the fixed rate but exclude variable rate.
  81  */
  82 static const struct dp_link_dpll chv_dpll[] = {
  83         /*
  84          * CHV requires to program fractional division for m2.
  85          * m2 is stored in fixed point format using formula below
  86          * (m2_int << 22) | m2_fraction
  87          */
  88         { 162000,       /* m2_int = 32, m2_fraction = 1677722 */
  89                 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
  90         { 270000,       /* m2_int = 27, m2_fraction = 0 */
  91                 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
  92         { 540000,       /* m2_int = 27, m2_fraction = 0 */
  93                 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
  94 };
  95
  96 static const int bxt_rates[] = { 162000, 216000, 243000, 270000,
  97                                   324000, 432000, 540000 };
  98 static const int skl_rates[] = { 162000, 216000, 270000,
  99                                   324000, 432000, 540000 };
 100 static const int default_rates[] = { 162000, 270000, 540000 };
 101
 102 /**
 103  * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
 104  * @intel_dp: DP struct
 105  *
 106  * If a CPU or PCH DP output is attached to an eDP panel, this function
 107  * will return true, and false otherwise.
 108  */
 109 static bool is_edp(struct intel_dp *intel_dp)
 110 {
 111         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 112
 113         return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
 114 }
 115
 116 static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
 117 {
 118         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 119
 120         return intel_dig_port->base.base.dev;
 121 }
 122
 123 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
 124 {
 125         return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
 126 }
 127
 128 static void intel_dp_link_down(struct intel_dp *intel_dp);
 129 static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
 130 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
 131 static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp);
 132 static void vlv_steal_power_sequencer(struct drm_device *dev,
 133                                       enum pipe pipe);
 134 static void intel_dp_unset_edid(struct intel_dp *intel_dp);
 135
 136 static int intel_dp_num_rates(u8 link_bw_code)
 137 {
 138         switch (link_bw_code) {
 139         default:
 140                 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
 141                      link_bw_code);
 142         case DP_LINK_BW_1_62:
 143                 return 1;
 144         case DP_LINK_BW_2_7:
 145                 return 2;
 146         case DP_LINK_BW_5_4:
 147                 return 3;
 148         }
 149 }
 150
 151 /* update sink rates from dpcd */
 152 static void intel_dp_set_sink_rates(struct intel_dp *intel_dp)
 153 {
 154         int i, num_rates;
 155
 156         num_rates = intel_dp_num_rates(intel_dp->dpcd[DP_MAX_LINK_RATE]);
 157
 158         for (i = 0; i < num_rates; i++)
 159                 intel_dp->sink_rates[i] = default_rates[i];
 160
 161         intel_dp->num_sink_rates = num_rates;
 162 }
 163
 164 /* Theoretical max between source and sink */
 165 static int intel_dp_max_common_rate(struct intel_dp *intel_dp)
 166 {
 167         return intel_dp->common_rates[intel_dp->num_common_rates - 1];
 168 }
 169
 170 /* Theoretical max between source and sink */
 171 static int intel_dp_max_common_lane_count(struct intel_dp *intel_dp)
 172 {
 173         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 174         int source_max = intel_dig_port->max_lanes;
 175         int sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
 176
 177         return min(source_max, sink_max);
 178 }
 179
 180 int intel_dp_max_lane_count(struct intel_dp *intel_dp)
 181 {
 182         return intel_dp->max_link_lane_count;
 183 }
 184
 185 int
 186 intel_dp_link_required(int pixel_clock, int bpp)
 187 {
 188         /* pixel_clock is in kHz, divide bpp by 8 for bit to Byte conversion */
 189         return DIV_ROUND_UP(pixel_clock * bpp, 8);
 190 }
 191
 192 int
 193 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
 194 {
 195         /* max_link_clock is the link symbol clock (LS_Clk) in kHz and not the
 196          * link rate that is generally expressed in Gbps. Since, 8 bits of data
 197          * is transmitted every LS_Clk per lane, there is no need to account for
 198          * the channel encoding that is done in the PHY layer here.
 199          */
 200
 201         return max_link_clock * max_lanes;
 202 }
 203
 204 static int
 205 intel_dp_downstream_max_dotclock(struct intel_dp *intel_dp)
 206 {
 207         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 208         struct intel_encoder *encoder = &intel_dig_port->base;
 209         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 210         int max_dotclk = dev_priv->max_dotclk_freq;
 211         int ds_max_dotclk;
 212
 213         int type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
 214
 215         if (type != DP_DS_PORT_TYPE_VGA)
 216                 return max_dotclk;
 217
 218         ds_max_dotclk = drm_dp_downstream_max_clock(intel_dp->dpcd,
 219                                                     intel_dp->downstream_ports);
 220
 221         if (ds_max_dotclk != 0)
 222                 max_dotclk = min(max_dotclk, ds_max_dotclk);
 223
 224         return max_dotclk;
 225 }
 226
 227 static void
 228 intel_dp_set_source_rates(struct intel_dp *intel_dp)
 229 {
 230         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
 231         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
 232         const int *source_rates;
 233         int size;
 234
 235         /* This should only be done once */
 236         WARN_ON(intel_dp->source_rates || intel_dp->num_source_rates);
 237
 238         if (IS_GEN9_LP(dev_priv)) {
 239                 source_rates = bxt_rates;
 240                 size = ARRAY_SIZE(bxt_rates);
 241         } else if (IS_GEN9_BC(dev_priv)) {
 242                 source_rates = skl_rates;
 243                 size = ARRAY_SIZE(skl_rates);
 244         } else {
 245                 source_rates = default_rates;
 246                 size = ARRAY_SIZE(default_rates);
 247         }
 248
 249         /* This depends on the fact that 5.4 is last value in the array */
 250         if (!intel_dp_source_supports_hbr2(intel_dp))
 251                 size--;
 252
 253         intel_dp->source_rates = source_rates;
 254         intel_dp->num_source_rates = size;
 255 }
 256
 257 static int intersect_rates(const int *source_rates, int source_len,
 258                            const int *sink_rates, int sink_len,
 259                            int *common_rates)
 260 {
 261         int i = 0, j = 0, k = 0;
 262
 263         while (i < source_len && j < sink_len) {
 264                 if (source_rates[i] == sink_rates[j]) {
 265                         if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
 266                                 return k;
 267                         common_rates[k] = source_rates[i];
 268                         ++k;
 269                         ++i;
 270                         ++j;
 271                 } else if (source_rates[i] < sink_rates[j]) {
 272                         ++i;
 273                 } else {
 274                         ++j;
 275                 }
 276         }
 277         return k;
 278 }
 279
 280 /* return index of rate in rates array, or -1 if not found */
 281 static int intel_dp_rate_index(const int *rates, int len, int rate)
 282 {
 283         int i;
 284
 285         for (i = 0; i < len; i++)
 286                 if (rate == rates[i])
 287                         return i;
 288
 289         return -1;
 290 }
 291
 292 static void intel_dp_set_common_rates(struct intel_dp *intel_dp)
 293 {
 294         WARN_ON(!intel_dp->num_source_rates || !intel_dp->num_sink_rates);
 295
 296         intel_dp->num_common_rates = intersect_rates(intel_dp->source_rates,
 297                                                      intel_dp->num_source_rates,
 298                                                      intel_dp->sink_rates,
 299                                                      intel_dp->num_sink_rates,
 300                                                      intel_dp->common_rates);
 301
 302         /* Paranoia, there should always be something in common. */
 303         if (WARN_ON(intel_dp->num_common_rates == 0)) {
 304                 intel_dp->common_rates[0] = default_rates[0];
 305                 intel_dp->num_common_rates = 1;
 306         }
 307 }
 308
 309 /* get length of common rates potentially limited by max_rate */
 310 static int intel_dp_common_len_rate_limit(struct intel_dp *intel_dp,
 311                                           int max_rate)
 312 {
 313         const int *common_rates = intel_dp->common_rates;
 314         int i, common_len = intel_dp->num_common_rates;
 315
 316         /* Limit results by potentially reduced max rate */
 317         for (i = 0; i < common_len; i++) {
 318                 if (common_rates[common_len - i - 1] <= max_rate)
 319                         return common_len - i;
 320         }
 321
 322         return 0;
 323 }
 324
 325 static bool intel_dp_link_params_valid(struct intel_dp *intel_dp)
 326 {
 327         /*
 328          * FIXME: we need to synchronize the current link parameters with
 329          * hardware readout. Currently fast link training doesn't work on
 330          * boot-up.
 331          */
 332         if (intel_dp->link_rate == 0 ||
 333             intel_dp->link_rate > intel_dp->max_link_rate)
 334                 return false;
 335
 336         if (intel_dp->lane_count == 0 ||
 337             intel_dp->lane_count > intel_dp_max_lane_count(intel_dp))
 338                 return false;
 339
 340         return true;
 341 }
 342
 343 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp,
 344                                             int link_rate, uint8_t lane_count)
 345 {
 346         int index;
 347
 348         index = intel_dp_rate_index(intel_dp->common_rates,
 349                                     intel_dp->num_common_rates,
 350                                     link_rate);
 351         if (index > 0) {
 352                 intel_dp->max_link_rate = intel_dp->common_rates[index - 1];
 353                 intel_dp->max_link_lane_count = lane_count;
 354         } else if (lane_count > 1) {
 355                 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
 356                 intel_dp->max_link_lane_count = lane_count >> 1;
 357         } else {
 358                 DRM_ERROR("Link Training Unsuccessful\n");
 359                 return -1;
 360         }
 361
 362         return 0;
 363 }
 364
 365 static enum drm_mode_status
 366 intel_dp_mode_valid(struct drm_connector *connector,
 367                     struct drm_display_mode *mode)
 368 {
 369         struct intel_dp *intel_dp = intel_attached_dp(connector);
 370         struct intel_connector *intel_connector = to_intel_connector(connector);
 371         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 372         int target_clock = mode->clock;
 373         int max_rate, mode_rate, max_lanes, max_link_clock;
 374         int max_dotclk;
 375
 376         max_dotclk = intel_dp_downstream_max_dotclock(intel_dp);
 377
 378         if (is_edp(intel_dp) && fixed_mode) {
 379                 if (mode->hdisplay > fixed_mode->hdisplay)
 380                         return MODE_PANEL;
 381
 382                 if (mode->vdisplay > fixed_mode->vdisplay)
 383                         return MODE_PANEL;
 384
 385                 target_clock = fixed_mode->clock;
 386         }
 387
 388         max_link_clock = intel_dp_max_link_rate(intel_dp);
 389         max_lanes = intel_dp_max_lane_count(intel_dp);
 390
 391         max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
 392         mode_rate = intel_dp_link_required(target_clock, 18);
 393
 394         if (mode_rate > max_rate || target_clock > max_dotclk)
 395                 return MODE_CLOCK_HIGH;
 396
 397         if (mode->clock < 10000)
 398                 return MODE_CLOCK_LOW;
 399
 400         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
 401                 return MODE_H_ILLEGAL;
 402
 403         return MODE_OK;
 404 }
 405
 406 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes)
 407 {
 408         int     i;
 409         uint32_t v = 0;
 410
 411         if (src_bytes > 4)
 412                 src_bytes = 4;
 413         for (i = 0; i < src_bytes; i++)
 414                 v |= ((uint32_t) src[i]) << ((3-i) * 8);
 415         return v;
 416 }
 417
 418 static void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
 419 {
 420         int i;
 421         if (dst_bytes > 4)
 422                 dst_bytes = 4;
 423         for (i = 0; i < dst_bytes; i++)
 424                 dst[i] = src >> ((3-i) * 8);
 425 }
 426
 427 static void
 428 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
 429                                     struct intel_dp *intel_dp);
 430 static void
 431 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
 432                                               struct intel_dp *intel_dp,
 433                                               bool force_disable_vdd);
 434 static void
 435 intel_dp_pps_init(struct drm_device *dev, struct intel_dp *intel_dp);
 436
 437 static void pps_lock(struct intel_dp *intel_dp)
 438 {
 439         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 440         struct intel_encoder *encoder = &intel_dig_port->base;
 441         struct drm_device *dev = encoder->base.dev;
 442         struct drm_i915_private *dev_priv = to_i915(dev);
 443
 444         /*
 445          * See vlv_power_sequencer_reset() why we need
 446          * a power domain reference here.
 447          */
 448         intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
 449
 450         mutex_lock(&dev_priv->pps_mutex);
 451 }
 452
 453 static void pps_unlock(struct intel_dp *intel_dp)
 454 {
 455         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 456         struct intel_encoder *encoder = &intel_dig_port->base;
 457         struct drm_device *dev = encoder->base.dev;
 458         struct drm_i915_private *dev_priv = to_i915(dev);
 459
 460         mutex_unlock(&dev_priv->pps_mutex);
 461
 462         intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
 463 }
 464
 465 static void
 466 vlv_power_sequencer_kick(struct intel_dp *intel_dp)
 467 {
 468         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 469         struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
 470         enum pipe pipe = intel_dp->pps_pipe;
 471         bool pll_enabled, release_cl_override = false;
 472         enum dpio_phy phy = DPIO_PHY(pipe);
 473         enum dpio_channel ch = vlv_pipe_to_channel(pipe);
 474         uint32_t DP;
 475
 476         if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN,
 477                  "skipping pipe %c power seqeuncer kick due to port %c being active\n",
 478                  pipe_name(pipe), port_name(intel_dig_port->port)))
 479                 return;
 480
 481         DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
 482                       pipe_name(pipe), port_name(intel_dig_port->port));
 483
 484         /* Preserve the BIOS-computed detected bit. This is
 485          * supposed to be read-only.
 486          */
 487         DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
 488         DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
 489         DP |= DP_PORT_WIDTH(1);
 490         DP |= DP_LINK_TRAIN_PAT_1;
 491
 492         if (IS_CHERRYVIEW(dev_priv))
 493                 DP |= DP_PIPE_SELECT_CHV(pipe);
 494         else if (pipe == PIPE_B)
 495                 DP |= DP_PIPEB_SELECT;
 496
 497         pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE;
 498
 499         /*
 500          * The DPLL for the pipe must be enabled for this to work.
 501          * So enable temporarily it if it's not already enabled.
 502          */
 503         if (!pll_enabled) {
 504                 release_cl_override = IS_CHERRYVIEW(dev_priv) &&
 505                         !chv_phy_powergate_ch(dev_priv, phy, ch, true);
 506
 507                 if (vlv_force_pll_on(dev_priv, pipe, IS_CHERRYVIEW(dev_priv) ?
 508                                      &chv_dpll[0].dpll : &vlv_dpll[0].dpll)) {
 509                         DRM_ERROR("Failed to force on pll for pipe %c!\n",
 510                                   pipe_name(pipe));
 511                         return;
 512                 }
 513         }
 514
 515         /*
 516          * Similar magic as in intel_dp_enable_port().
 517          * We _must_ do this port enable + disable trick
 518          * to make this power seqeuencer lock onto the port.
 519          * Otherwise even VDD force bit won't work.
 520          */
 521         I915_WRITE(intel_dp->output_reg, DP);
 522         POSTING_READ(intel_dp->output_reg);
 523
 524         I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN);
 525         POSTING_READ(intel_dp->output_reg);
 526
 527         I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
 528         POSTING_READ(intel_dp->output_reg);
 529
 530         if (!pll_enabled) {
 531                 vlv_force_pll_off(dev_priv, pipe);
 532
 533                 if (release_cl_override)
 534                         chv_phy_powergate_ch(dev_priv, phy, ch, false);
 535         }
 536 }
 537
 538 static enum pipe vlv_find_free_pps(struct drm_i915_private *dev_priv)
 539 {
 540         struct intel_encoder *encoder;
 541         unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
 542
 543         /*
 544          * We don't have power sequencer currently.
 545          * Pick one that's not used by other ports.
 546          */
 547         for_each_intel_encoder(&dev_priv->drm, encoder) {
 548                 struct intel_dp *intel_dp;
 549
 550                 if (encoder->type != INTEL_OUTPUT_DP &&
 551                     encoder->type != INTEL_OUTPUT_EDP)
 552                         continue;
 553
 554                 intel_dp = enc_to_intel_dp(&encoder->base);
 555
 556                 if (encoder->type == INTEL_OUTPUT_EDP) {
 557                         WARN_ON(intel_dp->active_pipe != INVALID_PIPE &&
 558                                 intel_dp->active_pipe != intel_dp->pps_pipe);
 559
 560                         if (intel_dp->pps_pipe != INVALID_PIPE)
 561                                 pipes &= ~(1 << intel_dp->pps_pipe);
 562                 } else {
 563                         WARN_ON(intel_dp->pps_pipe != INVALID_PIPE);
 564
 565                         if (intel_dp->active_pipe != INVALID_PIPE)
 566                                 pipes &= ~(1 << intel_dp->active_pipe);
 567                 }
 568         }
 569
 570         if (pipes == 0)
 571                 return INVALID_PIPE;
 572
 573         return ffs(pipes) - 1;
 574 }
 575
 576 static enum pipe
 577 vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
 578 {
 579         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 580         struct drm_device *dev = intel_dig_port->base.base.dev;
 581         struct drm_i915_private *dev_priv = to_i915(dev);
 582         enum pipe pipe;
 583
 584         lockdep_assert_held(&dev_priv->pps_mutex);
 585
 586         /* We should never land here with regular DP ports */
 587         WARN_ON(!is_edp(intel_dp));
 588
 589         WARN_ON(intel_dp->active_pipe != INVALID_PIPE &&
 590                 intel_dp->active_pipe != intel_dp->pps_pipe);
 591
 592         if (intel_dp->pps_pipe != INVALID_PIPE)
 593                 return intel_dp->pps_pipe;
 594
 595         pipe = vlv_find_free_pps(dev_priv);
 596
 597         /*
 598          * Didn't find one. This should not happen since there
 599          * are two power sequencers and up to two eDP ports.
 600          */
 601         if (WARN_ON(pipe == INVALID_PIPE))
 602                 pipe = PIPE_A;
 603
 604         vlv_steal_power_sequencer(dev, pipe);
 605         intel_dp->pps_pipe = pipe;
 606
 607         DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
 608                       pipe_name(intel_dp->pps_pipe),
 609                       port_name(intel_dig_port->port));
 610
 611         /* init power sequencer on this pipe and port */
 612         intel_dp_init_panel_power_sequencer(dev, intel_dp);
 613         intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, true);
 614
 615         /*
 616          * Even vdd force doesn't work until we've made
 617          * the power sequencer lock in on the port.
 618          */
 619         vlv_power_sequencer_kick(intel_dp);
 620
 621         return intel_dp->pps_pipe;
 622 }
 623
 624 static int
 625 bxt_power_sequencer_idx(struct intel_dp *intel_dp)
 626 {
 627         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 628         struct drm_device *dev = intel_dig_port->base.base.dev;
 629         struct drm_i915_private *dev_priv = to_i915(dev);
 630
 631         lockdep_assert_held(&dev_priv->pps_mutex);
 632
 633         /* We should never land here with regular DP ports */
 634         WARN_ON(!is_edp(intel_dp));
 635
 636         /*
 637          * TODO: BXT has 2 PPS instances. The correct port->PPS instance
 638          * mapping needs to be retrieved from VBT, for now just hard-code to
 639          * use instance #0 always.
 640          */
 641         if (!intel_dp->pps_reset)
 642                 return 0;
 643
 644         intel_dp->pps_reset = false;
 645
 646         /*
 647          * Only the HW needs to be reprogrammed, the SW state is fixed and
 648          * has been setup during connector init.
 649          */
 650         intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, false);
 651
 652         return 0;
 653 }
 654
 655 typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
 656                                enum pipe pipe);
 657
 658 static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
 659                                enum pipe pipe)
 660 {
 661         return I915_READ(PP_STATUS(pipe)) & PP_ON;
 662 }
 663
 664 static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
 665                                 enum pipe pipe)
 666 {
 667         return I915_READ(PP_CONTROL(pipe)) & EDP_FORCE_VDD;
 668 }
 669
 670 static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
 671                          enum pipe pipe)
 672 {
 673         return true;
 674 }
 675
 676 static enum pipe
 677 vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
 678                      enum port port,
 679                      vlv_pipe_check pipe_check)
 680 {
 681         enum pipe pipe;
 682
 683         for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
 684                 u32 port_sel = I915_READ(PP_ON_DELAYS(pipe)) &
 685                         PANEL_PORT_SELECT_MASK;
 686
 687                 if (port_sel != PANEL_PORT_SELECT_VLV(port))
 688                         continue;
 689
 690                 if (!pipe_check(dev_priv, pipe))
 691                         continue;
 692
 693                 return pipe;
 694         }
 695
 696         return INVALID_PIPE;
 697 }
 698
 699 static void
 700 vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
 701 {
 702         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 703         struct drm_device *dev = intel_dig_port->base.base.dev;
 704         struct drm_i915_private *dev_priv = to_i915(dev);
 705         enum port port = intel_dig_port->port;
 706
 707         lockdep_assert_held(&dev_priv->pps_mutex);
 708
 709         /* try to find a pipe with this port selected */
 710         /* first pick one where the panel is on */
 711         intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 712                                                   vlv_pipe_has_pp_on);
 713         /* didn't find one? pick one where vdd is on */
 714         if (intel_dp->pps_pipe == INVALID_PIPE)
 715                 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 716                                                           vlv_pipe_has_vdd_on);
 717         /* didn't find one? pick one with just the correct port */
 718         if (intel_dp->pps_pipe == INVALID_PIPE)
 719                 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 720                                                           vlv_pipe_any);
 721
 722         /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
 723         if (intel_dp->pps_pipe == INVALID_PIPE) {
 724                 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
 725                               port_name(port));
 726                 return;
 727         }
 728
 729         DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
 730                       port_name(port), pipe_name(intel_dp->pps_pipe));
 731
 732         intel_dp_init_panel_power_sequencer(dev, intel_dp);
 733         intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, false);
 734 }
 735
 736 void intel_power_sequencer_reset(struct drm_i915_private *dev_priv)
 737 {
 738         struct drm_device *dev = &dev_priv->drm;
 739         struct intel_encoder *encoder;
 740
 741         if (WARN_ON(!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) &&
 742                     !IS_GEN9_LP(dev_priv)))
 743                 return;
 744
 745         /*
 746          * We can't grab pps_mutex here due to deadlock with power_domain
 747          * mutex when power_domain functions are called while holding pps_mutex.
 748          * That also means that in order to use pps_pipe the code needs to
 749          * hold both a power domain reference and pps_mutex, and the power domain
 750          * reference get/put must be done while _not_ holding pps_mutex.
 751          * pps_{lock,unlock}() do these steps in the correct order, so one
 752          * should use them always.
 753          */
 754
 755         for_each_intel_encoder(dev, encoder) {
 756                 struct intel_dp *intel_dp;
 757
 758                 if (encoder->type != INTEL_OUTPUT_DP &&
 759                     encoder->type != INTEL_OUTPUT_EDP)
 760                         continue;
 761
 762                 intel_dp = enc_to_intel_dp(&encoder->base);
 763
 764                 WARN_ON(intel_dp->active_pipe != INVALID_PIPE);
 765
 766                 if (encoder->type != INTEL_OUTPUT_EDP)
 767                         continue;
 768
 769                 if (IS_GEN9_LP(dev_priv))
 770                         intel_dp->pps_reset = true;
 771                 else
 772                         intel_dp->pps_pipe = INVALID_PIPE;
 773         }
 774 }
 775
 776 struct pps_registers {
 777         i915_reg_t pp_ctrl;
 778         i915_reg_t pp_stat;
 779         i915_reg_t pp_on;
 780         i915_reg_t pp_off;
 781         i915_reg_t pp_div;
 782 };
 783
 784 static void intel_pps_get_registers(struct drm_i915_private *dev_priv,
 785                                     struct intel_dp *intel_dp,
 786                                     struct pps_registers *regs)
 787 {
 788         int pps_idx = 0;
 789
 790         memset(regs, 0, sizeof(*regs));
 791
 792         if (IS_GEN9_LP(dev_priv))
 793                 pps_idx = bxt_power_sequencer_idx(intel_dp);
 794         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
 795                 pps_idx = vlv_power_sequencer_pipe(intel_dp);
 796
 797         regs->pp_ctrl = PP_CONTROL(pps_idx);
 798         regs->pp_stat = PP_STATUS(pps_idx);
 799         regs->pp_on = PP_ON_DELAYS(pps_idx);
 800         regs->pp_off = PP_OFF_DELAYS(pps_idx);
 801         if (!IS_GEN9_LP(dev_priv))
 802                 regs->pp_div = PP_DIVISOR(pps_idx);
 803 }
 804
 805 static i915_reg_t
 806 _pp_ctrl_reg(struct intel_dp *intel_dp)
 807 {
 808         struct pps_registers regs;
 809
 810         intel_pps_get_registers(to_i915(intel_dp_to_dev(intel_dp)), intel_dp,
 811                                 &regs);
 812
 813         return regs.pp_ctrl;
 814 }
 815
 816 static i915_reg_t
 817 _pp_stat_reg(struct intel_dp *intel_dp)
 818 {
 819         struct pps_registers regs;
 820
 821         intel_pps_get_registers(to_i915(intel_dp_to_dev(intel_dp)), intel_dp,
 822                                 &regs);
 823
 824         return regs.pp_stat;
 825 }
 826
 827 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing
 828    This function only applicable when panel PM state is not to be tracked */
 829 static int edp_notify_handler(struct notifier_block *this, unsigned long code,
 830                               void *unused)
 831 {
 832         struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
 833                                                  edp_notifier);
 834         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 835         struct drm_i915_private *dev_priv = to_i915(dev);
 836
 837         if (!is_edp(intel_dp) || code != SYS_RESTART)
 838                 return 0;
 839
 840         pps_lock(intel_dp);
 841
 842         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
 843                 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
 844                 i915_reg_t pp_ctrl_reg, pp_div_reg;
 845                 u32 pp_div;
 846
 847                 pp_ctrl_reg = PP_CONTROL(pipe);
 848                 pp_div_reg  = PP_DIVISOR(pipe);
 849                 pp_div = I915_READ(pp_div_reg);
 850                 pp_div &= PP_REFERENCE_DIVIDER_MASK;
 851
 852                 /* 0x1F write to PP_DIV_REG sets max cycle delay */
 853                 I915_WRITE(pp_div_reg, pp_div | 0x1F);
 854                 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
 855                 msleep(intel_dp->panel_power_cycle_delay);
 856         }
 857
 858         pps_unlock(intel_dp);
 859
 860         return 0;
 861 }
 862
 863 static bool edp_have_panel_power(struct intel_dp *intel_dp)
 864 {
 865         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 866         struct drm_i915_private *dev_priv = to_i915(dev);
 867
 868         lockdep_assert_held(&dev_priv->pps_mutex);
 869
 870         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
 871             intel_dp->pps_pipe == INVALID_PIPE)
 872                 return false;
 873
 874         return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
 875 }
 876
 877 static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
 878 {
 879         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 880         struct drm_i915_private *dev_priv = to_i915(dev);
 881
 882         lockdep_assert_held(&dev_priv->pps_mutex);
 883
 884         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
 885             intel_dp->pps_pipe == INVALID_PIPE)
 886                 return false;
 887
 888         return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
 889 }
 890
 891 static void
 892 intel_dp_check_edp(struct intel_dp *intel_dp)
 893 {
 894         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 895         struct drm_i915_private *dev_priv = to_i915(dev);
 896
 897         if (!is_edp(intel_dp))
 898                 return;
 899
 900         if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
 901                 WARN(1, "eDP powered off while attempting aux channel communication.\n");
 902                 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
 903                               I915_READ(_pp_stat_reg(intel_dp)),
 904                               I915_READ(_pp_ctrl_reg(intel_dp)));
 905         }
 906 }
 907
 908 static uint32_t
 909 intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
 910 {
 911         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 912         struct drm_device *dev = intel_dig_port->base.base.dev;
 913         struct drm_i915_private *dev_priv = to_i915(dev);
 914         i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg;
 915         uint32_t status;
 916         bool done;
 917
 918 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 919         if (has_aux_irq)
 920                 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
 921                                           msecs_to_jiffies_timeout(10));
 922         else
 923                 done = wait_for(C, 10) == 0;
 924         if (!done)
 925                 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
 926                           has_aux_irq);
 927 #undef C
 928
 929         return status;
 930 }
 931
 932 static uint32_t g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 933 {
 934         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 935         struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
 936
 937         if (index)
 938                 return 0;
 939
 940         /*
 941          * The clock divider is based off the hrawclk, and would like to run at
 942          * 2MHz.  So, take the hrawclk value and divide by 2000 and use that
 943          */
 944         return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
 945 }
 946
 947 static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 948 {
 949         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 950         struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
 951
 952         if (index)
 953                 return 0;
 954
 955         /*
 956          * The clock divider is based off the cdclk or PCH rawclk, and would
 957          * like to run at 2MHz.  So, take the cdclk or PCH rawclk value and
 958          * divide by 2000 and use that
 959          */
 960         if (intel_dig_port->port == PORT_A)
 961                 return DIV_ROUND_CLOSEST(dev_priv->cdclk.hw.cdclk, 2000);
 962         else
 963                 return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000);
 964 }
 965
 966 static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 967 {
 968         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 969         struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
 970
 971         if (intel_dig_port->port != PORT_A && HAS_PCH_LPT_H(dev_priv)) {
 972                 /* Workaround for non-ULT HSW */
 973                 switch (index) {
 974                 case 0: return 63;
 975                 case 1: return 72;
 976                 default: return 0;
 977                 }
 978         }
 979
 980         return ilk_get_aux_clock_divider(intel_dp, index);
 981 }
 982
 983 static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 984 {
 985         /*
 986          * SKL doesn't need us to program the AUX clock divider (Hardware will
 987          * derive the clock from CDCLK automatically). We still implement the
 988          * get_aux_clock_divider vfunc to plug-in into the existing code.
 989          */
 990         return index ? 0 : 1;
 991 }
 992
 993 static uint32_t g4x_get_aux_send_ctl(struct intel_dp *intel_dp,
 994                                      bool has_aux_irq,
 995                                      int send_bytes,
 996                                      uint32_t aux_clock_divider)
 997 {
 998         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 999         struct drm_i915_private *dev_priv =
1000                         to_i915(intel_dig_port->base.base.dev);
1001         uint32_t precharge, timeout;
1002
1003         if (IS_GEN6(dev_priv))
1004                 precharge = 3;
1005         else
1006                 precharge = 5;
1007
1008         if (IS_BROADWELL(dev_priv) && intel_dig_port->port == PORT_A)
1009                 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
1010         else
1011                 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
1012
1013         return DP_AUX_CH_CTL_SEND_BUSY |
1014                DP_AUX_CH_CTL_DONE |
1015                (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
1016                DP_AUX_CH_CTL_TIME_OUT_ERROR |
1017                timeout |
1018                DP_AUX_CH_CTL_RECEIVE_ERROR |
1019                (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1020                (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
1021                (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
1022 }
1023
1024 static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp,
1025                                       bool has_aux_irq,
1026                                       int send_bytes,
1027                                       uint32_t unused)
1028 {
1029         return DP_AUX_CH_CTL_SEND_BUSY |
1030                DP_AUX_CH_CTL_DONE |
1031                (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
1032                DP_AUX_CH_CTL_TIME_OUT_ERROR |
1033                DP_AUX_CH_CTL_TIME_OUT_1600us |
1034                DP_AUX_CH_CTL_RECEIVE_ERROR |
1035                (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
1036                DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) |
1037                DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
1038 }
1039
1040 static int
1041 intel_dp_aux_ch(struct intel_dp *intel_dp,
1042                 const uint8_t *send, int send_bytes,
1043                 uint8_t *recv, int recv_size)
1044 {
1045         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1046         struct drm_i915_private *dev_priv =
1047                         to_i915(intel_dig_port->base.base.dev);
1048         i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg;
1049         uint32_t aux_clock_divider;
1050         int i, ret, recv_bytes;
1051         uint32_t status;
1052         int try, clock = 0;
1053         bool has_aux_irq = HAS_AUX_IRQ(dev_priv);
1054         bool vdd;
1055
1056         pps_lock(intel_dp);
1057
1058         /*
1059          * We will be called with VDD already enabled for dpcd/edid/oui reads.
1060          * In such cases we want to leave VDD enabled and it's up to upper layers
1061          * to turn it off. But for eg. i2c-dev access we need to turn it on/off
1062          * ourselves.
1063          */
1064         vdd = edp_panel_vdd_on(intel_dp);
1065
1066         /* dp aux is extremely sensitive to irq latency, hence request the
1067          * lowest possible wakeup latency and so prevent the cpu from going into
1068          * deep sleep states.
1069          */
1070         pm_qos_update_request(&dev_priv->pm_qos, 0);
1071
1072         intel_dp_check_edp(intel_dp);
1073
1074         /* Try to wait for any previous AUX channel activity */
1075         for (try = 0; try < 3; try++) {
1076                 status = I915_READ_NOTRACE(ch_ctl);
1077                 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
1078                         break;
1079                 msleep(1);
1080         }
1081
1082         if (try == 3) {
1083                 static u32 last_status = -1;
1084                 const u32 status = I915_READ(ch_ctl);
1085
1086                 if (status != last_status) {
1087                         WARN(1, "dp_aux_ch not started status 0x%08x\n",
1088                              status);
1089                         last_status = status;
1090                 }
1091
1092                 ret = -EBUSY;
1093                 goto out;
1094         }
1095
1096         /* Only 5 data registers! */
1097         if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
1098                 ret = -E2BIG;
1099                 goto out;
1100         }
1101
1102         while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
1103                 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
1104                                                           has_aux_irq,
1105                                                           send_bytes,
1106                                                           aux_clock_divider);
1107
1108                 /* Must try at least 3 times according to DP spec */
1109                 for (try = 0; try < 5; try++) {
1110                         /* Load the send data into the aux channel data registers */
1111                         for (i = 0; i < send_bytes; i += 4)
1112                                 I915_WRITE(intel_dp->aux_ch_data_reg[i >> 2],
1113                                            intel_dp_pack_aux(send + i,
1114                                                              send_bytes - i));
1115
1116                         /* Send the command and wait for it to complete */
1117                         I915_WRITE(ch_ctl, send_ctl);
1118
1119                         status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
1120
1121                         /* Clear done status and any errors */
1122                         I915_WRITE(ch_ctl,
1123                                    status |
1124                                    DP_AUX_CH_CTL_DONE |
1125                                    DP_AUX_CH_CTL_TIME_OUT_ERROR |
1126                                    DP_AUX_CH_CTL_RECEIVE_ERROR);
1127
1128                         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR)
1129                                 continue;
1130
1131                         /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
1132                          *   400us delay required for errors and timeouts
1133                          *   Timeout errors from the HW already meet this
1134                          *   requirement so skip to next iteration
1135                          */
1136                         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1137                                 usleep_range(400, 500);
1138                                 continue;
1139                         }
1140                         if (status & DP_AUX_CH_CTL_DONE)
1141                                 goto done;
1142                 }
1143         }
1144
1145         if ((status & DP_AUX_CH_CTL_DONE) == 0) {
1146                 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
1147                 ret = -EBUSY;
1148                 goto out;
1149         }
1150
1151 done:
1152         /* Check for timeout or receive error.
1153          * Timeouts occur when the sink is not connected
1154          */
1155         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
1156                 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
1157                 ret = -EIO;
1158                 goto out;
1159         }
1160
1161         /* Timeouts occur when the device isn't connected, so they're
1162          * "normal" -- don't fill the kernel log with these */
1163         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
1164                 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
1165                 ret = -ETIMEDOUT;
1166                 goto out;
1167         }
1168
1169         /* Unload any bytes sent back from the other side */
1170         recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
1171                       DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
1172
1173         /*
1174          * By BSpec: "Message sizes of 0 or >20 are not allowed."
1175          * We have no idea of what happened so we return -EBUSY so
1176          * drm layer takes care for the necessary retries.
1177          */
1178         if (recv_bytes == 0 || recv_bytes > 20) {
1179                 DRM_DEBUG_KMS("Forbidden recv_bytes = %d on aux transaction\n",
1180                               recv_bytes);
1181                 /*
1182                  * FIXME: This patch was created on top of a series that
1183                  * organize the retries at drm level. There EBUSY should
1184                  * also take care for 1ms wait before retrying.
1185                  * That aux retries re-org is still needed and after that is
1186                  * merged we remove this sleep from here.
1187                  */
1188                 usleep_range(1000, 1500);
1189                 ret = -EBUSY;
1190                 goto out;
1191         }
1192
1193         if (recv_bytes > recv_size)
1194                 recv_bytes = recv_size;
1195
1196         for (i = 0; i < recv_bytes; i += 4)
1197                 intel_dp_unpack_aux(I915_READ(intel_dp->aux_ch_data_reg[i >> 2]),
1198                                     recv + i, recv_bytes - i);
1199
1200         ret = recv_bytes;
1201 out:
1202         pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
1203
1204         if (vdd)
1205                 edp_panel_vdd_off(intel_dp, false);
1206
1207         pps_unlock(intel_dp);
1208
1209         return ret;
1210 }
1211
1212 #define BARE_ADDRESS_SIZE       3
1213 #define HEADER_SIZE             (BARE_ADDRESS_SIZE + 1)
1214 static ssize_t
1215 intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
1216 {
1217         struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
1218         uint8_t txbuf[20], rxbuf[20];
1219         size_t txsize, rxsize;
1220         int ret;
1221
1222         txbuf[0] = (msg->request << 4) |
1223                 ((msg->address >> 16) & 0xf);
1224         txbuf[1] = (msg->address >> 8) & 0xff;
1225         txbuf[2] = msg->address & 0xff;
1226         txbuf[3] = msg->size - 1;
1227
1228         switch (msg->request & ~DP_AUX_I2C_MOT) {
1229         case DP_AUX_NATIVE_WRITE:
1230         case DP_AUX_I2C_WRITE:
1231         case DP_AUX_I2C_WRITE_STATUS_UPDATE:
1232                 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
1233                 rxsize = 2; /* 0 or 1 data bytes */
1234
1235                 if (WARN_ON(txsize > 20))
1236                         return -E2BIG;
1237
1238                 WARN_ON(!msg->buffer != !msg->size);
1239
1240                 if (msg->buffer)
1241                         memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
1242
1243                 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
1244                 if (ret > 0) {
1245                         msg->reply = rxbuf[0] >> 4;
1246
1247                         if (ret > 1) {
1248                                 /* Number of bytes written in a short write. */
1249                                 ret = clamp_t(int, rxbuf[1], 0, msg->size);
1250                         } else {
1251                                 /* Return payload size. */
1252                                 ret = msg->size;
1253                         }
1254                 }
1255                 break;
1256
1257         case DP_AUX_NATIVE_READ:
1258         case DP_AUX_I2C_READ:
1259                 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
1260                 rxsize = msg->size + 1;
1261
1262                 if (WARN_ON(rxsize > 20))
1263                         return -E2BIG;
1264
1265                 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
1266                 if (ret > 0) {
1267                         msg->reply = rxbuf[0] >> 4;
1268                         /*
1269                          * Assume happy day, and copy the data. The caller is
1270                          * expected to check msg->reply before touching it.
1271                          *
1272                          * Return payload size.
1273                          */
1274                         ret--;
1275                         memcpy(msg->buffer, rxbuf + 1, ret);
1276                 }
1277                 break;
1278
1279         default:
1280                 ret = -EINVAL;
1281                 break;
1282         }
1283
1284         return ret;
1285 }
1286
1287 static enum port intel_aux_port(struct drm_i915_private *dev_priv,
1288                                 enum port port)
1289 {
1290         const struct ddi_vbt_port_info *info =
1291                 &dev_priv->vbt.ddi_port_info[port];
1292         enum port aux_port;
1293
1294         if (!info->alternate_aux_channel) {
1295                 DRM_DEBUG_KMS("using AUX %c for port %c (platform default)\n",
1296                               port_name(port), port_name(port));
1297                 return port;
1298         }
1299
1300         switch (info->alternate_aux_channel) {
1301         case DP_AUX_A:
1302                 aux_port = PORT_A;
1303                 break;
1304         case DP_AUX_B:
1305                 aux_port = PORT_B;
1306                 break;
1307         case DP_AUX_C:
1308                 aux_port = PORT_C;
1309                 break;
1310         case DP_AUX_D:
1311                 aux_port = PORT_D;
1312                 break;
1313         default:
1314                 MISSING_CASE(info->alternate_aux_channel);
1315                 aux_port = PORT_A;
1316                 break;
1317         }
1318
1319         DRM_DEBUG_KMS("using AUX %c for port %c (VBT)\n",
1320                       port_name(aux_port), port_name(port));
1321
1322         return aux_port;
1323 }
1324
1325 static i915_reg_t g4x_aux_ctl_reg(struct drm_i915_private *dev_priv,
1326                                   enum port port)
1327 {
1328         switch (port) {
1329         case PORT_B:
1330         case PORT_C:
1331         case PORT_D:
1332                 return DP_AUX_CH_CTL(port);
1333         default:
1334                 MISSING_CASE(port);
1335                 return DP_AUX_CH_CTL(PORT_B);
1336         }
1337 }
1338
1339 static i915_reg_t g4x_aux_data_reg(struct drm_i915_private *dev_priv,
1340                                    enum port port, int index)
1341 {
1342         switch (port) {
1343         case PORT_B:
1344         case PORT_C:
1345         case PORT_D:
1346                 return DP_AUX_CH_DATA(port, index);
1347         default:
1348                 MISSING_CASE(port);
1349                 return DP_AUX_CH_DATA(PORT_B, index);
1350         }
1351 }
1352
1353 static i915_reg_t ilk_aux_ctl_reg(struct drm_i915_private *dev_priv,
1354                                   enum port port)
1355 {
1356         switch (port) {
1357         case PORT_A:
1358                 return DP_AUX_CH_CTL(port);
1359         case PORT_B:
1360         case PORT_C:
1361         case PORT_D:
1362                 return PCH_DP_AUX_CH_CTL(port);
1363         default:
1364                 MISSING_CASE(port);
1365                 return DP_AUX_CH_CTL(PORT_A);
1366         }
1367 }
1368
1369 static i915_reg_t ilk_aux_data_reg(struct drm_i915_private *dev_priv,
1370                                    enum port port, int index)
1371 {
1372         switch (port) {
1373         case PORT_A:
1374                 return DP_AUX_CH_DATA(port, index);
1375         case PORT_B:
1376         case PORT_C:
1377         case PORT_D:
1378                 return PCH_DP_AUX_CH_DATA(port, index);
1379         default:
1380                 MISSING_CASE(port);
1381                 return DP_AUX_CH_DATA(PORT_A, index);
1382         }
1383 }
1384
1385 static i915_reg_t skl_aux_ctl_reg(struct drm_i915_private *dev_priv,
1386                                   enum port port)
1387 {
1388         switch (port) {
1389         case PORT_A:
1390         case PORT_B:
1391         case PORT_C:
1392         case PORT_D:
1393                 return DP_AUX_CH_CTL(port);
1394         default:
1395                 MISSING_CASE(port);
1396                 return DP_AUX_CH_CTL(PORT_A);
1397         }
1398 }
1399
1400 static i915_reg_t skl_aux_data_reg(struct drm_i915_private *dev_priv,
1401                                    enum port port, int index)
1402 {
1403         switch (port) {
1404         case PORT_A:
1405         case PORT_B:
1406         case PORT_C:
1407         case PORT_D:
1408                 return DP_AUX_CH_DATA(port, index);
1409         default:
1410                 MISSING_CASE(port);
1411                 return DP_AUX_CH_DATA(PORT_A, index);
1412         }
1413 }
1414
1415 static i915_reg_t intel_aux_ctl_reg(struct drm_i915_private *dev_priv,
1416                                     enum port port)
1417 {
1418         if (INTEL_INFO(dev_priv)->gen >= 9)
1419                 return skl_aux_ctl_reg(dev_priv, port);
1420         else if (HAS_PCH_SPLIT(dev_priv))
1421                 return ilk_aux_ctl_reg(dev_priv, port);
1422         else
1423                 return g4x_aux_ctl_reg(dev_priv, port);
1424 }
1425
1426 static i915_reg_t intel_aux_data_reg(struct drm_i915_private *dev_priv,
1427                                      enum port port, int index)
1428 {
1429         if (INTEL_INFO(dev_priv)->gen >= 9)
1430                 return skl_aux_data_reg(dev_priv, port, index);
1431         else if (HAS_PCH_SPLIT(dev_priv))
1432                 return ilk_aux_data_reg(dev_priv, port, index);
1433         else
1434                 return g4x_aux_data_reg(dev_priv, port, index);
1435 }
1436
1437 static void intel_aux_reg_init(struct intel_dp *intel_dp)
1438 {
1439         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
1440         enum port port = intel_aux_port(dev_priv,
1441                                         dp_to_dig_port(intel_dp)->port);
1442         int i;
1443
1444         intel_dp->aux_ch_ctl_reg = intel_aux_ctl_reg(dev_priv, port);
1445         for (i = 0; i < ARRAY_SIZE(intel_dp->aux_ch_data_reg); i++)
1446                 intel_dp->aux_ch_data_reg[i] = intel_aux_data_reg(dev_priv, port, i);
1447 }
1448
1449 static void
1450 intel_dp_aux_fini(struct intel_dp *intel_dp)
1451 {
1452         kfree(intel_dp->aux.name);
1453 }
1454
1455 static void
1456 intel_dp_aux_init(struct intel_dp *intel_dp)
1457 {
1458         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1459         enum port port = intel_dig_port->port;
1460
1461         intel_aux_reg_init(intel_dp);
1462         drm_dp_aux_init(&intel_dp->aux);
1463
1464         /* Failure to allocate our preferred name is not critical */
1465         intel_dp->aux.name = kasprintf(GFP_KERNEL, "DPDDC-%c", port_name(port));
1466         intel_dp->aux.transfer = intel_dp_aux_transfer;
1467 }
1468
1469 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp)
1470 {
1471         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1472         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
1473
1474         if ((IS_HASWELL(dev_priv) && !IS_HSW_ULX(dev_priv)) ||
1475             IS_BROADWELL(dev_priv) || (INTEL_GEN(dev_priv) >= 9))
1476                 return true;
1477         else
1478                 return false;
1479 }
1480
1481 static void
1482 intel_dp_set_clock(struct intel_encoder *encoder,
1483                    struct intel_crtc_state *pipe_config)
1484 {
1485         struct drm_device *dev = encoder->base.dev;
1486         struct drm_i915_private *dev_priv = to_i915(dev);
1487         const struct dp_link_dpll *divisor = NULL;
1488         int i, count = 0;
1489
1490         if (IS_G4X(dev_priv)) {
1491                 divisor = gen4_dpll;
1492                 count = ARRAY_SIZE(gen4_dpll);
1493         } else if (HAS_PCH_SPLIT(dev_priv)) {
1494                 divisor = pch_dpll;
1495                 count = ARRAY_SIZE(pch_dpll);
1496         } else if (IS_CHERRYVIEW(dev_priv)) {
1497                 divisor = chv_dpll;
1498                 count = ARRAY_SIZE(chv_dpll);
1499         } else if (IS_VALLEYVIEW(dev_priv)) {
1500                 divisor = vlv_dpll;
1501                 count = ARRAY_SIZE(vlv_dpll);
1502         }
1503
1504         if (divisor && count) {
1505                 for (i = 0; i < count; i++) {
1506                         if (pipe_config->port_clock == divisor[i].clock) {
1507                                 pipe_config->dpll = divisor[i].dpll;
1508                                 pipe_config->clock_set = true;
1509                                 break;
1510                         }
1511                 }
1512         }
1513 }
1514
1515 static void snprintf_int_array(char *str, size_t len,
1516                                const int *array, int nelem)
1517 {
1518         int i;
1519
1520         str[0] = '\0';
1521
1522         for (i = 0; i < nelem; i++) {
1523                 int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]);
1524                 if (r >= len)
1525                         return;
1526                 str += r;
1527                 len -= r;
1528         }
1529 }
1530
1531 static void intel_dp_print_rates(struct intel_dp *intel_dp)
1532 {
1533         char str[128]; /* FIXME: too big for stack? */
1534
1535         if ((drm_debug & DRM_UT_KMS) == 0)
1536                 return;
1537
1538         snprintf_int_array(str, sizeof(str),
1539                            intel_dp->source_rates, intel_dp->num_source_rates);
1540         DRM_DEBUG_KMS("source rates: %s\n", str);
1541
1542         snprintf_int_array(str, sizeof(str),
1543                            intel_dp->sink_rates, intel_dp->num_sink_rates);
1544         DRM_DEBUG_KMS("sink rates: %s\n", str);
1545
1546         snprintf_int_array(str, sizeof(str),
1547                            intel_dp->common_rates, intel_dp->num_common_rates);
1548         DRM_DEBUG_KMS("common rates: %s\n", str);
1549 }
1550
1551 static int rate_to_index(int find, const int *rates)
1552 {
1553         int i = 0;
1554
1555         for (i = 0; i < DP_MAX_SUPPORTED_RATES; ++i)
1556                 if (find == rates[i])
1557                         break;
1558
1559         return i;
1560 }
1561
1562 int
1563 intel_dp_max_link_rate(struct intel_dp *intel_dp)
1564 {
1565         int len;
1566
1567         len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->max_link_rate);
1568         if (WARN_ON(len <= 0))
1569                 return 162000;
1570
1571         return intel_dp->common_rates[len - 1];
1572 }
1573
1574 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
1575 {
1576         int i = intel_dp_rate_index(intel_dp->sink_rates,
1577                                     intel_dp->num_sink_rates, rate);
1578
1579         if (WARN_ON(i < 0))
1580                 i = 0;
1581
1582         return i;
1583 }
1584
1585 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1586                            uint8_t *link_bw, uint8_t *rate_select)
1587 {
1588         /* eDP 1.4 rate select method. */
1589         if (intel_dp->use_rate_select) {
1590                 *link_bw = 0;
1591                 *rate_select =
1592                         intel_dp_rate_select(intel_dp, port_clock);
1593         } else {
1594                 *link_bw = drm_dp_link_rate_to_bw_code(port_clock);
1595                 *rate_select = 0;
1596         }
1597 }
1598
1599 static int intel_dp_compute_bpp(struct intel_dp *intel_dp,
1600                                 struct intel_crtc_state *pipe_config)
1601 {
1602         int bpp, bpc;
1603
1604         bpp = pipe_config->pipe_bpp;
1605         bpc = drm_dp_downstream_max_bpc(intel_dp->dpcd, intel_dp->downstream_ports);
1606
1607         if (bpc > 0)
1608                 bpp = min(bpp, 3*bpc);
1609
1610         /* For DP Compliance we override the computed bpp for the pipe */
1611         if (intel_dp->compliance.test_data.bpc != 0) {
1612                 pipe_config->pipe_bpp = 3*intel_dp->compliance.test_data.bpc;
1613                 pipe_config->dither_force_disable = pipe_config->pipe_bpp == 6*3;
1614                 DRM_DEBUG_KMS("Setting pipe_bpp to %d\n",
1615                               pipe_config->pipe_bpp);
1616         }
1617         return bpp;
1618 }
1619
1620 bool
1621 intel_dp_compute_config(struct intel_encoder *encoder,
1622                         struct intel_crtc_state *pipe_config,
1623                         struct drm_connector_state *conn_state)
1624 {
1625         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1626         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1627         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1628         enum port port = dp_to_dig_port(intel_dp)->port;
1629         struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
1630         struct intel_connector *intel_connector = intel_dp->attached_connector;
1631         int lane_count, clock;
1632         int min_lane_count = 1;
1633         int max_lane_count = intel_dp_max_lane_count(intel_dp);
1634         /* Conveniently, the link BW constants become indices with a shift...*/
1635         int min_clock = 0;
1636         int max_clock;
1637         int bpp, mode_rate;
1638         int link_avail, link_clock;
1639         int common_len;
1640         uint8_t link_bw, rate_select;
1641         bool reduce_m_n = drm_dp_has_quirk(&intel_dp->desc,
1642                                            DP_DPCD_QUIRK_LIMITED_M_N);
1643
1644         common_len = intel_dp_common_len_rate_limit(intel_dp,
1645                                                     intel_dp->max_link_rate);
1646
1647         /* No common link rates between source and sink */
1648         WARN_ON(common_len <= 0);
1649
1650         max_clock = common_len - 1;
1651
1652         if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && port != PORT_A)
1653                 pipe_config->has_pch_encoder = true;
1654
1655         pipe_config->has_drrs = false;
1656         pipe_config->has_audio = intel_dp->has_audio && port != PORT_A;
1657
1658         if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
1659                 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
1660                                        adjusted_mode);
1661
1662                 if (INTEL_GEN(dev_priv) >= 9) {
1663                         int ret;
1664                         ret = skl_update_scaler_crtc(pipe_config);
1665                         if (ret)
1666                                 return ret;
1667                 }
1668
1669                 if (HAS_GMCH_DISPLAY(dev_priv))
1670                         intel_gmch_panel_fitting(intel_crtc, pipe_config,
1671                                                  intel_connector->panel.fitting_mode);
1672                 else
1673                         intel_pch_panel_fitting(intel_crtc, pipe_config,
1674                                                 intel_connector->panel.fitting_mode);
1675         }
1676
1677         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
1678                 return false;
1679
1680         /* Use values requested by Compliance Test Request */
1681         if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
1682                 int index;
1683
1684                 index = intel_dp_rate_index(intel_dp->common_rates,
1685                                             intel_dp->num_common_rates,
1686                                             intel_dp->compliance.test_link_rate);
1687                 if (index >= 0)
1688                         min_clock = max_clock = index;
1689                 min_lane_count = max_lane_count = intel_dp->compliance.test_lane_count;
1690         }
1691         DRM_DEBUG_KMS("DP link computation with max lane count %i "
1692                       "max bw %d pixel clock %iKHz\n",
1693                       max_lane_count, intel_dp->common_rates[max_clock],
1694                       adjusted_mode->crtc_clock);
1695
1696         /* Walk through all bpp values. Luckily they're all nicely spaced with 2
1697          * bpc in between. */
1698         bpp = intel_dp_compute_bpp(intel_dp, pipe_config);
1699         if (is_edp(intel_dp)) {
1700
1701                 /* Get bpp from vbt only for panels that dont have bpp in edid */
1702                 if (intel_connector->base.display_info.bpc == 0 &&
1703                         (dev_priv->vbt.edp.bpp && dev_priv->vbt.edp.bpp < bpp)) {
1704                         DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1705                                       dev_priv->vbt.edp.bpp);
1706                         bpp = dev_priv->vbt.edp.bpp;
1707                 }
1708
1709                 /*
1710                  * Use the maximum clock and number of lanes the eDP panel
1711                  * advertizes being capable of. The panels are generally
1712                  * designed to support only a single clock and lane
1713                  * configuration, and typically these values correspond to the
1714                  * native resolution of the panel.
1715                  */
1716                 min_lane_count = max_lane_count;
1717                 min_clock = max_clock;
1718         }
1719
1720         for (; bpp >= 6*3; bpp -= 2*3) {
1721                 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1722                                                    bpp);
1723
1724                 for (clock = min_clock; clock <= max_clock; clock++) {
1725                         for (lane_count = min_lane_count;
1726                                 lane_count <= max_lane_count;
1727                                 lane_count <<= 1) {
1728
1729                                 link_clock = intel_dp->common_rates[clock];
1730                                 link_avail = intel_dp_max_data_rate(link_clock,
1731                                                                     lane_count);
1732
1733                                 if (mode_rate <= link_avail) {
1734                                         goto found;
1735                                 }
1736                         }
1737                 }
1738         }
1739
1740         return false;
1741
1742 found:
1743         if (intel_dp->color_range_auto) {
1744                 /*
1745                  * See:
1746                  * CEA-861-E - 5.1 Default Encoding Parameters
1747                  * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1748                  */
1749                 pipe_config->limited_color_range =
1750                         bpp != 18 &&
1751                         drm_default_rgb_quant_range(adjusted_mode) ==
1752                         HDMI_QUANTIZATION_RANGE_LIMITED;
1753         } else {
1754                 pipe_config->limited_color_range =
1755                         intel_dp->limited_color_range;
1756         }
1757
1758         pipe_config->lane_count = lane_count;
1759
1760         pipe_config->pipe_bpp = bpp;
1761         pipe_config->port_clock = intel_dp->common_rates[clock];
1762
1763         intel_dp_compute_rate(intel_dp, pipe_config->port_clock,
1764                               &link_bw, &rate_select);
1765
1766         DRM_DEBUG_KMS("DP link bw %02x rate select %02x lane count %d clock %d bpp %d\n",
1767                       link_bw, rate_select, pipe_config->lane_count,
1768                       pipe_config->port_clock, bpp);
1769         DRM_DEBUG_KMS("DP link bw required %i available %i\n",
1770                       mode_rate, link_avail);
1771
1772         intel_link_compute_m_n(bpp, lane_count,
1773                                adjusted_mode->crtc_clock,
1774                                pipe_config->port_clock,
1775                                &pipe_config->dp_m_n,
1776                                reduce_m_n);
1777
1778         if (intel_connector->panel.downclock_mode != NULL &&
1779                 dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) {
1780                         pipe_config->has_drrs = true;
1781                         intel_link_compute_m_n(bpp, lane_count,
1782                                 intel_connector->panel.downclock_mode->clock,
1783                                 pipe_config->port_clock,
1784                                 &pipe_config->dp_m2_n2,
1785                                 reduce_m_n);
1786         }
1787
1788         /*
1789          * DPLL0 VCO may need to be adjusted to get the correct
1790          * clock for eDP. This will affect cdclk as well.
1791          */
1792         if (is_edp(intel_dp) && IS_GEN9_BC(dev_priv)) {
1793                 int vco;
1794
1795                 switch (pipe_config->port_clock / 2) {
1796                 case 108000:
1797                 case 216000:
1798                         vco = 8640000;
1799                         break;
1800                 default:
1801                         vco = 8100000;
1802                         break;
1803                 }
1804
1805                 to_intel_atomic_state(pipe_config->base.state)->cdclk.logical.vco = vco;
1806         }
1807
1808         if (!HAS_DDI(dev_priv))
1809                 intel_dp_set_clock(encoder, pipe_config);
1810
1811         return true;
1812 }
1813
1814 void intel_dp_set_link_params(struct intel_dp *intel_dp,
1815                               int link_rate, uint8_t lane_count,
1816                               bool link_mst)
1817 {
1818         intel_dp->link_rate = link_rate;
1819         intel_dp->lane_count = lane_count;
1820         intel_dp->link_mst = link_mst;
1821 }
1822
1823 static void intel_dp_prepare(struct intel_encoder *encoder,
1824                              struct intel_crtc_state *pipe_config)
1825 {
1826         struct drm_device *dev = encoder->base.dev;
1827         struct drm_i915_private *dev_priv = to_i915(dev);
1828         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1829         enum port port = dp_to_dig_port(intel_dp)->port;
1830         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1831         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1832
1833         intel_dp_set_link_params(intel_dp, pipe_config->port_clock,
1834                                  pipe_config->lane_count,
1835                                  intel_crtc_has_type(pipe_config,
1836                                                      INTEL_OUTPUT_DP_MST));
1837
1838         /*
1839          * There are four kinds of DP registers:
1840          *
1841          *      IBX PCH
1842          *      SNB CPU
1843          *      IVB CPU
1844          *      CPT PCH
1845          *
1846          * IBX PCH and CPU are the same for almost everything,
1847          * except that the CPU DP PLL is configured in this
1848          * register
1849          *
1850          * CPT PCH is quite different, having many bits moved
1851          * to the TRANS_DP_CTL register instead. That
1852          * configuration happens (oddly) in ironlake_pch_enable
1853          */
1854
1855         /* Preserve the BIOS-computed detected bit. This is
1856          * supposed to be read-only.
1857          */
1858         intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
1859
1860         /* Handle DP bits in common between all three register formats */
1861         intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
1862         intel_dp->DP |= DP_PORT_WIDTH(pipe_config->lane_count);
1863
1864         /* Split out the IBX/CPU vs CPT settings */
1865
1866         if (IS_GEN7(dev_priv) && port == PORT_A) {
1867                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1868                         intel_dp->DP |= DP_SYNC_HS_HIGH;
1869                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1870                         intel_dp->DP |= DP_SYNC_VS_HIGH;
1871                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1872
1873                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1874                         intel_dp->DP |= DP_ENHANCED_FRAMING;
1875
1876                 intel_dp->DP |= crtc->pipe << 29;
1877         } else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
1878                 u32 trans_dp;
1879
1880                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1881
1882                 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1883                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1884                         trans_dp |= TRANS_DP_ENH_FRAMING;
1885                 else
1886                         trans_dp &= ~TRANS_DP_ENH_FRAMING;
1887                 I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp);
1888         } else {
1889                 if (IS_G4X(dev_priv) && pipe_config->limited_color_range)
1890                         intel_dp->DP |= DP_COLOR_RANGE_16_235;
1891
1892                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1893                         intel_dp->DP |= DP_SYNC_HS_HIGH;
1894                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1895                         intel_dp->DP |= DP_SYNC_VS_HIGH;
1896                 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1897
1898                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1899                         intel_dp->DP |= DP_ENHANCED_FRAMING;
1900
1901                 if (IS_CHERRYVIEW(dev_priv))
1902                         intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
1903                 else if (crtc->pipe == PIPE_B)
1904                         intel_dp->DP |= DP_PIPEB_SELECT;
1905         }
1906 }
1907
1908 #define IDLE_ON_MASK            (PP_ON | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
1909 #define IDLE_ON_VALUE           (PP_ON | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_ON_IDLE)
1910
1911 #define IDLE_OFF_MASK           (PP_ON | PP_SEQUENCE_MASK | 0                     | 0)
1912 #define IDLE_OFF_VALUE          (0     | PP_SEQUENCE_NONE | 0                     | 0)
1913
1914 #define IDLE_CYCLE_MASK         (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1915 #define IDLE_CYCLE_VALUE        (0     | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
1916
1917 static void intel_pps_verify_state(struct drm_i915_private *dev_priv,
1918                                    struct intel_dp *intel_dp);
1919
1920 static void wait_panel_status(struct intel_dp *intel_dp,
1921                                        u32 mask,
1922                                        u32 value)
1923 {
1924         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1925         struct drm_i915_private *dev_priv = to_i915(dev);
1926         i915_reg_t pp_stat_reg, pp_ctrl_reg;
1927
1928         lockdep_assert_held(&dev_priv->pps_mutex);
1929
1930         intel_pps_verify_state(dev_priv, intel_dp);
1931
1932         pp_stat_reg = _pp_stat_reg(intel_dp);
1933         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1934
1935         DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1936                         mask, value,
1937                         I915_READ(pp_stat_reg),
1938                         I915_READ(pp_ctrl_reg));
1939
1940         if (intel_wait_for_register(dev_priv,
1941                                     pp_stat_reg, mask, value,
1942                                     5000))
1943                 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1944                                 I915_READ(pp_stat_reg),
1945                                 I915_READ(pp_ctrl_reg));
1946
1947         DRM_DEBUG_KMS("Wait complete\n");
1948 }
1949
1950 static void wait_panel_on(struct intel_dp *intel_dp)
1951 {
1952         DRM_DEBUG_KMS("Wait for panel power on\n");
1953         wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
1954 }
1955
1956 static void wait_panel_off(struct intel_dp *intel_dp)
1957 {
1958         DRM_DEBUG_KMS("Wait for panel power off time\n");
1959         wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
1960 }
1961
1962 static void wait_panel_power_cycle(struct intel_dp *intel_dp)
1963 {
1964         ktime_t panel_power_on_time;
1965         s64 panel_power_off_duration;
1966
1967         DRM_DEBUG_KMS("Wait for panel power cycle\n");
1968
1969         /* take the difference of currrent time and panel power off time
1970          * and then make panel wait for t11_t12 if needed. */
1971         panel_power_on_time = ktime_get_boottime();
1972         panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->panel_power_off_time);
1973
1974         /* When we disable the VDD override bit last we have to do the manual
1975          * wait. */
1976         if (panel_power_off_duration < (s64)intel_dp->panel_power_cycle_delay)
1977                 wait_remaining_ms_from_jiffies(jiffies,
1978                                        intel_dp->panel_power_cycle_delay - panel_power_off_duration);
1979
1980         wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
1981 }
1982
1983 static void wait_backlight_on(struct intel_dp *intel_dp)
1984 {
1985         wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1986                                        intel_dp->backlight_on_delay);
1987 }
1988
1989 static void edp_wait_backlight_off(struct intel_dp *intel_dp)
1990 {
1991         wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1992                                        intel_dp->backlight_off_delay);
1993 }
1994
1995 /* Read the current pp_control value, unlocking the register if it
1996  * is locked
1997  */
1998
1999 static  u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
2000 {
2001         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2002         struct drm_i915_private *dev_priv = to_i915(dev);
2003         u32 control;
2004
2005         lockdep_assert_held(&dev_priv->pps_mutex);
2006
2007         control = I915_READ(_pp_ctrl_reg(intel_dp));
2008         if (WARN_ON(!HAS_DDI(dev_priv) &&
2009                     (control & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS)) {
2010                 control &= ~PANEL_UNLOCK_MASK;
2011                 control |= PANEL_UNLOCK_REGS;
2012         }
2013         return control;
2014 }
2015
2016 /*
2017  * Must be paired with edp_panel_vdd_off().
2018  * Must hold pps_mutex around the whole on/off sequence.
2019  * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
2020  */
2021 static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
2022 {
2023         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2024         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2025         struct drm_i915_private *dev_priv = to_i915(dev);
2026         u32 pp;
2027         i915_reg_t pp_stat_reg, pp_ctrl_reg;
2028         bool need_to_disable = !intel_dp->want_panel_vdd;
2029
2030         lockdep_assert_held(&dev_priv->pps_mutex);
2031
2032         if (!is_edp(intel_dp))
2033                 return false;
2034
2035         cancel_delayed_work(&intel_dp->panel_vdd_work);
2036         intel_dp->want_panel_vdd = true;
2037
2038         if (edp_have_panel_vdd(intel_dp))
2039                 return need_to_disable;
2040
2041         intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
2042
2043         DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
2044                       port_name(intel_dig_port->port));
2045
2046         if (!edp_have_panel_power(intel_dp))
2047                 wait_panel_power_cycle(intel_dp);
2048
2049         pp = ironlake_get_pp_control(intel_dp);
2050         pp |= EDP_FORCE_VDD;
2051
2052         pp_stat_reg = _pp_stat_reg(intel_dp);
2053         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2054
2055         I915_WRITE(pp_ctrl_reg, pp);
2056         POSTING_READ(pp_ctrl_reg);
2057         DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2058                         I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
2059         /*
2060          * If the panel wasn't on, delay before accessing aux channel
2061          */
2062         if (!edp_have_panel_power(intel_dp)) {
2063                 DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n",
2064                               port_name(intel_dig_port->port));
2065                 msleep(intel_dp->panel_power_up_delay);
2066         }
2067
2068         return need_to_disable;
2069 }
2070
2071 /*
2072  * Must be paired with intel_edp_panel_vdd_off() or
2073  * intel_edp_panel_off().
2074  * Nested calls to these functions are not allowed since
2075  * we drop the lock. Caller must use some higher level
2076  * locking to prevent nested calls from other threads.
2077  */
2078 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
2079 {
2080         bool vdd;
2081
2082         if (!is_edp(intel_dp))
2083                 return;
2084
2085         pps_lock(intel_dp);
2086         vdd = edp_panel_vdd_on(intel_dp);
2087         pps_unlock(intel_dp);
2088
2089         I915_STATE_WARN(!vdd, "eDP port %c VDD already requested on\n",
2090              port_name(dp_to_dig_port(intel_dp)->port));
2091 }
2092
2093 static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
2094 {
2095         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2096         struct drm_i915_private *dev_priv = to_i915(dev);
2097         struct intel_digital_port *intel_dig_port =
2098                 dp_to_dig_port(intel_dp);
2099         u32 pp;
2100         i915_reg_t pp_stat_reg, pp_ctrl_reg;
2101
2102         lockdep_assert_held(&dev_priv->pps_mutex);
2103
2104         WARN_ON(intel_dp->want_panel_vdd);
2105
2106         if (!edp_have_panel_vdd(intel_dp))
2107                 return;
2108
2109         DRM_DEBUG_KMS("Turning eDP port %c VDD off\n",
2110                       port_name(intel_dig_port->port));
2111
2112         pp = ironlake_get_pp_control(intel_dp);
2113         pp &= ~EDP_FORCE_VDD;
2114
2115         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2116         pp_stat_reg = _pp_stat_reg(intel_dp);
2117
2118         I915_WRITE(pp_ctrl_reg, pp);
2119         POSTING_READ(pp_ctrl_reg);
2120
2121         /* Make sure sequencer is idle before allowing subsequent activity */
2122         DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
2123         I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
2124
2125         if ((pp & PANEL_POWER_ON) == 0)
2126                 intel_dp->panel_power_off_time = ktime_get_boottime();
2127
2128         intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
2129 }
2130
2131 static void edp_panel_vdd_work(struct work_struct *__work)
2132 {
2133         struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
2134                                                  struct intel_dp, panel_vdd_work);
2135
2136         pps_lock(intel_dp);
2137         if (!intel_dp->want_panel_vdd)
2138                 edp_panel_vdd_off_sync(intel_dp);
2139         pps_unlock(intel_dp);
2140 }
2141
2142 static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
2143 {
2144         unsigned long delay;
2145
2146         /*
2147          * Queue the timer to fire a long time from now (relative to the power
2148          * down delay) to keep the panel power up across a sequence of
2149          * operations.
2150          */
2151         delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
2152         schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
2153 }
2154
2155 /*
2156  * Must be paired with edp_panel_vdd_on().
2157  * Must hold pps_mutex around the whole on/off sequence.
2158  * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
2159  */
2160 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
2161 {
2162         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
2163
2164         lockdep_assert_held(&dev_priv->pps_mutex);
2165
2166         if (!is_edp(intel_dp))
2167                 return;
2168
2169         I915_STATE_WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on",
2170              port_name(dp_to_dig_port(intel_dp)->port));
2171
2172         intel_dp->want_panel_vdd = false;
2173
2174         if (sync)
2175                 edp_panel_vdd_off_sync(intel_dp);
2176         else
2177                 edp_panel_vdd_schedule_off(intel_dp);
2178 }
2179
2180 static void edp_panel_on(struct intel_dp *intel_dp)
2181 {
2182         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2183         struct drm_i915_private *dev_priv = to_i915(dev);
2184         u32 pp;
2185         i915_reg_t pp_ctrl_reg;
2186
2187         lockdep_assert_held(&dev_priv->pps_mutex);
2188
2189         if (!is_edp(intel_dp))
2190                 return;
2191
2192         DRM_DEBUG_KMS("Turn eDP port %c panel power on\n",
2193                       port_name(dp_to_dig_port(intel_dp)->port));
2194
2195         if (WARN(edp_have_panel_power(intel_dp),
2196                  "eDP port %c panel power already on\n",
2197                  port_name(dp_to_dig_port(intel_dp)->port)))
2198                 return;
2199
2200         wait_panel_power_cycle(intel_dp);
2201
2202         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2203         pp = ironlake_get_pp_control(intel_dp);
2204         if (IS_GEN5(dev_priv)) {
2205                 /* ILK workaround: disable reset around power sequence */
2206                 pp &= ~PANEL_POWER_RESET;
2207                 I915_WRITE(pp_ctrl_reg, pp);
2208                 POSTING_READ(pp_ctrl_reg);
2209         }
2210
2211         pp |= PANEL_POWER_ON;
2212         if (!IS_GEN5(dev_priv))
2213                 pp |= PANEL_POWER_RESET;
2214
2215         I915_WRITE(pp_ctrl_reg, pp);
2216         POSTING_READ(pp_ctrl_reg);
2217
2218         wait_panel_on(intel_dp);
2219         intel_dp->last_power_on = jiffies;
2220
2221         if (IS_GEN5(dev_priv)) {
2222                 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
2223                 I915_WRITE(pp_ctrl_reg, pp);
2224                 POSTING_READ(pp_ctrl_reg);
2225         }
2226 }
2227
2228 void intel_edp_panel_on(struct intel_dp *intel_dp)
2229 {
2230         if (!is_edp(intel_dp))
2231                 return;
2232
2233         pps_lock(intel_dp);
2234         edp_panel_on(intel_dp);
2235         pps_unlock(intel_dp);
2236 }
2237
2238
2239 static void edp_panel_off(struct intel_dp *intel_dp)
2240 {
2241         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2242         struct drm_i915_private *dev_priv = to_i915(dev);
2243         u32 pp;
2244         i915_reg_t pp_ctrl_reg;
2245
2246         lockdep_assert_held(&dev_priv->pps_mutex);
2247
2248         if (!is_edp(intel_dp))
2249                 return;
2250
2251         DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",
2252                       port_name(dp_to_dig_port(intel_dp)->port));
2253
2254         WARN(!intel_dp->want_panel_vdd, "Need eDP port %c VDD to turn off panel\n",
2255              port_name(dp_to_dig_port(intel_dp)->port));
2256
2257         pp = ironlake_get_pp_control(intel_dp);
2258         /* We need to switch off panel power _and_ force vdd, for otherwise some
2259          * panels get very unhappy and cease to work. */
2260         pp &= ~(PANEL_POWER_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
2261                 EDP_BLC_ENABLE);
2262
2263         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2264
2265         intel_dp->want_panel_vdd = false;
2266
2267         I915_WRITE(pp_ctrl_reg, pp);
2268         POSTING_READ(pp_ctrl_reg);
2269
2270         intel_dp->panel_power_off_time = ktime_get_boottime();
2271         wait_panel_off(intel_dp);
2272
2273         /* We got a reference when we enabled the VDD. */
2274         intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
2275 }
2276
2277 void intel_edp_panel_off(struct intel_dp *intel_dp)
2278 {
2279         if (!is_edp(intel_dp))
2280                 return;
2281
2282         pps_lock(intel_dp);
2283         edp_panel_off(intel_dp);
2284         pps_unlock(intel_dp);
2285 }
2286
2287 /* Enable backlight in the panel power control. */
2288 static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
2289 {
2290         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2291         struct drm_device *dev = intel_dig_port->base.base.dev;
2292         struct drm_i915_private *dev_priv = to_i915(dev);
2293         u32 pp;
2294         i915_reg_t pp_ctrl_reg;
2295
2296         /*
2297          * If we enable the backlight right away following a panel power
2298          * on, we may see slight flicker as the panel syncs with the eDP
2299          * link.  So delay a bit to make sure the image is solid before
2300          * allowing it to appear.
2301          */
2302         wait_backlight_on(intel_dp);
2303
2304         pps_lock(intel_dp);
2305
2306         pp = ironlake_get_pp_control(intel_dp);
2307         pp |= EDP_BLC_ENABLE;
2308
2309         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2310
2311         I915_WRITE(pp_ctrl_reg, pp);
2312         POSTING_READ(pp_ctrl_reg);
2313
2314         pps_unlock(intel_dp);
2315 }
2316
2317 /* Enable backlight PWM and backlight PP control. */
2318 void intel_edp_backlight_on(struct intel_dp *intel_dp)
2319 {
2320         if (!is_edp(intel_dp))
2321                 return;
2322
2323         DRM_DEBUG_KMS("\n");
2324
2325         intel_panel_enable_backlight(intel_dp->attached_connector);
2326         _intel_edp_backlight_on(intel_dp);
2327 }
2328
2329 /* Disable backlight in the panel power control. */
2330 static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
2331 {
2332         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2333         struct drm_i915_private *dev_priv = to_i915(dev);
2334         u32 pp;
2335         i915_reg_t pp_ctrl_reg;
2336
2337         if (!is_edp(intel_dp))
2338                 return;
2339
2340         pps_lock(intel_dp);
2341
2342         pp = ironlake_get_pp_control(intel_dp);
2343         pp &= ~EDP_BLC_ENABLE;
2344
2345         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2346
2347         I915_WRITE(pp_ctrl_reg, pp);
2348         POSTING_READ(pp_ctrl_reg);
2349
2350         pps_unlock(intel_dp);
2351
2352         intel_dp->last_backlight_off = jiffies;
2353         edp_wait_backlight_off(intel_dp);
2354 }
2355
2356 /* Disable backlight PP control and backlight PWM. */
2357 void intel_edp_backlight_off(struct intel_dp *intel_dp)
2358 {
2359         if (!is_edp(intel_dp))
2360                 return;
2361
2362         DRM_DEBUG_KMS("\n");
2363
2364         _intel_edp_backlight_off(intel_dp);
2365         intel_panel_disable_backlight(intel_dp->attached_connector);
2366 }
2367
2368 /*
2369  * Hook for controlling the panel power control backlight through the bl_power
2370  * sysfs attribute. Take care to handle multiple calls.
2371  */
2372 static void intel_edp_backlight_power(struct intel_connector *connector,
2373                                       bool enable)
2374 {
2375         struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
2376         bool is_enabled;
2377
2378         pps_lock(intel_dp);
2379         is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
2380         pps_unlock(intel_dp);
2381
2382         if (is_enabled == enable)
2383                 return;
2384
2385         DRM_DEBUG_KMS("panel power control backlight %s\n",
2386                       enable ? "enable" : "disable");
2387
2388         if (enable)
2389                 _intel_edp_backlight_on(intel_dp);
2390         else
2391                 _intel_edp_backlight_off(intel_dp);
2392 }
2393
2394 static void assert_dp_port(struct intel_dp *intel_dp, bool state)
2395 {
2396         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2397         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2398         bool cur_state = I915_READ(intel_dp->output_reg) & DP_PORT_EN;
2399
2400         I915_STATE_WARN(cur_state != state,
2401                         "DP port %c state assertion failure (expected %s, current %s)\n",
2402                         port_name(dig_port->port),
2403                         onoff(state), onoff(cur_state));
2404 }
2405 #define assert_dp_port_disabled(d) assert_dp_port((d), false)
2406
2407 static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state)
2408 {
2409         bool cur_state = I915_READ(DP_A) & DP_PLL_ENABLE;
2410
2411         I915_STATE_WARN(cur_state != state,
2412                         "eDP PLL state assertion failure (expected %s, current %s)\n",
2413                         onoff(state), onoff(cur_state));
2414 }
2415 #define assert_edp_pll_enabled(d) assert_edp_pll((d), true)
2416 #define assert_edp_pll_disabled(d) assert_edp_pll((d), false)
2417
2418 static void ironlake_edp_pll_on(struct intel_dp *intel_dp,
2419                                 struct intel_crtc_state *pipe_config)
2420 {
2421         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
2422         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2423
2424         assert_pipe_disabled(dev_priv, crtc->pipe);
2425         assert_dp_port_disabled(intel_dp);
2426         assert_edp_pll_disabled(dev_priv);
2427
2428         DRM_DEBUG_KMS("enabling eDP PLL for clock %d\n",
2429                       pipe_config->port_clock);
2430
2431         intel_dp->DP &= ~DP_PLL_FREQ_MASK;
2432
2433         if (pipe_config->port_clock == 162000)
2434                 intel_dp->DP |= DP_PLL_FREQ_162MHZ;
2435         else
2436                 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
2437
2438         I915_WRITE(DP_A, intel_dp->DP);
2439         POSTING_READ(DP_A);
2440         udelay(500);
2441
2442         /*
2443          * [DevILK] Work around required when enabling DP PLL
2444          * while a pipe is enabled going to FDI:
2445          * 1. Wait for the start of vertical blank on the enabled pipe going to FDI
2446          * 2. Program DP PLL enable
2447          */
2448         if (IS_GEN5(dev_priv))
2449                 intel_wait_for_vblank_if_active(dev_priv, !crtc->pipe);
2450
2451         intel_dp->DP |= DP_PLL_ENABLE;
2452
2453         I915_WRITE(DP_A, intel_dp->DP);
2454         POSTING_READ(DP_A);
2455         udelay(200);
2456 }
2457
2458 static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
2459 {
2460         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2461         struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
2462         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2463
2464         assert_pipe_disabled(dev_priv, crtc->pipe);
2465         assert_dp_port_disabled(intel_dp);
2466         assert_edp_pll_enabled(dev_priv);
2467
2468         DRM_DEBUG_KMS("disabling eDP PLL\n");
2469
2470         intel_dp->DP &= ~DP_PLL_ENABLE;
2471
2472         I915_WRITE(DP_A, intel_dp->DP);
2473         POSTING_READ(DP_A);
2474         udelay(200);
2475 }
2476
2477 /* If the sink supports it, try to set the power state appropriately */
2478 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
2479 {
2480         int ret, i;
2481
2482         /* Should have a valid DPCD by this point */
2483         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
2484                 return;
2485
2486         if (mode != DRM_MODE_DPMS_ON) {
2487                 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2488                                          DP_SET_POWER_D3);
2489         } else {
2490                 struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
2491
2492                 /*
2493                  * When turning on, we need to retry for 1ms to give the sink
2494                  * time to wake up.
2495                  */
2496                 for (i = 0; i < 3; i++) {
2497                         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2498                                                  DP_SET_POWER_D0);
2499                         if (ret == 1)
2500                                 break;
2501                         msleep(1);
2502                 }
2503
2504                 if (ret == 1 && lspcon->active)
2505                         lspcon_wait_pcon_mode(lspcon);
2506         }
2507
2508         if (ret != 1)
2509                 DRM_DEBUG_KMS("failed to %s sink power state\n",
2510                               mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
2511 }
2512
2513 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
2514                                   enum pipe *pipe)
2515 {
2516         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2517         enum port port = dp_to_dig_port(intel_dp)->port;
2518         struct drm_device *dev = encoder->base.dev;
2519         struct drm_i915_private *dev_priv = to_i915(dev);
2520         u32 tmp;
2521         bool ret;
2522
2523         if (!intel_display_power_get_if_enabled(dev_priv,
2524                                                 encoder->power_domain))
2525                 return false;
2526
2527         ret = false;
2528
2529         tmp = I915_READ(intel_dp->output_reg);
2530
2531         if (!(tmp & DP_PORT_EN))
2532                 goto out;
2533
2534         if (IS_GEN7(dev_priv) && port == PORT_A) {
2535                 *pipe = PORT_TO_PIPE_CPT(tmp);
2536         } else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
2537                 enum pipe p;
2538
2539                 for_each_pipe(dev_priv, p) {
2540                         u32 trans_dp = I915_READ(TRANS_DP_CTL(p));
2541                         if (TRANS_DP_PIPE_TO_PORT(trans_dp) == port) {
2542                                 *pipe = p;
2543                                 ret = true;
2544
2545                                 goto out;
2546                         }
2547                 }
2548
2549                 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
2550                               i915_mmio_reg_offset(intel_dp->output_reg));
2551         } else if (IS_CHERRYVIEW(dev_priv)) {
2552                 *pipe = DP_PORT_TO_PIPE_CHV(tmp);
2553         } else {
2554                 *pipe = PORT_TO_PIPE(tmp);
2555         }
2556
2557         ret = true;
2558
2559 out:
2560         intel_display_power_put(dev_priv, encoder->power_domain);
2561
2562         return ret;
2563 }
2564
2565 static void intel_dp_get_config(struct intel_encoder *encoder,
2566                                 struct intel_crtc_state *pipe_config)
2567 {
2568         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2569         u32 tmp, flags = 0;
2570         struct drm_device *dev = encoder->base.dev;
2571         struct drm_i915_private *dev_priv = to_i915(dev);
2572         enum port port = dp_to_dig_port(intel_dp)->port;
2573         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2574
2575         tmp = I915_READ(intel_dp->output_reg);
2576
2577         pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A;
2578
2579         if (HAS_PCH_CPT(dev_priv) && port != PORT_A) {
2580                 u32 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
2581
2582                 if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH)
2583                         flags |= DRM_MODE_FLAG_PHSYNC;
2584                 else
2585                         flags |= DRM_MODE_FLAG_NHSYNC;
2586
2587                 if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH)
2588                         flags |= DRM_MODE_FLAG_PVSYNC;
2589                 else
2590                         flags |= DRM_MODE_FLAG_NVSYNC;
2591         } else {
2592                 if (tmp & DP_SYNC_HS_HIGH)
2593                         flags |= DRM_MODE_FLAG_PHSYNC;
2594                 else
2595                         flags |= DRM_MODE_FLAG_NHSYNC;
2596
2597                 if (tmp & DP_SYNC_VS_HIGH)
2598                         flags |= DRM_MODE_FLAG_PVSYNC;
2599                 else
2600                         flags |= DRM_MODE_FLAG_NVSYNC;
2601         }
2602
2603         pipe_config->base.adjusted_mode.flags |= flags;
2604
2605         if (IS_G4X(dev_priv) && tmp & DP_COLOR_RANGE_16_235)
2606                 pipe_config->limited_color_range = true;
2607
2608         pipe_config->lane_count =
2609                 ((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1;
2610
2611         intel_dp_get_m_n(crtc, pipe_config);
2612
2613         if (port == PORT_A) {
2614                 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ)
2615                         pipe_config->port_clock = 162000;
2616                 else
2617                         pipe_config->port_clock = 270000;
2618         }
2619
2620         pipe_config->base.adjusted_mode.crtc_clock =
2621                 intel_dotclock_calculate(pipe_config->port_clock,
2622                                          &pipe_config->dp_m_n);
2623
2624         if (is_edp(intel_dp) && dev_priv->vbt.edp.bpp &&
2625             pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) {
2626                 /*
2627                  * This is a big fat ugly hack.
2628                  *
2629                  * Some machines in UEFI boot mode provide us a VBT that has 18
2630                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2631                  * unknown we fail to light up. Yet the same BIOS boots up with
2632                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2633                  * max, not what it tells us to use.
2634                  *
2635                  * Note: This will still be broken if the eDP panel is not lit
2636                  * up by the BIOS, and thus we can't get the mode at module
2637                  * load.
2638                  */
2639                 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2640                               pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp);
2641                 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp;
2642         }
2643 }
2644
2645 static void intel_disable_dp(struct intel_encoder *encoder,
2646                              struct intel_crtc_state *old_crtc_state,
2647                              struct drm_connector_state *old_conn_state)
2648 {
2649         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2650         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2651
2652         if (old_crtc_state->has_audio)
2653                 intel_audio_codec_disable(encoder);
2654
2655         if (HAS_PSR(dev_priv) && !HAS_DDI(dev_priv))
2656                 intel_psr_disable(intel_dp);
2657
2658         /* Make sure the panel is off before trying to change the mode. But also
2659          * ensure that we have vdd while we switch off the panel. */
2660         intel_edp_panel_vdd_on(intel_dp);
2661         intel_edp_backlight_off(intel_dp);
2662         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
2663         intel_edp_panel_off(intel_dp);
2664
2665         /* disable the port before the pipe on g4x */
2666         if (INTEL_GEN(dev_priv) < 5)
2667                 intel_dp_link_down(intel_dp);
2668 }
2669
2670 static void ilk_post_disable_dp(struct intel_encoder *encoder,
2671                                 struct intel_crtc_state *old_crtc_state,
2672                                 struct drm_connector_state *old_conn_state)
2673 {
2674         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2675         enum port port = dp_to_dig_port(intel_dp)->port;
2676
2677         intel_dp_link_down(intel_dp);
2678
2679         /* Only ilk+ has port A */
2680         if (port == PORT_A)
2681                 ironlake_edp_pll_off(intel_dp);
2682 }
2683
2684 static void vlv_post_disable_dp(struct intel_encoder *encoder,
2685                                 struct intel_crtc_state *old_crtc_state,
2686                                 struct drm_connector_state *old_conn_state)
2687 {
2688         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2689
2690         intel_dp_link_down(intel_dp);
2691 }
2692
2693 static void chv_post_disable_dp(struct intel_encoder *encoder,
2694                                 struct intel_crtc_state *old_crtc_state,
2695                                 struct drm_connector_state *old_conn_state)
2696 {
2697         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2698         struct drm_device *dev = encoder->base.dev;
2699         struct drm_i915_private *dev_priv = to_i915(dev);
2700
2701         intel_dp_link_down(intel_dp);
2702
2703         mutex_lock(&dev_priv->sb_lock);
2704
2705         /* Assert data lane reset */
2706         chv_data_lane_soft_reset(encoder, true);
2707
2708         mutex_unlock(&dev_priv->sb_lock);
2709 }
2710
2711 static void
2712 _intel_dp_set_link_train(struct intel_dp *intel_dp,
2713                          uint32_t *DP,
2714                          uint8_t dp_train_pat)
2715 {
2716         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2717         struct drm_device *dev = intel_dig_port->base.base.dev;
2718         struct drm_i915_private *dev_priv = to_i915(dev);
2719         enum port port = intel_dig_port->port;
2720
2721         if (dp_train_pat & DP_TRAINING_PATTERN_MASK)
2722                 DRM_DEBUG_KMS("Using DP training pattern TPS%d\n",
2723                               dp_train_pat & DP_TRAINING_PATTERN_MASK);
2724
2725         if (HAS_DDI(dev_priv)) {
2726                 uint32_t temp = I915_READ(DP_TP_CTL(port));
2727
2728                 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2729                         temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2730                 else
2731                         temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2732
2733                 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2734                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2735                 case DP_TRAINING_PATTERN_DISABLE:
2736                         temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2737
2738                         break;
2739                 case DP_TRAINING_PATTERN_1:
2740                         temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2741                         break;
2742                 case DP_TRAINING_PATTERN_2:
2743                         temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2744                         break;
2745                 case DP_TRAINING_PATTERN_3:
2746                         temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2747                         break;
2748                 }
2749                 I915_WRITE(DP_TP_CTL(port), temp);
2750
2751         } else if ((IS_GEN7(dev_priv) && port == PORT_A) ||
2752                    (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
2753                 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
2754
2755                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2756                 case DP_TRAINING_PATTERN_DISABLE:
2757                         *DP |= DP_LINK_TRAIN_OFF_CPT;
2758                         break;
2759                 case DP_TRAINING_PATTERN_1:
2760                         *DP |= DP_LINK_TRAIN_PAT_1_CPT;
2761                         break;
2762                 case DP_TRAINING_PATTERN_2:
2763                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2764                         break;
2765                 case DP_TRAINING_PATTERN_3:
2766                         DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
2767                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2768                         break;
2769                 }
2770
2771         } else {
2772                 if (IS_CHERRYVIEW(dev_priv))
2773                         *DP &= ~DP_LINK_TRAIN_MASK_CHV;
2774                 else
2775                         *DP &= ~DP_LINK_TRAIN_MASK;
2776
2777                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2778                 case DP_TRAINING_PATTERN_DISABLE:
2779                         *DP |= DP_LINK_TRAIN_OFF;
2780                         break;
2781                 case DP_TRAINING_PATTERN_1:
2782                         *DP |= DP_LINK_TRAIN_PAT_1;
2783                         break;
2784                 case DP_TRAINING_PATTERN_2:
2785                         *DP |= DP_LINK_TRAIN_PAT_2;
2786                         break;
2787                 case DP_TRAINING_PATTERN_3:
2788                         if (IS_CHERRYVIEW(dev_priv)) {
2789                                 *DP |= DP_LINK_TRAIN_PAT_3_CHV;
2790                         } else {
2791                                 DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n");
2792                                 *DP |= DP_LINK_TRAIN_PAT_2;
2793                         }
2794                         break;
2795                 }
2796         }
2797 }
2798
2799 static void intel_dp_enable_port(struct intel_dp *intel_dp,
2800                                  struct intel_crtc_state *old_crtc_state)
2801 {
2802         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2803         struct drm_i915_private *dev_priv = to_i915(dev);
2804
2805         /* enable with pattern 1 (as per spec) */
2806
2807         intel_dp_program_link_training_pattern(intel_dp, DP_TRAINING_PATTERN_1);
2808
2809         /*
2810          * Magic for VLV/CHV. We _must_ first set up the register
2811          * without actually enabling the port, and then do another
2812          * write to enable the port. Otherwise link training will
2813          * fail when the power sequencer is freshly used for this port.
2814          */
2815         intel_dp->DP |= DP_PORT_EN;
2816         if (old_crtc_state->has_audio)
2817                 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
2818
2819         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2820         POSTING_READ(intel_dp->output_reg);
2821 }
2822
2823 static void intel_enable_dp(struct intel_encoder *encoder,
2824                             struct intel_crtc_state *pipe_config,
2825                             struct drm_connector_state *conn_state)
2826 {
2827         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2828         struct drm_device *dev = encoder->base.dev;
2829         struct drm_i915_private *dev_priv = to_i915(dev);
2830         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2831         uint32_t dp_reg = I915_READ(intel_dp->output_reg);
2832         enum pipe pipe = crtc->pipe;
2833
2834         if (WARN_ON(dp_reg & DP_PORT_EN))
2835                 return;
2836
2837         pps_lock(intel_dp);
2838
2839         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
2840                 vlv_init_panel_power_sequencer(intel_dp);
2841
2842         intel_dp_enable_port(intel_dp, pipe_config);
2843
2844         edp_panel_vdd_on(intel_dp);
2845         edp_panel_on(intel_dp);
2846         edp_panel_vdd_off(intel_dp, true);
2847
2848         pps_unlock(intel_dp);
2849
2850         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
2851                 unsigned int lane_mask = 0x0;
2852
2853                 if (IS_CHERRYVIEW(dev_priv))
2854                         lane_mask = intel_dp_unused_lane_mask(pipe_config->lane_count);
2855
2856                 vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp),
2857                                     lane_mask);
2858         }
2859
2860         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
2861         intel_dp_start_link_train(intel_dp);
2862         intel_dp_stop_link_train(intel_dp);
2863
2864         if (pipe_config->has_audio) {
2865                 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
2866                                  pipe_name(pipe));
2867                 intel_audio_codec_enable(encoder, pipe_config, conn_state);
2868         }
2869 }
2870
2871 static void g4x_enable_dp(struct intel_encoder *encoder,
2872                           struct intel_crtc_state *pipe_config,
2873                           struct drm_connector_state *conn_state)
2874 {
2875         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2876
2877         intel_enable_dp(encoder, pipe_config, conn_state);
2878         intel_edp_backlight_on(intel_dp);
2879 }
2880
2881 static void vlv_enable_dp(struct intel_encoder *encoder,
2882                           struct intel_crtc_state *pipe_config,
2883                           struct drm_connector_state *conn_state)
2884 {
2885         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2886
2887         intel_edp_backlight_on(intel_dp);
2888         intel_psr_enable(intel_dp);
2889 }
2890
2891 static void g4x_pre_enable_dp(struct intel_encoder *encoder,
2892                               struct intel_crtc_state *pipe_config,
2893                               struct drm_connector_state *conn_state)
2894 {
2895         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2896         enum port port = dp_to_dig_port(intel_dp)->port;
2897
2898         intel_dp_prepare(encoder, pipe_config);
2899
2900         /* Only ilk+ has port A */
2901         if (port == PORT_A)
2902                 ironlake_edp_pll_on(intel_dp, pipe_config);
2903 }
2904
2905 static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
2906 {
2907         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2908         struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev);
2909         enum pipe pipe = intel_dp->pps_pipe;
2910         i915_reg_t pp_on_reg = PP_ON_DELAYS(pipe);
2911
2912         WARN_ON(intel_dp->active_pipe != INVALID_PIPE);
2913
2914         if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B))
2915                 return;
2916
2917         edp_panel_vdd_off_sync(intel_dp);
2918
2919         /*
2920          * VLV seems to get confused when multiple power seqeuencers
2921          * have the same port selected (even if only one has power/vdd
2922          * enabled). The failure manifests as vlv_wait_port_ready() failing
2923          * CHV on the other hand doesn't seem to mind having the same port
2924          * selected in multiple power seqeuencers, but let's clear the
2925          * port select always when logically disconnecting a power sequencer
2926          * from a port.
2927          */
2928         DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n",
2929                       pipe_name(pipe), port_name(intel_dig_port->port));
2930         I915_WRITE(pp_on_reg, 0);
2931         POSTING_READ(pp_on_reg);
2932
2933         intel_dp->pps_pipe = INVALID_PIPE;
2934 }
2935
2936 static void vlv_steal_power_sequencer(struct drm_device *dev,
2937                                       enum pipe pipe)
2938 {
2939         struct drm_i915_private *dev_priv = to_i915(dev);
2940         struct intel_encoder *encoder;
2941
2942         lockdep_assert_held(&dev_priv->pps_mutex);
2943
2944         for_each_intel_encoder(dev, encoder) {
2945                 struct intel_dp *intel_dp;
2946                 enum port port;
2947
2948                 if (encoder->type != INTEL_OUTPUT_DP &&
2949                     encoder->type != INTEL_OUTPUT_EDP)
2950                         continue;
2951
2952                 intel_dp = enc_to_intel_dp(&encoder->base);
2953                 port = dp_to_dig_port(intel_dp)->port;
2954
2955                 WARN(intel_dp->active_pipe == pipe,
2956                      "stealing pipe %c power sequencer from active (e)DP port %c\n",
2957                      pipe_name(pipe), port_name(port));
2958
2959                 if (intel_dp->pps_pipe != pipe)
2960                         continue;
2961
2962                 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
2963                               pipe_name(pipe), port_name(port));
2964
2965                 /* make sure vdd is off before we steal it */
2966                 vlv_detach_power_sequencer(intel_dp);
2967         }
2968 }
2969
2970 static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp)
2971 {
2972         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2973         struct intel_encoder *encoder = &intel_dig_port->base;
2974         struct drm_device *dev = encoder->base.dev;
2975         struct drm_i915_private *dev_priv = to_i915(dev);
2976         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2977
2978         lockdep_assert_held(&dev_priv->pps_mutex);
2979
2980         WARN_ON(intel_dp->active_pipe != INVALID_PIPE);
2981
2982         if (intel_dp->pps_pipe != INVALID_PIPE &&
2983             intel_dp->pps_pipe != crtc->pipe) {
2984                 /*
2985                  * If another power sequencer was being used on this
2986                  * port previously make sure to turn off vdd there while
2987                  * we still have control of it.
2988                  */
2989                 vlv_detach_power_sequencer(intel_dp);
2990         }
2991
2992         /*
2993          * We may be stealing the power
2994          * sequencer from another port.
2995          */
2996         vlv_steal_power_sequencer(dev, crtc->pipe);
2997
2998         intel_dp->active_pipe = crtc->pipe;
2999
3000         if (!is_edp(intel_dp))
3001                 return;
3002
3003         /* now it's all ours */
3004         intel_dp->pps_pipe = crtc->pipe;
3005
3006         DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
3007                       pipe_name(intel_dp->pps_pipe), port_name(intel_dig_port->port));
3008
3009         /* init power sequencer on this pipe and port */
3010         intel_dp_init_panel_power_sequencer(dev, intel_dp);
3011         intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, true);
3012 }
3013
3014 static void vlv_pre_enable_dp(struct intel_encoder *encoder,
3015                               struct intel_crtc_state *pipe_config,
3016                               struct drm_connector_state *conn_state)
3017 {
3018         vlv_phy_pre_encoder_enable(encoder);
3019
3020         intel_enable_dp(encoder, pipe_config, conn_state);
3021 }
3022
3023 static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder,
3024                                   struct intel_crtc_state *pipe_config,
3025                                   struct drm_connector_state *conn_state)
3026 {
3027         intel_dp_prepare(encoder, pipe_config);
3028
3029         vlv_phy_pre_pll_enable(encoder);
3030 }
3031
3032 static void chv_pre_enable_dp(struct intel_encoder *encoder,
3033                               struct intel_crtc_state *pipe_config,
3034                               struct drm_connector_state *conn_state)
3035 {
3036         chv_phy_pre_encoder_enable(encoder);
3037
3038         intel_enable_dp(encoder, pipe_config, conn_state);
3039
3040         /* Second common lane will stay alive on its own now */
3041         chv_phy_release_cl2_override(encoder);
3042 }
3043
3044 static void chv_dp_pre_pll_enable(struct intel_encoder *encoder,
3045                                   struct intel_crtc_state *pipe_config,
3046                                   struct drm_connector_state *conn_state)
3047 {
3048         intel_dp_prepare(encoder, pipe_config);
3049
3050         chv_phy_pre_pll_enable(encoder);
3051 }
3052
3053 static void chv_dp_post_pll_disable(struct intel_encoder *encoder,
3054                                     struct intel_crtc_state *pipe_config,
3055                                     struct drm_connector_state *conn_state)
3056 {
3057         chv_phy_post_pll_disable(encoder);
3058 }
3059
3060 /*
3061  * Fetch AUX CH registers 0x202 - 0x207 which contain
3062  * link status information
3063  */
3064 bool
3065 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
3066 {
3067         return drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS, link_status,
3068                                 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
3069 }
3070
3071 static bool intel_dp_get_y_cord_status(struct intel_dp *intel_dp)
3072 {
3073         uint8_t psr_caps = 0;
3074
3075         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PSR_CAPS, &psr_caps) != 1)
3076                 return false;
3077         return psr_caps & DP_PSR2_SU_Y_COORDINATE_REQUIRED;
3078 }
3079
3080 static bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp)
3081 {
3082         uint8_t dprx = 0;
3083
3084         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_DPRX_FEATURE_ENUMERATION_LIST,
3085                               &dprx) != 1)
3086                 return false;
3087         return dprx & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED;
3088 }
3089
3090 static bool intel_dp_get_alpm_status(struct intel_dp *intel_dp)
3091 {
3092         uint8_t alpm_caps = 0;
3093
3094         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_RECEIVER_ALPM_CAP,
3095                               &alpm_caps) != 1)
3096                 return false;
3097         return alpm_caps & DP_ALPM_CAP;
3098 }
3099
3100 /* These are source-specific values. */
3101 uint8_t
3102 intel_dp_voltage_max(struct intel_dp *intel_dp)
3103 {
3104         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
3105         enum port port = dp_to_dig_port(intel_dp)->port;
3106
3107         if (IS_GEN9_LP(dev_priv))
3108                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3109         else if (INTEL_GEN(dev_priv) >= 9) {
3110                 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3111                 return intel_ddi_dp_voltage_max(encoder);
3112         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
3113                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3114         else if (IS_GEN7(dev_priv) && port == PORT_A)
3115                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
3116         else if (HAS_PCH_CPT(dev_priv) && port != PORT_A)
3117                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3118         else
3119                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
3120 }
3121
3122 uint8_t
3123 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
3124 {
3125         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
3126         enum port port = dp_to_dig_port(intel_dp)->port;
3127
3128         if (INTEL_GEN(dev_priv) >= 9) {
3129                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3130                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3131                         return DP_TRAIN_PRE_EMPH_LEVEL_3;
3132                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3133                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3134                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3135                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3136                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3137                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3138                 default:
3139                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3140                 }
3141         } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
3142                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3143                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3144                         return DP_TRAIN_PRE_EMPH_LEVEL_3;
3145                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3146                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3147                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3148                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3149                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3150                 default:
3151                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3152                 }
3153         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
3154                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3155                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3156                         return DP_TRAIN_PRE_EMPH_LEVEL_3;
3157                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3158                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3159                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3160                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3161                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3162                 default:
3163                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3164                 }
3165         } else if (IS_GEN7(dev_priv) && port == PORT_A) {
3166                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3167                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3168                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3169                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3170                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3171                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3172                 default:
3173                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3174                 }
3175         } else {
3176                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3177                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3178                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3179                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3180                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3181                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3182                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3183                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3184                 default:
3185                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3186                 }
3187         }
3188 }
3189
3190 static uint32_t vlv_signal_levels(struct intel_dp *intel_dp)
3191 {
3192         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3193         unsigned long demph_reg_value, preemph_reg_value,
3194                 uniqtranscale_reg_value;
3195         uint8_t train_set = intel_dp->train_set[0];
3196
3197         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3198         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3199                 preemph_reg_value = 0x0004000;
3200                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3201                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3202                         demph_reg_value = 0x2B405555;
3203                         uniqtranscale_reg_value = 0x552AB83A;
3204                         break;
3205                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3206                         demph_reg_value = 0x2B404040;
3207                         uniqtranscale_reg_value = 0x5548B83A;
3208                         break;
3209                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3210                         demph_reg_value = 0x2B245555;
3211                         uniqtranscale_reg_value = 0x5560B83A;
3212                         break;
3213                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3214                         demph_reg_value = 0x2B405555;
3215                         uniqtranscale_reg_value = 0x5598DA3A;
3216                         break;
3217                 default:
3218                         return 0;
3219                 }
3220                 break;
3221         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3222                 preemph_reg_value = 0x0002000;
3223                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3224                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3225                         demph_reg_value = 0x2B404040;
3226                         uniqtranscale_reg_value = 0x5552B83A;
3227                         break;
3228                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3229                         demph_reg_value = 0x2B404848;
3230                         uniqtranscale_reg_value = 0x5580B83A;
3231                         break;
3232                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3233                         demph_reg_value = 0x2B404040;
3234                         uniqtranscale_reg_value = 0x55ADDA3A;
3235                         break;
3236                 default:
3237                         return 0;
3238                 }
3239                 break;
3240         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3241                 preemph_reg_value = 0x0000000;
3242                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3243                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3244                         demph_reg_value = 0x2B305555;
3245                         uniqtranscale_reg_value = 0x5570B83A;
3246                         break;
3247                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3248                         demph_reg_value = 0x2B2B4040;
3249                         uniqtranscale_reg_value = 0x55ADDA3A;
3250                         break;
3251                 default:
3252                         return 0;
3253                 }
3254                 break;
3255         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3256                 preemph_reg_value = 0x0006000;
3257                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3258                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3259                         demph_reg_value = 0x1B405555;
3260                         uniqtranscale_reg_value = 0x55ADDA3A;
3261                         break;
3262                 default:
3263                         return 0;
3264                 }
3265                 break;
3266         default:
3267                 return 0;
3268         }
3269
3270         vlv_set_phy_signal_level(encoder, demph_reg_value, preemph_reg_value,
3271                                  uniqtranscale_reg_value, 0);
3272
3273         return 0;
3274 }
3275
3276 static uint32_t chv_signal_levels(struct intel_dp *intel_dp)
3277 {
3278         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
3279         u32 deemph_reg_value, margin_reg_value;
3280         bool uniq_trans_scale = false;
3281         uint8_t train_set = intel_dp->train_set[0];
3282
3283         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3284         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3285                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3286                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3287                         deemph_reg_value = 128;
3288                         margin_reg_value = 52;
3289                         break;
3290                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3291                         deemph_reg_value = 128;
3292                         margin_reg_value = 77;
3293                         break;
3294                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3295                         deemph_reg_value = 128;
3296                         margin_reg_value = 102;
3297                         break;
3298                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3299                         deemph_reg_value = 128;
3300                         margin_reg_value = 154;
3301                         uniq_trans_scale = true;
3302                         break;
3303                 default:
3304                         return 0;
3305                 }
3306                 break;
3307         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3308                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3309                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3310                         deemph_reg_value = 85;
3311                         margin_reg_value = 78;
3312                         break;
3313                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3314                         deemph_reg_value = 85;
3315                         margin_reg_value = 116;
3316                         break;
3317                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3318                         deemph_reg_value = 85;
3319                         margin_reg_value = 154;
3320                         break;
3321                 default:
3322                         return 0;
3323                 }
3324                 break;
3325         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3326                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3327                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3328                         deemph_reg_value = 64;
3329                         margin_reg_value = 104;
3330                         break;
3331                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3332                         deemph_reg_value = 64;
3333                         margin_reg_value = 154;
3334                         break;
3335                 default:
3336                         return 0;
3337                 }
3338                 break;
3339         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3340                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3341                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3342                         deemph_reg_value = 43;
3343                         margin_reg_value = 154;
3344                         break;
3345                 default:
3346                         return 0;
3347                 }
3348                 break;
3349         default:
3350                 return 0;
3351         }
3352
3353         chv_set_phy_signal_level(encoder, deemph_reg_value,
3354                                  margin_reg_value, uniq_trans_scale);
3355
3356         return 0;
3357 }
3358
3359 static uint32_t
3360 gen4_signal_levels(uint8_t train_set)
3361 {
3362         uint32_t        signal_levels = 0;
3363
3364         switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3365         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3366         default:
3367                 signal_levels |= DP_VOLTAGE_0_4;
3368                 break;
3369         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3370                 signal_levels |= DP_VOLTAGE_0_6;
3371                 break;
3372         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3373                 signal_levels |= DP_VOLTAGE_0_8;
3374                 break;
3375         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3376                 signal_levels |= DP_VOLTAGE_1_2;
3377                 break;
3378         }
3379         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3380         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3381         default:
3382                 signal_levels |= DP_PRE_EMPHASIS_0;
3383                 break;
3384         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3385                 signal_levels |= DP_PRE_EMPHASIS_3_5;
3386                 break;
3387         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3388                 signal_levels |= DP_PRE_EMPHASIS_6;
3389                 break;
3390         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3391                 signal_levels |= DP_PRE_EMPHASIS_9_5;
3392                 break;
3393         }
3394         return signal_levels;
3395 }
3396
3397 /* Gen6's DP voltage swing and pre-emphasis control */
3398 static uint32_t
3399 gen6_edp_signal_levels(uint8_t train_set)
3400 {
3401         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3402                                          DP_TRAIN_PRE_EMPHASIS_MASK);
3403         switch (signal_levels) {
3404         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3405         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3406                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3407         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3408                 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
3409         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3410         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3411                 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
3412         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3413         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3414                 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
3415         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3416         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3417                 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
3418         default:
3419                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3420                               "0x%x\n", signal_levels);
3421                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3422         }
3423 }
3424
3425 /* Gen7's DP voltage swing and pre-emphasis control */
3426 static uint32_t
3427 gen7_edp_signal_levels(uint8_t train_set)
3428 {
3429         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3430                                          DP_TRAIN_PRE_EMPHASIS_MASK);
3431         switch (signal_levels) {
3432         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3433                 return EDP_LINK_TRAIN_400MV_0DB_IVB;
3434         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3435                 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
3436         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3437                 return EDP_LINK_TRAIN_400MV_6DB_IVB;
3438
3439         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3440                 return EDP_LINK_TRAIN_600MV_0DB_IVB;
3441         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3442                 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
3443
3444         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3445                 return EDP_LINK_TRAIN_800MV_0DB_IVB;
3446         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3447                 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
3448
3449         default:
3450                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3451                               "0x%x\n", signal_levels);
3452                 return EDP_LINK_TRAIN_500MV_0DB_IVB;
3453         }
3454 }
3455
3456 void
3457 intel_dp_set_signal_levels(struct intel_dp *intel_dp)
3458 {
3459         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3460         enum port port = intel_dig_port->port;
3461         struct drm_device *dev = intel_dig_port->base.base.dev;
3462         struct drm_i915_private *dev_priv = to_i915(dev);
3463         uint32_t signal_levels, mask = 0;
3464         uint8_t train_set = intel_dp->train_set[0];
3465
3466         if (HAS_DDI(dev_priv)) {
3467                 signal_levels = ddi_signal_levels(intel_dp);
3468
3469                 if (IS_GEN9_LP(dev_priv))
3470                         signal_levels = 0;
3471                 else
3472                         mask = DDI_BUF_EMP_MASK;
3473         } else if (IS_CHERRYVIEW(dev_priv)) {
3474                 signal_levels = chv_signal_levels(intel_dp);
3475         } else if (IS_VALLEYVIEW(dev_priv)) {
3476                 signal_levels = vlv_signal_levels(intel_dp);
3477         } else if (IS_GEN7(dev_priv) && port == PORT_A) {
3478                 signal_levels = gen7_edp_signal_levels(train_set);
3479                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
3480         } else if (IS_GEN6(dev_priv) && port == PORT_A) {
3481                 signal_levels = gen6_edp_signal_levels(train_set);
3482                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
3483         } else {
3484                 signal_levels = gen4_signal_levels(train_set);
3485                 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
3486         }
3487
3488         if (mask)
3489                 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
3490
3491         DRM_DEBUG_KMS("Using vswing level %d\n",
3492                 train_set & DP_TRAIN_VOLTAGE_SWING_MASK);
3493         DRM_DEBUG_KMS("Using pre-emphasis level %d\n",
3494                 (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >>
3495                         DP_TRAIN_PRE_EMPHASIS_SHIFT);
3496
3497         intel_dp->DP = (intel_dp->DP & ~mask) | signal_levels;
3498
3499         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3500         POSTING_READ(intel_dp->output_reg);
3501 }
3502
3503 void
3504 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
3505                                        uint8_t dp_train_pat)
3506 {
3507         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3508         struct drm_i915_private *dev_priv =
3509                 to_i915(intel_dig_port->base.base.dev);
3510
3511         _intel_dp_set_link_train(intel_dp, &intel_dp->DP, dp_train_pat);
3512
3513         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3514         POSTING_READ(intel_dp->output_reg);
3515 }
3516
3517 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
3518 {
3519         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3520         struct drm_device *dev = intel_dig_port->base.base.dev;
3521         struct drm_i915_private *dev_priv = to_i915(dev);
3522         enum port port = intel_dig_port->port;
3523         uint32_t val;
3524
3525         if (!HAS_DDI(dev_priv))
3526                 return;
3527
3528         val = I915_READ(DP_TP_CTL(port));
3529         val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3530         val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3531         I915_WRITE(DP_TP_CTL(port), val);
3532
3533         /*
3534          * On PORT_A we can have only eDP in SST mode. There the only reason
3535          * we need to set idle transmission mode is to work around a HW issue
3536          * where we enable the pipe while not in idle link-training mode.
3537          * In this case there is requirement to wait for a minimum number of
3538          * idle patterns to be sent.
3539          */
3540         if (port == PORT_A)
3541                 return;
3542
3543         if (intel_wait_for_register(dev_priv,DP_TP_STATUS(port),
3544                                     DP_TP_STATUS_IDLE_DONE,
3545                                     DP_TP_STATUS_IDLE_DONE,
3546                                     1))
3547                 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3548 }
3549
3550 static void
3551 intel_dp_link_down(struct intel_dp *intel_dp)
3552 {
3553         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3554         struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
3555         enum port port = intel_dig_port->port;
3556         struct drm_device *dev = intel_dig_port->base.base.dev;
3557         struct drm_i915_private *dev_priv = to_i915(dev);
3558         uint32_t DP = intel_dp->DP;
3559
3560         if (WARN_ON(HAS_DDI(dev_priv)))
3561                 return;
3562
3563         if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
3564                 return;
3565
3566         DRM_DEBUG_KMS("\n");
3567
3568         if ((IS_GEN7(dev_priv) && port == PORT_A) ||
3569             (HAS_PCH_CPT(dev_priv) && port != PORT_A)) {
3570                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
3571                 DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
3572         } else {
3573                 if (IS_CHERRYVIEW(dev_priv))
3574                         DP &= ~DP_LINK_TRAIN_MASK_CHV;
3575                 else
3576                         DP &= ~DP_LINK_TRAIN_MASK;
3577                 DP |= DP_LINK_TRAIN_PAT_IDLE;
3578         }
3579         I915_WRITE(intel_dp->output_reg, DP);
3580         POSTING_READ(intel_dp->output_reg);
3581
3582         DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
3583         I915_WRITE(intel_dp->output_reg, DP);
3584         POSTING_READ(intel_dp->output_reg);
3585
3586         /*
3587          * HW workaround for IBX, we need to move the port
3588          * to transcoder A after disabling it to allow the
3589          * matching HDMI port to be enabled on transcoder A.
3590          */
3591         if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B && port != PORT_A) {
3592                 /*
3593                  * We get CPU/PCH FIFO underruns on the other pipe when
3594                  * doing the workaround. Sweep them under the rug.
3595                  */
3596                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
3597                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
3598
3599                 /* always enable with pattern 1 (as per spec) */
3600                 DP &= ~(DP_PIPEB_SELECT | DP_LINK_TRAIN_MASK);
3601                 DP |= DP_PORT_EN | DP_LINK_TRAIN_PAT_1;
3602                 I915_WRITE(intel_dp->output_reg, DP);
3603                 POSTING_READ(intel_dp->output_reg);
3604
3605                 DP &= ~DP_PORT_EN;
3606                 I915_WRITE(intel_dp->output_reg, DP);
3607                 POSTING_READ(intel_dp->output_reg);
3608
3609                 intel_wait_for_vblank_if_active(dev_priv, PIPE_A);
3610                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
3611                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
3612         }
3613
3614         msleep(intel_dp->panel_power_down_delay);
3615
3616         intel_dp->DP = DP;
3617
3618         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
3619                 pps_lock(intel_dp);
3620                 intel_dp->active_pipe = INVALID_PIPE;
3621                 pps_unlock(intel_dp);
3622         }
3623 }
3624
3625 bool
3626 intel_dp_read_dpcd(struct intel_dp *intel_dp)
3627 {
3628         if (drm_dp_dpcd_read(&intel_dp->aux, 0x000, intel_dp->dpcd,
3629                              sizeof(intel_dp->dpcd)) < 0)
3630                 return false; /* aux transfer failed */
3631
3632         DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
3633
3634         return intel_dp->dpcd[DP_DPCD_REV] != 0;
3635 }
3636
3637 static bool
3638 intel_edp_init_dpcd(struct intel_dp *intel_dp)
3639 {
3640         struct drm_i915_private *dev_priv =
3641                 to_i915(dp_to_dig_port(intel_dp)->base.base.dev);
3642
3643         /* this function is meant to be called only once */
3644         WARN_ON(intel_dp->dpcd[DP_DPCD_REV] != 0);
3645
3646         if (!intel_dp_read_dpcd(intel_dp))
3647                 return false;
3648
3649         drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
3650                          drm_dp_is_branch(intel_dp->dpcd));
3651
3652         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
3653                 dev_priv->no_aux_handshake = intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
3654                         DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
3655
3656         /* Check if the panel supports PSR */
3657         drm_dp_dpcd_read(&intel_dp->aux, DP_PSR_SUPPORT,
3658                          intel_dp->psr_dpcd,
3659                          sizeof(intel_dp->psr_dpcd));
3660         if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
3661                 dev_priv->psr.sink_support = true;
3662                 DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
3663         }
3664
3665         if (INTEL_GEN(dev_priv) >= 9 &&
3666             (intel_dp->psr_dpcd[0] & DP_PSR2_IS_SUPPORTED)) {
3667                 uint8_t frame_sync_cap;
3668
3669                 dev_priv->psr.sink_support = true;
3670                 if (drm_dp_dpcd_readb(&intel_dp->aux,
3671                                       DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP,
3672                                       &frame_sync_cap) != 1)
3673                         frame_sync_cap = 0;
3674                 dev_priv->psr.aux_frame_sync = frame_sync_cap ? true : false;
3675                 /* PSR2 needs frame sync as well */
3676                 dev_priv->psr.psr2_support = dev_priv->psr.aux_frame_sync;
3677                 DRM_DEBUG_KMS("PSR2 %s on sink",
3678                               dev_priv->psr.psr2_support ? "supported" : "not supported");
3679
3680                 if (dev_priv->psr.psr2_support) {
3681                         dev_priv->psr.y_cord_support =
3682                                 intel_dp_get_y_cord_status(intel_dp);
3683                         dev_priv->psr.colorimetry_support =
3684                                 intel_dp_get_colorimetry_status(intel_dp);
3685                         dev_priv->psr.alpm =
3686                                 intel_dp_get_alpm_status(intel_dp);
3687                 }
3688
3689         }
3690
3691         /* Read the eDP Display control capabilities registers */
3692         if ((intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] & DP_DPCD_DISPLAY_CONTROL_CAPABLE) &&
3693             drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV,
3694                              intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) ==
3695                              sizeof(intel_dp->edp_dpcd))
3696                 DRM_DEBUG_KMS("EDP DPCD : %*ph\n", (int) sizeof(intel_dp->edp_dpcd),
3697                               intel_dp->edp_dpcd);
3698
3699         /* Intermediate frequency support */
3700         if (intel_dp->edp_dpcd[0] >= 0x03) { /* eDp v1.4 or higher */
3701                 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
3702                 int i;
3703
3704                 drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES,
3705                                 sink_rates, sizeof(sink_rates));
3706
3707                 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
3708                         int val = le16_to_cpu(sink_rates[i]);
3709
3710                         if (val == 0)
3711                                 break;
3712
3713                         /* Value read multiplied by 200kHz gives the per-lane
3714                          * link rate in kHz. The source rates are, however,
3715                          * stored in terms of LS_Clk kHz. The full conversion
3716                          * back to symbols is
3717                          * (val * 200kHz)*(8/10 ch. encoding)*(1/8 bit to Byte)
3718                          */
3719                         intel_dp->sink_rates[i] = (val * 200) / 10;
3720                 }
3721                 intel_dp->num_sink_rates = i;
3722         }
3723
3724         if (intel_dp->num_sink_rates)
3725                 intel_dp->use_rate_select = true;
3726         else
3727                 intel_dp_set_sink_rates(intel_dp);
3728
3729         intel_dp_set_common_rates(intel_dp);
3730
3731         return true;
3732 }
3733
3734
3735 static bool
3736 intel_dp_get_dpcd(struct intel_dp *intel_dp)
3737 {
3738         u8 sink_count;
3739
3740         if (!intel_dp_read_dpcd(intel_dp))
3741                 return false;
3742
3743         /* Don't clobber cached eDP rates. */
3744         if (!is_edp(intel_dp)) {
3745                 intel_dp_set_sink_rates(intel_dp);
3746                 intel_dp_set_common_rates(intel_dp);
3747         }
3748
3749         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_SINK_COUNT, &sink_count) <= 0)
3750                 return false;
3751
3752         /*
3753          * Sink count can change between short pulse hpd hence
3754          * a member variable in intel_dp will track any changes
3755          * between short pulse interrupts.
3756          */
3757         intel_dp->sink_count = DP_GET_SINK_COUNT(sink_count);
3758
3759         /*
3760          * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that
3761          * a dongle is present but no display. Unless we require to know
3762          * if a dongle is present or not, we don't need to update
3763          * downstream port information. So, an early return here saves
3764          * time from performing other operations which are not required.
3765          */
3766         if (!is_edp(intel_dp) && !intel_dp->sink_count)
3767                 return false;
3768
3769         if (!drm_dp_is_branch(intel_dp->dpcd))
3770                 return true; /* native DP sink */
3771
3772         if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
3773                 return true; /* no per-port downstream info */
3774
3775         if (drm_dp_dpcd_read(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
3776                              intel_dp->downstream_ports,
3777                              DP_MAX_DOWNSTREAM_PORTS) < 0)
3778                 return false; /* downstream port status fetch failed */
3779
3780         return true;
3781 }
3782
3783 static bool
3784 intel_dp_can_mst(struct intel_dp *intel_dp)
3785 {
3786         u8 mstm_cap;
3787
3788         if (!i915.enable_dp_mst)
3789                 return false;
3790
3791         if (!intel_dp->can_mst)
3792                 return false;
3793
3794         if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
3795                 return false;
3796
3797         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_MSTM_CAP, &mstm_cap) != 1)
3798                 return false;
3799
3800         return mstm_cap & DP_MST_CAP;
3801 }
3802
3803 static void
3804 intel_dp_configure_mst(struct intel_dp *intel_dp)
3805 {
3806         if (!i915.enable_dp_mst)
3807                 return;
3808
3809         if (!intel_dp->can_mst)
3810                 return;
3811
3812         intel_dp->is_mst = intel_dp_can_mst(intel_dp);
3813
3814         if (intel_dp->is_mst)
3815                 DRM_DEBUG_KMS("Sink is MST capable\n");
3816         else
3817                 DRM_DEBUG_KMS("Sink is not MST capable\n");
3818
3819         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
3820                                         intel_dp->is_mst);
3821 }
3822
3823 static int intel_dp_sink_crc_stop(struct intel_dp *intel_dp)
3824 {
3825         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3826         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
3827         struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
3828         u8 buf;
3829         int ret = 0;
3830         int count = 0;
3831         int attempts = 10;
3832
3833         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0) {
3834                 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
3835                 ret = -EIO;
3836                 goto out;
3837         }
3838
3839         if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3840                                buf & ~DP_TEST_SINK_START) < 0) {
3841                 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
3842                 ret = -EIO;
3843                 goto out;
3844         }
3845
3846         do {
3847                 intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
3848
3849                 if (drm_dp_dpcd_readb(&intel_dp->aux,
3850                                       DP_TEST_SINK_MISC, &buf) < 0) {
3851                         ret = -EIO;
3852                         goto out;
3853                 }
3854                 count = buf & DP_TEST_COUNT_MASK;
3855         } while (--attempts && count);
3856
3857         if (attempts == 0) {
3858                 DRM_DEBUG_KMS("TIMEOUT: Sink CRC counter is not zeroed after calculation is stopped\n");
3859                 ret = -ETIMEDOUT;
3860         }
3861
3862  out:
3863         hsw_enable_ips(intel_crtc);
3864         return ret;
3865 }
3866
3867 static int intel_dp_sink_crc_start(struct intel_dp *intel_dp)
3868 {
3869         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3870         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
3871         struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
3872         u8 buf;
3873         int ret;
3874
3875         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0)
3876                 return -EIO;
3877
3878         if (!(buf & DP_TEST_CRC_SUPPORTED))
3879                 return -ENOTTY;
3880
3881         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0)
3882                 return -EIO;
3883
3884         if (buf & DP_TEST_SINK_START) {
3885                 ret = intel_dp_sink_crc_stop(intel_dp);
3886                 if (ret)
3887                         return ret;
3888         }
3889
3890         hsw_disable_ips(intel_crtc);
3891
3892         if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3893                                buf | DP_TEST_SINK_START) < 0) {
3894                 hsw_enable_ips(intel_crtc);
3895                 return -EIO;
3896         }
3897
3898         intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
3899         return 0;
3900 }
3901
3902 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
3903 {
3904         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3905         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
3906         struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
3907         u8 buf;
3908         int count, ret;
3909         int attempts = 6;
3910
3911         ret = intel_dp_sink_crc_start(intel_dp);
3912         if (ret)
3913                 return ret;
3914
3915         do {
3916                 intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
3917
3918                 if (drm_dp_dpcd_readb(&intel_dp->aux,
3919                                       DP_TEST_SINK_MISC, &buf) < 0) {
3920                         ret = -EIO;
3921                         goto stop;
3922                 }
3923                 count = buf & DP_TEST_COUNT_MASK;
3924
3925         } while (--attempts && count == 0);
3926
3927         if (attempts == 0) {
3928                 DRM_ERROR("Panel is unable to calculate any CRC after 6 vblanks\n");
3929                 ret = -ETIMEDOUT;
3930                 goto stop;
3931         }
3932
3933         if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0) {
3934                 ret = -EIO;
3935                 goto stop;
3936         }
3937
3938 stop:
3939         intel_dp_sink_crc_stop(intel_dp);
3940         return ret;
3941 }
3942
3943 static bool
3944 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3945 {
3946         return drm_dp_dpcd_readb(&intel_dp->aux, DP_DEVICE_SERVICE_IRQ_VECTOR,
3947                                  sink_irq_vector) == 1;
3948 }
3949
3950 static bool
3951 intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
3952 {
3953         int ret;
3954
3955         ret = drm_dp_dpcd_read(&intel_dp->aux,
3956                                              DP_SINK_COUNT_ESI,
3957                                              sink_irq_vector, 14);
3958         if (ret != 14)
3959                 return false;
3960
3961         return true;
3962 }
3963
3964 static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp)
3965 {
3966         int status = 0;
3967         int min_lane_count = 1;
3968         int link_rate_index, test_link_rate;
3969         uint8_t test_lane_count, test_link_bw;
3970         /* (DP CTS 1.2)
3971          * 4.3.1.11
3972          */
3973         /* Read the TEST_LANE_COUNT and TEST_LINK_RTAE fields (DP CTS 3.1.4) */
3974         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LANE_COUNT,
3975                                    &test_lane_count);
3976
3977         if (status <= 0) {
3978                 DRM_DEBUG_KMS("Lane count read failed\n");
3979                 return DP_TEST_NAK;
3980         }
3981         test_lane_count &= DP_MAX_LANE_COUNT_MASK;
3982         /* Validate the requested lane count */
3983         if (test_lane_count < min_lane_count ||
3984             test_lane_count > intel_dp->max_link_lane_count)
3985                 return DP_TEST_NAK;
3986
3987         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LINK_RATE,
3988                                    &test_link_bw);
3989         if (status <= 0) {
3990                 DRM_DEBUG_KMS("Link Rate read failed\n");
3991                 return DP_TEST_NAK;
3992         }
3993         /* Validate the requested link rate */
3994         test_link_rate = drm_dp_bw_code_to_link_rate(test_link_bw);
3995         link_rate_index = intel_dp_rate_index(intel_dp->common_rates,
3996                                               intel_dp->num_common_rates,
3997                                               test_link_rate);
3998         if (link_rate_index < 0)
3999                 return DP_TEST_NAK;
4000
4001         intel_dp->compliance.test_lane_count = test_lane_count;
4002         intel_dp->compliance.test_link_rate = test_link_rate;
4003
4004         return DP_TEST_ACK;
4005 }
4006
4007 static uint8_t intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
4008 {
4009         uint8_t test_pattern;
4010         uint8_t test_misc;
4011         __be16 h_width, v_height;
4012         int status = 0;
4013
4014         /* Read the TEST_PATTERN (DP CTS 3.1.5) */
4015         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_PATTERN,
4016                                    &test_pattern);
4017         if (status <= 0) {
4018                 DRM_DEBUG_KMS("Test pattern read failed\n");
4019                 return DP_TEST_NAK;
4020         }
4021         if (test_pattern != DP_COLOR_RAMP)
4022                 return DP_TEST_NAK;
4023
4024         status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_H_WIDTH_HI,
4025                                   &h_width, 2);
4026         if (status <= 0) {
4027                 DRM_DEBUG_KMS("H Width read failed\n");
4028                 return DP_TEST_NAK;
4029         }
4030
4031         status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_V_HEIGHT_HI,
4032                                   &v_height, 2);
4033         if (status <= 0) {
4034                 DRM_DEBUG_KMS("V Height read failed\n");
4035                 return DP_TEST_NAK;
4036         }
4037
4038         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_MISC0,
4039                                    &test_misc);
4040         if (status <= 0) {
4041                 DRM_DEBUG_KMS("TEST MISC read failed\n");
4042                 return DP_TEST_NAK;
4043         }
4044         if ((test_misc & DP_TEST_COLOR_FORMAT_MASK) != DP_COLOR_FORMAT_RGB)
4045                 return DP_TEST_NAK;
4046         if (test_misc & DP_TEST_DYNAMIC_RANGE_CEA)
4047                 return DP_TEST_NAK;
4048         switch (test_misc & DP_TEST_BIT_DEPTH_MASK) {
4049         case DP_TEST_BIT_DEPTH_6:
4050                 intel_dp->compliance.test_data.bpc = 6;
4051                 break;
4052         case DP_TEST_BIT_DEPTH_8:
4053                 intel_dp->compliance.test_data.bpc = 8;
4054                 break;
4055         default:
4056                 return DP_TEST_NAK;
4057         }
4058
4059         intel_dp->compliance.test_data.video_pattern = test_pattern;
4060         intel_dp->compliance.test_data.hdisplay = be16_to_cpu(h_width);
4061         intel_dp->compliance.test_data.vdisplay = be16_to_cpu(v_height);
4062         /* Set test active flag here so userspace doesn't interrupt things */
4063         intel_dp->compliance.test_active = 1;
4064
4065         return DP_TEST_ACK;
4066 }
4067
4068 static uint8_t intel_dp_autotest_edid(struct intel_dp *intel_dp)
4069 {
4070         uint8_t test_result = DP_TEST_ACK;
4071         struct intel_connector *intel_connector = intel_dp->attached_connector;
4072         struct drm_connector *connector = &intel_connector->base;
4073
4074         if (intel_connector->detect_edid == NULL ||
4075             connector->edid_corrupt ||
4076             intel_dp->aux.i2c_defer_count > 6) {
4077                 /* Check EDID read for NACKs, DEFERs and corruption
4078                  * (DP CTS 1.2 Core r1.1)
4079                  *    4.2.2.4 : Failed EDID read, I2C_NAK
4080                  *    4.2.2.5 : Failed EDID read, I2C_DEFER
4081                  *    4.2.2.6 : EDID corruption detected
4082                  * Use failsafe mode for all cases
4083                  */
4084                 if (intel_dp->aux.i2c_nack_count > 0 ||
4085                         intel_dp->aux.i2c_defer_count > 0)
4086                         DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n",
4087                                       intel_dp->aux.i2c_nack_count,
4088                                       intel_dp->aux.i2c_defer_count);
4089                 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_FAILSAFE;
4090         } else {
4091                 struct edid *block = intel_connector->detect_edid;
4092
4093                 /* We have to write the checksum
4094                  * of the last block read
4095                  */
4096                 block += intel_connector->detect_edid->extensions;
4097
4098                 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_EDID_CHECKSUM,
4099                                        block->checksum) <= 0)
4100                         DRM_DEBUG_KMS("Failed to write EDID checksum\n");
4101
4102                 test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE;
4103                 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_PREFERRED;
4104         }
4105
4106         /* Set test active flag here so userspace doesn't interrupt things */
4107         intel_dp->compliance.test_active = 1;
4108
4109         return test_result;
4110 }
4111
4112 static uint8_t intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
4113 {
4114         uint8_t test_result = DP_TEST_NAK;
4115         return test_result;
4116 }
4117
4118 static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
4119 {
4120         uint8_t response = DP_TEST_NAK;
4121         uint8_t request = 0;
4122         int status;
4123
4124         status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_REQUEST, &request);
4125         if (status <= 0) {
4126                 DRM_DEBUG_KMS("Could not read test request from sink\n");
4127                 goto update_status;
4128         }
4129
4130         switch (request) {
4131         case DP_TEST_LINK_TRAINING:
4132                 DRM_DEBUG_KMS("LINK_TRAINING test requested\n");
4133                 response = intel_dp_autotest_link_training(intel_dp);
4134                 break;
4135         case DP_TEST_LINK_VIDEO_PATTERN:
4136                 DRM_DEBUG_KMS("TEST_PATTERN test requested\n");
4137                 response = intel_dp_autotest_video_pattern(intel_dp);
4138                 break;
4139         case DP_TEST_LINK_EDID_READ:
4140                 DRM_DEBUG_KMS("EDID test requested\n");
4141                 response = intel_dp_autotest_edid(intel_dp);
4142                 break;
4143         case DP_TEST_LINK_PHY_TEST_PATTERN:
4144                 DRM_DEBUG_KMS("PHY_PATTERN test requested\n");
4145                 response = intel_dp_autotest_phy_pattern(intel_dp);
4146                 break;
4147         default:
4148                 DRM_DEBUG_KMS("Invalid test request '%02x'\n", request);
4149                 break;
4150         }
4151
4152         if (response & DP_TEST_ACK)
4153                 intel_dp->compliance.test_type = request;
4154
4155 update_status:
4156         status = drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, response);
4157         if (status <= 0)
4158                 DRM_DEBUG_KMS("Could not write test response to sink\n");
4159 }
4160
4161 static int
4162 intel_dp_check_mst_status(struct intel_dp *intel_dp)
4163 {
4164         bool bret;
4165
4166         if (intel_dp->is_mst) {
4167                 u8 esi[16] = { 0 };
4168                 int ret = 0;
4169                 int retry;
4170                 bool handled;
4171                 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4172 go_again:
4173                 if (bret == true) {
4174
4175                         /* check link status - esi[10] = 0x200c */
4176                         if (intel_dp->active_mst_links &&
4177                             !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
4178                                 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
4179                                 intel_dp_start_link_train(intel_dp);
4180                                 intel_dp_stop_link_train(intel_dp);
4181                         }
4182
4183                         DRM_DEBUG_KMS("got esi %3ph\n", esi);
4184                         ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
4185
4186                         if (handled) {
4187                                 for (retry = 0; retry < 3; retry++) {
4188                                         int wret;
4189                                         wret = drm_dp_dpcd_write(&intel_dp->aux,
4190                                                                  DP_SINK_COUNT_ESI+1,
4191                                                                  &esi[1], 3);
4192                                         if (wret == 3) {
4193                                                 break;
4194                                         }
4195                                 }
4196
4197                                 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4198                                 if (bret == true) {
4199                                         DRM_DEBUG_KMS("got esi2 %3ph\n", esi);
4200                                         goto go_again;
4201                                 }
4202                         } else
4203                                 ret = 0;
4204
4205                         return ret;
4206                 } else {
4207                         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4208                         DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
4209                         intel_dp->is_mst = false;
4210                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4211                         /* send a hotplug event */
4212                         drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
4213                 }
4214         }
4215         return -EINVAL;
4216 }
4217
4218 static void
4219 intel_dp_retrain_link(struct intel_dp *intel_dp)
4220 {
4221         struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
4222         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4223         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
4224
4225         /* Suppress underruns caused by re-training */
4226         intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
4227         if (crtc->config->has_pch_encoder)
4228                 intel_set_pch_fifo_underrun_reporting(dev_priv,
4229                                                       intel_crtc_pch_transcoder(crtc), false);
4230
4231         intel_dp_start_link_train(intel_dp);
4232         intel_dp_stop_link_train(intel_dp);
4233
4234         /* Keep underrun reporting disabled until things are stable */
4235         intel_wait_for_vblank(dev_priv, crtc->pipe);
4236
4237         intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
4238         if (crtc->config->has_pch_encoder)
4239                 intel_set_pch_fifo_underrun_reporting(dev_priv,
4240                                                       intel_crtc_pch_transcoder(crtc), true);
4241 }
4242
4243 static void
4244 intel_dp_check_link_status(struct intel_dp *intel_dp)
4245 {
4246         struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
4247         struct drm_device *dev = intel_dp_to_dev(intel_dp);
4248         u8 link_status[DP_LINK_STATUS_SIZE];
4249
4250         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
4251
4252         if (!intel_dp_get_link_status(intel_dp, link_status)) {
4253                 DRM_ERROR("Failed to get link status\n");
4254                 return;
4255         }
4256
4257         if (!intel_encoder->base.crtc)
4258                 return;
4259
4260         if (!to_intel_crtc(intel_encoder->base.crtc)->active)
4261                 return;
4262
4263         /*
4264          * Validate the cached values of intel_dp->link_rate and
4265          * intel_dp->lane_count before attempting to retrain.
4266          */
4267         if (!intel_dp_link_params_valid(intel_dp))
4268                 return;
4269
4270         /* Retrain if Channel EQ or CR not ok */
4271         if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
4272                 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
4273                               intel_encoder->base.name);
4274
4275                 intel_dp_retrain_link(intel_dp);
4276         }
4277 }
4278
4279 /*
4280  * According to DP spec
4281  * 5.1.2:
4282  *  1. Read DPCD
4283  *  2. Configure link according to Receiver Capabilities
4284  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
4285  *  4. Check link status on receipt of hot-plug interrupt
4286  *
4287  * intel_dp_short_pulse -  handles short pulse interrupts
4288  * when full detection is not required.
4289  * Returns %true if short pulse is handled and full detection
4290  * is NOT required and %false otherwise.
4291  */
4292 static bool
4293 intel_dp_short_pulse(struct intel_dp *intel_dp)
4294 {
4295         struct drm_device *dev = intel_dp_to_dev(intel_dp);
4296         struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
4297         u8 sink_irq_vector = 0;
4298         u8 old_sink_count = intel_dp->sink_count;
4299         bool ret;
4300
4301         /*
4302          * Clearing compliance test variables to allow capturing
4303          * of values for next automated test request.
4304          */
4305         memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
4306
4307         /*
4308          * Now read the DPCD to see if it's actually running
4309          * If the current value of sink count doesn't match with
4310          * the value that was stored earlier or dpcd read failed
4311          * we need to do full detection
4312          */
4313         ret = intel_dp_get_dpcd(intel_dp);
4314
4315         if ((old_sink_count != intel_dp->sink_count) || !ret) {
4316                 /* No need to proceed if we are going to do full detect */
4317                 return false;
4318         }
4319
4320         /* Try to read the source of the interrupt */
4321         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4322             intel_dp_get_sink_irq(intel_dp, &sink_irq_vector) &&
4323             sink_irq_vector != 0) {
4324                 /* Clear interrupt source */
4325                 drm_dp_dpcd_writeb(&intel_dp->aux,
4326                                    DP_DEVICE_SERVICE_IRQ_VECTOR,
4327                                    sink_irq_vector);
4328
4329                 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
4330                         intel_dp_handle_test_request(intel_dp);
4331                 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
4332                         DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4333         }
4334
4335         drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
4336         intel_dp_check_link_status(intel_dp);
4337         drm_modeset_unlock(&dev->mode_config.connection_mutex);
4338         if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) {
4339                 DRM_DEBUG_KMS("Link Training Compliance Test requested\n");
4340                 /* Send a Hotplug Uevent to userspace to start modeset */
4341                 drm_kms_helper_hotplug_event(intel_encoder->base.dev);
4342         }
4343
4344         return true;
4345 }
4346
4347 /* XXX this is probably wrong for multiple downstream ports */
4348 static enum drm_connector_status
4349 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
4350 {
4351         struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
4352         uint8_t *dpcd = intel_dp->dpcd;
4353         uint8_t type;
4354
4355         if (lspcon->active)
4356                 lspcon_resume(lspcon);
4357
4358         if (!intel_dp_get_dpcd(intel_dp))
4359                 return connector_status_disconnected;
4360
4361         if (is_edp(intel_dp))
4362                 return connector_status_connected;
4363
4364         /* if there's no downstream port, we're done */
4365         if (!drm_dp_is_branch(dpcd))
4366                 return connector_status_connected;
4367
4368         /* If we're HPD-aware, SINK_COUNT changes dynamically */
4369         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4370             intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
4371
4372                 return intel_dp->sink_count ?
4373                 connector_status_connected : connector_status_disconnected;
4374         }
4375
4376         if (intel_dp_can_mst(intel_dp))
4377                 return connector_status_connected;
4378
4379         /* If no HPD, poke DDC gently */
4380         if (drm_probe_ddc(&intel_dp->aux.ddc))
4381                 return connector_status_connected;
4382
4383         /* Well we tried, say unknown for unreliable port types */
4384         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
4385                 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
4386                 if (type == DP_DS_PORT_TYPE_VGA ||
4387                     type == DP_DS_PORT_TYPE_NON_EDID)
4388                         return connector_status_unknown;
4389         } else {
4390                 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
4391                         DP_DWN_STRM_PORT_TYPE_MASK;
4392                 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
4393                     type == DP_DWN_STRM_PORT_TYPE_OTHER)
4394                         return connector_status_unknown;
4395         }
4396
4397         /* Anything else is out of spec, warn and ignore */
4398         DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
4399         return connector_status_disconnected;
4400 }
4401
4402 static enum drm_connector_status
4403 edp_detect(struct intel_dp *intel_dp)
4404 {
4405         struct drm_device *dev = intel_dp_to_dev(intel_dp);
4406         struct drm_i915_private *dev_priv = to_i915(dev);
4407         enum drm_connector_status status;
4408
4409         status = intel_panel_detect(dev_priv);
4410         if (status == connector_status_unknown)
4411                 status = connector_status_connected;
4412
4413         return status;
4414 }
4415
4416 static bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
4417                                        struct intel_digital_port *port)
4418 {
4419         u32 bit;
4420
4421         switch (port->port) {
4422         case PORT_A:
4423                 return true;
4424         case PORT_B:
4425                 bit = SDE_PORTB_HOTPLUG;
4426                 break;
4427         case PORT_C:
4428                 bit = SDE_PORTC_HOTPLUG;
4429                 break;
4430         case PORT_D:
4431                 bit = SDE_PORTD_HOTPLUG;
4432                 break;
4433         default:
4434                 MISSING_CASE(port->port);
4435                 return false;
4436         }
4437
4438         return I915_READ(SDEISR) & bit;
4439 }
4440
4441 static bool cpt_digital_port_connected(struct drm_i915_private *dev_priv,
4442                                        struct intel_digital_port *port)
4443 {
4444         u32 bit;
4445
4446         switch (port->port) {
4447         case PORT_A:
4448                 return true;
4449         case PORT_B:
4450                 bit = SDE_PORTB_HOTPLUG_CPT;
4451                 break;
4452         case PORT_C:
4453                 bit = SDE_PORTC_HOTPLUG_CPT;
4454                 break;
4455         case PORT_D:
4456                 bit = SDE_PORTD_HOTPLUG_CPT;
4457                 break;
4458         case PORT_E:
4459                 bit = SDE_PORTE_HOTPLUG_SPT;
4460                 break;
4461         default:
4462                 MISSING_CASE(port->port);
4463                 return false;
4464         }
4465
4466         return I915_READ(SDEISR) & bit;
4467 }
4468
4469 static bool g4x_digital_port_connected(struct drm_i915_private *dev_priv,
4470                                        struct intel_digital_port *port)
4471 {
4472         u32 bit;
4473
4474         switch (port->port) {
4475         case PORT_B:
4476                 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
4477                 break;
4478         case PORT_C:
4479                 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
4480                 break;
4481         case PORT_D:
4482                 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
4483                 break;
4484         default:
4485                 MISSING_CASE(port->port);
4486                 return false;
4487         }
4488
4489         return I915_READ(PORT_HOTPLUG_STAT) & bit;
4490 }
4491
4492 static bool gm45_digital_port_connected(struct drm_i915_private *dev_priv,
4493                                         struct intel_digital_port *port)
4494 {
4495         u32 bit;
4496
4497         switch (port->port) {
4498         case PORT_B:
4499                 bit = PORTB_HOTPLUG_LIVE_STATUS_GM45;
4500                 break;
4501         case PORT_C:
4502                 bit = PORTC_HOTPLUG_LIVE_STATUS_GM45;
4503                 break;
4504         case PORT_D:
4505                 bit = PORTD_HOTPLUG_LIVE_STATUS_GM45;
4506                 break;
4507         default:
4508                 MISSING_CASE(port->port);
4509                 return false;
4510         }
4511
4512         return I915_READ(PORT_HOTPLUG_STAT) & bit;
4513 }
4514
4515 static bool bxt_digital_port_connected(struct drm_i915_private *dev_priv,
4516                                        struct intel_digital_port *intel_dig_port)
4517 {
4518         struct intel_encoder *intel_encoder = &intel_dig_port->base;
4519         enum port port;
4520         u32 bit;
4521
4522         intel_hpd_pin_to_port(intel_encoder->hpd_pin, &port);
4523         switch (port) {
4524         case PORT_A:
4525                 bit = BXT_DE_PORT_HP_DDIA;
4526                 break;
4527         case PORT_B:
4528                 bit = BXT_DE_PORT_HP_DDIB;
4529                 break;
4530         case PORT_C:
4531                 bit = BXT_DE_PORT_HP_DDIC;
4532                 break;
4533         default:
4534                 MISSING_CASE(port);
4535                 return false;
4536         }
4537
4538         return I915_READ(GEN8_DE_PORT_ISR) & bit;
4539 }
4540
4541 /*
4542  * intel_digital_port_connected - is the specified port connected?
4543  * @dev_priv: i915 private structure
4544  * @port: the port to test
4545  *
4546  * Return %true if @port is connected, %false otherwise.
4547  */
4548 bool intel_digital_port_connected(struct drm_i915_private *dev_priv,
4549                                   struct intel_digital_port *port)
4550 {
4551         if (HAS_PCH_IBX(dev_priv))
4552                 return ibx_digital_port_connected(dev_priv, port);
4553         else if (HAS_PCH_SPLIT(dev_priv))
4554                 return cpt_digital_port_connected(dev_priv, port);
4555         else if (IS_GEN9_LP(dev_priv))
4556                 return bxt_digital_port_connected(dev_priv, port);
4557         else if (IS_GM45(dev_priv))
4558                 return gm45_digital_port_connected(dev_priv, port);
4559         else
4560                 return g4x_digital_port_connected(dev_priv, port);
4561 }
4562
4563 static struct edid *
4564 intel_dp_get_edid(struct intel_dp *intel_dp)
4565 {
4566         struct intel_connector *intel_connector = intel_dp->attached_connector;
4567
4568         /* use cached edid if we have one */
4569         if (intel_connector->edid) {
4570                 /* invalid edid */
4571                 if (IS_ERR(intel_connector->edid))
4572                         return NULL;
4573
4574                 return drm_edid_duplicate(intel_connector->edid);
4575         } else
4576                 return drm_get_edid(&intel_connector->base,
4577                                     &intel_dp->aux.ddc);
4578 }
4579
4580 static void
4581 intel_dp_set_edid(struct intel_dp *intel_dp)
4582 {
4583         struct intel_connector *intel_connector = intel_dp->attached_connector;
4584         struct edid *edid;
4585
4586         intel_dp_unset_edid(intel_dp);
4587         edid = intel_dp_get_edid(intel_dp);
4588         intel_connector->detect_edid = edid;
4589
4590         if (intel_dp->force_audio != HDMI_AUDIO_AUTO)
4591                 intel_dp->has_audio = intel_dp->force_audio == HDMI_AUDIO_ON;
4592         else
4593                 intel_dp->has_audio = drm_detect_monitor_audio(edid);
4594 }
4595
4596 static void
4597 intel_dp_unset_edid(struct intel_dp *intel_dp)
4598 {
4599         struct intel_connector *intel_connector = intel_dp->attached_connector;
4600
4601         kfree(intel_connector->detect_edid);
4602         intel_connector->detect_edid = NULL;
4603
4604         intel_dp->has_audio = false;
4605 }
4606
4607 static int
4608 intel_dp_long_pulse(struct intel_connector *intel_connector)
4609 {
4610         struct drm_connector *connector = &intel_connector->base;
4611         struct intel_dp *intel_dp = intel_attached_dp(connector);
4612         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4613         struct intel_encoder *intel_encoder = &intel_dig_port->base;
4614         struct drm_device *dev = connector->dev;
4615         enum drm_connector_status status;
4616         u8 sink_irq_vector = 0;
4617
4618         WARN_ON(!drm_modeset_is_locked(&connector->dev->mode_config.connection_mutex));
4619
4620         intel_display_power_get(to_i915(dev), intel_dp->aux_power_domain);
4621
4622         /* Can't disconnect eDP, but you can close the lid... */
4623         if (is_edp(intel_dp))
4624                 status = edp_detect(intel_dp);
4625         else if (intel_digital_port_connected(to_i915(dev),
4626                                               dp_to_dig_port(intel_dp)))
4627                 status = intel_dp_detect_dpcd(intel_dp);
4628         else
4629                 status = connector_status_disconnected;
4630
4631         if (status == connector_status_disconnected) {
4632                 memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance));
4633
4634                 if (intel_dp->is_mst) {
4635                         DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
4636                                       intel_dp->is_mst,
4637                                       intel_dp->mst_mgr.mst_state);
4638                         intel_dp->is_mst = false;
4639                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
4640                                                         intel_dp->is_mst);
4641                 }
4642
4643                 goto out;
4644         }
4645
4646         if (intel_encoder->type != INTEL_OUTPUT_EDP)
4647                 intel_encoder->type = INTEL_OUTPUT_DP;
4648
4649         DRM_DEBUG_KMS("Display Port TPS3 support: source %s, sink %s\n",
4650                       yesno(intel_dp_source_supports_hbr2(intel_dp)),
4651                       yesno(drm_dp_tps3_supported(intel_dp->dpcd)));
4652
4653         if (intel_dp->reset_link_params) {
4654                 /* Initial max link lane count */
4655                 intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp);
4656
4657                 /* Initial max link rate */
4658                 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp);
4659
4660                 intel_dp->reset_link_params = false;
4661         }
4662
4663         intel_dp_print_rates(intel_dp);
4664
4665         drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc,
4666                          drm_dp_is_branch(intel_dp->dpcd));
4667
4668         intel_dp_configure_mst(intel_dp);
4669
4670         if (intel_dp->is_mst) {
4671                 /*
4672                  * If we are in MST mode then this connector
4673                  * won't appear connected or have anything
4674                  * with EDID on it
4675                  */
4676                 status = connector_status_disconnected;
4677                 goto out;
4678         } else {
4679                 /*
4680                  * If display is now connected check links status,
4681                  * there has been known issues of link loss triggerring
4682                  * long pulse.
4683                  *
4684                  * Some sinks (eg. ASUS PB287Q) seem to perform some
4685                  * weird HPD ping pong during modesets. So we can apparently
4686                  * end up with HPD going low during a modeset, and then
4687                  * going back up soon after. And once that happens we must
4688                  * retrain the link to get a picture. That's in case no
4689                  * userspace component reacted to intermittent HPD dip.
4690                  */
4691                 intel_dp_check_link_status(intel_dp);
4692         }
4693
4694         /*
4695          * Clearing NACK and defer counts to get their exact values
4696          * while reading EDID which are required by Compliance tests
4697          * 4.2.2.4 and 4.2.2.5
4698          */
4699         intel_dp->aux.i2c_nack_count = 0;
4700         intel_dp->aux.i2c_defer_count = 0;
4701
4702         intel_dp_set_edid(intel_dp);
4703         if (is_edp(intel_dp) || intel_connector->detect_edid)
4704                 status = connector_status_connected;
4705         intel_dp->detect_done = true;
4706
4707         /* Try to read the source of the interrupt */
4708         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4709             intel_dp_get_sink_irq(intel_dp, &sink_irq_vector) &&
4710             sink_irq_vector != 0) {
4711                 /* Clear interrupt source */
4712                 drm_dp_dpcd_writeb(&intel_dp->aux,
4713                                    DP_DEVICE_SERVICE_IRQ_VECTOR,
4714                                    sink_irq_vector);
4715
4716                 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
4717                         intel_dp_handle_test_request(intel_dp);
4718                 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
4719                         DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4720         }
4721
4722 out:
4723         if (status != connector_status_connected && !intel_dp->is_mst)
4724                 intel_dp_unset_edid(intel_dp);
4725
4726         intel_display_power_put(to_i915(dev), intel_dp->aux_power_domain);
4727         return status;
4728 }
4729
4730 static int
4731 intel_dp_detect(struct drm_connector *connector,
4732                 struct drm_modeset_acquire_ctx *ctx,
4733                 bool force)
4734 {
4735         struct intel_dp *intel_dp = intel_attached_dp(connector);
4736         int status = connector->status;
4737
4738         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4739                       connector->base.id, connector->name);
4740
4741         /* If full detect is not performed yet, do a full detect */
4742         if (!intel_dp->detect_done)
4743                 status = intel_dp_long_pulse(intel_dp->attached_connector);
4744
4745         intel_dp->detect_done = false;
4746
4747         return status;
4748 }
4749
4750 static void
4751 intel_dp_force(struct drm_connector *connector)
4752 {
4753         struct intel_dp *intel_dp = intel_attached_dp(connector);
4754         struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
4755         struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
4756
4757         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4758                       connector->base.id, connector->name);
4759         intel_dp_unset_edid(intel_dp);
4760
4761         if (connector->status != connector_status_connected)
4762                 return;
4763
4764         intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
4765
4766         intel_dp_set_edid(intel_dp);
4767
4768         intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
4769
4770         if (intel_encoder->type != INTEL_OUTPUT_EDP)
4771                 intel_encoder->type = INTEL_OUTPUT_DP;
4772 }
4773
4774 static int intel_dp_get_modes(struct drm_connector *connector)
4775 {
4776         struct intel_connector *intel_connector = to_intel_connector(connector);
4777         struct edid *edid;
4778
4779         edid = intel_connector->detect_edid;
4780         if (edid) {
4781                 int ret = intel_connector_update_modes(connector, edid);
4782                 if (ret)
4783                         return ret;
4784         }
4785
4786         /* if eDP has no EDID, fall back to fixed mode */
4787         if (is_edp(intel_attached_dp(connector)) &&
4788             intel_connector->panel.fixed_mode) {
4789                 struct drm_display_mode *mode;
4790
4791                 mode = drm_mode_duplicate(connector->dev,
4792                                           intel_connector->panel.fixed_mode);
4793                 if (mode) {
4794                         drm_mode_probed_add(connector, mode);
4795                         return 1;
4796                 }
4797         }
4798
4799         return 0;
4800 }
4801
4802 static bool
4803 intel_dp_detect_audio(struct drm_connector *connector)
4804 {
4805         bool has_audio = false;
4806         struct edid *edid;
4807
4808         edid = to_intel_connector(connector)->detect_edid;
4809         if (edid)
4810                 has_audio = drm_detect_monitor_audio(edid);
4811
4812         return has_audio;
4813 }
4814
4815 static int
4816 intel_dp_set_property(struct drm_connector *connector,
4817                       struct drm_property *property,
4818                       uint64_t val)
4819 {
4820         struct drm_i915_private *dev_priv = to_i915(connector->dev);
4821         struct intel_connector *intel_connector = to_intel_connector(connector);
4822         struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
4823         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4824         int ret;
4825
4826         ret = drm_object_property_set_value(&connector->base, property, val);
4827         if (ret)
4828                 return ret;
4829
4830         if (property == dev_priv->force_audio_property) {
4831                 int i = val;
4832                 bool has_audio;
4833
4834                 if (i == intel_dp->force_audio)
4835                         return 0;
4836
4837                 intel_dp->force_audio = i;
4838
4839                 if (i == HDMI_AUDIO_AUTO)
4840                         has_audio = intel_dp_detect_audio(connector);
4841                 else
4842                         has_audio = (i == HDMI_AUDIO_ON);
4843
4844                 if (has_audio == intel_dp->has_audio)
4845                         return 0;
4846
4847                 intel_dp->has_audio = has_audio;
4848                 goto done;
4849         }
4850
4851         if (property == dev_priv->broadcast_rgb_property) {
4852                 bool old_auto = intel_dp->color_range_auto;
4853                 bool old_range = intel_dp->limited_color_range;
4854
4855                 switch (val) {
4856                 case INTEL_BROADCAST_RGB_AUTO:
4857                         intel_dp->color_range_auto = true;
4858                         break;
4859                 case INTEL_BROADCAST_RGB_FULL:
4860                         intel_dp->color_range_auto = false;
4861                         intel_dp->limited_color_range = false;
4862                         break;
4863                 case INTEL_BROADCAST_RGB_LIMITED:
4864                         intel_dp->color_range_auto = false;
4865                         intel_dp->limited_color_range = true;
4866                         break;
4867                 default:
4868                         return -EINVAL;
4869                 }
4870
4871                 if (old_auto == intel_dp->color_range_auto &&
4872                     old_range == intel_dp->limited_color_range)
4873                         return 0;
4874
4875                 goto done;
4876         }
4877
4878         if (is_edp(intel_dp) &&
4879             property == connector->dev->mode_config.scaling_mode_property) {
4880                 if (val == DRM_MODE_SCALE_NONE) {
4881                         DRM_DEBUG_KMS("no scaling not supported\n");
4882                         return -EINVAL;
4883                 }
4884                 if (HAS_GMCH_DISPLAY(dev_priv) &&
4885                     val == DRM_MODE_SCALE_CENTER) {
4886                         DRM_DEBUG_KMS("centering not supported\n");
4887                         return -EINVAL;
4888                 }
4889
4890                 if (intel_connector->panel.fitting_mode == val) {
4891                         /* the eDP scaling property is not changed */
4892                         return 0;
4893                 }
4894                 intel_connector->panel.fitting_mode = val;
4895
4896                 goto done;
4897         }
4898
4899         return -EINVAL;
4900
4901 done:
4902         if (intel_encoder->base.crtc)
4903                 intel_crtc_restore_mode(intel_encoder->base.crtc);
4904
4905         return 0;
4906 }
4907
4908 static int
4909 intel_dp_connector_register(struct drm_connector *connector)
4910 {
4911         struct intel_dp *intel_dp = intel_attached_dp(connector);
4912         int ret;
4913
4914         ret = intel_connector_register(connector);
4915         if (ret)
4916                 return ret;
4917
4918         i915_debugfs_connector_add(connector);
4919
4920         DRM_DEBUG_KMS("registering %s bus for %s\n",
4921                       intel_dp->aux.name, connector->kdev->kobj.name);
4922
4923         intel_dp->aux.dev = connector->kdev;
4924         return drm_dp_aux_register(&intel_dp->aux);
4925 }
4926
4927 static void
4928 intel_dp_connector_unregister(struct drm_connector *connector)
4929 {
4930         drm_dp_aux_unregister(&intel_attached_dp(connector)->aux);
4931         intel_connector_unregister(connector);
4932 }
4933
4934 static void
4935 intel_dp_connector_destroy(struct drm_connector *connector)
4936 {
4937         struct intel_connector *intel_connector = to_intel_connector(connector);
4938
4939         kfree(intel_connector->detect_edid);
4940
4941         if (!IS_ERR_OR_NULL(intel_connector->edid))
4942                 kfree(intel_connector->edid);
4943
4944         /* Can't call is_edp() since the encoder may have been destroyed
4945          * already. */
4946         if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
4947                 intel_panel_fini(&intel_connector->panel);
4948
4949         drm_connector_cleanup(connector);
4950         kfree(connector);
4951 }
4952
4953 void intel_dp_encoder_destroy(struct drm_encoder *encoder)
4954 {
4955         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
4956         struct intel_dp *intel_dp = &intel_dig_port->dp;
4957
4958         intel_dp_mst_encoder_cleanup(intel_dig_port);
4959         if (is_edp(intel_dp)) {
4960                 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
4961                 /*
4962                  * vdd might still be enabled do to the delayed vdd off.
4963                  * Make sure vdd is actually turned off here.
4964                  */
4965                 pps_lock(intel_dp);
4966                 edp_panel_vdd_off_sync(intel_dp);
4967                 pps_unlock(intel_dp);
4968
4969                 if (intel_dp->edp_notifier.notifier_call) {
4970                         unregister_reboot_notifier(&intel_dp->edp_notifier);
4971                         intel_dp->edp_notifier.notifier_call = NULL;
4972                 }
4973         }
4974
4975         intel_dp_aux_fini(intel_dp);
4976
4977         drm_encoder_cleanup(encoder);
4978         kfree(intel_dig_port);
4979 }
4980
4981 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
4982 {
4983         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4984
4985         if (!is_edp(intel_dp))
4986                 return;
4987
4988         /*
4989          * vdd might still be enabled do to the delayed vdd off.
4990          * Make sure vdd is actually turned off here.
4991          */
4992         cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
4993         pps_lock(intel_dp);
4994         edp_panel_vdd_off_sync(intel_dp);
4995         pps_unlock(intel_dp);
4996 }
4997
4998 static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
4999 {
5000         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
5001         struct drm_device *dev = intel_dig_port->base.base.dev;
5002         struct drm_i915_private *dev_priv = to_i915(dev);
5003
5004         lockdep_assert_held(&dev_priv->pps_mutex);
5005
5006         if (!edp_have_panel_vdd(intel_dp))
5007                 return;
5008
5009         /*
5010          * The VDD bit needs a power domain reference, so if the bit is
5011          * already enabled when we boot or resume, grab this reference and
5012          * schedule a vdd off, so we don't hold on to the reference
5013          * indefinitely.
5014          */
5015         DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
5016         intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
5017
5018         edp_panel_vdd_schedule_off(intel_dp);
5019 }
5020
5021 static enum pipe vlv_active_pipe(struct intel_dp *intel_dp)
5022 {
5023         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
5024
5025         if ((intel_dp->DP & DP_PORT_EN) == 0)
5026                 return INVALID_PIPE;
5027
5028         if (IS_CHERRYVIEW(dev_priv))
5029                 return DP_PORT_TO_PIPE_CHV(intel_dp->DP);
5030         else
5031                 return PORT_TO_PIPE(intel_dp->DP);
5032 }
5033
5034 void intel_dp_encoder_reset(struct drm_encoder *encoder)
5035 {
5036         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
5037         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
5038         struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp);
5039
5040         if (!HAS_DDI(dev_priv))
5041                 intel_dp->DP = I915_READ(intel_dp->output_reg);
5042
5043         if (lspcon->active)
5044                 lspcon_resume(lspcon);
5045
5046         intel_dp->reset_link_params = true;
5047
5048         pps_lock(intel_dp);
5049
5050         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5051                 intel_dp->active_pipe = vlv_active_pipe(intel_dp);
5052
5053         if (is_edp(intel_dp)) {
5054                 /* Reinit the power sequencer, in case BIOS did something with it. */
5055                 intel_dp_pps_init(encoder->dev, intel_dp);
5056                 intel_edp_panel_vdd_sanitize(intel_dp);
5057         }
5058
5059         pps_unlock(intel_dp);
5060 }
5061
5062 static const struct drm_connector_funcs intel_dp_connector_funcs = {
5063         .dpms = drm_atomic_helper_connector_dpms,
5064         .force = intel_dp_force,
5065         .fill_modes = drm_helper_probe_single_connector_modes,
5066         .set_property = intel_dp_set_property,
5067         .atomic_get_property = intel_connector_atomic_get_property,
5068         .late_register = intel_dp_connector_register,
5069         .early_unregister = intel_dp_connector_unregister,
5070         .destroy = intel_dp_connector_destroy,
5071         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
5072         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
5073 };
5074
5075 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
5076         .detect_ctx = intel_dp_detect,
5077         .get_modes = intel_dp_get_modes,
5078         .mode_valid = intel_dp_mode_valid,
5079 };
5080
5081 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
5082         .reset = intel_dp_encoder_reset,
5083         .destroy = intel_dp_encoder_destroy,
5084 };
5085
5086 enum irqreturn
5087 intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
5088 {
5089         struct intel_dp *intel_dp = &intel_dig_port->dp;
5090         struct drm_device *dev = intel_dig_port->base.base.dev;
5091         struct drm_i915_private *dev_priv = to_i915(dev);
5092         enum irqreturn ret = IRQ_NONE;
5093
5094         if (intel_dig_port->base.type != INTEL_OUTPUT_EDP &&
5095             intel_dig_port->base.type != INTEL_OUTPUT_HDMI)
5096                 intel_dig_port->base.type = INTEL_OUTPUT_DP;
5097
5098         if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) {
5099                 /*
5100                  * vdd off can generate a long pulse on eDP which
5101                  * would require vdd on to handle it, and thus we
5102                  * would end up in an endless cycle of
5103                  * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..."
5104                  */
5105                 DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n",
5106                               port_name(intel_dig_port->port));
5107                 return IRQ_HANDLED;
5108         }
5109
5110         DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
5111                       port_name(intel_dig_port->port),
5112                       long_hpd ? "long" : "short");
5113
5114         if (long_hpd) {
5115                 intel_dp->reset_link_params = true;
5116                 intel_dp->detect_done = false;
5117                 return IRQ_NONE;
5118         }
5119
5120         intel_display_power_get(dev_priv, intel_dp->aux_power_domain);
5121
5122         if (intel_dp->is_mst) {
5123                 if (intel_dp_check_mst_status(intel_dp) == -EINVAL) {
5124                         /*
5125                          * If we were in MST mode, and device is not
5126                          * there, get out of MST mode
5127                          */
5128                         DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n",
5129                                       intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
5130                         intel_dp->is_mst = false;
5131                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr,
5132                                                         intel_dp->is_mst);
5133                         intel_dp->detect_done = false;
5134                         goto put_power;
5135                 }
5136         }
5137
5138         if (!intel_dp->is_mst) {
5139                 if (!intel_dp_short_pulse(intel_dp)) {
5140                         intel_dp->detect_done = false;
5141                         goto put_power;
5142                 }
5143         }
5144
5145         ret = IRQ_HANDLED;
5146
5147 put_power:
5148         intel_display_power_put(dev_priv, intel_dp->aux_power_domain);
5149
5150         return ret;
5151 }
5152
5153 /* check the VBT to see whether the eDP is on another port */
5154 bool intel_dp_is_edp(struct drm_i915_private *dev_priv, enum port port)
5155 {
5156         /*
5157          * eDP not supported on g4x. so bail out early just
5158          * for a bit extra safety in case the VBT is bonkers.
5159          */
5160         if (INTEL_GEN(dev_priv) < 5)
5161                 return false;
5162
5163         if (INTEL_GEN(dev_priv) < 9 && port == PORT_A)
5164                 return true;
5165
5166         return intel_bios_is_port_edp(dev_priv, port);
5167 }
5168
5169 static void
5170 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
5171 {
5172         struct intel_connector *intel_connector = to_intel_connector(connector);
5173
5174         intel_attach_force_audio_property(connector);
5175         intel_attach_broadcast_rgb_property(connector);
5176         intel_dp->color_range_auto = true;
5177
5178         if (is_edp(intel_dp)) {
5179                 drm_mode_create_scaling_mode_property(connector->dev);
5180                 drm_object_attach_property(
5181                         &connector->base,
5182                         connector->dev->mode_config.scaling_mode_property,
5183                         DRM_MODE_SCALE_ASPECT);
5184                 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
5185         }
5186 }
5187
5188 static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
5189 {
5190         intel_dp->panel_power_off_time = ktime_get_boottime();
5191         intel_dp->last_power_on = jiffies;
5192         intel_dp->last_backlight_off = jiffies;
5193 }
5194
5195 static void
5196 intel_pps_readout_hw_state(struct drm_i915_private *dev_priv,
5197                            struct intel_dp *intel_dp, struct edp_power_seq *seq)
5198 {
5199         u32 pp_on, pp_off, pp_div = 0, pp_ctl = 0;
5200         struct pps_registers regs;
5201
5202         intel_pps_get_registers(dev_priv, intel_dp, &regs);
5203
5204         /* Workaround: Need to write PP_CONTROL with the unlock key as
5205          * the very first thing. */
5206         pp_ctl = ironlake_get_pp_control(intel_dp);
5207
5208         pp_on = I915_READ(regs.pp_on);
5209         pp_off = I915_READ(regs.pp_off);
5210         if (!IS_GEN9_LP(dev_priv)) {
5211                 I915_WRITE(regs.pp_ctrl, pp_ctl);
5212                 pp_div = I915_READ(regs.pp_div);
5213         }
5214
5215         /* Pull timing values out of registers */
5216         seq->t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
5217                      PANEL_POWER_UP_DELAY_SHIFT;
5218
5219         seq->t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
5220                   PANEL_LIGHT_ON_DELAY_SHIFT;
5221
5222         seq->t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
5223                   PANEL_LIGHT_OFF_DELAY_SHIFT;
5224
5225         seq->t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
5226                    PANEL_POWER_DOWN_DELAY_SHIFT;
5227
5228         if (IS_GEN9_LP(dev_priv)) {
5229                 u16 tmp = (pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >>
5230                         BXT_POWER_CYCLE_DELAY_SHIFT;
5231                 if (tmp > 0)
5232                         seq->t11_t12 = (tmp - 1) * 1000;
5233                 else
5234                         seq->t11_t12 = 0;
5235         } else {
5236                 seq->t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
5237                        PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
5238         }
5239 }
5240
5241 static void
5242 intel_pps_dump_state(const char *state_name, const struct edp_power_seq *seq)
5243 {
5244         DRM_DEBUG_KMS("%s t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
5245                       state_name,
5246                       seq->t1_t3, seq->t8, seq->t9, seq->t10, seq->t11_t12);
5247 }
5248
5249 static void
5250 intel_pps_verify_state(struct drm_i915_private *dev_priv,
5251                        struct intel_dp *intel_dp)
5252 {
5253         struct edp_power_seq hw;
5254         struct edp_power_seq *sw = &intel_dp->pps_delays;
5255
5256         intel_pps_readout_hw_state(dev_priv, intel_dp, &hw);
5257
5258         if (hw.t1_t3 != sw->t1_t3 || hw.t8 != sw->t8 || hw.t9 != sw->t9 ||
5259             hw.t10 != sw->t10 || hw.t11_t12 != sw->t11_t12) {
5260                 DRM_ERROR("PPS state mismatch\n");
5261                 intel_pps_dump_state("sw", sw);
5262                 intel_pps_dump_state("hw", &hw);
5263         }
5264 }
5265
5266 static void
5267 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
5268                                     struct intel_dp *intel_dp)
5269 {
5270         struct drm_i915_private *dev_priv = to_i915(dev);
5271         struct edp_power_seq cur, vbt, spec,
5272                 *final = &intel_dp->pps_delays;
5273
5274         lockdep_assert_held(&dev_priv->pps_mutex);
5275
5276         /* already initialized? */
5277         if (final->t11_t12 != 0)
5278                 return;
5279
5280         intel_pps_readout_hw_state(dev_priv, intel_dp, &cur);
5281
5282         intel_pps_dump_state("cur", &cur);
5283
5284         vbt = dev_priv->vbt.edp.pps;
5285
5286         /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
5287          * our hw here, which are all in 100usec. */
5288         spec.t1_t3 = 210 * 10;
5289         spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
5290         spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
5291         spec.t10 = 500 * 10;
5292         /* This one is special and actually in units of 100ms, but zero
5293          * based in the hw (so we need to add 100 ms). But the sw vbt
5294          * table multiplies it with 1000 to make it in units of 100usec,
5295          * too. */
5296         spec.t11_t12 = (510 + 100) * 10;
5297
5298         intel_pps_dump_state("vbt", &vbt);
5299
5300         /* Use the max of the register settings and vbt. If both are
5301          * unset, fall back to the spec limits. */
5302 #define assign_final(field)     final->field = (max(cur.field, vbt.field) == 0 ? \
5303                                        spec.field : \
5304                                        max(cur.field, vbt.field))
5305         assign_final(t1_t3);
5306         assign_final(t8);
5307         assign_final(t9);
5308         assign_final(t10);
5309         assign_final(t11_t12);
5310 #undef assign_final
5311
5312 #define get_delay(field)        (DIV_ROUND_UP(final->field, 10))
5313         intel_dp->panel_power_up_delay = get_delay(t1_t3);
5314         intel_dp->backlight_on_delay = get_delay(t8);
5315         intel_dp->backlight_off_delay = get_delay(t9);
5316         intel_dp->panel_power_down_delay = get_delay(t10);
5317         intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
5318 #undef get_delay
5319
5320         DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
5321                       intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
5322                       intel_dp->panel_power_cycle_delay);
5323
5324         DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
5325                       intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
5326
5327         /*
5328          * We override the HW backlight delays to 1 because we do manual waits
5329          * on them. For T8, even BSpec recommends doing it. For T9, if we
5330          * don't do this, we'll end up waiting for the backlight off delay
5331          * twice: once when we do the manual sleep, and once when we disable
5332          * the panel and wait for the PP_STATUS bit to become zero.
5333          */
5334         final->t8 = 1;
5335         final->t9 = 1;
5336 }
5337
5338 static void
5339 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
5340                                               struct intel_dp *intel_dp,
5341                                               bool force_disable_vdd)
5342 {
5343         struct drm_i915_private *dev_priv = to_i915(dev);
5344         u32 pp_on, pp_off, pp_div, port_sel = 0;
5345         int div = dev_priv->rawclk_freq / 1000;
5346         struct pps_registers regs;
5347         enum port port = dp_to_dig_port(intel_dp)->port;
5348         const struct edp_power_seq *seq = &intel_dp->pps_delays;
5349
5350         lockdep_assert_held(&dev_priv->pps_mutex);
5351
5352         intel_pps_get_registers(dev_priv, intel_dp, &regs);
5353
5354         /*
5355          * On some VLV machines the BIOS can leave the VDD
5356          * enabled even on power seqeuencers which aren't
5357          * hooked up to any port. This would mess up the
5358          * power domain tracking the first time we pick
5359          * one of these power sequencers for use since
5360          * edp_panel_vdd_on() would notice that the VDD was
5361          * already on and therefore wouldn't grab the power
5362          * domain reference. Disable VDD first to avoid this.
5363          * This also avoids spuriously turning the VDD on as
5364          * soon as the new power seqeuencer gets initialized.
5365          */
5366         if (force_disable_vdd) {
5367                 u32 pp = ironlake_get_pp_control(intel_dp);
5368
5369                 WARN(pp & PANEL_POWER_ON, "Panel power already on\n");
5370
5371                 if (pp & EDP_FORCE_VDD)
5372                         DRM_DEBUG_KMS("VDD already on, disabling first\n");
5373
5374                 pp &= ~EDP_FORCE_VDD;
5375
5376                 I915_WRITE(regs.pp_ctrl, pp);
5377         }
5378
5379         pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
5380                 (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
5381         pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
5382                  (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
5383         /* Compute the divisor for the pp clock, simply match the Bspec
5384          * formula. */
5385         if (IS_GEN9_LP(dev_priv)) {
5386                 pp_div = I915_READ(regs.pp_ctrl);
5387                 pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK;
5388                 pp_div |= (DIV_ROUND_UP((seq->t11_t12 + 1), 1000)
5389                                 << BXT_POWER_CYCLE_DELAY_SHIFT);
5390         } else {
5391                 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
5392                 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
5393                                 << PANEL_POWER_CYCLE_DELAY_SHIFT);
5394         }
5395
5396         /* Haswell doesn't have any port selection bits for the panel
5397          * power sequencer any more. */
5398         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
5399                 port_sel = PANEL_PORT_SELECT_VLV(port);
5400         } else if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
5401                 if (port == PORT_A)
5402                         port_sel = PANEL_PORT_SELECT_DPA;
5403                 else
5404                         port_sel = PANEL_PORT_SELECT_DPD;
5405         }
5406
5407         pp_on |= port_sel;
5408
5409         I915_WRITE(regs.pp_on, pp_on);
5410         I915_WRITE(regs.pp_off, pp_off);
5411         if (IS_GEN9_LP(dev_priv))
5412                 I915_WRITE(regs.pp_ctrl, pp_div);
5413         else
5414                 I915_WRITE(regs.pp_div, pp_div);
5415
5416         DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
5417                       I915_READ(regs.pp_on),
5418                       I915_READ(regs.pp_off),
5419                       IS_GEN9_LP(dev_priv) ?
5420                       (I915_READ(regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK) :
5421                       I915_READ(regs.pp_div));
5422 }
5423
5424 static void intel_dp_pps_init(struct drm_device *dev,
5425                               struct intel_dp *intel_dp)
5426 {
5427         struct drm_i915_private *dev_priv = to_i915(dev);
5428
5429         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
5430                 vlv_initial_power_sequencer_setup(intel_dp);
5431         } else {
5432                 intel_dp_init_panel_power_sequencer(dev, intel_dp);
5433                 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, false);
5434         }
5435 }
5436
5437 /**
5438  * intel_dp_set_drrs_state - program registers for RR switch to take effect
5439  * @dev_priv: i915 device
5440  * @crtc_state: a pointer to the active intel_crtc_state
5441  * @refresh_rate: RR to be programmed
5442  *
5443  * This function gets called when refresh rate (RR) has to be changed from
5444  * one frequency to another. Switches can be between high and low RR
5445  * supported by the panel or to any other RR based on media playback (in
5446  * this case, RR value needs to be passed from user space).
5447  *
5448  * The caller of this function needs to take a lock on dev_priv->drrs.
5449  */
5450 static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv,
5451                                     struct intel_crtc_state *crtc_state,
5452                                     int refresh_rate)
5453 {
5454         struct intel_encoder *encoder;
5455         struct intel_digital_port *dig_port = NULL;
5456         struct intel_dp *intel_dp = dev_priv->drrs.dp;
5457         struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc);
5458         enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
5459
5460         if (refresh_rate <= 0) {
5461                 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
5462                 return;
5463         }
5464
5465         if (intel_dp == NULL) {
5466                 DRM_DEBUG_KMS("DRRS not supported.\n");
5467                 return;
5468         }
5469
5470         /*
5471          * FIXME: This needs proper synchronization with psr state for some
5472          * platforms that cannot have PSR and DRRS enabled at the same time.
5473          */
5474
5475         dig_port = dp_to_dig_port(intel_dp);
5476         encoder = &dig_port->base;
5477         intel_crtc = to_intel_crtc(encoder->base.crtc);
5478
5479         if (!intel_crtc) {
5480                 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
5481                 return;
5482         }
5483
5484         if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) {
5485                 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
5486                 return;
5487         }
5488
5489         if (intel_dp->attached_connector->panel.downclock_mode->vrefresh ==
5490                         refresh_rate)
5491                 index = DRRS_LOW_RR;
5492
5493         if (index == dev_priv->drrs.refresh_rate_type) {
5494                 DRM_DEBUG_KMS(
5495                         "DRRS requested for previously set RR...ignoring\n");
5496                 return;
5497         }
5498
5499         if (!crtc_state->base.active) {
5500                 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
5501                 return;
5502         }
5503
5504         if (INTEL_GEN(dev_priv) >= 8 && !IS_CHERRYVIEW(dev_priv)) {
5505                 switch (index) {
5506                 case DRRS_HIGH_RR:
5507                         intel_dp_set_m_n(intel_crtc, M1_N1);
5508                         break;
5509                 case DRRS_LOW_RR:
5510                         intel_dp_set_m_n(intel_crtc, M2_N2);
5511                         break;
5512                 case DRRS_MAX_RR:
5513                 default:
5514                         DRM_ERROR("Unsupported refreshrate type\n");
5515                 }
5516         } else if (INTEL_GEN(dev_priv) > 6) {
5517                 i915_reg_t reg = PIPECONF(crtc_state->cpu_transcoder);
5518                 u32 val;
5519
5520                 val = I915_READ(reg);
5521                 if (index > DRRS_HIGH_RR) {
5522                         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5523                                 val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
5524                         else
5525                                 val |= PIPECONF_EDP_RR_MODE_SWITCH;
5526                 } else {
5527                         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5528                                 val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
5529                         else
5530                                 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
5531                 }
5532                 I915_WRITE(reg, val);
5533         }
5534
5535         dev_priv->drrs.refresh_rate_type = index;
5536
5537         DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
5538 }
5539
5540 /**
5541  * intel_edp_drrs_enable - init drrs struct if supported
5542  * @intel_dp: DP struct
5543  * @crtc_state: A pointer to the active crtc state.
5544  *
5545  * Initializes frontbuffer_bits and drrs.dp
5546  */
5547 void intel_edp_drrs_enable(struct intel_dp *intel_dp,
5548                            struct intel_crtc_state *crtc_state)
5549 {
5550         struct drm_device *dev = intel_dp_to_dev(intel_dp);
5551         struct drm_i915_private *dev_priv = to_i915(dev);
5552
5553         if (!crtc_state->has_drrs) {
5554                 DRM_DEBUG_KMS("Panel doesn't support DRRS\n");
5555                 return;
5556         }
5557
5558         mutex_lock(&dev_priv->drrs.mutex);
5559         if (WARN_ON(dev_priv->drrs.dp)) {
5560                 DRM_ERROR("DRRS already enabled\n");
5561                 goto unlock;
5562         }
5563
5564         dev_priv->drrs.busy_frontbuffer_bits = 0;
5565
5566         dev_priv->drrs.dp = intel_dp;
5567
5568 unlock:
5569         mutex_unlock(&dev_priv->drrs.mutex);
5570 }
5571
5572 /**
5573  * intel_edp_drrs_disable - Disable DRRS
5574  * @intel_dp: DP struct
5575  * @old_crtc_state: Pointer to old crtc_state.
5576  *
5577  */
5578 void intel_edp_drrs_disable(struct intel_dp *intel_dp,
5579                             struct intel_crtc_state *old_crtc_state)
5580 {
5581         struct drm_device *dev = intel_dp_to_dev(intel_dp);
5582         struct drm_i915_private *dev_priv = to_i915(dev);
5583
5584         if (!old_crtc_state->has_drrs)
5585                 return;
5586
5587         mutex_lock(&dev_priv->drrs.mutex);
5588         if (!dev_priv->drrs.dp) {
5589                 mutex_unlock(&dev_priv->drrs.mutex);
5590                 return;
5591         }
5592
5593         if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5594                 intel_dp_set_drrs_state(dev_priv, old_crtc_state,
5595                         intel_dp->attached_connector->panel.fixed_mode->vrefresh);
5596
5597         dev_priv->drrs.dp = NULL;
5598         mutex_unlock(&dev_priv->drrs.mutex);
5599
5600         cancel_delayed_work_sync(&dev_priv->drrs.work);
5601 }
5602
5603 static void intel_edp_drrs_downclock_work(struct work_struct *work)
5604 {
5605         struct drm_i915_private *dev_priv =
5606                 container_of(work, typeof(*dev_priv), drrs.work.work);
5607         struct intel_dp *intel_dp;
5608
5609         mutex_lock(&dev_priv->drrs.mutex);
5610
5611         intel_dp = dev_priv->drrs.dp;
5612
5613         if (!intel_dp)
5614                 goto unlock;
5615
5616         /*
5617          * The delayed work can race with an invalidate hence we need to
5618          * recheck.
5619          */
5620
5621         if (dev_priv->drrs.busy_frontbuffer_bits)
5622                 goto unlock;
5623
5624         if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR) {
5625                 struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
5626
5627                 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
5628                         intel_dp->attached_connector->panel.downclock_mode->vrefresh);
5629         }
5630
5631 unlock:
5632         mutex_unlock(&dev_priv->drrs.mutex);
5633 }
5634
5635 /**
5636  * intel_edp_drrs_invalidate - Disable Idleness DRRS
5637  * @dev_priv: i915 device
5638  * @frontbuffer_bits: frontbuffer plane tracking bits
5639  *
5640  * This function gets called everytime rendering on the given planes start.
5641  * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).
5642  *
5643  * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5644  */
5645 void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv,
5646                                unsigned int frontbuffer_bits)
5647 {
5648         struct drm_crtc *crtc;
5649         enum pipe pipe;
5650
5651         if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
5652                 return;
5653
5654         cancel_delayed_work(&dev_priv->drrs.work);
5655
5656         mutex_lock(&dev_priv->drrs.mutex);
5657         if (!dev_priv->drrs.dp) {
5658                 mutex_unlock(&dev_priv->drrs.mutex);
5659                 return;
5660         }
5661
5662         crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
5663         pipe = to_intel_crtc(crtc)->pipe;
5664
5665         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
5666         dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits;
5667
5668         /* invalidate means busy screen hence upclock */
5669         if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5670                 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
5671                         dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh);
5672
5673         mutex_unlock(&dev_priv->drrs.mutex);
5674 }
5675
5676 /**
5677  * intel_edp_drrs_flush - Restart Idleness DRRS
5678  * @dev_priv: i915 device
5679  * @frontbuffer_bits: frontbuffer plane tracking bits
5680  *
5681  * This function gets called every time rendering on the given planes has
5682  * completed or flip on a crtc is completed. So DRRS should be upclocked
5683  * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again,
5684  * if no other planes are dirty.
5685  *
5686  * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5687  */
5688 void intel_edp_drrs_flush(struct drm_i915_private *dev_priv,
5689                           unsigned int frontbuffer_bits)
5690 {
5691         struct drm_crtc *crtc;
5692         enum pipe pipe;
5693
5694         if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
5695                 return;
5696
5697         cancel_delayed_work(&dev_priv->drrs.work);
5698
5699         mutex_lock(&dev_priv->drrs.mutex);
5700         if (!dev_priv->drrs.dp) {
5701                 mutex_unlock(&dev_priv->drrs.mutex);
5702                 return;
5703         }
5704
5705         crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
5706         pipe = to_intel_crtc(crtc)->pipe;
5707
5708         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
5709         dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits;
5710
5711         /* flush means busy screen hence upclock */
5712         if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5713                 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config,
5714                                 dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh);
5715
5716         /*
5717          * flush also means no more activity hence schedule downclock, if all
5718          * other fbs are quiescent too
5719          */
5720         if (!dev_priv->drrs.busy_frontbuffer_bits)
5721                 schedule_delayed_work(&dev_priv->drrs.work,
5722                                 msecs_to_jiffies(1000));
5723         mutex_unlock(&dev_priv->drrs.mutex);
5724 }
5725
5726 /**
5727  * DOC: Display Refresh Rate Switching (DRRS)
5728  *
5729  * Display Refresh Rate Switching (DRRS) is a power conservation feature
5730  * which enables swtching between low and high refresh rates,
5731  * dynamically, based on the usage scenario. This feature is applicable
5732  * for internal panels.
5733  *
5734  * Indication that the panel supports DRRS is given by the panel EDID, which
5735  * would list multiple refresh rates for one resolution.
5736  *
5737  * DRRS is of 2 types - static and seamless.
5738  * Static DRRS involves changing refresh rate (RR) by doing a full modeset
5739  * (may appear as a blink on screen) and is used in dock-undock scenario.
5740  * Seamless DRRS involves changing RR without any visual effect to the user
5741  * and can be used during normal system usage. This is done by programming
5742  * certain registers.
5743  *
5744  * Support for static/seamless DRRS may be indicated in the VBT based on
5745  * inputs from the panel spec.
5746  *
5747  * DRRS saves power by switching to low RR based on usage scenarios.
5748  *
5749  * The implementation is based on frontbuffer tracking implementation.  When
5750  * there is a disturbance on the screen triggered by user activity or a periodic
5751  * system activity, DRRS is disabled (RR is changed to high RR).  When there is
5752  * no movement on screen, after a timeout of 1 second, a switch to low RR is
5753  * made.
5754  *
5755  * For integration with frontbuffer tracking code, intel_edp_drrs_invalidate()
5756  * and intel_edp_drrs_flush() are called.
5757  *
5758  * DRRS can be further extended to support other internal panels and also
5759  * the scenario of video playback wherein RR is set based on the rate
5760  * requested by userspace.
5761  */
5762
5763 /**
5764  * intel_dp_drrs_init - Init basic DRRS work and mutex.
5765  * @intel_connector: eDP connector
5766  * @fixed_mode: preferred mode of panel
5767  *
5768  * This function is  called only once at driver load to initialize basic
5769  * DRRS stuff.
5770  *
5771  * Returns:
5772  * Downclock mode if panel supports it, else return NULL.
5773  * DRRS support is determined by the presence of downclock mode (apart
5774  * from VBT setting).
5775  */
5776 static struct drm_display_mode *
5777 intel_dp_drrs_init(struct intel_connector *intel_connector,
5778                 struct drm_display_mode *fixed_mode)
5779 {
5780         struct drm_connector *connector = &intel_connector->base;
5781         struct drm_device *dev = connector->dev;
5782         struct drm_i915_private *dev_priv = to_i915(dev);
5783         struct drm_display_mode *downclock_mode = NULL;
5784
5785         INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work);
5786         mutex_init(&dev_priv->drrs.mutex);
5787
5788         if (INTEL_GEN(dev_priv) <= 6) {
5789                 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
5790                 return NULL;
5791         }
5792
5793         if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
5794                 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
5795                 return NULL;
5796         }
5797
5798         downclock_mode = intel_find_panel_downclock
5799                                         (dev_priv, fixed_mode, connector);
5800
5801         if (!downclock_mode) {
5802                 DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n");
5803                 return NULL;
5804         }
5805
5806         dev_priv->drrs.type = dev_priv->vbt.drrs_type;
5807
5808         dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR;
5809         DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
5810         return downclock_mode;
5811 }
5812
5813 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
5814                                      struct intel_connector *intel_connector)
5815 {
5816         struct drm_connector *connector = &intel_connector->base;
5817         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
5818         struct intel_encoder *intel_encoder = &intel_dig_port->base;
5819         struct drm_device *dev = intel_encoder->base.dev;
5820         struct drm_i915_private *dev_priv = to_i915(dev);
5821         struct drm_display_mode *fixed_mode = NULL;
5822         struct drm_display_mode *downclock_mode = NULL;
5823         bool has_dpcd;
5824         struct drm_display_mode *scan;
5825         struct edid *edid;
5826         enum pipe pipe = INVALID_PIPE;
5827
5828         if (!is_edp(intel_dp))
5829                 return true;
5830
5831         /*
5832          * On IBX/CPT we may get here with LVDS already registered. Since the
5833          * driver uses the only internal power sequencer available for both
5834          * eDP and LVDS bail out early in this case to prevent interfering
5835          * with an already powered-on LVDS power sequencer.
5836          */
5837         if (intel_get_lvds_encoder(dev)) {
5838                 WARN_ON(!(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)));
5839                 DRM_INFO("LVDS was detected, not registering eDP\n");
5840
5841                 return false;
5842         }
5843
5844         pps_lock(intel_dp);
5845
5846         intel_dp_init_panel_power_timestamps(intel_dp);
5847         intel_dp_pps_init(dev, intel_dp);
5848         intel_edp_panel_vdd_sanitize(intel_dp);
5849
5850         pps_unlock(intel_dp);
5851
5852         /* Cache DPCD and EDID for edp. */
5853         has_dpcd = intel_edp_init_dpcd(intel_dp);
5854
5855         if (!has_dpcd) {
5856                 /* if this fails, presume the device is a ghost */
5857                 DRM_INFO("failed to retrieve link info, disabling eDP\n");
5858                 goto out_vdd_off;
5859         }
5860
5861         mutex_lock(&dev->mode_config.mutex);
5862         edid = drm_get_edid(connector, &intel_dp->aux.ddc);
5863         if (edid) {
5864                 if (drm_add_edid_modes(connector, edid)) {
5865                         drm_mode_connector_update_edid_property(connector,
5866                                                                 edid);
5867                         drm_edid_to_eld(connector, edid);
5868                 } else {
5869                         kfree(edid);
5870                         edid = ERR_PTR(-EINVAL);
5871                 }
5872         } else {
5873                 edid = ERR_PTR(-ENOENT);
5874         }
5875         intel_connector->edid = edid;
5876
5877         /* prefer fixed mode from EDID if available */
5878         list_for_each_entry(scan, &connector->probed_modes, head) {
5879                 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
5880                         fixed_mode = drm_mode_duplicate(dev, scan);
5881                         downclock_mode = intel_dp_drrs_init(
5882                                                 intel_connector, fixed_mode);
5883                         break;
5884                 }
5885         }
5886
5887         /* fallback to VBT if available for eDP */
5888         if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
5889                 fixed_mode = drm_mode_duplicate(dev,
5890                                         dev_priv->vbt.lfp_lvds_vbt_mode);
5891                 if (fixed_mode) {
5892                         fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
5893                         connector->display_info.width_mm = fixed_mode->width_mm;
5894                         connector->display_info.height_mm = fixed_mode->height_mm;
5895                 }
5896         }
5897         mutex_unlock(&dev->mode_config.mutex);
5898
5899         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
5900                 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
5901                 register_reboot_notifier(&intel_dp->edp_notifier);
5902
5903                 /*
5904                  * Figure out the current pipe for the initial backlight setup.
5905                  * If the current pipe isn't valid, try the PPS pipe, and if that
5906                  * fails just assume pipe A.
5907                  */
5908                 pipe = vlv_active_pipe(intel_dp);
5909
5910                 if (pipe != PIPE_A && pipe != PIPE_B)
5911                         pipe = intel_dp->pps_pipe;
5912
5913                 if (pipe != PIPE_A && pipe != PIPE_B)
5914                         pipe = PIPE_A;
5915
5916                 DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n",
5917                               pipe_name(pipe));
5918         }
5919
5920         intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
5921         intel_connector->panel.backlight.power = intel_edp_backlight_power;
5922         intel_panel_setup_backlight(connector, pipe);
5923
5924         return true;
5925
5926 out_vdd_off:
5927         cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
5928         /*
5929          * vdd might still be enabled do to the delayed vdd off.
5930          * Make sure vdd is actually turned off here.
5931          */
5932         pps_lock(intel_dp);
5933         edp_panel_vdd_off_sync(intel_dp);
5934         pps_unlock(intel_dp);
5935
5936         return false;
5937 }
5938
5939 /* Set up the hotplug pin and aux power domain. */
5940 static void
5941 intel_dp_init_connector_port_info(struct intel_digital_port *intel_dig_port)
5942 {
5943         struct intel_encoder *encoder = &intel_dig_port->base;
5944         struct intel_dp *intel_dp = &intel_dig_port->dp;
5945
5946         switch (intel_dig_port->port) {
5947         case PORT_A:
5948                 encoder->hpd_pin = HPD_PORT_A;
5949                 intel_dp->aux_power_domain = POWER_DOMAIN_AUX_A;
5950                 break;
5951         case PORT_B:
5952                 encoder->hpd_pin = HPD_PORT_B;
5953                 intel_dp->aux_power_domain = POWER_DOMAIN_AUX_B;
5954                 break;
5955         case PORT_C:
5956                 encoder->hpd_pin = HPD_PORT_C;
5957                 intel_dp->aux_power_domain = POWER_DOMAIN_AUX_C;
5958                 break;
5959         case PORT_D:
5960                 encoder->hpd_pin = HPD_PORT_D;
5961                 intel_dp->aux_power_domain = POWER_DOMAIN_AUX_D;
5962                 break;
5963         case PORT_E:
5964                 encoder->hpd_pin = HPD_PORT_E;
5965
5966                 /* FIXME: Check VBT for actual wiring of PORT E */
5967                 intel_dp->aux_power_domain = POWER_DOMAIN_AUX_D;
5968                 break;
5969         default:
5970                 MISSING_CASE(intel_dig_port->port);
5971         }
5972 }
5973
5974 static void intel_dp_modeset_retry_work_fn(struct work_struct *work)
5975 {
5976         struct intel_connector *intel_connector;
5977         struct drm_connector *connector;
5978
5979         intel_connector = container_of(work, typeof(*intel_connector),
5980                                        modeset_retry_work);
5981         connector = &intel_connector->base;
5982         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", connector->base.id,
5983                       connector->name);
5984
5985         /* Grab the locks before changing connector property*/
5986         mutex_lock(&connector->dev->mode_config.mutex);
5987         /* Set connector link status to BAD and send a Uevent to notify
5988          * userspace to do a modeset.
5989          */
5990         drm_mode_connector_set_link_status_property(connector,
5991                                                     DRM_MODE_LINK_STATUS_BAD);
5992         mutex_unlock(&connector->dev->mode_config.mutex);
5993         /* Send Hotplug uevent so userspace can reprobe */
5994         drm_kms_helper_hotplug_event(connector->dev);
5995 }
5996
5997 bool
5998 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
5999                         struct intel_connector *intel_connector)
6000 {
6001         struct drm_connector *connector = &intel_connector->base;
6002         struct intel_dp *intel_dp = &intel_dig_port->dp;
6003         struct intel_encoder *intel_encoder = &intel_dig_port->base;
6004         struct drm_device *dev = intel_encoder->base.dev;
6005         struct drm_i915_private *dev_priv = to_i915(dev);
6006         enum port port = intel_dig_port->port;
6007         int type;
6008
6009         /* Initialize the work for modeset in case of link train failure */
6010         INIT_WORK(&intel_connector->modeset_retry_work,
6011                   intel_dp_modeset_retry_work_fn);
6012
6013         if (WARN(intel_dig_port->max_lanes < 1,
6014                  "Not enough lanes (%d) for DP on port %c\n",
6015                  intel_dig_port->max_lanes, port_name(port)))
6016                 return false;
6017
6018         intel_dp_set_source_rates(intel_dp);
6019
6020         intel_dp->reset_link_params = true;
6021         intel_dp->pps_pipe = INVALID_PIPE;
6022         intel_dp->active_pipe = INVALID_PIPE;
6023
6024         /* intel_dp vfuncs */
6025         if (INTEL_GEN(dev_priv) >= 9)
6026                 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
6027         else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
6028                 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
6029         else if (HAS_PCH_SPLIT(dev_priv))
6030                 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
6031         else
6032                 intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider;
6033
6034         if (INTEL_GEN(dev_priv) >= 9)
6035                 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
6036         else
6037                 intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl;
6038
6039         if (HAS_DDI(dev_priv))
6040                 intel_dp->prepare_link_retrain = intel_ddi_prepare_link_retrain;
6041
6042         /* Preserve the current hw state. */
6043         intel_dp->DP = I915_READ(intel_dp->output_reg);
6044         intel_dp->attached_connector = intel_connector;
6045
6046         if (intel_dp_is_edp(dev_priv, port))
6047                 type = DRM_MODE_CONNECTOR_eDP;
6048         else
6049                 type = DRM_MODE_CONNECTOR_DisplayPort;
6050
6051         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
6052                 intel_dp->active_pipe = vlv_active_pipe(intel_dp);
6053
6054         /*
6055          * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
6056          * for DP the encoder type can be set by the caller to
6057          * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
6058          */
6059         if (type == DRM_MODE_CONNECTOR_eDP)
6060                 intel_encoder->type = INTEL_OUTPUT_EDP;
6061
6062         /* eDP only on port B and/or C on vlv/chv */
6063         if (WARN_ON((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
6064                     is_edp(intel_dp) && port != PORT_B && port != PORT_C))
6065                 return false;
6066
6067         DRM_DEBUG_KMS("Adding %s connector on port %c\n",
6068                         type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
6069                         port_name(port));
6070
6071         drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
6072         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
6073
6074         connector->interlace_allowed = true;
6075         connector->doublescan_allowed = 0;
6076
6077         intel_dp_init_connector_port_info(intel_dig_port);
6078
6079         intel_dp_aux_init(intel_dp);
6080
6081         INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
6082                           edp_panel_vdd_work);
6083
6084         intel_connector_attach_encoder(intel_connector, intel_encoder);
6085
6086         if (HAS_DDI(dev_priv))
6087                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
6088         else
6089                 intel_connector->get_hw_state = intel_connector_get_hw_state;
6090
6091         /* init MST on ports that can support it */
6092         if (HAS_DP_MST(dev_priv) && !is_edp(intel_dp) &&
6093             (port == PORT_B || port == PORT_C || port == PORT_D))
6094                 intel_dp_mst_encoder_init(intel_dig_port,
6095                                           intel_connector->base.base.id);
6096
6097         if (!intel_edp_init_connector(intel_dp, intel_connector)) {
6098                 intel_dp_aux_fini(intel_dp);
6099                 intel_dp_mst_encoder_cleanup(intel_dig_port);
6100                 goto fail;
6101         }
6102
6103         intel_dp_add_properties(intel_dp, connector);
6104
6105         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
6106          * 0xd.  Failure to do so will result in spurious interrupts being
6107          * generated on the port when a cable is not attached.
6108          */
6109         if (IS_G4X(dev_priv) && !IS_GM45(dev_priv)) {
6110                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
6111                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
6112         }
6113
6114         return true;
6115
6116 fail:
6117         drm_connector_cleanup(connector);
6118
6119         return false;
6120 }
6121
6122 bool intel_dp_init(struct drm_i915_private *dev_priv,
6123                    i915_reg_t output_reg,
6124                    enum port port)
6125 {
6126         struct intel_digital_port *intel_dig_port;
6127         struct intel_encoder *intel_encoder;
6128         struct drm_encoder *encoder;
6129         struct intel_connector *intel_connector;
6130
6131         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
6132         if (!intel_dig_port)
6133                 return false;
6134
6135         intel_connector = intel_connector_alloc();
6136         if (!intel_connector)
6137                 goto err_connector_alloc;
6138
6139         intel_encoder = &intel_dig_port->base;
6140         encoder = &intel_encoder->base;
6141
6142         if (drm_encoder_init(&dev_priv->drm, &intel_encoder->base,
6143                              &intel_dp_enc_funcs, DRM_MODE_ENCODER_TMDS,
6144                              "DP %c", port_name(port)))
6145                 goto err_encoder_init;
6146
6147         intel_encoder->compute_config = intel_dp_compute_config;
6148         intel_encoder->disable = intel_disable_dp;
6149         intel_encoder->get_hw_state = intel_dp_get_hw_state;
6150         intel_encoder->get_config = intel_dp_get_config;
6151         intel_encoder->suspend = intel_dp_encoder_suspend;
6152         if (IS_CHERRYVIEW(dev_priv)) {
6153                 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
6154                 intel_encoder->pre_enable = chv_pre_enable_dp;
6155                 intel_encoder->enable = vlv_enable_dp;
6156                 intel_encoder->post_disable = chv_post_disable_dp;
6157                 intel_encoder->post_pll_disable = chv_dp_post_pll_disable;
6158         } else if (IS_VALLEYVIEW(dev_priv)) {
6159                 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
6160                 intel_encoder->pre_enable = vlv_pre_enable_dp;
6161                 intel_encoder->enable = vlv_enable_dp;
6162                 intel_encoder->post_disable = vlv_post_disable_dp;
6163         } else {
6164                 intel_encoder->pre_enable = g4x_pre_enable_dp;
6165                 intel_encoder->enable = g4x_enable_dp;
6166                 if (INTEL_GEN(dev_priv) >= 5)
6167                         intel_encoder->post_disable = ilk_post_disable_dp;
6168         }
6169
6170         intel_dig_port->port = port;
6171         intel_dig_port->dp.output_reg = output_reg;
6172         intel_dig_port->max_lanes = 4;
6173
6174         intel_encoder->type = INTEL_OUTPUT_DP;
6175         intel_encoder->power_domain = intel_port_to_power_domain(port);
6176         if (IS_CHERRYVIEW(dev_priv)) {
6177                 if (port == PORT_D)
6178                         intel_encoder->crtc_mask = 1 << 2;
6179                 else
6180                         intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
6181         } else {
6182                 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
6183         }
6184         intel_encoder->cloneable = 0;
6185         intel_encoder->port = port;
6186
6187         intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
6188         dev_priv->hotplug.irq_port[port] = intel_dig_port;
6189
6190         if (!intel_dp_init_connector(intel_dig_port, intel_connector))
6191                 goto err_init_connector;
6192
6193         return true;
6194
6195 err_init_connector:
6196         drm_encoder_cleanup(encoder);
6197 err_encoder_init:
6198         kfree(intel_connector);
6199 err_connector_alloc:
6200         kfree(intel_dig_port);
6201         return false;
6202 }
6203
6204 void intel_dp_mst_suspend(struct drm_device *dev)
6205 {
6206         struct drm_i915_private *dev_priv = to_i915(dev);
6207         int i;
6208
6209         /* disable MST */
6210         for (i = 0; i < I915_MAX_PORTS; i++) {
6211                 struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i];
6212
6213                 if (!intel_dig_port || !intel_dig_port->dp.can_mst)
6214                         continue;
6215
6216                 if (intel_dig_port->dp.is_mst)
6217                         drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr);
6218         }
6219 }
6220
6221 void intel_dp_mst_resume(struct drm_device *dev)
6222 {
6223         struct drm_i915_private *dev_priv = to_i915(dev);
6224         int i;
6225
6226         for (i = 0; i < I915_MAX_PORTS; i++) {
6227                 struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i];
6228                 int ret;
6229
6230                 if (!intel_dig_port || !intel_dig_port->dp.can_mst)
6231                         continue;
6232
6233                 ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr);
6234                 if (ret)
6235                         intel_dp_check_mst_status(&intel_dig_port->dp);
6236         }
6237 }