drivers/gpu/drm/amd/amdgpu/amdgpu_object.c

   1 /*
   2  * Copyright 2009 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26 /*
  27  * Authors:
  28  *    Jerome Glisse <[email protected]>
  29  *    Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
  30  *    Dave Airlie
  31  */
  32 #include <linux/list.h>
  33 #include <linux/slab.h>
  34 #include <drm/drmP.h>
  35 #include <drm/amdgpu_drm.h>
  36 #include <drm/drm_cache.h>
  37 #include "amdgpu.h"
  38 #include "amdgpu_trace.h"
  39
  40 static void amdgpu_ttm_bo_destroy(struct ttm_buffer_object *tbo)
  41 {
  42         struct amdgpu_device *adev = amdgpu_ttm_adev(tbo->bdev);
  43         struct amdgpu_bo *bo = ttm_to_amdgpu_bo(tbo);
  44
  45         amdgpu_bo_kunmap(bo);
  46
  47         drm_gem_object_release(&bo->gem_base);
  48         amdgpu_bo_unref(&bo->parent);
  49         if (!list_empty(&bo->shadow_list)) {
  50                 mutex_lock(&adev->shadow_list_lock);
  51                 list_del_init(&bo->shadow_list);
  52                 mutex_unlock(&adev->shadow_list_lock);
  53         }
  54         kfree(bo->metadata);
  55         kfree(bo);
  56 }
  57
  58 bool amdgpu_ttm_bo_is_amdgpu_bo(struct ttm_buffer_object *bo)
  59 {
  60         if (bo->destroy == &amdgpu_ttm_bo_destroy)
  61                 return true;
  62         return false;
  63 }
  64
  65 void amdgpu_ttm_placement_from_domain(struct amdgpu_bo *abo, u32 domain)
  66 {
  67         struct amdgpu_device *adev = amdgpu_ttm_adev(abo->tbo.bdev);
  68         struct ttm_placement *placement = &abo->placement;
  69         struct ttm_place *places = abo->placements;
  70         u64 flags = abo->flags;
  71         u32 c = 0;
  72
  73         if (domain & AMDGPU_GEM_DOMAIN_VRAM) {
  74                 unsigned visible_pfn = adev->mc.visible_vram_size >> PAGE_SHIFT;
  75
  76                 places[c].fpfn = 0;
  77                 places[c].lpfn = 0;
  78                 places[c].flags = TTM_PL_FLAG_WC | TTM_PL_FLAG_UNCACHED |
  79                         TTM_PL_FLAG_VRAM;
  80
  81                 if (flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED)
  82                         places[c].lpfn = visible_pfn;
  83                 else
  84                         places[c].flags |= TTM_PL_FLAG_TOPDOWN;
  85
  86                 if (flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)
  87                         places[c].flags |= TTM_PL_FLAG_CONTIGUOUS;
  88                 c++;
  89         }
  90
  91         if (domain & AMDGPU_GEM_DOMAIN_GTT) {
  92                 places[c].fpfn = 0;
  93                 if (flags & AMDGPU_GEM_CREATE_SHADOW)
  94                         places[c].lpfn = adev->mc.gart_size >> PAGE_SHIFT;
  95                 else
  96                         places[c].lpfn = 0;
  97                 places[c].flags = TTM_PL_FLAG_TT;
  98                 if (flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC)
  99                         places[c].flags |= TTM_PL_FLAG_WC |
 100                                 TTM_PL_FLAG_UNCACHED;
 101                 else
 102                         places[c].flags |= TTM_PL_FLAG_CACHED;
 103                 c++;
 104         }
 105
 106         if (domain & AMDGPU_GEM_DOMAIN_CPU) {
 107                 places[c].fpfn = 0;
 108                 places[c].lpfn = 0;
 109                 places[c].flags = TTM_PL_FLAG_SYSTEM;
 110                 if (flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC)
 111                         places[c].flags |= TTM_PL_FLAG_WC |
 112                                 TTM_PL_FLAG_UNCACHED;
 113                 else
 114                         places[c].flags |= TTM_PL_FLAG_CACHED;
 115                 c++;
 116         }
 117
 118         if (domain & AMDGPU_GEM_DOMAIN_GDS) {
 119                 places[c].fpfn = 0;
 120                 places[c].lpfn = 0;
 121                 places[c].flags = TTM_PL_FLAG_UNCACHED | AMDGPU_PL_FLAG_GDS;
 122                 c++;
 123         }
 124
 125         if (domain & AMDGPU_GEM_DOMAIN_GWS) {
 126                 places[c].fpfn = 0;
 127                 places[c].lpfn = 0;
 128                 places[c].flags = TTM_PL_FLAG_UNCACHED | AMDGPU_PL_FLAG_GWS;
 129                 c++;
 130         }
 131
 132         if (domain & AMDGPU_GEM_DOMAIN_OA) {
 133                 places[c].fpfn = 0;
 134                 places[c].lpfn = 0;
 135                 places[c].flags = TTM_PL_FLAG_UNCACHED | AMDGPU_PL_FLAG_OA;
 136                 c++;
 137         }
 138
 139         if (!c) {
 140                 places[c].fpfn = 0;
 141                 places[c].lpfn = 0;
 142                 places[c].flags = TTM_PL_MASK_CACHING | TTM_PL_FLAG_SYSTEM;
 143                 c++;
 144         }
 145
 146         placement->num_placement = c;
 147         placement->placement = places;
 148
 149         placement->num_busy_placement = c;
 150         placement->busy_placement = places;
 151 }
 152
 153 /**
 154  * amdgpu_bo_create_reserved - create reserved BO for kernel use
 155  *
 156  * @adev: amdgpu device object
 157  * @size: size for the new BO
 158  * @align: alignment for the new BO
 159  * @domain: where to place it
 160  * @bo_ptr: resulting BO
 161  * @gpu_addr: GPU addr of the pinned BO
 162  * @cpu_addr: optional CPU address mapping
 163  *
 164  * Allocates and pins a BO for kernel internal use, and returns it still
 165  * reserved.
 166  *
 167  * Returns 0 on success, negative error code otherwise.
 168  */
 169 int amdgpu_bo_create_reserved(struct amdgpu_device *adev,
 170                               unsigned long size, int align,
 171                               u32 domain, struct amdgpu_bo **bo_ptr,
 172                               u64 *gpu_addr, void **cpu_addr)
 173 {
 174         bool free = false;
 175         int r;
 176
 177         if (!*bo_ptr) {
 178                 r = amdgpu_bo_create(adev, size, align, true, domain,
 179                                      AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED |
 180                                      AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS,
 181                                      NULL, NULL, 0, bo_ptr);
 182                 if (r) {
 183                         dev_err(adev->dev, "(%d) failed to allocate kernel bo\n",
 184                                 r);
 185                         return r;
 186                 }
 187                 free = true;
 188         }
 189
 190         r = amdgpu_bo_reserve(*bo_ptr, false);
 191         if (r) {
 192                 dev_err(adev->dev, "(%d) failed to reserve kernel bo\n", r);
 193                 goto error_free;
 194         }
 195
 196         r = amdgpu_bo_pin(*bo_ptr, domain, gpu_addr);
 197         if (r) {
 198                 dev_err(adev->dev, "(%d) kernel bo pin failed\n", r);
 199                 goto error_unreserve;
 200         }
 201
 202         if (cpu_addr) {
 203                 r = amdgpu_bo_kmap(*bo_ptr, cpu_addr);
 204                 if (r) {
 205                         dev_err(adev->dev, "(%d) kernel bo map failed\n", r);
 206                         goto error_unreserve;
 207                 }
 208         }
 209
 210         return 0;
 211
 212 error_unreserve:
 213         amdgpu_bo_unreserve(*bo_ptr);
 214
 215 error_free:
 216         if (free)
 217                 amdgpu_bo_unref(bo_ptr);
 218
 219         return r;
 220 }
 221
 222 /**
 223  * amdgpu_bo_create_kernel - create BO for kernel use
 224  *
 225  * @adev: amdgpu device object
 226  * @size: size for the new BO
 227  * @align: alignment for the new BO
 228  * @domain: where to place it
 229  * @bo_ptr: resulting BO
 230  * @gpu_addr: GPU addr of the pinned BO
 231  * @cpu_addr: optional CPU address mapping
 232  *
 233  * Allocates and pins a BO for kernel internal use.
 234  *
 235  * Returns 0 on success, negative error code otherwise.
 236  */
 237 int amdgpu_bo_create_kernel(struct amdgpu_device *adev,
 238                             unsigned long size, int align,
 239                             u32 domain, struct amdgpu_bo **bo_ptr,
 240                             u64 *gpu_addr, void **cpu_addr)
 241 {
 242         int r;
 243
 244         r = amdgpu_bo_create_reserved(adev, size, align, domain, bo_ptr,
 245                                       gpu_addr, cpu_addr);
 246
 247         if (r)
 248                 return r;
 249
 250         amdgpu_bo_unreserve(*bo_ptr);
 251
 252         return 0;
 253 }
 254
 255 /**
 256  * amdgpu_bo_free_kernel - free BO for kernel use
 257  *
 258  * @bo: amdgpu BO to free
 259  *
 260  * unmaps and unpin a BO for kernel internal use.
 261  */
 262 void amdgpu_bo_free_kernel(struct amdgpu_bo **bo, u64 *gpu_addr,
 263                            void **cpu_addr)
 264 {
 265         if (*bo == NULL)
 266                 return;
 267
 268         if (likely(amdgpu_bo_reserve(*bo, true) == 0)) {
 269                 if (cpu_addr)
 270                         amdgpu_bo_kunmap(*bo);
 271
 272                 amdgpu_bo_unpin(*bo);
 273                 amdgpu_bo_unreserve(*bo);
 274         }
 275         amdgpu_bo_unref(bo);
 276
 277         if (gpu_addr)
 278                 *gpu_addr = 0;
 279
 280         if (cpu_addr)
 281                 *cpu_addr = NULL;
 282 }
 283
 284 /* Validate bo size is bit bigger then the request domain */
 285 static bool amdgpu_bo_validate_size(struct amdgpu_device *adev,
 286                                           unsigned long size, u32 domain)
 287 {
 288         struct ttm_mem_type_manager *man = NULL;
 289
 290         /*
 291          * If GTT is part of requested domains the check must succeed to
 292          * allow fall back to GTT
 293          */
 294         if (domain & AMDGPU_GEM_DOMAIN_GTT) {
 295                 man = &adev->mman.bdev.man[TTM_PL_TT];
 296
 297                 if (size < (man->size << PAGE_SHIFT))
 298                         return true;
 299                 else
 300                         goto fail;
 301         }
 302
 303         if (domain & AMDGPU_GEM_DOMAIN_VRAM) {
 304                 man = &adev->mman.bdev.man[TTM_PL_VRAM];
 305
 306                 if (size < (man->size << PAGE_SHIFT))
 307                         return true;
 308                 else
 309                         goto fail;
 310         }
 311
 312
 313         /* TODO add more domains checks, such as AMDGPU_GEM_DOMAIN_CPU */
 314         return true;
 315
 316 fail:
 317         DRM_DEBUG("BO size %lu > total memory in domain: %llu\n", size,
 318                   man->size << PAGE_SHIFT);
 319         return false;
 320 }
 321
 322 static int amdgpu_bo_do_create(struct amdgpu_device *adev,
 323                                unsigned long size, int byte_align,
 324                                bool kernel, u32 domain, u64 flags,
 325                                struct sg_table *sg,
 326                                struct reservation_object *resv,
 327                                uint64_t init_value,
 328                                struct amdgpu_bo **bo_ptr)
 329 {
 330         struct ttm_operation_ctx ctx = {
 331                 .interruptible = !kernel,
 332                 .no_wait_gpu = false,
 333                 .allow_reserved_eviction = true,
 334                 .resv = resv
 335         };
 336         struct amdgpu_bo *bo;
 337         enum ttm_bo_type type;
 338         unsigned long page_align;
 339         size_t acc_size;
 340         int r;
 341
 342         page_align = roundup(byte_align, PAGE_SIZE) >> PAGE_SHIFT;
 343         size = ALIGN(size, PAGE_SIZE);
 344
 345         if (!amdgpu_bo_validate_size(adev, size, domain))
 346                 return -ENOMEM;
 347
 348         if (kernel) {
 349                 type = ttm_bo_type_kernel;
 350         } else if (sg) {
 351                 type = ttm_bo_type_sg;
 352         } else {
 353                 type = ttm_bo_type_device;
 354         }
 355         *bo_ptr = NULL;
 356
 357         acc_size = ttm_bo_dma_acc_size(&adev->mman.bdev, size,
 358                                        sizeof(struct amdgpu_bo));
 359
 360         bo = kzalloc(sizeof(struct amdgpu_bo), GFP_KERNEL);
 361         if (bo == NULL)
 362                 return -ENOMEM;
 363         r = drm_gem_object_init(adev->ddev, &bo->gem_base, size);
 364         if (unlikely(r)) {
 365                 kfree(bo);
 366                 return r;
 367         }
 368         INIT_LIST_HEAD(&bo->shadow_list);
 369         INIT_LIST_HEAD(&bo->va);
 370         bo->preferred_domains = domain & (AMDGPU_GEM_DOMAIN_VRAM |
 371                                          AMDGPU_GEM_DOMAIN_GTT |
 372                                          AMDGPU_GEM_DOMAIN_CPU |
 373                                          AMDGPU_GEM_DOMAIN_GDS |
 374                                          AMDGPU_GEM_DOMAIN_GWS |
 375                                          AMDGPU_GEM_DOMAIN_OA);
 376         bo->allowed_domains = bo->preferred_domains;
 377         if (!kernel && bo->allowed_domains == AMDGPU_GEM_DOMAIN_VRAM)
 378                 bo->allowed_domains |= AMDGPU_GEM_DOMAIN_GTT;
 379
 380         bo->flags = flags;
 381
 382 #ifdef CONFIG_X86_32
 383         /* XXX: Write-combined CPU mappings of GTT seem broken on 32-bit
 384          * See https://bugs.freedesktop.org/show_bug.cgi?id=84627
 385          */
 386         bo->flags &= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC;
 387 #elif defined(CONFIG_X86) && !defined(CONFIG_X86_PAT)
 388         /* Don't try to enable write-combining when it can't work, or things
 389          * may be slow
 390          * See https://bugs.freedesktop.org/show_bug.cgi?id=88758
 391          */
 392
 393 #ifndef CONFIG_COMPILE_TEST
 394 #warning Please enable CONFIG_MTRR and CONFIG_X86_PAT for better performance \
 395          thanks to write-combining
 396 #endif
 397
 398         if (bo->flags & AMDGPU_GEM_CREATE_CPU_GTT_USWC)
 399                 DRM_INFO_ONCE("Please enable CONFIG_MTRR and CONFIG_X86_PAT for "
 400                               "better performance thanks to write-combining\n");
 401         bo->flags &= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC;
 402 #else
 403         /* For architectures that don't support WC memory,
 404          * mask out the WC flag from the BO
 405          */
 406         if (!drm_arch_can_wc_memory())
 407                 bo->flags &= ~AMDGPU_GEM_CREATE_CPU_GTT_USWC;
 408 #endif
 409
 410         bo->tbo.bdev = &adev->mman.bdev;
 411         amdgpu_ttm_placement_from_domain(bo, domain);
 412
 413         r = ttm_bo_init_reserved(&adev->mman.bdev, &bo->tbo, size, type,
 414                                  &bo->placement, page_align, &ctx, NULL,
 415                                  acc_size, sg, resv, &amdgpu_ttm_bo_destroy);
 416         if (unlikely(r != 0))
 417                 return r;
 418
 419         if (adev->mc.visible_vram_size < adev->mc.real_vram_size &&
 420             bo->tbo.mem.mem_type == TTM_PL_VRAM &&
 421             bo->tbo.mem.start < adev->mc.visible_vram_size >> PAGE_SHIFT)
 422                 amdgpu_cs_report_moved_bytes(adev, ctx.bytes_moved,
 423                                              ctx.bytes_moved);
 424         else
 425                 amdgpu_cs_report_moved_bytes(adev, ctx.bytes_moved, 0);
 426
 427         if (kernel)
 428                 bo->tbo.priority = 1;
 429
 430         if (flags & AMDGPU_GEM_CREATE_VRAM_CLEARED &&
 431             bo->tbo.mem.placement & TTM_PL_FLAG_VRAM) {
 432                 struct dma_fence *fence;
 433
 434                 r = amdgpu_fill_buffer(bo, init_value, bo->tbo.resv, &fence);
 435                 if (unlikely(r))
 436                         goto fail_unreserve;
 437
 438                 amdgpu_bo_fence(bo, fence, false);
 439                 dma_fence_put(bo->tbo.moving);
 440                 bo->tbo.moving = dma_fence_get(fence);
 441                 dma_fence_put(fence);
 442         }
 443         if (!resv)
 444                 amdgpu_bo_unreserve(bo);
 445         *bo_ptr = bo;
 446
 447         trace_amdgpu_bo_create(bo);
 448
 449         /* Treat CPU_ACCESS_REQUIRED only as a hint if given by UMD */
 450         if (type == ttm_bo_type_device)
 451                 bo->flags &= ~AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
 452
 453         return 0;
 454
 455 fail_unreserve:
 456         if (!resv)
 457                 ww_mutex_unlock(&bo->tbo.resv->lock);
 458         amdgpu_bo_unref(&bo);
 459         return r;
 460 }
 461
 462 static int amdgpu_bo_create_shadow(struct amdgpu_device *adev,
 463                                    unsigned long size, int byte_align,
 464                                    struct amdgpu_bo *bo)
 465 {
 466         int r;
 467
 468         if (bo->shadow)
 469                 return 0;
 470
 471         r = amdgpu_bo_do_create(adev, size, byte_align, true,
 472                                 AMDGPU_GEM_DOMAIN_GTT,
 473                                 AMDGPU_GEM_CREATE_CPU_GTT_USWC |
 474                                 AMDGPU_GEM_CREATE_SHADOW,
 475                                 NULL, bo->tbo.resv, 0,
 476                                 &bo->shadow);
 477         if (!r) {
 478                 bo->shadow->parent = amdgpu_bo_ref(bo);
 479                 mutex_lock(&adev->shadow_list_lock);
 480                 list_add_tail(&bo->shadow_list, &adev->shadow_list);
 481                 mutex_unlock(&adev->shadow_list_lock);
 482         }
 483
 484         return r;
 485 }
 486
 487 /* init_value will only take effect when flags contains
 488  * AMDGPU_GEM_CREATE_VRAM_CLEARED.
 489  */
 490 int amdgpu_bo_create(struct amdgpu_device *adev,
 491                      unsigned long size, int byte_align,
 492                      bool kernel, u32 domain, u64 flags,
 493                      struct sg_table *sg,
 494                      struct reservation_object *resv,
 495                      uint64_t init_value,
 496                      struct amdgpu_bo **bo_ptr)
 497 {
 498         uint64_t parent_flags = flags & ~AMDGPU_GEM_CREATE_SHADOW;
 499         int r;
 500
 501         r = amdgpu_bo_do_create(adev, size, byte_align, kernel, domain,
 502                                 parent_flags, sg, resv, init_value, bo_ptr);
 503         if (r)
 504                 return r;
 505
 506         if ((flags & AMDGPU_GEM_CREATE_SHADOW) && amdgpu_need_backup(adev)) {
 507                 if (!resv)
 508                         WARN_ON(reservation_object_lock((*bo_ptr)->tbo.resv,
 509                                                         NULL));
 510
 511                 r = amdgpu_bo_create_shadow(adev, size, byte_align, (*bo_ptr));
 512
 513                 if (!resv)
 514                         reservation_object_unlock((*bo_ptr)->tbo.resv);
 515
 516                 if (r)
 517                         amdgpu_bo_unref(bo_ptr);
 518         }
 519
 520         return r;
 521 }
 522
 523 int amdgpu_bo_backup_to_shadow(struct amdgpu_device *adev,
 524                                struct amdgpu_ring *ring,
 525                                struct amdgpu_bo *bo,
 526                                struct reservation_object *resv,
 527                                struct dma_fence **fence,
 528                                bool direct)
 529
 530 {
 531         struct amdgpu_bo *shadow = bo->shadow;
 532         uint64_t bo_addr, shadow_addr;
 533         int r;
 534
 535         if (!shadow)
 536                 return -EINVAL;
 537
 538         bo_addr = amdgpu_bo_gpu_offset(bo);
 539         shadow_addr = amdgpu_bo_gpu_offset(bo->shadow);
 540
 541         r = reservation_object_reserve_shared(bo->tbo.resv);
 542         if (r)
 543                 goto err;
 544
 545         r = amdgpu_copy_buffer(ring, bo_addr, shadow_addr,
 546                                amdgpu_bo_size(bo), resv, fence,
 547                                direct, false);
 548         if (!r)
 549                 amdgpu_bo_fence(bo, *fence, true);
 550
 551 err:
 552         return r;
 553 }
 554
 555 int amdgpu_bo_validate(struct amdgpu_bo *bo)
 556 {
 557         struct ttm_operation_ctx ctx = { false, false };
 558         uint32_t domain;
 559         int r;
 560
 561         if (bo->pin_count)
 562                 return 0;
 563
 564         domain = bo->preferred_domains;
 565
 566 retry:
 567         amdgpu_ttm_placement_from_domain(bo, domain);
 568         r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
 569         if (unlikely(r == -ENOMEM) && domain != bo->allowed_domains) {
 570                 domain = bo->allowed_domains;
 571                 goto retry;
 572         }
 573
 574         return r;
 575 }
 576
 577 int amdgpu_bo_restore_from_shadow(struct amdgpu_device *adev,
 578                                   struct amdgpu_ring *ring,
 579                                   struct amdgpu_bo *bo,
 580                                   struct reservation_object *resv,
 581                                   struct dma_fence **fence,
 582                                   bool direct)
 583
 584 {
 585         struct amdgpu_bo *shadow = bo->shadow;
 586         uint64_t bo_addr, shadow_addr;
 587         int r;
 588
 589         if (!shadow)
 590                 return -EINVAL;
 591
 592         bo_addr = amdgpu_bo_gpu_offset(bo);
 593         shadow_addr = amdgpu_bo_gpu_offset(bo->shadow);
 594
 595         r = reservation_object_reserve_shared(bo->tbo.resv);
 596         if (r)
 597                 goto err;
 598
 599         r = amdgpu_copy_buffer(ring, shadow_addr, bo_addr,
 600                                amdgpu_bo_size(bo), resv, fence,
 601                                direct, false);
 602         if (!r)
 603                 amdgpu_bo_fence(bo, *fence, true);
 604
 605 err:
 606         return r;
 607 }
 608
 609 int amdgpu_bo_kmap(struct amdgpu_bo *bo, void **ptr)
 610 {
 611         void *kptr;
 612         long r;
 613
 614         if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)
 615                 return -EPERM;
 616
 617         kptr = amdgpu_bo_kptr(bo);
 618         if (kptr) {
 619                 if (ptr)
 620                         *ptr = kptr;
 621                 return 0;
 622         }
 623
 624         r = reservation_object_wait_timeout_rcu(bo->tbo.resv, false, false,
 625                                                 MAX_SCHEDULE_TIMEOUT);
 626         if (r < 0)
 627                 return r;
 628
 629         r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap);
 630         if (r)
 631                 return r;
 632
 633         if (ptr)
 634                 *ptr = amdgpu_bo_kptr(bo);
 635
 636         return 0;
 637 }
 638
 639 void *amdgpu_bo_kptr(struct amdgpu_bo *bo)
 640 {
 641         bool is_iomem;
 642
 643         return ttm_kmap_obj_virtual(&bo->kmap, &is_iomem);
 644 }
 645
 646 void amdgpu_bo_kunmap(struct amdgpu_bo *bo)
 647 {
 648         if (bo->kmap.bo)
 649                 ttm_bo_kunmap(&bo->kmap);
 650 }
 651
 652 struct amdgpu_bo *amdgpu_bo_ref(struct amdgpu_bo *bo)
 653 {
 654         if (bo == NULL)
 655                 return NULL;
 656
 657         ttm_bo_reference(&bo->tbo);
 658         return bo;
 659 }
 660
 661 void amdgpu_bo_unref(struct amdgpu_bo **bo)
 662 {
 663         struct ttm_buffer_object *tbo;
 664
 665         if ((*bo) == NULL)
 666                 return;
 667
 668         tbo = &((*bo)->tbo);
 669         ttm_bo_unref(&tbo);
 670         if (tbo == NULL)
 671                 *bo = NULL;
 672 }
 673
 674 int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain,
 675                              u64 min_offset, u64 max_offset,
 676                              u64 *gpu_addr)
 677 {
 678         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
 679         struct ttm_operation_ctx ctx = { false, false };
 680         int r, i;
 681
 682         if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm))
 683                 return -EPERM;
 684
 685         if (WARN_ON_ONCE(min_offset > max_offset))
 686                 return -EINVAL;
 687
 688         /* A shared bo cannot be migrated to VRAM */
 689         if (bo->prime_shared_count && (domain == AMDGPU_GEM_DOMAIN_VRAM))
 690                 return -EINVAL;
 691
 692         if (bo->pin_count) {
 693                 uint32_t mem_type = bo->tbo.mem.mem_type;
 694
 695                 if (!(domain & amdgpu_mem_type_to_domain(mem_type)))
 696                         return -EINVAL;
 697
 698                 bo->pin_count++;
 699                 if (gpu_addr)
 700                         *gpu_addr = amdgpu_bo_gpu_offset(bo);
 701
 702                 if (max_offset != 0) {
 703                         u64 domain_start = bo->tbo.bdev->man[mem_type].gpu_offset;
 704                         WARN_ON_ONCE(max_offset <
 705                                      (amdgpu_bo_gpu_offset(bo) - domain_start));
 706                 }
 707
 708                 return 0;
 709         }
 710
 711         bo->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
 712         /* force to pin into visible video ram */
 713         if (!(bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS))
 714                 bo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
 715         amdgpu_ttm_placement_from_domain(bo, domain);
 716         for (i = 0; i < bo->placement.num_placement; i++) {
 717                 unsigned fpfn, lpfn;
 718
 719                 fpfn = min_offset >> PAGE_SHIFT;
 720                 lpfn = max_offset >> PAGE_SHIFT;
 721
 722                 if (fpfn > bo->placements[i].fpfn)
 723                         bo->placements[i].fpfn = fpfn;
 724                 if (!bo->placements[i].lpfn ||
 725                     (lpfn && lpfn < bo->placements[i].lpfn))
 726                         bo->placements[i].lpfn = lpfn;
 727                 bo->placements[i].flags |= TTM_PL_FLAG_NO_EVICT;
 728         }
 729
 730         r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
 731         if (unlikely(r)) {
 732                 dev_err(adev->dev, "%p pin failed\n", bo);
 733                 goto error;
 734         }
 735
 736         r = amdgpu_ttm_alloc_gart(&bo->tbo);
 737         if (unlikely(r)) {
 738                 dev_err(adev->dev, "%p bind failed\n", bo);
 739                 goto error;
 740         }
 741
 742         bo->pin_count = 1;
 743         if (gpu_addr != NULL)
 744                 *gpu_addr = amdgpu_bo_gpu_offset(bo);
 745
 746         domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type);
 747         if (domain == AMDGPU_GEM_DOMAIN_VRAM) {
 748                 adev->vram_pin_size += amdgpu_bo_size(bo);
 749                 if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)
 750                         adev->invisible_pin_size += amdgpu_bo_size(bo);
 751         } else if (domain == AMDGPU_GEM_DOMAIN_GTT) {
 752                 adev->gart_pin_size += amdgpu_bo_size(bo);
 753         }
 754
 755 error:
 756         return r;
 757 }
 758
 759 int amdgpu_bo_pin(struct amdgpu_bo *bo, u32 domain, u64 *gpu_addr)
 760 {
 761         return amdgpu_bo_pin_restricted(bo, domain, 0, 0, gpu_addr);
 762 }
 763
 764 int amdgpu_bo_unpin(struct amdgpu_bo *bo)
 765 {
 766         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
 767         struct ttm_operation_ctx ctx = { false, false };
 768         int r, i;
 769
 770         if (!bo->pin_count) {
 771                 dev_warn(adev->dev, "%p unpin not necessary\n", bo);
 772                 return 0;
 773         }
 774         bo->pin_count--;
 775         if (bo->pin_count)
 776                 return 0;
 777         for (i = 0; i < bo->placement.num_placement; i++) {
 778                 bo->placements[i].lpfn = 0;
 779                 bo->placements[i].flags &= ~TTM_PL_FLAG_NO_EVICT;
 780         }
 781         r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
 782         if (unlikely(r)) {
 783                 dev_err(adev->dev, "%p validate failed for unpin\n", bo);
 784                 goto error;
 785         }
 786
 787         if (bo->tbo.mem.mem_type == TTM_PL_VRAM) {
 788                 adev->vram_pin_size -= amdgpu_bo_size(bo);
 789                 if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)
 790                         adev->invisible_pin_size -= amdgpu_bo_size(bo);
 791         } else if (bo->tbo.mem.mem_type == TTM_PL_TT) {
 792                 adev->gart_pin_size -= amdgpu_bo_size(bo);
 793         }
 794
 795 error:
 796         return r;
 797 }
 798
 799 int amdgpu_bo_evict_vram(struct amdgpu_device *adev)
 800 {
 801         /* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */
 802         if (0 && (adev->flags & AMD_IS_APU)) {
 803                 /* Useless to evict on IGP chips */
 804                 return 0;
 805         }
 806         return ttm_bo_evict_mm(&adev->mman.bdev, TTM_PL_VRAM);
 807 }
 808
 809 static const char *amdgpu_vram_names[] = {
 810         "UNKNOWN",
 811         "GDDR1",
 812         "DDR2",
 813         "GDDR3",
 814         "GDDR4",
 815         "GDDR5",
 816         "HBM",
 817         "DDR3"
 818 };
 819
 820 int amdgpu_bo_init(struct amdgpu_device *adev)
 821 {
 822         /* reserve PAT memory space to WC for VRAM */
 823         arch_io_reserve_memtype_wc(adev->mc.aper_base,
 824                                    adev->mc.aper_size);
 825
 826         /* Add an MTRR for the VRAM */
 827         adev->mc.vram_mtrr = arch_phys_wc_add(adev->mc.aper_base,
 828                                               adev->mc.aper_size);
 829         DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n",
 830                  adev->mc.mc_vram_size >> 20,
 831                  (unsigned long long)adev->mc.aper_size >> 20);
 832         DRM_INFO("RAM width %dbits %s\n",
 833                  adev->mc.vram_width, amdgpu_vram_names[adev->mc.vram_type]);
 834         return amdgpu_ttm_init(adev);
 835 }
 836
 837 void amdgpu_bo_fini(struct amdgpu_device *adev)
 838 {
 839         amdgpu_ttm_fini(adev);
 840         arch_phys_wc_del(adev->mc.vram_mtrr);
 841         arch_io_free_memtype_wc(adev->mc.aper_base, adev->mc.aper_size);
 842 }
 843
 844 int amdgpu_bo_fbdev_mmap(struct amdgpu_bo *bo,
 845                              struct vm_area_struct *vma)
 846 {
 847         return ttm_fbdev_mmap(vma, &bo->tbo);
 848 }
 849
 850 int amdgpu_bo_set_tiling_flags(struct amdgpu_bo *bo, u64 tiling_flags)
 851 {
 852         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
 853
 854         if (adev->family <= AMDGPU_FAMILY_CZ &&
 855             AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT) > 6)
 856                 return -EINVAL;
 857
 858         bo->tiling_flags = tiling_flags;
 859         return 0;
 860 }
 861
 862 void amdgpu_bo_get_tiling_flags(struct amdgpu_bo *bo, u64 *tiling_flags)
 863 {
 864         lockdep_assert_held(&bo->tbo.resv->lock.base);
 865
 866         if (tiling_flags)
 867                 *tiling_flags = bo->tiling_flags;
 868 }
 869
 870 int amdgpu_bo_set_metadata (struct amdgpu_bo *bo, void *metadata,
 871                             uint32_t metadata_size, uint64_t flags)
 872 {
 873         void *buffer;
 874
 875         if (!metadata_size) {
 876                 if (bo->metadata_size) {
 877                         kfree(bo->metadata);
 878                         bo->metadata = NULL;
 879                         bo->metadata_size = 0;
 880                 }
 881                 return 0;
 882         }
 883
 884         if (metadata == NULL)
 885                 return -EINVAL;
 886
 887         buffer = kmemdup(metadata, metadata_size, GFP_KERNEL);
 888         if (buffer == NULL)
 889                 return -ENOMEM;
 890
 891         kfree(bo->metadata);
 892         bo->metadata_flags = flags;
 893         bo->metadata = buffer;
 894         bo->metadata_size = metadata_size;
 895
 896         return 0;
 897 }
 898
 899 int amdgpu_bo_get_metadata(struct amdgpu_bo *bo, void *buffer,
 900                            size_t buffer_size, uint32_t *metadata_size,
 901                            uint64_t *flags)
 902 {
 903         if (!buffer && !metadata_size)
 904                 return -EINVAL;
 905
 906         if (buffer) {
 907                 if (buffer_size < bo->metadata_size)
 908                         return -EINVAL;
 909
 910                 if (bo->metadata_size)
 911                         memcpy(buffer, bo->metadata, bo->metadata_size);
 912         }
 913
 914         if (metadata_size)
 915                 *metadata_size = bo->metadata_size;
 916         if (flags)
 917                 *flags = bo->metadata_flags;
 918
 919         return 0;
 920 }
 921
 922 void amdgpu_bo_move_notify(struct ttm_buffer_object *bo,
 923                            bool evict,
 924                            struct ttm_mem_reg *new_mem)
 925 {
 926         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 927         struct amdgpu_bo *abo;
 928         struct ttm_mem_reg *old_mem = &bo->mem;
 929
 930         if (!amdgpu_ttm_bo_is_amdgpu_bo(bo))
 931                 return;
 932
 933         abo = ttm_to_amdgpu_bo(bo);
 934         amdgpu_vm_bo_invalidate(adev, abo, evict);
 935
 936         amdgpu_bo_kunmap(abo);
 937
 938         /* remember the eviction */
 939         if (evict)
 940                 atomic64_inc(&adev->num_evictions);
 941
 942         /* update statistics */
 943         if (!new_mem)
 944                 return;
 945
 946         /* move_notify is called before move happens */
 947         trace_amdgpu_ttm_bo_move(abo, new_mem->mem_type, old_mem->mem_type);
 948 }
 949
 950 int amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
 951 {
 952         struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
 953         struct ttm_operation_ctx ctx = { false, false };
 954         struct amdgpu_bo *abo;
 955         unsigned long offset, size;
 956         int r;
 957
 958         if (!amdgpu_ttm_bo_is_amdgpu_bo(bo))
 959                 return 0;
 960
 961         abo = ttm_to_amdgpu_bo(bo);
 962
 963         /* Remember that this BO was accessed by the CPU */
 964         abo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
 965
 966         if (bo->mem.mem_type != TTM_PL_VRAM)
 967                 return 0;
 968
 969         size = bo->mem.num_pages << PAGE_SHIFT;
 970         offset = bo->mem.start << PAGE_SHIFT;
 971         if ((offset + size) <= adev->mc.visible_vram_size)
 972                 return 0;
 973
 974         /* Can't move a pinned BO to visible VRAM */
 975         if (abo->pin_count > 0)
 976                 return -EINVAL;
 977
 978         /* hurrah the memory is not visible ! */
 979         atomic64_inc(&adev->num_vram_cpu_page_faults);
 980         amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM |
 981                                          AMDGPU_GEM_DOMAIN_GTT);
 982
 983         /* Avoid costly evictions; only set GTT as a busy placement */
 984         abo->placement.num_busy_placement = 1;
 985         abo->placement.busy_placement = &abo->placements[1];
 986
 987         r = ttm_bo_validate(bo, &abo->placement, &ctx);
 988         if (unlikely(r != 0))
 989                 return r;
 990
 991         offset = bo->mem.start << PAGE_SHIFT;
 992         /* this should never happen */
 993         if (bo->mem.mem_type == TTM_PL_VRAM &&
 994             (offset + size) > adev->mc.visible_vram_size)
 995                 return -EINVAL;
 996
 997         return 0;
 998 }
 999
1000 /**
1001  * amdgpu_bo_fence - add fence to buffer object
1002  *
1003  * @bo: buffer object in question
1004  * @fence: fence to add
1005  * @shared: true if fence should be added shared
1006  *
1007  */
1008 void amdgpu_bo_fence(struct amdgpu_bo *bo, struct dma_fence *fence,
1009                      bool shared)
1010 {
1011         struct reservation_object *resv = bo->tbo.resv;
1012
1013         if (shared)
1014                 reservation_object_add_shared_fence(resv, fence);
1015         else
1016                 reservation_object_add_excl_fence(resv, fence);
1017 }
1018
1019 /**
1020  * amdgpu_bo_gpu_offset - return GPU offset of bo
1021  * @bo: amdgpu object for which we query the offset
1022  *
1023  * Returns current GPU offset of the object.
1024  *
1025  * Note: object should either be pinned or reserved when calling this
1026  * function, it might be useful to add check for this for debugging.
1027  */
1028 u64 amdgpu_bo_gpu_offset(struct amdgpu_bo *bo)
1029 {
1030         WARN_ON_ONCE(bo->tbo.mem.mem_type == TTM_PL_SYSTEM);
1031         WARN_ON_ONCE(bo->tbo.mem.mem_type == TTM_PL_TT &&
1032                      !amdgpu_gtt_mgr_has_gart_addr(&bo->tbo.mem));
1033         WARN_ON_ONCE(!ww_mutex_is_locked(&bo->tbo.resv->lock) &&
1034                      !bo->pin_count);
1035         WARN_ON_ONCE(bo->tbo.mem.start == AMDGPU_BO_INVALID_OFFSET);
1036         WARN_ON_ONCE(bo->tbo.mem.mem_type == TTM_PL_VRAM &&
1037                      !(bo->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS));
1038
1039         return bo->tbo.offset;
1040 }