sound/soc/dwc/designware_i2s.c

   1 /*
   2  * ALSA SoC Synopsys I2S Audio Layer
   3  *
   4  * sound/soc/dwc/designware_i2s.c
   5  *
   6  * Copyright (C) 2010 ST Microelectronics
   7  * Rajeev Kumar <[email protected]>
   8  *
   9  * This file is licensed under the terms of the GNU General Public
  10  * License version 2. This program is licensed "as is" without any
  11  * warranty of any kind, whether express or implied.
  12  */
  13
  14 #include <linux/clk.h>
  15 #include <linux/device.h>
  16 #include <linux/init.h>
  17 #include <linux/io.h>
  18 #include <linux/interrupt.h>
  19 #include <linux/module.h>
  20 #include <linux/slab.h>
  21 #include <sound/designware_i2s.h>
  22 #include <sound/pcm.h>
  23 #include <sound/pcm_params.h>
  24 #include <sound/soc.h>
  25 #include <sound/dmaengine_pcm.h>
  26
  27 /* common register for all channel */
  28 #define IER             0x000
  29 #define IRER            0x004
  30 #define ITER            0x008
  31 #define CER             0x00C
  32 #define CCR             0x010
  33 #define RXFFR           0x014
  34 #define TXFFR           0x018
  35
  36 /* I2STxRxRegisters for all channels */
  37 #define LRBR_LTHR(x)    (0x40 * x + 0x020)
  38 #define RRBR_RTHR(x)    (0x40 * x + 0x024)
  39 #define RER(x)          (0x40 * x + 0x028)
  40 #define TER(x)          (0x40 * x + 0x02C)
  41 #define RCR(x)          (0x40 * x + 0x030)
  42 #define TCR(x)          (0x40 * x + 0x034)
  43 #define ISR(x)          (0x40 * x + 0x038)
  44 #define IMR(x)          (0x40 * x + 0x03C)
  45 #define ROR(x)          (0x40 * x + 0x040)
  46 #define TOR(x)          (0x40 * x + 0x044)
  47 #define RFCR(x)         (0x40 * x + 0x048)
  48 #define TFCR(x)         (0x40 * x + 0x04C)
  49 #define RFF(x)          (0x40 * x + 0x050)
  50 #define TFF(x)          (0x40 * x + 0x054)
  51
  52 /* I2SCOMPRegisters */
  53 #define I2S_COMP_PARAM_2        0x01F0
  54 #define I2S_COMP_PARAM_1        0x01F4
  55 #define I2S_COMP_VERSION        0x01F8
  56 #define I2S_COMP_TYPE           0x01FC
  57
  58 /*
  59  * Component parameter register fields - define the I2S block's
  60  * configuration.
  61  */
  62 #define COMP1_TX_WORDSIZE_3(r)  (((r) & GENMASK(27, 25)) >> 25)
  63 #define COMP1_TX_WORDSIZE_2(r)  (((r) & GENMASK(24, 22)) >> 22)
  64 #define COMP1_TX_WORDSIZE_1(r)  (((r) & GENMASK(21, 19)) >> 19)
  65 #define COMP1_TX_WORDSIZE_0(r)  (((r) & GENMASK(18, 16)) >> 16)
  66 #define COMP1_TX_CHANNELS(r)    (((r) & GENMASK(10, 9)) >> 9)
  67 #define COMP1_RX_CHANNELS(r)    (((r) & GENMASK(8, 7)) >> 7)
  68 #define COMP1_RX_ENABLED(r)     (((r) & BIT(6)) >> 6)
  69 #define COMP1_TX_ENABLED(r)     (((r) & BIT(5)) >> 5)
  70 #define COMP1_MODE_EN(r)        (((r) & BIT(4)) >> 4)
  71 #define COMP1_FIFO_DEPTH_GLOBAL(r)      (((r) & GENMASK(3, 2)) >> 2)
  72 #define COMP1_APB_DATA_WIDTH(r) (((r) & GENMASK(1, 0)) >> 0)
  73
  74 #define COMP2_RX_WORDSIZE_3(r)  (((r) & GENMASK(12, 10)) >> 10)
  75 #define COMP2_RX_WORDSIZE_2(r)  (((r) & GENMASK(9, 7)) >> 7)
  76 #define COMP2_RX_WORDSIZE_1(r)  (((r) & GENMASK(5, 3)) >> 3)
  77 #define COMP2_RX_WORDSIZE_0(r)  (((r) & GENMASK(2, 0)) >> 0)
  78
  79 /* Number of entries in WORDSIZE and DATA_WIDTH parameter registers */
  80 #define COMP_MAX_WORDSIZE       (1 << 3)
  81 #define COMP_MAX_DATA_WIDTH     (1 << 2)
  82
  83 #define MAX_CHANNEL_NUM         8
  84 #define MIN_CHANNEL_NUM         2
  85
  86 union dw_i2s_snd_dma_data {
  87         struct i2s_dma_data pd;
  88         struct snd_dmaengine_dai_dma_data dt;
  89 };
  90
  91 struct dw_i2s_dev {
  92         void __iomem *i2s_base;
  93         struct clk *clk;
  94         int active;
  95         unsigned int capability;
  96         struct device *dev;
  97
  98         /* data related to DMA transfers b/w i2s and DMAC */
  99         union dw_i2s_snd_dma_data play_dma_data;
 100         union dw_i2s_snd_dma_data capture_dma_data;
 101         struct i2s_clk_config_data config;
 102         int (*i2s_clk_cfg)(struct i2s_clk_config_data *config);
 103 };
 104
 105 static inline void i2s_write_reg(void __iomem *io_base, int reg, u32 val)
 106 {
 107         writel(val, io_base + reg);
 108 }
 109
 110 static inline u32 i2s_read_reg(void __iomem *io_base, int reg)
 111 {
 112         return readl(io_base + reg);
 113 }
 114
 115 static inline void i2s_disable_channels(struct dw_i2s_dev *dev, u32 stream)
 116 {
 117         u32 i = 0;
 118
 119         if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
 120                 for (i = 0; i < 4; i++)
 121                         i2s_write_reg(dev->i2s_base, TER(i), 0);
 122         } else {
 123                 for (i = 0; i < 4; i++)
 124                         i2s_write_reg(dev->i2s_base, RER(i), 0);
 125         }
 126 }
 127
 128 static inline void i2s_clear_irqs(struct dw_i2s_dev *dev, u32 stream)
 129 {
 130         u32 i = 0;
 131
 132         if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
 133                 for (i = 0; i < 4; i++)
 134                         i2s_read_reg(dev->i2s_base, TOR(i));
 135         } else {
 136                 for (i = 0; i < 4; i++)
 137                         i2s_read_reg(dev->i2s_base, ROR(i));
 138         }
 139 }
 140
 141 static void i2s_start(struct dw_i2s_dev *dev,
 142                       struct snd_pcm_substream *substream)
 143 {
 144         u32 i, irq;
 145         i2s_write_reg(dev->i2s_base, IER, 1);
 146
 147         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 148                 for (i = 0; i < 4; i++) {
 149                         irq = i2s_read_reg(dev->i2s_base, IMR(i));
 150                         i2s_write_reg(dev->i2s_base, IMR(i), irq & ~0x30);
 151                 }
 152                 i2s_write_reg(dev->i2s_base, ITER, 1);
 153         } else {
 154                 for (i = 0; i < 4; i++) {
 155                         irq = i2s_read_reg(dev->i2s_base, IMR(i));
 156                         i2s_write_reg(dev->i2s_base, IMR(i), irq & ~0x03);
 157                 }
 158                 i2s_write_reg(dev->i2s_base, IRER, 1);
 159         }
 160
 161         i2s_write_reg(dev->i2s_base, CER, 1);
 162 }
 163
 164 static void i2s_stop(struct dw_i2s_dev *dev,
 165                 struct snd_pcm_substream *substream)
 166 {
 167         u32 i = 0, irq;
 168
 169         i2s_clear_irqs(dev, substream->stream);
 170         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 171                 i2s_write_reg(dev->i2s_base, ITER, 0);
 172
 173                 for (i = 0; i < 4; i++) {
 174                         irq = i2s_read_reg(dev->i2s_base, IMR(i));
 175                         i2s_write_reg(dev->i2s_base, IMR(i), irq | 0x30);
 176                 }
 177         } else {
 178                 i2s_write_reg(dev->i2s_base, IRER, 0);
 179
 180                 for (i = 0; i < 4; i++) {
 181                         irq = i2s_read_reg(dev->i2s_base, IMR(i));
 182                         i2s_write_reg(dev->i2s_base, IMR(i), irq | 0x03);
 183                 }
 184         }
 185
 186         if (!dev->active) {
 187                 i2s_write_reg(dev->i2s_base, CER, 0);
 188                 i2s_write_reg(dev->i2s_base, IER, 0);
 189         }
 190 }
 191
 192 static int dw_i2s_startup(struct snd_pcm_substream *substream,
 193                 struct snd_soc_dai *cpu_dai)
 194 {
 195         struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(cpu_dai);
 196         union dw_i2s_snd_dma_data *dma_data = NULL;
 197
 198         if (!(dev->capability & DWC_I2S_RECORD) &&
 199                         (substream->stream == SNDRV_PCM_STREAM_CAPTURE))
 200                 return -EINVAL;
 201
 202         if (!(dev->capability & DWC_I2S_PLAY) &&
 203                         (substream->stream == SNDRV_PCM_STREAM_PLAYBACK))
 204                 return -EINVAL;
 205
 206         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 207                 dma_data = &dev->play_dma_data;
 208         else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE)
 209                 dma_data = &dev->capture_dma_data;
 210
 211         snd_soc_dai_set_dma_data(cpu_dai, substream, (void *)dma_data);
 212
 213         return 0;
 214 }
 215
 216 static int dw_i2s_hw_params(struct snd_pcm_substream *substream,
 217                 struct snd_pcm_hw_params *params, struct snd_soc_dai *dai)
 218 {
 219         struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
 220         struct i2s_clk_config_data *config = &dev->config;
 221         u32 ccr, xfer_resolution, ch_reg, irq;
 222         int ret;
 223
 224         switch (params_format(params)) {
 225         case SNDRV_PCM_FORMAT_S16_LE:
 226                 config->data_width = 16;
 227                 ccr = 0x00;
 228                 xfer_resolution = 0x02;
 229                 break;
 230
 231         case SNDRV_PCM_FORMAT_S24_LE:
 232                 config->data_width = 24;
 233                 ccr = 0x08;
 234                 xfer_resolution = 0x04;
 235                 break;
 236
 237         case SNDRV_PCM_FORMAT_S32_LE:
 238                 config->data_width = 32;
 239                 ccr = 0x10;
 240                 xfer_resolution = 0x05;
 241                 break;
 242
 243         default:
 244                 dev_err(dev->dev, "designware-i2s: unsuppted PCM fmt");
 245                 return -EINVAL;
 246         }
 247
 248         config->chan_nr = params_channels(params);
 249
 250         switch (config->chan_nr) {
 251         case EIGHT_CHANNEL_SUPPORT:
 252         case SIX_CHANNEL_SUPPORT:
 253         case FOUR_CHANNEL_SUPPORT:
 254         case TWO_CHANNEL_SUPPORT:
 255                 break;
 256         default:
 257                 dev_err(dev->dev, "channel not supported\n");
 258                 return -EINVAL;
 259         }
 260
 261         i2s_disable_channels(dev, substream->stream);
 262
 263         for (ch_reg = 0; ch_reg < (config->chan_nr / 2); ch_reg++) {
 264                 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
 265                         i2s_write_reg(dev->i2s_base, TCR(ch_reg),
 266                                       xfer_resolution);
 267                         i2s_write_reg(dev->i2s_base, TFCR(ch_reg), 0x02);
 268                         irq = i2s_read_reg(dev->i2s_base, IMR(ch_reg));
 269                         i2s_write_reg(dev->i2s_base, IMR(ch_reg), irq & ~0x30);
 270                         i2s_write_reg(dev->i2s_base, TER(ch_reg), 1);
 271                 } else {
 272                         i2s_write_reg(dev->i2s_base, RCR(ch_reg),
 273                                       xfer_resolution);
 274                         i2s_write_reg(dev->i2s_base, RFCR(ch_reg), 0x07);
 275                         irq = i2s_read_reg(dev->i2s_base, IMR(ch_reg));
 276                         i2s_write_reg(dev->i2s_base, IMR(ch_reg), irq & ~0x03);
 277                         i2s_write_reg(dev->i2s_base, RER(ch_reg), 1);
 278                 }
 279         }
 280
 281         i2s_write_reg(dev->i2s_base, CCR, ccr);
 282
 283         config->sample_rate = params_rate(params);
 284
 285         if (dev->i2s_clk_cfg) {
 286                 ret = dev->i2s_clk_cfg(config);
 287                 if (ret < 0) {
 288                         dev_err(dev->dev, "runtime audio clk config fail\n");
 289                         return ret;
 290                 }
 291         } else {
 292                 u32 bitclk = config->sample_rate * config->data_width * 2;
 293
 294                 ret = clk_set_rate(dev->clk, bitclk);
 295                 if (ret) {
 296                         dev_err(dev->dev, "Can't set I2S clock rate: %d\n",
 297                                 ret);
 298                         return ret;
 299                 }
 300         }
 301
 302         return 0;
 303 }
 304
 305 static void dw_i2s_shutdown(struct snd_pcm_substream *substream,
 306                 struct snd_soc_dai *dai)
 307 {
 308         snd_soc_dai_set_dma_data(dai, substream, NULL);
 309 }
 310
 311 static int dw_i2s_prepare(struct snd_pcm_substream *substream,
 312                           struct snd_soc_dai *dai)
 313 {
 314         struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
 315
 316         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
 317                 i2s_write_reg(dev->i2s_base, TXFFR, 1);
 318         else
 319                 i2s_write_reg(dev->i2s_base, RXFFR, 1);
 320
 321         return 0;
 322 }
 323
 324 static int dw_i2s_trigger(struct snd_pcm_substream *substream,
 325                 int cmd, struct snd_soc_dai *dai)
 326 {
 327         struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
 328         int ret = 0;
 329
 330         switch (cmd) {
 331         case SNDRV_PCM_TRIGGER_START:
 332         case SNDRV_PCM_TRIGGER_RESUME:
 333         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 334                 dev->active++;
 335                 i2s_start(dev, substream);
 336                 break;
 337
 338         case SNDRV_PCM_TRIGGER_STOP:
 339         case SNDRV_PCM_TRIGGER_SUSPEND:
 340         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 341                 dev->active--;
 342                 i2s_stop(dev, substream);
 343                 break;
 344         default:
 345                 ret = -EINVAL;
 346                 break;
 347         }
 348         return ret;
 349 }
 350
 351 static struct snd_soc_dai_ops dw_i2s_dai_ops = {
 352         .startup        = dw_i2s_startup,
 353         .shutdown       = dw_i2s_shutdown,
 354         .hw_params      = dw_i2s_hw_params,
 355         .prepare        = dw_i2s_prepare,
 356         .trigger        = dw_i2s_trigger,
 357 };
 358
 359 static const struct snd_soc_component_driver dw_i2s_component = {
 360         .name           = "dw-i2s",
 361 };
 362
 363 #ifdef CONFIG_PM
 364
 365 static int dw_i2s_suspend(struct snd_soc_dai *dai)
 366 {
 367         struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
 368
 369         clk_disable(dev->clk);
 370         return 0;
 371 }
 372
 373 static int dw_i2s_resume(struct snd_soc_dai *dai)
 374 {
 375         struct dw_i2s_dev *dev = snd_soc_dai_get_drvdata(dai);
 376
 377         clk_enable(dev->clk);
 378         return 0;
 379 }
 380
 381 #else
 382 #define dw_i2s_suspend  NULL
 383 #define dw_i2s_resume   NULL
 384 #endif
 385
 386 /*
 387  * The following tables allow a direct lookup of various parameters
 388  * defined in the I2S block's configuration in terms of sound system
 389  * parameters.  Each table is sized to the number of entries possible
 390  * according to the number of configuration bits describing an I2S
 391  * block parameter.
 392  */
 393
 394 /* Maximum bit resolution of a channel - not uniformly spaced */
 395 static const u32 fifo_width[COMP_MAX_WORDSIZE] = {
 396         12, 16, 20, 24, 32, 0, 0, 0
 397 };
 398
 399 /* Width of (DMA) bus */
 400 static const u32 bus_widths[COMP_MAX_DATA_WIDTH] = {
 401         DMA_SLAVE_BUSWIDTH_1_BYTE,
 402         DMA_SLAVE_BUSWIDTH_2_BYTES,
 403         DMA_SLAVE_BUSWIDTH_4_BYTES,
 404         DMA_SLAVE_BUSWIDTH_UNDEFINED
 405 };
 406
 407 /* PCM format to support channel resolution */
 408 static const u32 formats[COMP_MAX_WORDSIZE] = {
 409         SNDRV_PCM_FMTBIT_S16_LE,
 410         SNDRV_PCM_FMTBIT_S16_LE,
 411         SNDRV_PCM_FMTBIT_S24_LE,
 412         SNDRV_PCM_FMTBIT_S24_LE,
 413         SNDRV_PCM_FMTBIT_S32_LE,
 414         0,
 415         0,
 416         0
 417 };
 418
 419 static int dw_configure_dai(struct dw_i2s_dev *dev,
 420                                    struct snd_soc_dai_driver *dw_i2s_dai,
 421                                    unsigned int rates)
 422 {
 423         /*
 424          * Read component parameter registers to extract
 425          * the I2S block's configuration.
 426          */
 427         u32 comp1 = i2s_read_reg(dev->i2s_base, I2S_COMP_PARAM_1);
 428         u32 comp2 = i2s_read_reg(dev->i2s_base, I2S_COMP_PARAM_2);
 429         u32 idx;
 430
 431         if (COMP1_TX_ENABLED(comp1)) {
 432                 dev_dbg(dev->dev, " designware: play supported\n");
 433                 idx = COMP1_TX_WORDSIZE_0(comp1);
 434                 if (WARN_ON(idx >= ARRAY_SIZE(formats)))
 435                         return -EINVAL;
 436                 dw_i2s_dai->playback.channels_min = MIN_CHANNEL_NUM;
 437                 dw_i2s_dai->playback.channels_max =
 438                                 1 << (COMP1_TX_CHANNELS(comp1) + 1);
 439                 dw_i2s_dai->playback.formats = formats[idx];
 440                 dw_i2s_dai->playback.rates = rates;
 441         }
 442
 443         if (COMP1_RX_ENABLED(comp1)) {
 444                 dev_dbg(dev->dev, "designware: record supported\n");
 445                 idx = COMP2_RX_WORDSIZE_0(comp2);
 446                 if (WARN_ON(idx >= ARRAY_SIZE(formats)))
 447                         return -EINVAL;
 448                 dw_i2s_dai->capture.channels_min = MIN_CHANNEL_NUM;
 449                 dw_i2s_dai->capture.channels_max =
 450                                 1 << (COMP1_RX_CHANNELS(comp1) + 1);
 451                 dw_i2s_dai->capture.formats = formats[idx];
 452                 dw_i2s_dai->capture.rates = rates;
 453         }
 454
 455         return 0;
 456 }
 457
 458 static int dw_configure_dai_by_pd(struct dw_i2s_dev *dev,
 459                                    struct snd_soc_dai_driver *dw_i2s_dai,
 460                                    struct resource *res,
 461                                    const struct i2s_platform_data *pdata)
 462 {
 463         u32 comp1 = i2s_read_reg(dev->i2s_base, I2S_COMP_PARAM_1);
 464         u32 idx = COMP1_APB_DATA_WIDTH(comp1);
 465         int ret;
 466
 467         if (WARN_ON(idx >= ARRAY_SIZE(bus_widths)))
 468                 return -EINVAL;
 469
 470         ret = dw_configure_dai(dev, dw_i2s_dai, pdata->snd_rates);
 471         if (ret < 0)
 472                 return ret;
 473
 474         /* Set DMA slaves info */
 475         dev->play_dma_data.pd.data = pdata->play_dma_data;
 476         dev->capture_dma_data.pd.data = pdata->capture_dma_data;
 477         dev->play_dma_data.pd.addr = res->start + I2S_TXDMA;
 478         dev->capture_dma_data.pd.addr = res->start + I2S_RXDMA;
 479         dev->play_dma_data.pd.max_burst = 16;
 480         dev->capture_dma_data.pd.max_burst = 16;
 481         dev->play_dma_data.pd.addr_width = bus_widths[idx];
 482         dev->capture_dma_data.pd.addr_width = bus_widths[idx];
 483         dev->play_dma_data.pd.filter = pdata->filter;
 484         dev->capture_dma_data.pd.filter = pdata->filter;
 485
 486         return 0;
 487 }
 488
 489 static int dw_configure_dai_by_dt(struct dw_i2s_dev *dev,
 490                                    struct snd_soc_dai_driver *dw_i2s_dai,
 491                                    struct resource *res)
 492 {
 493         u32 comp1 = i2s_read_reg(dev->i2s_base, I2S_COMP_PARAM_1);
 494         u32 comp2 = i2s_read_reg(dev->i2s_base, I2S_COMP_PARAM_2);
 495         u32 fifo_depth = 1 << (1 + COMP1_FIFO_DEPTH_GLOBAL(comp1));
 496         u32 idx = COMP1_APB_DATA_WIDTH(comp1);
 497         u32 idx2;
 498         int ret;
 499
 500         if (WARN_ON(idx >= ARRAY_SIZE(bus_widths)))
 501                 return -EINVAL;
 502
 503         ret = dw_configure_dai(dev, dw_i2s_dai, SNDRV_PCM_RATE_8000_192000);
 504         if (ret < 0)
 505                 return ret;
 506
 507         if (COMP1_TX_ENABLED(comp1)) {
 508                 idx2 = COMP1_TX_WORDSIZE_0(comp1);
 509
 510                 dev->capability |= DWC_I2S_PLAY;
 511                 dev->play_dma_data.dt.addr = res->start + I2S_TXDMA;
 512                 dev->play_dma_data.dt.addr_width = bus_widths[idx];
 513                 dev->play_dma_data.dt.chan_name = "TX";
 514                 dev->play_dma_data.dt.fifo_size = fifo_depth *
 515                         (fifo_width[idx2]) >> 8;
 516                 dev->play_dma_data.dt.maxburst = 16;
 517         }
 518         if (COMP1_RX_ENABLED(comp1)) {
 519                 idx2 = COMP2_RX_WORDSIZE_0(comp2);
 520
 521                 dev->capability |= DWC_I2S_RECORD;
 522                 dev->capture_dma_data.dt.addr = res->start + I2S_RXDMA;
 523                 dev->capture_dma_data.dt.addr_width = bus_widths[idx];
 524                 dev->capture_dma_data.dt.chan_name = "RX";
 525                 dev->capture_dma_data.dt.fifo_size = fifo_depth *
 526                         (fifo_width[idx2] >> 8);
 527                 dev->capture_dma_data.dt.maxburst = 16;
 528         }
 529
 530         return 0;
 531
 532 }
 533
 534 static int dw_i2s_probe(struct platform_device *pdev)
 535 {
 536         const struct i2s_platform_data *pdata = pdev->dev.platform_data;
 537         struct dw_i2s_dev *dev;
 538         struct resource *res;
 539         int ret;
 540         struct snd_soc_dai_driver *dw_i2s_dai;
 541
 542         dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
 543         if (!dev) {
 544                 dev_warn(&pdev->dev, "kzalloc fail\n");
 545                 return -ENOMEM;
 546         }
 547
 548         dw_i2s_dai = devm_kzalloc(&pdev->dev, sizeof(*dw_i2s_dai), GFP_KERNEL);
 549         if (!dw_i2s_dai)
 550                 return -ENOMEM;
 551
 552         dw_i2s_dai->ops = &dw_i2s_dai_ops;
 553         dw_i2s_dai->suspend = dw_i2s_suspend;
 554         dw_i2s_dai->resume = dw_i2s_resume;
 555
 556         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 557         dev->i2s_base = devm_ioremap_resource(&pdev->dev, res);
 558         if (IS_ERR(dev->i2s_base))
 559                 return PTR_ERR(dev->i2s_base);
 560
 561         dev->dev = &pdev->dev;
 562         if (pdata) {
 563                 ret = dw_configure_dai_by_pd(dev, dw_i2s_dai, res, pdata);
 564                 if (ret < 0)
 565                         return ret;
 566
 567                 dev->capability = pdata->cap;
 568                 dev->i2s_clk_cfg = pdata->i2s_clk_cfg;
 569                 if (!dev->i2s_clk_cfg) {
 570                         dev_err(&pdev->dev, "no clock configure method\n");
 571                         return -ENODEV;
 572                 }
 573
 574                 dev->clk = devm_clk_get(&pdev->dev, NULL);
 575         } else {
 576                 ret = dw_configure_dai_by_dt(dev, dw_i2s_dai, res);
 577                 if (ret < 0)
 578                         return ret;
 579
 580                 dev->clk = devm_clk_get(&pdev->dev, "i2sclk");
 581         }
 582         if (IS_ERR(dev->clk))
 583                 return PTR_ERR(dev->clk);
 584
 585         ret = clk_prepare_enable(dev->clk);
 586         if (ret < 0)
 587                 return ret;
 588
 589         dev_set_drvdata(&pdev->dev, dev);
 590         ret = devm_snd_soc_register_component(&pdev->dev, &dw_i2s_component,
 591                                          dw_i2s_dai, 1);
 592         if (ret != 0) {
 593                 dev_err(&pdev->dev, "not able to register dai\n");
 594                 goto err_clk_disable;
 595         }
 596
 597         if (!pdata) {
 598                 ret = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
 599                 if (ret) {
 600                         dev_err(&pdev->dev,
 601                                 "Could not register PCM: %d\n", ret);
 602                         goto err_clk_disable;
 603                 }
 604         }
 605
 606         return 0;
 607
 608 err_clk_disable:
 609         clk_disable_unprepare(dev->clk);
 610         return ret;
 611 }
 612
 613 static int dw_i2s_remove(struct platform_device *pdev)
 614 {
 615         struct dw_i2s_dev *dev = dev_get_drvdata(&pdev->dev);
 616
 617         clk_disable_unprepare(dev->clk);
 618
 619         return 0;
 620 }
 621
 622 #ifdef CONFIG_OF
 623 static const struct of_device_id dw_i2s_of_match[] = {
 624         { .compatible = "snps,designware-i2s",   },
 625         {},
 626 };
 627
 628 MODULE_DEVICE_TABLE(of, dw_i2s_of_match);
 629 #endif
 630
 631 static struct platform_driver dw_i2s_driver = {
 632         .probe          = dw_i2s_probe,
 633         .remove         = dw_i2s_remove,
 634         .driver         = {
 635                 .name   = "designware-i2s",
 636                 .of_match_table = of_match_ptr(dw_i2s_of_match),
 637         },
 638 };
 639
 640 module_platform_driver(dw_i2s_driver);
 641
 642 MODULE_AUTHOR("Rajeev Kumar <[email protected]>");
 643 MODULE_DESCRIPTION("DESIGNWARE I2S SoC Interface");
 644 MODULE_LICENSE("GPL");
 645 MODULE_ALIAS("platform:designware_i2s");