drivers/gpu/drm/i915/intel_lvds.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  * Copyright (c) 2006 Dave Airlie <[email protected]>
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *      Eric Anholt <[email protected]>
  26  *      Dave Airlie <[email protected]>
  27  *      Jesse Barnes <[email protected]>
  28  */
  29
  30 #include <acpi/button.h>
  31 #include <linux/dmi.h>
  32 #include <linux/i2c.h>
  33 #include <linux/slab.h>
  34 #include <linux/vga_switcheroo.h>
  35 #include <drm/drmP.h>
  36 #include <drm/drm_atomic_helper.h>
  37 #include <drm/drm_crtc.h>
  38 #include <drm/drm_edid.h>
  39 #include "intel_drv.h"
  40 #include <drm/i915_drm.h>
  41 #include "i915_drv.h"
  42 #include <linux/acpi.h>
  43
  44 /* Private structure for the integrated LVDS support */
  45 struct intel_lvds_connector {
  46         struct intel_connector base;
  47
  48         struct notifier_block lid_notifier;
  49 };
  50
  51 struct intel_lvds_pps {
  52         /* 100us units */
  53         int t1_t2;
  54         int t3;
  55         int t4;
  56         int t5;
  57         int tx;
  58
  59         int divider;
  60
  61         int port;
  62         bool powerdown_on_reset;
  63 };
  64
  65 struct intel_lvds_encoder {
  66         struct intel_encoder base;
  67
  68         bool is_dual_link;
  69         i915_reg_t reg;
  70         u32 a3_power;
  71
  72         struct intel_lvds_pps init_pps;
  73         u32 init_lvds_val;
  74
  75         struct intel_lvds_connector *attached_connector;
  76 };
  77
  78 static struct intel_lvds_encoder *to_lvds_encoder(struct drm_encoder *encoder)
  79 {
  80         return container_of(encoder, struct intel_lvds_encoder, base.base);
  81 }
  82
  83 static struct intel_lvds_connector *to_lvds_connector(struct drm_connector *connector)
  84 {
  85         return container_of(connector, struct intel_lvds_connector, base.base);
  86 }
  87
  88 static bool intel_lvds_get_hw_state(struct intel_encoder *encoder,
  89                                     enum pipe *pipe)
  90 {
  91         struct drm_device *dev = encoder->base.dev;
  92         struct drm_i915_private *dev_priv = to_i915(dev);
  93         struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
  94         u32 tmp;
  95         bool ret;
  96
  97         if (!intel_display_power_get_if_enabled(dev_priv,
  98                                                 encoder->power_domain))
  99                 return false;
 100
 101         ret = false;
 102
 103         tmp = I915_READ(lvds_encoder->reg);
 104
 105         if (!(tmp & LVDS_PORT_EN))
 106                 goto out;
 107
 108         if (HAS_PCH_CPT(dev_priv))
 109                 *pipe = PORT_TO_PIPE_CPT(tmp);
 110         else
 111                 *pipe = PORT_TO_PIPE(tmp);
 112
 113         ret = true;
 114
 115 out:
 116         intel_display_power_put(dev_priv, encoder->power_domain);
 117
 118         return ret;
 119 }
 120
 121 static void intel_lvds_get_config(struct intel_encoder *encoder,
 122                                   struct intel_crtc_state *pipe_config)
 123 {
 124         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 125         struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
 126         u32 tmp, flags = 0;
 127
 128         pipe_config->output_types |= BIT(INTEL_OUTPUT_LVDS);
 129
 130         tmp = I915_READ(lvds_encoder->reg);
 131         if (tmp & LVDS_HSYNC_POLARITY)
 132                 flags |= DRM_MODE_FLAG_NHSYNC;
 133         else
 134                 flags |= DRM_MODE_FLAG_PHSYNC;
 135         if (tmp & LVDS_VSYNC_POLARITY)
 136                 flags |= DRM_MODE_FLAG_NVSYNC;
 137         else
 138                 flags |= DRM_MODE_FLAG_PVSYNC;
 139
 140         pipe_config->base.adjusted_mode.flags |= flags;
 141
 142         if (INTEL_GEN(dev_priv) < 5)
 143                 pipe_config->gmch_pfit.lvds_border_bits =
 144                         tmp & LVDS_BORDER_ENABLE;
 145
 146         /* gen2/3 store dither state in pfit control, needs to match */
 147         if (INTEL_GEN(dev_priv) < 4) {
 148                 tmp = I915_READ(PFIT_CONTROL);
 149
 150                 pipe_config->gmch_pfit.control |= tmp & PANEL_8TO6_DITHER_ENABLE;
 151         }
 152
 153         pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock;
 154 }
 155
 156 static void intel_lvds_pps_get_hw_state(struct drm_i915_private *dev_priv,
 157                                         struct intel_lvds_pps *pps)
 158 {
 159         u32 val;
 160
 161         pps->powerdown_on_reset = I915_READ(PP_CONTROL(0)) & PANEL_POWER_RESET;
 162
 163         val = I915_READ(PP_ON_DELAYS(0));
 164         pps->port = (val & PANEL_PORT_SELECT_MASK) >>
 165                     PANEL_PORT_SELECT_SHIFT;
 166         pps->t1_t2 = (val & PANEL_POWER_UP_DELAY_MASK) >>
 167                      PANEL_POWER_UP_DELAY_SHIFT;
 168         pps->t5 = (val & PANEL_LIGHT_ON_DELAY_MASK) >>
 169                   PANEL_LIGHT_ON_DELAY_SHIFT;
 170
 171         val = I915_READ(PP_OFF_DELAYS(0));
 172         pps->t3 = (val & PANEL_POWER_DOWN_DELAY_MASK) >>
 173                   PANEL_POWER_DOWN_DELAY_SHIFT;
 174         pps->tx = (val & PANEL_LIGHT_OFF_DELAY_MASK) >>
 175                   PANEL_LIGHT_OFF_DELAY_SHIFT;
 176
 177         val = I915_READ(PP_DIVISOR(0));
 178         pps->divider = (val & PP_REFERENCE_DIVIDER_MASK) >>
 179                        PP_REFERENCE_DIVIDER_SHIFT;
 180         val = (val & PANEL_POWER_CYCLE_DELAY_MASK) >>
 181               PANEL_POWER_CYCLE_DELAY_SHIFT;
 182         /*
 183          * Remove the BSpec specified +1 (100ms) offset that accounts for a
 184          * too short power-cycle delay due to the asynchronous programming of
 185          * the register.
 186          */
 187         if (val)
 188                 val--;
 189         /* Convert from 100ms to 100us units */
 190         pps->t4 = val * 1000;
 191
 192         if (INTEL_GEN(dev_priv) <= 4 &&
 193             pps->t1_t2 == 0 && pps->t5 == 0 && pps->t3 == 0 && pps->tx == 0) {
 194                 DRM_DEBUG_KMS("Panel power timings uninitialized, "
 195                               "setting defaults\n");
 196                 /* Set T2 to 40ms and T5 to 200ms in 100 usec units */
 197                 pps->t1_t2 = 40 * 10;
 198                 pps->t5 = 200 * 10;
 199                 /* Set T3 to 35ms and Tx to 200ms in 100 usec units */
 200                 pps->t3 = 35 * 10;
 201                 pps->tx = 200 * 10;
 202         }
 203
 204         DRM_DEBUG_DRIVER("LVDS PPS:t1+t2 %d t3 %d t4 %d t5 %d tx %d "
 205                          "divider %d port %d powerdown_on_reset %d\n",
 206                          pps->t1_t2, pps->t3, pps->t4, pps->t5, pps->tx,
 207                          pps->divider, pps->port, pps->powerdown_on_reset);
 208 }
 209
 210 static void intel_lvds_pps_init_hw(struct drm_i915_private *dev_priv,
 211                                    struct intel_lvds_pps *pps)
 212 {
 213         u32 val;
 214
 215         val = I915_READ(PP_CONTROL(0));
 216         WARN_ON((val & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS);
 217         if (pps->powerdown_on_reset)
 218                 val |= PANEL_POWER_RESET;
 219         I915_WRITE(PP_CONTROL(0), val);
 220
 221         I915_WRITE(PP_ON_DELAYS(0), (pps->port << PANEL_PORT_SELECT_SHIFT) |
 222                                     (pps->t1_t2 << PANEL_POWER_UP_DELAY_SHIFT) |
 223                                     (pps->t5 << PANEL_LIGHT_ON_DELAY_SHIFT));
 224         I915_WRITE(PP_OFF_DELAYS(0), (pps->t3 << PANEL_POWER_DOWN_DELAY_SHIFT) |
 225                                      (pps->tx << PANEL_LIGHT_OFF_DELAY_SHIFT));
 226
 227         val = pps->divider << PP_REFERENCE_DIVIDER_SHIFT;
 228         val |= (DIV_ROUND_UP(pps->t4, 1000) + 1) <<
 229                PANEL_POWER_CYCLE_DELAY_SHIFT;
 230         I915_WRITE(PP_DIVISOR(0), val);
 231 }
 232
 233 static void intel_pre_enable_lvds(struct intel_encoder *encoder,
 234                                   const struct intel_crtc_state *pipe_config,
 235                                   const struct drm_connector_state *conn_state)
 236 {
 237         struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
 238         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 239         struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
 240         const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
 241         int pipe = crtc->pipe;
 242         u32 temp;
 243
 244         if (HAS_PCH_SPLIT(dev_priv)) {
 245                 assert_fdi_rx_pll_disabled(dev_priv, pipe);
 246                 assert_shared_dpll_disabled(dev_priv,
 247                                             pipe_config->shared_dpll);
 248         } else {
 249                 assert_pll_disabled(dev_priv, pipe);
 250         }
 251
 252         intel_lvds_pps_init_hw(dev_priv, &lvds_encoder->init_pps);
 253
 254         temp = lvds_encoder->init_lvds_val;
 255         temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
 256
 257         if (HAS_PCH_CPT(dev_priv)) {
 258                 temp &= ~PORT_TRANS_SEL_MASK;
 259                 temp |= PORT_TRANS_SEL_CPT(pipe);
 260         } else {
 261                 if (pipe == 1) {
 262                         temp |= LVDS_PIPEB_SELECT;
 263                 } else {
 264                         temp &= ~LVDS_PIPEB_SELECT;
 265                 }
 266         }
 267
 268         /* set the corresponsding LVDS_BORDER bit */
 269         temp &= ~LVDS_BORDER_ENABLE;
 270         temp |= pipe_config->gmch_pfit.lvds_border_bits;
 271
 272         /*
 273          * Set the B0-B3 data pairs corresponding to whether we're going to
 274          * set the DPLLs for dual-channel mode or not.
 275          */
 276         if (lvds_encoder->is_dual_link)
 277                 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
 278         else
 279                 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
 280
 281         /*
 282          * It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
 283          * appropriately here, but we need to look more thoroughly into how
 284          * panels behave in the two modes. For now, let's just maintain the
 285          * value we got from the BIOS.
 286          */
 287         temp &= ~LVDS_A3_POWER_MASK;
 288         temp |= lvds_encoder->a3_power;
 289
 290         /*
 291          * Set the dithering flag on LVDS as needed, note that there is no
 292          * special lvds dither control bit on pch-split platforms, dithering is
 293          * only controlled through the PIPECONF reg.
 294          */
 295         if (IS_GEN4(dev_priv)) {
 296                 /*
 297                  * Bspec wording suggests that LVDS port dithering only exists
 298                  * for 18bpp panels.
 299                  */
 300                 if (pipe_config->dither && pipe_config->pipe_bpp == 18)
 301                         temp |= LVDS_ENABLE_DITHER;
 302                 else
 303                         temp &= ~LVDS_ENABLE_DITHER;
 304         }
 305         temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
 306         if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
 307                 temp |= LVDS_HSYNC_POLARITY;
 308         if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
 309                 temp |= LVDS_VSYNC_POLARITY;
 310
 311         I915_WRITE(lvds_encoder->reg, temp);
 312 }
 313
 314 /*
 315  * Sets the power state for the panel.
 316  */
 317 static void intel_enable_lvds(struct intel_encoder *encoder,
 318                               const struct intel_crtc_state *pipe_config,
 319                               const struct drm_connector_state *conn_state)
 320 {
 321         struct drm_device *dev = encoder->base.dev;
 322         struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
 323         struct drm_i915_private *dev_priv = to_i915(dev);
 324
 325         I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) | LVDS_PORT_EN);
 326
 327         I915_WRITE(PP_CONTROL(0), I915_READ(PP_CONTROL(0)) | PANEL_POWER_ON);
 328         POSTING_READ(lvds_encoder->reg);
 329         if (intel_wait_for_register(dev_priv, PP_STATUS(0), PP_ON, PP_ON, 1000))
 330                 DRM_ERROR("timed out waiting for panel to power on\n");
 331
 332         intel_panel_enable_backlight(pipe_config, conn_state);
 333 }
 334
 335 static void intel_disable_lvds(struct intel_encoder *encoder,
 336                                const struct intel_crtc_state *old_crtc_state,
 337                                const struct drm_connector_state *old_conn_state)
 338 {
 339         struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
 340         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 341
 342         I915_WRITE(PP_CONTROL(0), I915_READ(PP_CONTROL(0)) & ~PANEL_POWER_ON);
 343         if (intel_wait_for_register(dev_priv, PP_STATUS(0), PP_ON, 0, 1000))
 344                 DRM_ERROR("timed out waiting for panel to power off\n");
 345
 346         I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) & ~LVDS_PORT_EN);
 347         POSTING_READ(lvds_encoder->reg);
 348 }
 349
 350 static void gmch_disable_lvds(struct intel_encoder *encoder,
 351                               const struct intel_crtc_state *old_crtc_state,
 352                               const struct drm_connector_state *old_conn_state)
 353
 354 {
 355         intel_panel_disable_backlight(old_conn_state);
 356
 357         intel_disable_lvds(encoder, old_crtc_state, old_conn_state);
 358 }
 359
 360 static void pch_disable_lvds(struct intel_encoder *encoder,
 361                              const struct intel_crtc_state *old_crtc_state,
 362                              const struct drm_connector_state *old_conn_state)
 363 {
 364         intel_panel_disable_backlight(old_conn_state);
 365 }
 366
 367 static void pch_post_disable_lvds(struct intel_encoder *encoder,
 368                                   const struct intel_crtc_state *old_crtc_state,
 369                                   const struct drm_connector_state *old_conn_state)
 370 {
 371         intel_disable_lvds(encoder, old_crtc_state, old_conn_state);
 372 }
 373
 374 static enum drm_mode_status
 375 intel_lvds_mode_valid(struct drm_connector *connector,
 376                       struct drm_display_mode *mode)
 377 {
 378         struct intel_connector *intel_connector = to_intel_connector(connector);
 379         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 380         int max_pixclk = to_i915(connector->dev)->max_dotclk_freq;
 381
 382         if (mode->hdisplay > fixed_mode->hdisplay)
 383                 return MODE_PANEL;
 384         if (mode->vdisplay > fixed_mode->vdisplay)
 385                 return MODE_PANEL;
 386         if (fixed_mode->clock > max_pixclk)
 387                 return MODE_CLOCK_HIGH;
 388
 389         return MODE_OK;
 390 }
 391
 392 static bool intel_lvds_compute_config(struct intel_encoder *intel_encoder,
 393                                       struct intel_crtc_state *pipe_config,
 394                                       struct drm_connector_state *conn_state)
 395 {
 396         struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
 397         struct intel_lvds_encoder *lvds_encoder =
 398                 to_lvds_encoder(&intel_encoder->base);
 399         struct intel_connector *intel_connector =
 400                 &lvds_encoder->attached_connector->base;
 401         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
 402         struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
 403         unsigned int lvds_bpp;
 404
 405         /* Should never happen!! */
 406         if (INTEL_GEN(dev_priv) < 4 && intel_crtc->pipe == 0) {
 407                 DRM_ERROR("Can't support LVDS on pipe A\n");
 408                 return false;
 409         }
 410
 411         if (lvds_encoder->a3_power == LVDS_A3_POWER_UP)
 412                 lvds_bpp = 8*3;
 413         else
 414                 lvds_bpp = 6*3;
 415
 416         if (lvds_bpp != pipe_config->pipe_bpp && !pipe_config->bw_constrained) {
 417                 DRM_DEBUG_KMS("forcing display bpp (was %d) to LVDS (%d)\n",
 418                               pipe_config->pipe_bpp, lvds_bpp);
 419                 pipe_config->pipe_bpp = lvds_bpp;
 420         }
 421
 422         /*
 423          * We have timings from the BIOS for the panel, put them in
 424          * to the adjusted mode.  The CRTC will be set up for this mode,
 425          * with the panel scaling set up to source from the H/VDisplay
 426          * of the original mode.
 427          */
 428         intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
 429                                adjusted_mode);
 430
 431         if (HAS_PCH_SPLIT(dev_priv)) {
 432                 pipe_config->has_pch_encoder = true;
 433
 434                 intel_pch_panel_fitting(intel_crtc, pipe_config,
 435                                         conn_state->scaling_mode);
 436         } else {
 437                 intel_gmch_panel_fitting(intel_crtc, pipe_config,
 438                                          conn_state->scaling_mode);
 439
 440         }
 441
 442         /*
 443          * XXX: It would be nice to support lower refresh rates on the
 444          * panels to reduce power consumption, and perhaps match the
 445          * user's requested refresh rate.
 446          */
 447
 448         return true;
 449 }
 450
 451 /*
 452  * Detect the LVDS connection.
 453  *
 454  * Since LVDS doesn't have hotlug, we use the lid as a proxy.  Open means
 455  * connected and closed means disconnected.  We also send hotplug events as
 456  * needed, using lid status notification from the input layer.
 457  */
 458 static enum drm_connector_status
 459 intel_lvds_detect(struct drm_connector *connector, bool force)
 460 {
 461         struct drm_i915_private *dev_priv = to_i915(connector->dev);
 462         enum drm_connector_status status;
 463
 464         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
 465                       connector->base.id, connector->name);
 466
 467         status = intel_panel_detect(dev_priv);
 468         if (status != connector_status_unknown)
 469                 return status;
 470
 471         return connector_status_connected;
 472 }
 473
 474 /*
 475  * Return the list of DDC modes if available, or the BIOS fixed mode otherwise.
 476  */
 477 static int intel_lvds_get_modes(struct drm_connector *connector)
 478 {
 479         struct intel_lvds_connector *lvds_connector = to_lvds_connector(connector);
 480         struct drm_device *dev = connector->dev;
 481         struct drm_display_mode *mode;
 482
 483         /* use cached edid if we have one */
 484         if (!IS_ERR_OR_NULL(lvds_connector->base.edid))
 485                 return drm_add_edid_modes(connector, lvds_connector->base.edid);
 486
 487         mode = drm_mode_duplicate(dev, lvds_connector->base.panel.fixed_mode);
 488         if (mode == NULL)
 489                 return 0;
 490
 491         drm_mode_probed_add(connector, mode);
 492         return 1;
 493 }
 494
 495 static int intel_no_modeset_on_lid_dmi_callback(const struct dmi_system_id *id)
 496 {
 497         DRM_INFO("Skipping forced modeset for %s\n", id->ident);
 498         return 1;
 499 }
 500
 501 /* The GPU hangs up on these systems if modeset is performed on LID open */
 502 static const struct dmi_system_id intel_no_modeset_on_lid[] = {
 503         {
 504                 .callback = intel_no_modeset_on_lid_dmi_callback,
 505                 .ident = "Toshiba Tecra A11",
 506                 .matches = {
 507                         DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
 508                         DMI_MATCH(DMI_PRODUCT_NAME, "TECRA A11"),
 509                 },
 510         },
 511
 512         { }     /* terminating entry */
 513 };
 514
 515 /*
 516  * Lid events. Note the use of 'modeset':
 517  *  - we set it to MODESET_ON_LID_OPEN on lid close,
 518  *    and set it to MODESET_DONE on open
 519  *  - we use it as a "only once" bit (ie we ignore
 520  *    duplicate events where it was already properly set)
 521  *  - the suspend/resume paths will set it to
 522  *    MODESET_SUSPENDED and ignore the lid open event,
 523  *    because they restore the mode ("lid open").
 524  */
 525 static int intel_lid_notify(struct notifier_block *nb, unsigned long val,
 526                             void *unused)
 527 {
 528         struct intel_lvds_connector *lvds_connector =
 529                 container_of(nb, struct intel_lvds_connector, lid_notifier);
 530         struct drm_connector *connector = &lvds_connector->base.base;
 531         struct drm_device *dev = connector->dev;
 532         struct drm_i915_private *dev_priv = to_i915(dev);
 533
 534         if (dev->switch_power_state != DRM_SWITCH_POWER_ON)
 535                 return NOTIFY_OK;
 536
 537         mutex_lock(&dev_priv->modeset_restore_lock);
 538         if (dev_priv->modeset_restore == MODESET_SUSPENDED)
 539                 goto exit;
 540         /*
 541          * check and update the status of LVDS connector after receiving
 542          * the LID nofication event.
 543          */
 544         connector->status = connector->funcs->detect(connector, false);
 545
 546         /* Don't force modeset on machines where it causes a GPU lockup */
 547         if (dmi_check_system(intel_no_modeset_on_lid))
 548                 goto exit;
 549         if (!acpi_lid_open()) {
 550                 /* do modeset on next lid open event */
 551                 dev_priv->modeset_restore = MODESET_ON_LID_OPEN;
 552                 goto exit;
 553         }
 554
 555         if (dev_priv->modeset_restore == MODESET_DONE)
 556                 goto exit;
 557
 558         /*
 559          * Some old platform's BIOS love to wreak havoc while the lid is closed.
 560          * We try to detect this here and undo any damage. The split for PCH
 561          * platforms is rather conservative and a bit arbitrary expect that on
 562          * those platforms VGA disabling requires actual legacy VGA I/O access,
 563          * and as part of the cleanup in the hw state restore we also redisable
 564          * the vga plane.
 565          */
 566         if (!HAS_PCH_SPLIT(dev_priv))
 567                 intel_display_resume(dev);
 568
 569         dev_priv->modeset_restore = MODESET_DONE;
 570
 571 exit:
 572         mutex_unlock(&dev_priv->modeset_restore_lock);
 573         return NOTIFY_OK;
 574 }
 575
 576 /**
 577  * intel_lvds_destroy - unregister and free LVDS structures
 578  * @connector: connector to free
 579  *
 580  * Unregister the DDC bus for this connector then free the driver private
 581  * structure.
 582  */
 583 static void intel_lvds_destroy(struct drm_connector *connector)
 584 {
 585         struct intel_lvds_connector *lvds_connector =
 586                 to_lvds_connector(connector);
 587
 588         if (lvds_connector->lid_notifier.notifier_call)
 589                 acpi_lid_notifier_unregister(&lvds_connector->lid_notifier);
 590
 591         if (!IS_ERR_OR_NULL(lvds_connector->base.edid))
 592                 kfree(lvds_connector->base.edid);
 593
 594         intel_panel_fini(&lvds_connector->base.panel);
 595
 596         drm_connector_cleanup(connector);
 597         kfree(connector);
 598 }
 599
 600 static const struct drm_connector_helper_funcs intel_lvds_connector_helper_funcs = {
 601         .get_modes = intel_lvds_get_modes,
 602         .mode_valid = intel_lvds_mode_valid,
 603         .atomic_check = intel_digital_connector_atomic_check,
 604 };
 605
 606 static const struct drm_connector_funcs intel_lvds_connector_funcs = {
 607         .detect = intel_lvds_detect,
 608         .fill_modes = drm_helper_probe_single_connector_modes,
 609         .atomic_get_property = intel_digital_connector_atomic_get_property,
 610         .atomic_set_property = intel_digital_connector_atomic_set_property,
 611         .late_register = intel_connector_register,
 612         .early_unregister = intel_connector_unregister,
 613         .destroy = intel_lvds_destroy,
 614         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
 615         .atomic_duplicate_state = intel_digital_connector_duplicate_state,
 616 };
 617
 618 static const struct drm_encoder_funcs intel_lvds_enc_funcs = {
 619         .destroy = intel_encoder_destroy,
 620 };
 621
 622 static int intel_no_lvds_dmi_callback(const struct dmi_system_id *id)
 623 {
 624         DRM_INFO("Skipping LVDS initialization for %s\n", id->ident);
 625         return 1;
 626 }
 627
 628 /* These systems claim to have LVDS, but really don't */
 629 static const struct dmi_system_id intel_no_lvds[] = {
 630         {
 631                 .callback = intel_no_lvds_dmi_callback,
 632                 .ident = "Apple Mac Mini (Core series)",
 633                 .matches = {
 634                         DMI_MATCH(DMI_SYS_VENDOR, "Apple"),
 635                         DMI_MATCH(DMI_PRODUCT_NAME, "Macmini1,1"),
 636                 },
 637         },
 638         {
 639                 .callback = intel_no_lvds_dmi_callback,
 640                 .ident = "Apple Mac Mini (Core 2 series)",
 641                 .matches = {
 642                         DMI_MATCH(DMI_SYS_VENDOR, "Apple"),
 643                         DMI_MATCH(DMI_PRODUCT_NAME, "Macmini2,1"),
 644                 },
 645         },
 646         {
 647                 .callback = intel_no_lvds_dmi_callback,
 648                 .ident = "MSI IM-945GSE-A",
 649                 .matches = {
 650                         DMI_MATCH(DMI_SYS_VENDOR, "MSI"),
 651                         DMI_MATCH(DMI_PRODUCT_NAME, "A9830IMS"),
 652                 },
 653         },
 654         {
 655                 .callback = intel_no_lvds_dmi_callback,
 656                 .ident = "Dell Studio Hybrid",
 657                 .matches = {
 658                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
 659                         DMI_MATCH(DMI_PRODUCT_NAME, "Studio Hybrid 140g"),
 660                 },
 661         },
 662         {
 663                 .callback = intel_no_lvds_dmi_callback,
 664                 .ident = "Dell OptiPlex FX170",
 665                 .matches = {
 666                         DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
 667                         DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex FX170"),
 668                 },
 669         },
 670         {
 671                 .callback = intel_no_lvds_dmi_callback,
 672                 .ident = "AOpen Mini PC",
 673                 .matches = {
 674                         DMI_MATCH(DMI_SYS_VENDOR, "AOpen"),
 675                         DMI_MATCH(DMI_PRODUCT_NAME, "i965GMx-IF"),
 676                 },
 677         },
 678         {
 679                 .callback = intel_no_lvds_dmi_callback,
 680                 .ident = "AOpen Mini PC MP915",
 681                 .matches = {
 682                         DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
 683                         DMI_MATCH(DMI_BOARD_NAME, "i915GMx-F"),
 684                 },
 685         },
 686         {
 687                 .callback = intel_no_lvds_dmi_callback,
 688                 .ident = "AOpen i915GMm-HFS",
 689                 .matches = {
 690                         DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
 691                         DMI_MATCH(DMI_BOARD_NAME, "i915GMm-HFS"),
 692                 },
 693         },
 694         {
 695                 .callback = intel_no_lvds_dmi_callback,
 696                 .ident = "AOpen i45GMx-I",
 697                 .matches = {
 698                         DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
 699                         DMI_MATCH(DMI_BOARD_NAME, "i45GMx-I"),
 700                 },
 701         },
 702         {
 703                 .callback = intel_no_lvds_dmi_callback,
 704                 .ident = "Aopen i945GTt-VFA",
 705                 .matches = {
 706                         DMI_MATCH(DMI_PRODUCT_VERSION, "AO00001JW"),
 707                 },
 708         },
 709         {
 710                 .callback = intel_no_lvds_dmi_callback,
 711                 .ident = "Clientron U800",
 712                 .matches = {
 713                         DMI_MATCH(DMI_SYS_VENDOR, "Clientron"),
 714                         DMI_MATCH(DMI_PRODUCT_NAME, "U800"),
 715                 },
 716         },
 717         {
 718                 .callback = intel_no_lvds_dmi_callback,
 719                 .ident = "Clientron E830",
 720                 .matches = {
 721                         DMI_MATCH(DMI_SYS_VENDOR, "Clientron"),
 722                         DMI_MATCH(DMI_PRODUCT_NAME, "E830"),
 723                 },
 724         },
 725         {
 726                 .callback = intel_no_lvds_dmi_callback,
 727                 .ident = "Asus EeeBox PC EB1007",
 728                 .matches = {
 729                         DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK Computer INC."),
 730                         DMI_MATCH(DMI_PRODUCT_NAME, "EB1007"),
 731                 },
 732         },
 733         {
 734                 .callback = intel_no_lvds_dmi_callback,
 735                 .ident = "Asus AT5NM10T-I",
 736                 .matches = {
 737                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
 738                         DMI_MATCH(DMI_BOARD_NAME, "AT5NM10T-I"),
 739                 },
 740         },
 741         {
 742                 .callback = intel_no_lvds_dmi_callback,
 743                 .ident = "Hewlett-Packard HP t5740",
 744                 .matches = {
 745                         DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
 746                         DMI_MATCH(DMI_PRODUCT_NAME, " t5740"),
 747                 },
 748         },
 749         {
 750                 .callback = intel_no_lvds_dmi_callback,
 751                 .ident = "Hewlett-Packard t5745",
 752                 .matches = {
 753                         DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
 754                         DMI_MATCH(DMI_PRODUCT_NAME, "hp t5745"),
 755                 },
 756         },
 757         {
 758                 .callback = intel_no_lvds_dmi_callback,
 759                 .ident = "Hewlett-Packard st5747",
 760                 .matches = {
 761                         DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
 762                         DMI_MATCH(DMI_PRODUCT_NAME, "hp st5747"),
 763                 },
 764         },
 765         {
 766                 .callback = intel_no_lvds_dmi_callback,
 767                 .ident = "MSI Wind Box DC500",
 768                 .matches = {
 769                         DMI_MATCH(DMI_BOARD_VENDOR, "MICRO-STAR INTERNATIONAL CO., LTD"),
 770                         DMI_MATCH(DMI_BOARD_NAME, "MS-7469"),
 771                 },
 772         },
 773         {
 774                 .callback = intel_no_lvds_dmi_callback,
 775                 .ident = "Gigabyte GA-D525TUD",
 776                 .matches = {
 777                         DMI_MATCH(DMI_BOARD_VENDOR, "Gigabyte Technology Co., Ltd."),
 778                         DMI_MATCH(DMI_BOARD_NAME, "D525TUD"),
 779                 },
 780         },
 781         {
 782                 .callback = intel_no_lvds_dmi_callback,
 783                 .ident = "Supermicro X7SPA-H",
 784                 .matches = {
 785                         DMI_MATCH(DMI_SYS_VENDOR, "Supermicro"),
 786                         DMI_MATCH(DMI_PRODUCT_NAME, "X7SPA-H"),
 787                 },
 788         },
 789         {
 790                 .callback = intel_no_lvds_dmi_callback,
 791                 .ident = "Fujitsu Esprimo Q900",
 792                 .matches = {
 793                         DMI_MATCH(DMI_SYS_VENDOR, "FUJITSU"),
 794                         DMI_MATCH(DMI_PRODUCT_NAME, "ESPRIMO Q900"),
 795                 },
 796         },
 797         {
 798                 .callback = intel_no_lvds_dmi_callback,
 799                 .ident = "Intel D410PT",
 800                 .matches = {
 801                         DMI_MATCH(DMI_BOARD_VENDOR, "Intel"),
 802                         DMI_MATCH(DMI_BOARD_NAME, "D410PT"),
 803                 },
 804         },
 805         {
 806                 .callback = intel_no_lvds_dmi_callback,
 807                 .ident = "Intel D425KT",
 808                 .matches = {
 809                         DMI_MATCH(DMI_BOARD_VENDOR, "Intel"),
 810                         DMI_EXACT_MATCH(DMI_BOARD_NAME, "D425KT"),
 811                 },
 812         },
 813         {
 814                 .callback = intel_no_lvds_dmi_callback,
 815                 .ident = "Intel D510MO",
 816                 .matches = {
 817                         DMI_MATCH(DMI_BOARD_VENDOR, "Intel"),
 818                         DMI_EXACT_MATCH(DMI_BOARD_NAME, "D510MO"),
 819                 },
 820         },
 821         {
 822                 .callback = intel_no_lvds_dmi_callback,
 823                 .ident = "Intel D525MW",
 824                 .matches = {
 825                         DMI_MATCH(DMI_BOARD_VENDOR, "Intel"),
 826                         DMI_EXACT_MATCH(DMI_BOARD_NAME, "D525MW"),
 827                 },
 828         },
 829
 830         { }     /* terminating entry */
 831 };
 832
 833 static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
 834 {
 835         DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
 836         return 1;
 837 }
 838
 839 static const struct dmi_system_id intel_dual_link_lvds[] = {
 840         {
 841                 .callback = intel_dual_link_lvds_callback,
 842                 .ident = "Apple MacBook Pro 15\" (2010)",
 843                 .matches = {
 844                         DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
 845                         DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro6,2"),
 846                 },
 847         },
 848         {
 849                 .callback = intel_dual_link_lvds_callback,
 850                 .ident = "Apple MacBook Pro 15\" (2011)",
 851                 .matches = {
 852                         DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
 853                         DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
 854                 },
 855         },
 856         {
 857                 .callback = intel_dual_link_lvds_callback,
 858                 .ident = "Apple MacBook Pro 15\" (2012)",
 859                 .matches = {
 860                         DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
 861                         DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro9,1"),
 862                 },
 863         },
 864         { }     /* terminating entry */
 865 };
 866
 867 struct intel_encoder *intel_get_lvds_encoder(struct drm_device *dev)
 868 {
 869         struct intel_encoder *intel_encoder;
 870
 871         for_each_intel_encoder(dev, intel_encoder)
 872                 if (intel_encoder->type == INTEL_OUTPUT_LVDS)
 873                         return intel_encoder;
 874
 875         return NULL;
 876 }
 877
 878 bool intel_is_dual_link_lvds(struct drm_device *dev)
 879 {
 880         struct intel_encoder *encoder = intel_get_lvds_encoder(dev);
 881
 882         return encoder && to_lvds_encoder(&encoder->base)->is_dual_link;
 883 }
 884
 885 static bool compute_is_dual_link_lvds(struct intel_lvds_encoder *lvds_encoder)
 886 {
 887         struct drm_device *dev = lvds_encoder->base.base.dev;
 888         unsigned int val;
 889         struct drm_i915_private *dev_priv = to_i915(dev);
 890
 891         /* use the module option value if specified */
 892         if (i915_modparams.lvds_channel_mode > 0)
 893                 return i915_modparams.lvds_channel_mode == 2;
 894
 895         /* single channel LVDS is limited to 112 MHz */
 896         if (lvds_encoder->attached_connector->base.panel.fixed_mode->clock
 897             > 112999)
 898                 return true;
 899
 900         if (dmi_check_system(intel_dual_link_lvds))
 901                 return true;
 902
 903         /*
 904          * BIOS should set the proper LVDS register value at boot, but
 905          * in reality, it doesn't set the value when the lid is closed;
 906          * we need to check "the value to be set" in VBT when LVDS
 907          * register is uninitialized.
 908          */
 909         val = I915_READ(lvds_encoder->reg);
 910         if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED)))
 911                 val = dev_priv->vbt.bios_lvds_val;
 912
 913         return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
 914 }
 915
 916 static bool intel_lvds_supported(struct drm_i915_private *dev_priv)
 917 {
 918         /*
 919          * With the introduction of the PCH we gained a dedicated
 920          * LVDS presence pin, use it.
 921          */
 922         if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))
 923                 return true;
 924
 925         /*
 926          * Otherwise LVDS was only attached to mobile products,
 927          * except for the inglorious 830gm
 928          */
 929         if (INTEL_GEN(dev_priv) <= 4 &&
 930             IS_MOBILE(dev_priv) && !IS_I830(dev_priv))
 931                 return true;
 932
 933         return false;
 934 }
 935
 936 /**
 937  * intel_lvds_init - setup LVDS connectors on this device
 938  * @dev_priv: i915 device
 939  *
 940  * Create the connector, register the LVDS DDC bus, and try to figure out what
 941  * modes we can display on the LVDS panel (if present).
 942  */
 943 void intel_lvds_init(struct drm_i915_private *dev_priv)
 944 {
 945         struct drm_device *dev = &dev_priv->drm;
 946         struct intel_lvds_encoder *lvds_encoder;
 947         struct intel_encoder *intel_encoder;
 948         struct intel_lvds_connector *lvds_connector;
 949         struct intel_connector *intel_connector;
 950         struct drm_connector *connector;
 951         struct drm_encoder *encoder;
 952         struct drm_display_mode *scan; /* *modes, *bios_mode; */
 953         struct drm_display_mode *fixed_mode = NULL;
 954         struct drm_display_mode *downclock_mode = NULL;
 955         struct edid *edid;
 956         i915_reg_t lvds_reg;
 957         u32 lvds;
 958         u8 pin;
 959         u32 allowed_scalers;
 960
 961         if (!intel_lvds_supported(dev_priv))
 962                 return;
 963
 964         /* Skip init on machines we know falsely report LVDS */
 965         if (dmi_check_system(intel_no_lvds))
 966                 return;
 967
 968         if (HAS_PCH_SPLIT(dev_priv))
 969                 lvds_reg = PCH_LVDS;
 970         else
 971                 lvds_reg = LVDS;
 972
 973         lvds = I915_READ(lvds_reg);
 974
 975         if (HAS_PCH_SPLIT(dev_priv)) {
 976                 if ((lvds & LVDS_DETECTED) == 0)
 977                         return;
 978                 if (dev_priv->vbt.edp.support) {
 979                         DRM_DEBUG_KMS("disable LVDS for eDP support\n");
 980                         return;
 981                 }
 982         }
 983
 984         pin = GMBUS_PIN_PANEL;
 985         if (!intel_bios_is_lvds_present(dev_priv, &pin)) {
 986                 if ((lvds & LVDS_PORT_EN) == 0) {
 987                         DRM_DEBUG_KMS("LVDS is not present in VBT\n");
 988                         return;
 989                 }
 990                 DRM_DEBUG_KMS("LVDS is not present in VBT, but enabled anyway\n");
 991         }
 992
 993         lvds_encoder = kzalloc(sizeof(*lvds_encoder), GFP_KERNEL);
 994         if (!lvds_encoder)
 995                 return;
 996
 997         lvds_connector = kzalloc(sizeof(*lvds_connector), GFP_KERNEL);
 998         if (!lvds_connector) {
 999                 kfree(lvds_encoder);
1000                 return;
1001         }
1002
1003         if (intel_connector_init(&lvds_connector->base) < 0) {
1004                 kfree(lvds_connector);
1005                 kfree(lvds_encoder);
1006                 return;
1007         }
1008
1009         lvds_encoder->attached_connector = lvds_connector;
1010
1011         intel_encoder = &lvds_encoder->base;
1012         encoder = &intel_encoder->base;
1013         intel_connector = &lvds_connector->base;
1014         connector = &intel_connector->base;
1015         drm_connector_init(dev, &intel_connector->base, &intel_lvds_connector_funcs,
1016                            DRM_MODE_CONNECTOR_LVDS);
1017
1018         drm_encoder_init(dev, &intel_encoder->base, &intel_lvds_enc_funcs,
1019                          DRM_MODE_ENCODER_LVDS, "LVDS");
1020
1021         intel_encoder->enable = intel_enable_lvds;
1022         intel_encoder->pre_enable = intel_pre_enable_lvds;
1023         intel_encoder->compute_config = intel_lvds_compute_config;
1024         if (HAS_PCH_SPLIT(dev_priv)) {
1025                 intel_encoder->disable = pch_disable_lvds;
1026                 intel_encoder->post_disable = pch_post_disable_lvds;
1027         } else {
1028                 intel_encoder->disable = gmch_disable_lvds;
1029         }
1030         intel_encoder->get_hw_state = intel_lvds_get_hw_state;
1031         intel_encoder->get_config = intel_lvds_get_config;
1032         intel_connector->get_hw_state = intel_connector_get_hw_state;
1033
1034         intel_connector_attach_encoder(intel_connector, intel_encoder);
1035
1036         intel_encoder->type = INTEL_OUTPUT_LVDS;
1037         intel_encoder->power_domain = POWER_DOMAIN_PORT_OTHER;
1038         intel_encoder->port = PORT_NONE;
1039         intel_encoder->cloneable = 0;
1040         if (HAS_PCH_SPLIT(dev_priv))
1041                 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
1042         else if (IS_GEN4(dev_priv))
1043                 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
1044         else
1045                 intel_encoder->crtc_mask = (1 << 1);
1046
1047         drm_connector_helper_add(connector, &intel_lvds_connector_helper_funcs);
1048         connector->display_info.subpixel_order = SubPixelHorizontalRGB;
1049         connector->interlace_allowed = false;
1050         connector->doublescan_allowed = false;
1051
1052         lvds_encoder->reg = lvds_reg;
1053
1054         /* create the scaling mode property */
1055         allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT);
1056         allowed_scalers |= BIT(DRM_MODE_SCALE_FULLSCREEN);
1057         allowed_scalers |= BIT(DRM_MODE_SCALE_CENTER);
1058         drm_connector_attach_scaling_mode_property(connector, allowed_scalers);
1059         connector->state->scaling_mode = DRM_MODE_SCALE_ASPECT;
1060
1061         intel_lvds_pps_get_hw_state(dev_priv, &lvds_encoder->init_pps);
1062         lvds_encoder->init_lvds_val = lvds;
1063
1064         /*
1065          * LVDS discovery:
1066          * 1) check for EDID on DDC
1067          * 2) check for VBT data
1068          * 3) check to see if LVDS is already on
1069          *    if none of the above, no panel
1070          * 4) make sure lid is open
1071          *    if closed, act like it's not there for now
1072          */
1073
1074         /*
1075          * Attempt to get the fixed panel mode from DDC.  Assume that the
1076          * preferred mode is the right one.
1077          */
1078         mutex_lock(&dev->mode_config.mutex);
1079         if (vga_switcheroo_handler_flags() & VGA_SWITCHEROO_CAN_SWITCH_DDC)
1080                 edid = drm_get_edid_switcheroo(connector,
1081                                     intel_gmbus_get_adapter(dev_priv, pin));
1082         else
1083                 edid = drm_get_edid(connector,
1084                                     intel_gmbus_get_adapter(dev_priv, pin));
1085         if (edid) {
1086                 if (drm_add_edid_modes(connector, edid)) {
1087                         drm_mode_connector_update_edid_property(connector,
1088                                                                 edid);
1089                 } else {
1090                         kfree(edid);
1091                         edid = ERR_PTR(-EINVAL);
1092                 }
1093         } else {
1094                 edid = ERR_PTR(-ENOENT);
1095         }
1096         lvds_connector->base.edid = edid;
1097
1098         list_for_each_entry(scan, &connector->probed_modes, head) {
1099                 if (scan->type & DRM_MODE_TYPE_PREFERRED) {
1100                         DRM_DEBUG_KMS("using preferred mode from EDID: ");
1101                         drm_mode_debug_printmodeline(scan);
1102
1103                         fixed_mode = drm_mode_duplicate(dev, scan);
1104                         if (fixed_mode)
1105                                 goto out;
1106                 }
1107         }
1108
1109         /* Failed to get EDID, what about VBT? */
1110         if (dev_priv->vbt.lfp_lvds_vbt_mode) {
1111                 DRM_DEBUG_KMS("using mode from VBT: ");
1112                 drm_mode_debug_printmodeline(dev_priv->vbt.lfp_lvds_vbt_mode);
1113
1114                 fixed_mode = drm_mode_duplicate(dev, dev_priv->vbt.lfp_lvds_vbt_mode);
1115                 if (fixed_mode) {
1116                         fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
1117                         connector->display_info.width_mm = fixed_mode->width_mm;
1118                         connector->display_info.height_mm = fixed_mode->height_mm;
1119                         goto out;
1120                 }
1121         }
1122
1123         /*
1124          * If we didn't get EDID, try checking if the panel is already turned
1125          * on.  If so, assume that whatever is currently programmed is the
1126          * correct mode.
1127          */
1128         fixed_mode = intel_encoder_current_mode(intel_encoder);
1129         if (fixed_mode) {
1130                 DRM_DEBUG_KMS("using current (BIOS) mode: ");
1131                 drm_mode_debug_printmodeline(fixed_mode);
1132                 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
1133         }
1134
1135         /* If we still don't have a mode after all that, give up. */
1136         if (!fixed_mode)
1137                 goto failed;
1138
1139 out:
1140         mutex_unlock(&dev->mode_config.mutex);
1141
1142         intel_panel_init(&intel_connector->panel, fixed_mode, NULL,
1143                          downclock_mode);
1144         intel_panel_setup_backlight(connector, INVALID_PIPE);
1145
1146         lvds_encoder->is_dual_link = compute_is_dual_link_lvds(lvds_encoder);
1147         DRM_DEBUG_KMS("detected %s-link lvds configuration\n",
1148                       lvds_encoder->is_dual_link ? "dual" : "single");
1149
1150         lvds_encoder->a3_power = lvds & LVDS_A3_POWER_MASK;
1151
1152         lvds_connector->lid_notifier.notifier_call = intel_lid_notify;
1153         if (acpi_lid_notifier_register(&lvds_connector->lid_notifier)) {
1154                 DRM_DEBUG_KMS("lid notifier registration failed\n");
1155                 lvds_connector->lid_notifier.notifier_call = NULL;
1156         }
1157
1158         return;
1159
1160 failed:
1161         mutex_unlock(&dev->mode_config.mutex);
1162
1163         DRM_DEBUG_KMS("No LVDS modes found, disabling.\n");
1164         drm_connector_cleanup(connector);
1165         drm_encoder_cleanup(encoder);
1166         kfree(lvds_encoder);
1167         kfree(lvds_connector);
1168         return;
1169 }