sound/soc/sof/intel/shim.h

   1 /* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
   2 /*
   3  * This file is provided under a dual BSD/GPLv2 license.  When using or
   4  * redistributing this file, you may do so under either license.
   5  *
   6  * Copyright(c) 2017 Intel Corporation. All rights reserved.
   7  *
   8  * Author: Liam Girdwood <[email protected]>
   9  */
  10
  11 #ifndef __SOF_INTEL_SHIM_H
  12 #define __SOF_INTEL_SHIM_H
  13
  14 enum sof_intel_hw_ip_version {
  15         SOF_INTEL_TANGIER,
  16         SOF_INTEL_BAYTRAIL,
  17         SOF_INTEL_BROADWELL,
  18         SOF_INTEL_CAVS_1_5,     /* SkyLake, KabyLake, AmberLake */
  19         SOF_INTEL_CAVS_1_5_PLUS,/* ApolloLake, GeminiLake */
  20         SOF_INTEL_CAVS_1_8,     /* CannonLake, CometLake, CoffeeLake */
  21         SOF_INTEL_CAVS_2_0,     /* IceLake, JasperLake */
  22         SOF_INTEL_CAVS_2_5,     /* TigerLake, AlderLake */
  23         SOF_INTEL_ACE_1_0,      /* MeteorLake */
  24 };
  25
  26 /*
  27  * SHIM registers for BYT, BSW, CHT, BDW
  28  */
  29
  30 #define SHIM_CSR                (SHIM_OFFSET + 0x00)
  31 #define SHIM_PISR               (SHIM_OFFSET + 0x08)
  32 #define SHIM_PIMR               (SHIM_OFFSET + 0x10)
  33 #define SHIM_ISRX               (SHIM_OFFSET + 0x18)
  34 #define SHIM_ISRD               (SHIM_OFFSET + 0x20)
  35 #define SHIM_IMRX               (SHIM_OFFSET + 0x28)
  36 #define SHIM_IMRD               (SHIM_OFFSET + 0x30)
  37 #define SHIM_IPCX               (SHIM_OFFSET + 0x38)
  38 #define SHIM_IPCD               (SHIM_OFFSET + 0x40)
  39 #define SHIM_ISRSC              (SHIM_OFFSET + 0x48)
  40 #define SHIM_ISRLPESC           (SHIM_OFFSET + 0x50)
  41 #define SHIM_IMRSC              (SHIM_OFFSET + 0x58)
  42 #define SHIM_IMRLPESC           (SHIM_OFFSET + 0x60)
  43 #define SHIM_IPCSC              (SHIM_OFFSET + 0x68)
  44 #define SHIM_IPCLPESC           (SHIM_OFFSET + 0x70)
  45 #define SHIM_CLKCTL             (SHIM_OFFSET + 0x78)
  46 #define SHIM_CSR2               (SHIM_OFFSET + 0x80)
  47 #define SHIM_LTRC               (SHIM_OFFSET + 0xE0)
  48 #define SHIM_HMDC               (SHIM_OFFSET + 0xE8)
  49
  50 #define SHIM_PWMCTRL            0x1000
  51
  52 /*
  53  * SST SHIM register bits for BYT, BSW, CHT, BDW
  54  * Register bit naming and functionaility can differ between devices.
  55  */
  56
  57 /* CSR / CS */
  58 #define SHIM_CSR_RST            BIT(1)
  59 #define SHIM_CSR_SBCS0          BIT(2)
  60 #define SHIM_CSR_SBCS1          BIT(3)
  61 #define SHIM_CSR_DCS(x)         ((x) << 4)
  62 #define SHIM_CSR_DCS_MASK       (0x7 << 4)
  63 #define SHIM_CSR_STALL          BIT(10)
  64 #define SHIM_CSR_S0IOCS         BIT(21)
  65 #define SHIM_CSR_S1IOCS         BIT(23)
  66 #define SHIM_CSR_LPCS           BIT(31)
  67 #define SHIM_CSR_24MHZ_LPCS \
  68         (SHIM_CSR_SBCS0 | SHIM_CSR_SBCS1 | SHIM_CSR_LPCS)
  69 #define SHIM_CSR_24MHZ_NO_LPCS  (SHIM_CSR_SBCS0 | SHIM_CSR_SBCS1)
  70 #define SHIM_BYT_CSR_RST        BIT(0)
  71 #define SHIM_BYT_CSR_VECTOR_SEL BIT(1)
  72 #define SHIM_BYT_CSR_STALL      BIT(2)
  73 #define SHIM_BYT_CSR_PWAITMODE  BIT(3)
  74
  75 /*  ISRX / ISC */
  76 #define SHIM_ISRX_BUSY          BIT(1)
  77 #define SHIM_ISRX_DONE          BIT(0)
  78 #define SHIM_BYT_ISRX_REQUEST   BIT(1)
  79
  80 /*  ISRD / ISD */
  81 #define SHIM_ISRD_BUSY          BIT(1)
  82 #define SHIM_ISRD_DONE          BIT(0)
  83
  84 /* IMRX / IMC */
  85 #define SHIM_IMRX_BUSY          BIT(1)
  86 #define SHIM_IMRX_DONE          BIT(0)
  87 #define SHIM_BYT_IMRX_REQUEST   BIT(1)
  88
  89 /* IMRD / IMD */
  90 #define SHIM_IMRD_DONE          BIT(0)
  91 #define SHIM_IMRD_BUSY          BIT(1)
  92 #define SHIM_IMRD_SSP0          BIT(16)
  93 #define SHIM_IMRD_DMAC0         BIT(21)
  94 #define SHIM_IMRD_DMAC1         BIT(22)
  95 #define SHIM_IMRD_DMAC          (SHIM_IMRD_DMAC0 | SHIM_IMRD_DMAC1)
  96
  97 /*  IPCX / IPCC */
  98 #define SHIM_IPCX_DONE          BIT(30)
  99 #define SHIM_IPCX_BUSY          BIT(31)
 100 #define SHIM_BYT_IPCX_DONE      BIT_ULL(62)
 101 #define SHIM_BYT_IPCX_BUSY      BIT_ULL(63)
 102
 103 /*  IPCD */
 104 #define SHIM_IPCD_DONE          BIT(30)
 105 #define SHIM_IPCD_BUSY          BIT(31)
 106 #define SHIM_BYT_IPCD_DONE      BIT_ULL(62)
 107 #define SHIM_BYT_IPCD_BUSY      BIT_ULL(63)
 108
 109 /* CLKCTL */
 110 #define SHIM_CLKCTL_SMOS(x)     ((x) << 24)
 111 #define SHIM_CLKCTL_MASK        (3 << 24)
 112 #define SHIM_CLKCTL_DCPLCG      BIT(18)
 113 #define SHIM_CLKCTL_SCOE1       BIT(17)
 114 #define SHIM_CLKCTL_SCOE0       BIT(16)
 115
 116 /* CSR2 / CS2 */
 117 #define SHIM_CSR2_SDFD_SSP0     BIT(1)
 118 #define SHIM_CSR2_SDFD_SSP1     BIT(2)
 119
 120 /* LTRC */
 121 #define SHIM_LTRC_VAL(x)        ((x) << 0)
 122
 123 /* HMDC */
 124 #define SHIM_HMDC_HDDA0(x)      ((x) << 0)
 125 #define SHIM_HMDC_HDDA1(x)      ((x) << 7)
 126 #define SHIM_HMDC_HDDA_E0_CH0   1
 127 #define SHIM_HMDC_HDDA_E0_CH1   2
 128 #define SHIM_HMDC_HDDA_E0_CH2   4
 129 #define SHIM_HMDC_HDDA_E0_CH3   8
 130 #define SHIM_HMDC_HDDA_E1_CH0   SHIM_HMDC_HDDA1(SHIM_HMDC_HDDA_E0_CH0)
 131 #define SHIM_HMDC_HDDA_E1_CH1   SHIM_HMDC_HDDA1(SHIM_HMDC_HDDA_E0_CH1)
 132 #define SHIM_HMDC_HDDA_E1_CH2   SHIM_HMDC_HDDA1(SHIM_HMDC_HDDA_E0_CH2)
 133 #define SHIM_HMDC_HDDA_E1_CH3   SHIM_HMDC_HDDA1(SHIM_HMDC_HDDA_E0_CH3)
 134 #define SHIM_HMDC_HDDA_E0_ALLCH \
 135         (SHIM_HMDC_HDDA_E0_CH0 | SHIM_HMDC_HDDA_E0_CH1 | \
 136          SHIM_HMDC_HDDA_E0_CH2 | SHIM_HMDC_HDDA_E0_CH3)
 137 #define SHIM_HMDC_HDDA_E1_ALLCH \
 138         (SHIM_HMDC_HDDA_E1_CH0 | SHIM_HMDC_HDDA_E1_CH1 | \
 139          SHIM_HMDC_HDDA_E1_CH2 | SHIM_HMDC_HDDA_E1_CH3)
 140
 141 /* Audio DSP PCI registers */
 142 #define PCI_VDRTCTL0            0xa0
 143 #define PCI_VDRTCTL1            0xa4
 144 #define PCI_VDRTCTL2            0xa8
 145 #define PCI_VDRTCTL3            0xaC
 146
 147 /* VDRTCTL0 */
 148 #define PCI_VDRTCL0_D3PGD               BIT(0)
 149 #define PCI_VDRTCL0_D3SRAMPGD           BIT(1)
 150 #define PCI_VDRTCL0_DSRAMPGE_SHIFT      12
 151 #define PCI_VDRTCL0_DSRAMPGE_MASK       GENMASK(PCI_VDRTCL0_DSRAMPGE_SHIFT + 19,\
 152                                                 PCI_VDRTCL0_DSRAMPGE_SHIFT)
 153 #define PCI_VDRTCL0_ISRAMPGE_SHIFT      2
 154 #define PCI_VDRTCL0_ISRAMPGE_MASK       GENMASK(PCI_VDRTCL0_ISRAMPGE_SHIFT + 9,\
 155                                                 PCI_VDRTCL0_ISRAMPGE_SHIFT)
 156
 157 /* VDRTCTL2 */
 158 #define PCI_VDRTCL2_DCLCGE              BIT(1)
 159 #define PCI_VDRTCL2_DTCGE               BIT(10)
 160 #define PCI_VDRTCL2_APLLSE_MASK         BIT(31)
 161
 162 /* PMCS */
 163 #define PCI_PMCS                0x84
 164 #define PCI_PMCS_PS_MASK        0x3
 165
 166 /* Intel quirks */
 167 #define SOF_INTEL_PROCEN_FMT_QUIRK BIT(0)
 168
 169 /* DSP hardware descriptor */
 170 struct sof_intel_dsp_desc {
 171         int cores_num;
 172         int host_managed_cores_mask;
 173         int init_core_mask; /* cores available after fw boot */
 174         int ipc_req;
 175         int ipc_req_mask;
 176         int ipc_ack;
 177         int ipc_ack_mask;
 178         int ipc_ctl;
 179         int rom_status_reg;
 180         int rom_init_timeout;
 181         int ssp_count;                  /* ssp count of the platform */
 182         int ssp_base_offset;            /* base address of the SSPs */
 183         u32 sdw_shim_base;
 184         u32 sdw_alh_base;
 185         u32 d0i3_offset;
 186         u32 quirks;
 187         enum sof_intel_hw_ip_version hw_ip_version;
 188         int (*read_sdw_lcount)(struct snd_sof_dev *sdev);
 189         void (*enable_sdw_irq)(struct snd_sof_dev *sdev, bool enable);
 190         bool (*check_sdw_irq)(struct snd_sof_dev *sdev);
 191         bool (*check_ipc_irq)(struct snd_sof_dev *sdev);
 192         int (*power_down_dsp)(struct snd_sof_dev *sdev);
 193         int (*disable_interrupts)(struct snd_sof_dev *sdev);
 194         int (*cl_init)(struct snd_sof_dev *sdev, int stream_tag, bool imr_boot);
 195 };
 196
 197 extern struct snd_sof_dsp_ops sof_tng_ops;
 198
 199 extern const struct sof_intel_dsp_desc tng_chip_info;
 200
 201 struct sof_intel_stream {
 202         size_t posn_offset;
 203 };
 204
 205 static inline const struct sof_intel_dsp_desc *get_chip_info(struct snd_sof_pdata *pdata)
 206 {
 207         const struct sof_dev_desc *desc = pdata->desc;
 208
 209         return desc->chip_info;
 210 }
 211
 212 #endif