sound/soc/atmel/mchp-pdmc.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 //
   3 // Driver for Microchip Pulse Density Microphone Controller (PDMC) interfaces
   4 //
   5 // Copyright (C) 2019-2022 Microchip Technology Inc. and its subsidiaries
   6 //
   7 // Author: Codrin Ciubotariu <[email protected]>
   8
   9 #include <dt-bindings/sound/microchip,pdmc.h>
  10
  11 #include <linux/bitfield.h>
  12 #include <linux/clk.h>
  13 #include <linux/module.h>
  14 #include <linux/of.h>
  15 #include <linux/pm_runtime.h>
  16 #include <linux/regmap.h>
  17
  18 #include <sound/core.h>
  19 #include <sound/dmaengine_pcm.h>
  20 #include <sound/pcm_params.h>
  21 #include <sound/tlv.h>
  22
  23 /*
  24  * ---- PDMC Register map ----
  25  */
  26 #define MCHP_PDMC_CR                    0x00    /* Control Register */
  27 #define MCHP_PDMC_MR                    0x04    /* Mode Register */
  28 #define MCHP_PDMC_CFGR                  0x08    /* Configuration Register */
  29 #define MCHP_PDMC_RHR                   0x0C    /* Receive Holding Register */
  30 #define MCHP_PDMC_IER                   0x14    /* Interrupt Enable Register */
  31 #define MCHP_PDMC_IDR                   0x18    /* Interrupt Disable Register */
  32 #define MCHP_PDMC_IMR                   0x1C    /* Interrupt Mask Register */
  33 #define MCHP_PDMC_ISR                   0x20    /* Interrupt Status Register */
  34 #define MCHP_PDMC_VER                   0x50    /* Version Register */
  35
  36 /*
  37  * ---- Control Register (Write-only) ----
  38  */
  39 #define MCHP_PDMC_CR_SWRST              BIT(0)  /* Software Reset */
  40
  41 /*
  42  * ---- Mode Register (Read/Write) ----
  43  */
  44 #define MCHP_PDMC_MR_PDMCEN_MASK        GENMASK(3, 0)
  45 #define MCHP_PDMC_MR_PDMCEN(ch)         (BIT(ch) & MCHP_PDMC_MR_PDMCEN_MASK)
  46
  47 #define MCHP_PDMC_MR_OSR_MASK           GENMASK(17, 16)
  48 #define MCHP_PDMC_MR_OSR64              (1 << 16)
  49 #define MCHP_PDMC_MR_OSR128             (2 << 16)
  50 #define MCHP_PDMC_MR_OSR256             (3 << 16)
  51
  52 #define MCHP_PDMC_MR_SINCORDER_MASK     GENMASK(23, 20)
  53
  54 #define MCHP_PDMC_MR_SINC_OSR_MASK      GENMASK(27, 24)
  55 #define MCHP_PDMC_MR_SINC_OSR_DIS       (0 << 24)
  56 #define MCHP_PDMC_MR_SINC_OSR_8         (1 << 24)
  57 #define MCHP_PDMC_MR_SINC_OSR_16        (2 << 24)
  58 #define MCHP_PDMC_MR_SINC_OSR_32        (3 << 24)
  59 #define MCHP_PDMC_MR_SINC_OSR_64        (4 << 24)
  60 #define MCHP_PDMC_MR_SINC_OSR_128       (5 << 24)
  61 #define MCHP_PDMC_MR_SINC_OSR_256       (6 << 24)
  62
  63 #define MCHP_PDMC_MR_CHUNK_MASK         GENMASK(31, 28)
  64
  65 /*
  66  * ---- Configuration Register (Read/Write) ----
  67  */
  68 #define MCHP_PDMC_CFGR_BSSEL_MASK       (BIT(0) | BIT(2) | BIT(4) | BIT(6))
  69 #define MCHP_PDMC_CFGR_BSSEL(ch)        BIT((ch) * 2)
  70
  71 #define MCHP_PDMC_CFGR_PDMSEL_MASK      (BIT(16) | BIT(18) | BIT(20) | BIT(22))
  72 #define MCHP_PDMC_CFGR_PDMSEL(ch)       BIT((ch) * 2 + 16)
  73
  74 /*
  75  * ---- Interrupt Enable/Disable/Mask/Status Registers ----
  76  */
  77 #define MCHP_PDMC_IR_RXRDY              BIT(0)
  78 #define MCHP_PDMC_IR_RXEMPTY            BIT(1)
  79 #define MCHP_PDMC_IR_RXFULL             BIT(2)
  80 #define MCHP_PDMC_IR_RXCHUNK            BIT(3)
  81 #define MCHP_PDMC_IR_RXUDR              BIT(4)
  82 #define MCHP_PDMC_IR_RXOVR              BIT(5)
  83
  84 /*
  85  * ---- Version Register (Read-only) ----
  86  */
  87 #define MCHP_PDMC_VER_VERSION           GENMASK(11, 0)
  88
  89 #define MCHP_PDMC_MAX_CHANNELS          4
  90 #define MCHP_PDMC_DS_NO                 2
  91 #define MCHP_PDMC_EDGE_NO               2
  92
  93 struct mic_map {
  94         int ds_pos;
  95         int clk_edge;
  96 };
  97
  98 struct mchp_pdmc_chmap {
  99         struct snd_pcm_chmap_elem *chmap;
 100         struct mchp_pdmc *dd;
 101         struct snd_pcm *pcm;
 102         struct snd_kcontrol *kctl;
 103 };
 104
 105 struct mchp_pdmc {
 106         struct mic_map channel_mic_map[MCHP_PDMC_MAX_CHANNELS];
 107         struct device *dev;
 108         struct snd_dmaengine_dai_dma_data addr;
 109         struct regmap *regmap;
 110         struct clk *pclk;
 111         struct clk *gclk;
 112         u32 pdmcen;
 113         u32 suspend_irq;
 114         u32 startup_delay_us;
 115         int mic_no;
 116         int sinc_order;
 117         bool audio_filter_en;
 118 };
 119
 120 static const char *const mchp_pdmc_sinc_filter_order_text[] = {
 121         "1", "2", "3", "4", "5"
 122 };
 123
 124 static const unsigned int mchp_pdmc_sinc_filter_order_values[] = {
 125         1, 2, 3, 4, 5,
 126 };
 127
 128 static const struct soc_enum mchp_pdmc_sinc_filter_order_enum = {
 129         .items = ARRAY_SIZE(mchp_pdmc_sinc_filter_order_text),
 130         .texts = mchp_pdmc_sinc_filter_order_text,
 131         .values = mchp_pdmc_sinc_filter_order_values,
 132 };
 133
 134 static int mchp_pdmc_sinc_order_get(struct snd_kcontrol *kcontrol,
 135                                     struct snd_ctl_elem_value *uvalue)
 136 {
 137         struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
 138         struct mchp_pdmc *dd = snd_soc_component_get_drvdata(component);
 139         struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
 140         unsigned int item;
 141
 142         item = snd_soc_enum_val_to_item(e, dd->sinc_order);
 143         uvalue->value.enumerated.item[0] = item;
 144
 145         return 0;
 146 }
 147
 148 static int mchp_pdmc_sinc_order_put(struct snd_kcontrol *kcontrol,
 149                                     struct snd_ctl_elem_value *uvalue)
 150 {
 151         struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
 152         struct mchp_pdmc *dd = snd_soc_component_get_drvdata(component);
 153         struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
 154         unsigned int *item = uvalue->value.enumerated.item;
 155         unsigned int val;
 156
 157         if (item[0] >= e->items)
 158                 return -EINVAL;
 159
 160         val = snd_soc_enum_item_to_val(e, item[0]) << e->shift_l;
 161         if (val == dd->sinc_order)
 162                 return 0;
 163
 164         dd->sinc_order = val;
 165
 166         return 1;
 167 }
 168
 169 static int mchp_pdmc_af_get(struct snd_kcontrol *kcontrol,
 170                             struct snd_ctl_elem_value *uvalue)
 171 {
 172         struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
 173         struct mchp_pdmc *dd = snd_soc_component_get_drvdata(component);
 174
 175         uvalue->value.integer.value[0] = !!dd->audio_filter_en;
 176
 177         return 0;
 178 }
 179
 180 static int mchp_pdmc_af_put(struct snd_kcontrol *kcontrol,
 181                             struct snd_ctl_elem_value *uvalue)
 182 {
 183         struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
 184         struct mchp_pdmc *dd = snd_soc_component_get_drvdata(component);
 185         bool af = uvalue->value.integer.value[0] ? true : false;
 186
 187         if (dd->audio_filter_en == af)
 188                 return 0;
 189
 190         dd->audio_filter_en = af;
 191
 192         return 1;
 193 }
 194
 195 static int mchp_pdmc_chmap_ctl_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
 196 {
 197         struct mchp_pdmc_chmap *info = snd_kcontrol_chip(kcontrol);
 198
 199         uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
 200         uinfo->count = info->dd->mic_no;
 201         uinfo->value.integer.min = 0;
 202         uinfo->value.integer.max = SNDRV_CHMAP_RR; /* maxmimum 4 channels */
 203         return 0;
 204 }
 205
 206 static inline struct snd_pcm_substream *
 207 mchp_pdmc_chmap_substream(struct mchp_pdmc_chmap *info, unsigned int idx)
 208 {
 209         struct snd_pcm_substream *s;
 210
 211         for (s = info->pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream; s; s = s->next)
 212                 if (s->number == idx)
 213                         return s;
 214         return NULL;
 215 }
 216
 217 static struct snd_pcm_chmap_elem *mchp_pdmc_chmap_get(struct snd_pcm_substream *substream,
 218                                                       struct mchp_pdmc_chmap *ch_info)
 219 {
 220         struct snd_pcm_chmap_elem *map;
 221
 222         for (map = ch_info->chmap; map->channels; map++) {
 223                 if (map->channels == substream->runtime->channels)
 224                         return map;
 225         }
 226         return NULL;
 227 }
 228
 229 static int mchp_pdmc_chmap_ctl_get(struct snd_kcontrol *kcontrol,
 230                                    struct snd_ctl_elem_value *ucontrol)
 231 {
 232         struct mchp_pdmc_chmap *info = snd_kcontrol_chip(kcontrol);
 233         struct mchp_pdmc *dd = info->dd;
 234         unsigned int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
 235         struct snd_pcm_substream *substream;
 236         const struct snd_pcm_chmap_elem *map;
 237         int i;
 238         u32 cfgr_val = 0;
 239
 240         if (!info->chmap)
 241                 return -EINVAL;
 242         substream = mchp_pdmc_chmap_substream(info, idx);
 243         if (!substream)
 244                 return -ENODEV;
 245         memset(ucontrol->value.integer.value, 0, sizeof(long) * info->dd->mic_no);
 246         if (!substream->runtime)
 247                 return 0; /* no channels set */
 248
 249         map = mchp_pdmc_chmap_get(substream, info);
 250         if (!map)
 251                 return -EINVAL;
 252
 253         for (i = 0; i < map->channels; i++) {
 254                 int map_idx = map->channels == 1 ? map->map[i] - SNDRV_CHMAP_MONO :
 255                                                    map->map[i] - SNDRV_CHMAP_FL;
 256
 257                 /* make sure the reported channel map is the real one, so write the map */
 258                 if (dd->channel_mic_map[map_idx].ds_pos)
 259                         cfgr_val |= MCHP_PDMC_CFGR_PDMSEL(i);
 260                 if (dd->channel_mic_map[map_idx].clk_edge)
 261                         cfgr_val |= MCHP_PDMC_CFGR_BSSEL(i);
 262
 263                 ucontrol->value.integer.value[i] = map->map[i];
 264         }
 265
 266         regmap_write(dd->regmap, MCHP_PDMC_CFGR, cfgr_val);
 267
 268         return 0;
 269 }
 270
 271 static int mchp_pdmc_chmap_ctl_put(struct snd_kcontrol *kcontrol,
 272                                    struct snd_ctl_elem_value *ucontrol)
 273 {
 274         struct mchp_pdmc_chmap *info = snd_kcontrol_chip(kcontrol);
 275         struct mchp_pdmc *dd = info->dd;
 276         unsigned int idx = snd_ctl_get_ioffidx(kcontrol, &ucontrol->id);
 277         struct snd_pcm_substream *substream;
 278         struct snd_pcm_chmap_elem *map;
 279         u32 cfgr_val = 0;
 280         int i;
 281
 282         if (!info->chmap)
 283                 return -EINVAL;
 284         substream = mchp_pdmc_chmap_substream(info, idx);
 285         if (!substream)
 286                 return -ENODEV;
 287
 288         map = mchp_pdmc_chmap_get(substream, info);
 289         if (!map)
 290                 return -EINVAL;
 291
 292         for (i = 0; i < map->channels; i++) {
 293                 int map_idx;
 294
 295                 map->map[i] = ucontrol->value.integer.value[i];
 296                 map_idx = map->channels == 1 ? map->map[i] - SNDRV_CHMAP_MONO :
 297                                                map->map[i] - SNDRV_CHMAP_FL;
 298
 299                 /* configure IP for the desired channel map */
 300                 if (dd->channel_mic_map[map_idx].ds_pos)
 301                         cfgr_val |= MCHP_PDMC_CFGR_PDMSEL(i);
 302                 if (dd->channel_mic_map[map_idx].clk_edge)
 303                         cfgr_val |= MCHP_PDMC_CFGR_BSSEL(i);
 304         }
 305
 306         regmap_write(dd->regmap, MCHP_PDMC_CFGR, cfgr_val);
 307
 308         return 0;
 309 }
 310
 311 static void mchp_pdmc_chmap_ctl_private_free(struct snd_kcontrol *kcontrol)
 312 {
 313         struct mchp_pdmc_chmap *info = snd_kcontrol_chip(kcontrol);
 314
 315         info->pcm->streams[SNDRV_PCM_STREAM_CAPTURE].chmap_kctl = NULL;
 316         kfree(info);
 317 }
 318
 319 static int mchp_pdmc_chmap_ctl_tlv(struct snd_kcontrol *kcontrol, int op_flag,
 320                                    unsigned int size, unsigned int __user *tlv)
 321 {
 322         struct mchp_pdmc_chmap *info = snd_kcontrol_chip(kcontrol);
 323         const struct snd_pcm_chmap_elem *map;
 324         unsigned int __user *dst;
 325         int c, count = 0;
 326
 327         if (!info->chmap)
 328                 return -EINVAL;
 329         if (size < 8)
 330                 return -ENOMEM;
 331         if (put_user(SNDRV_CTL_TLVT_CONTAINER, tlv))
 332                 return -EFAULT;
 333         size -= 8;
 334         dst = tlv + 2;
 335         for (map = info->chmap; map->channels; map++) {
 336                 int chs_bytes = map->channels * 4;
 337
 338                 if (size < 8)
 339                         return -ENOMEM;
 340                 if (put_user(SNDRV_CTL_TLVT_CHMAP_VAR, dst) ||
 341                     put_user(chs_bytes, dst + 1))
 342                         return -EFAULT;
 343                 dst += 2;
 344                 size -= 8;
 345                 count += 8;
 346                 if (size < chs_bytes)
 347                         return -ENOMEM;
 348                 size -= chs_bytes;
 349                 count += chs_bytes;
 350                 for (c = 0; c < map->channels; c++) {
 351                         if (put_user(map->map[c], dst))
 352                                 return -EFAULT;
 353                         dst++;
 354                 }
 355         }
 356         if (put_user(count, tlv + 1))
 357                 return -EFAULT;
 358         return 0;
 359 }
 360
 361 static const struct snd_kcontrol_new mchp_pdmc_snd_controls[] = {
 362         SOC_SINGLE_BOOL_EXT("Audio Filter", 0, &mchp_pdmc_af_get, &mchp_pdmc_af_put),
 363         {
 364                 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
 365                 .name = "SINC Filter Order",
 366                 .info = snd_soc_info_enum_double,
 367                 .get = mchp_pdmc_sinc_order_get,
 368                 .put = mchp_pdmc_sinc_order_put,
 369                 .private_value = (unsigned long)&mchp_pdmc_sinc_filter_order_enum,
 370         },
 371 };
 372
 373 static int mchp_pdmc_close(struct snd_soc_component *component,
 374                            struct snd_pcm_substream *substream)
 375 {
 376         return snd_soc_add_component_controls(component, mchp_pdmc_snd_controls,
 377                                               ARRAY_SIZE(mchp_pdmc_snd_controls));
 378 }
 379
 380 static int mchp_pdmc_open(struct snd_soc_component *component,
 381                           struct snd_pcm_substream *substream)
 382 {
 383         int i;
 384
 385         /* remove controls that can't be changed at runtime */
 386         for (i = 0; i < ARRAY_SIZE(mchp_pdmc_snd_controls); i++) {
 387                 const struct snd_kcontrol_new *control = &mchp_pdmc_snd_controls[i];
 388                 struct snd_ctl_elem_id id;
 389                 struct snd_kcontrol *kctl;
 390                 int err;
 391
 392                 if (component->name_prefix)
 393                         snprintf(id.name, sizeof(id.name), "%s %s", component->name_prefix,
 394                                  control->name);
 395                 else
 396                         strscpy(id.name, control->name, sizeof(id.name));
 397
 398                 id.numid = 0;
 399                 id.iface = control->iface;
 400                 id.device = control->device;
 401                 id.subdevice = control->subdevice;
 402                 id.index = control->index;
 403                 kctl = snd_ctl_find_id(component->card->snd_card, &id);
 404                 if (!kctl) {
 405                         dev_err(component->dev, "Failed to find %s\n", control->name);
 406                         continue;
 407                 }
 408                 err = snd_ctl_remove(component->card->snd_card, kctl);
 409                 if (err < 0) {
 410                         dev_err(component->dev, "%d: Failed to remove %s\n", err,
 411                                 control->name);
 412                         continue;
 413                 }
 414         }
 415
 416         return 0;
 417 }
 418
 419 static const struct snd_soc_component_driver mchp_pdmc_dai_component = {
 420         .name = "mchp-pdmc",
 421         .controls = mchp_pdmc_snd_controls,
 422         .num_controls = ARRAY_SIZE(mchp_pdmc_snd_controls),
 423         .open = &mchp_pdmc_open,
 424         .close = &mchp_pdmc_close,
 425         .legacy_dai_naming = 1,
 426         .start_dma_last = 1,
 427 };
 428
 429 static const unsigned int mchp_pdmc_1mic[] = {1};
 430 static const unsigned int mchp_pdmc_2mic[] = {1, 2};
 431 static const unsigned int mchp_pdmc_3mic[] = {1, 2, 3};
 432 static const unsigned int mchp_pdmc_4mic[] = {1, 2, 3, 4};
 433
 434 static const struct snd_pcm_hw_constraint_list mchp_pdmc_chan_constr[] = {
 435         {
 436                 .list = mchp_pdmc_1mic,
 437                 .count = ARRAY_SIZE(mchp_pdmc_1mic),
 438         },
 439         {
 440                 .list = mchp_pdmc_2mic,
 441                 .count = ARRAY_SIZE(mchp_pdmc_2mic),
 442         },
 443         {
 444                 .list = mchp_pdmc_3mic,
 445                 .count = ARRAY_SIZE(mchp_pdmc_3mic),
 446         },
 447         {
 448                 .list = mchp_pdmc_4mic,
 449                 .count = ARRAY_SIZE(mchp_pdmc_4mic),
 450         },
 451 };
 452
 453 static int mchp_pdmc_startup(struct snd_pcm_substream *substream,
 454                              struct snd_soc_dai *dai)
 455 {
 456         struct mchp_pdmc *dd = snd_soc_dai_get_drvdata(dai);
 457
 458         regmap_write(dd->regmap, MCHP_PDMC_CR, MCHP_PDMC_CR_SWRST);
 459
 460         snd_pcm_hw_constraint_list(substream->runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
 461                                    &mchp_pdmc_chan_constr[dd->mic_no - 1]);
 462
 463         return 0;
 464 }
 465
 466 static int mchp_pdmc_dai_probe(struct snd_soc_dai *dai)
 467 {
 468         struct mchp_pdmc *dd = snd_soc_dai_get_drvdata(dai);
 469
 470         snd_soc_dai_init_dma_data(dai, NULL, &dd->addr);
 471
 472         return 0;
 473 }
 474
 475 static int mchp_pdmc_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
 476 {
 477         unsigned int fmt_master = fmt & SND_SOC_DAIFMT_MASTER_MASK;
 478         unsigned int fmt_format = fmt & SND_SOC_DAIFMT_FORMAT_MASK;
 479
 480         /* IP needs to be bitclock master */
 481         if (fmt_master != SND_SOC_DAIFMT_BP_FP &&
 482             fmt_master != SND_SOC_DAIFMT_BP_FC)
 483                 return -EINVAL;
 484
 485         /* IP supports only PDM interface */
 486         if (fmt_format != SND_SOC_DAIFMT_PDM)
 487                 return -EINVAL;
 488
 489         return 0;
 490 }
 491
 492 static u32 mchp_pdmc_mr_set_osr(int audio_filter_en, unsigned int osr)
 493 {
 494         if (audio_filter_en) {
 495                 switch (osr) {
 496                 case 64:
 497                         return MCHP_PDMC_MR_OSR64;
 498                 case 128:
 499                         return MCHP_PDMC_MR_OSR128;
 500                 case 256:
 501                         return MCHP_PDMC_MR_OSR256;
 502                 }
 503         } else {
 504                 switch (osr) {
 505                 case 8:
 506                         return MCHP_PDMC_MR_SINC_OSR_8;
 507                 case 16:
 508                         return MCHP_PDMC_MR_SINC_OSR_16;
 509                 case 32:
 510                         return MCHP_PDMC_MR_SINC_OSR_32;
 511                 case 64:
 512                         return MCHP_PDMC_MR_SINC_OSR_64;
 513                 case 128:
 514                         return MCHP_PDMC_MR_SINC_OSR_128;
 515                 case 256:
 516                         return MCHP_PDMC_MR_SINC_OSR_256;
 517                 }
 518         }
 519         return 0;
 520 }
 521
 522 static inline int mchp_pdmc_period_to_maxburst(int period_size)
 523 {
 524         if (!(period_size % 8))
 525                 return 8;
 526         if (!(period_size % 4))
 527                 return 4;
 528         if (!(period_size % 2))
 529                 return 2;
 530         return 1;
 531 }
 532
 533 static struct snd_pcm_chmap_elem mchp_pdmc_std_chmaps[] = {
 534         { .channels = 1,
 535           .map = { SNDRV_CHMAP_MONO } },
 536         { .channels = 2,
 537           .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR } },
 538         { .channels = 3,
 539           .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR,
 540                    SNDRV_CHMAP_RL } },
 541         { .channels = 4,
 542           .map = { SNDRV_CHMAP_FL, SNDRV_CHMAP_FR,
 543                    SNDRV_CHMAP_RL, SNDRV_CHMAP_RR } },
 544         { }
 545 };
 546
 547 static int mchp_pdmc_hw_params(struct snd_pcm_substream *substream,
 548                                struct snd_pcm_hw_params *params,
 549                                struct snd_soc_dai *dai)
 550 {
 551         struct mchp_pdmc *dd = snd_soc_dai_get_drvdata(dai);
 552         struct snd_soc_component *comp = dai->component;
 553         unsigned long gclk_rate = 0;
 554         unsigned long best_diff_rate = ~0UL;
 555         unsigned int channels = params_channels(params);
 556         unsigned int osr = 0, osr_start;
 557         unsigned int fs = params_rate(params);
 558         u32 mr_val = 0;
 559         u32 cfgr_val = 0;
 560         int i;
 561         int ret;
 562
 563         dev_dbg(comp->dev, "%s() rate=%u format=%#x width=%u channels=%u\n",
 564                 __func__, params_rate(params), params_format(params),
 565                 params_width(params), params_channels(params));
 566
 567         if (channels > dd->mic_no) {
 568                 dev_err(comp->dev, "more channels %u than microphones %d\n",
 569                         channels, dd->mic_no);
 570                 return -EINVAL;
 571         }
 572
 573         dd->pdmcen = 0;
 574         for (i = 0; i < channels; i++) {
 575                 dd->pdmcen |= MCHP_PDMC_MR_PDMCEN(i);
 576                 if (dd->channel_mic_map[i].ds_pos)
 577                         cfgr_val |= MCHP_PDMC_CFGR_PDMSEL(i);
 578                 if (dd->channel_mic_map[i].clk_edge)
 579                         cfgr_val |= MCHP_PDMC_CFGR_BSSEL(i);
 580         }
 581
 582         for (osr_start = dd->audio_filter_en ? 64 : 8;
 583              osr_start <= 256 && best_diff_rate; osr_start *= 2) {
 584                 long round_rate;
 585                 unsigned long diff_rate;
 586
 587                 round_rate = clk_round_rate(dd->gclk,
 588                                             (unsigned long)fs * 16 * osr_start);
 589                 if (round_rate < 0)
 590                         continue;
 591                 diff_rate = abs((fs * 16 * osr_start) - round_rate);
 592                 if (diff_rate < best_diff_rate) {
 593                         best_diff_rate = diff_rate;
 594                         osr = osr_start;
 595                         gclk_rate = fs * 16 * osr;
 596                 }
 597         }
 598         if (!gclk_rate) {
 599                 dev_err(comp->dev, "invalid sampling rate: %u\n", fs);
 600                 return -EINVAL;
 601         }
 602
 603         /* CLK is enabled by runtime PM. */
 604         clk_disable_unprepare(dd->gclk);
 605
 606         /* set the rate */
 607         ret = clk_set_rate(dd->gclk, gclk_rate);
 608         clk_prepare_enable(dd->gclk);
 609         if (ret) {
 610                 dev_err(comp->dev, "unable to set rate %lu to GCLK: %d\n",
 611                         gclk_rate, ret);
 612                 return ret;
 613         }
 614
 615         mr_val |= mchp_pdmc_mr_set_osr(dd->audio_filter_en, osr);
 616
 617         mr_val |= FIELD_PREP(MCHP_PDMC_MR_SINCORDER_MASK, dd->sinc_order);
 618
 619         dd->addr.maxburst = mchp_pdmc_period_to_maxburst(snd_pcm_lib_period_bytes(substream));
 620         mr_val |= FIELD_PREP(MCHP_PDMC_MR_CHUNK_MASK, dd->addr.maxburst);
 621         dev_dbg(comp->dev, "maxburst set to %d\n", dd->addr.maxburst);
 622
 623         snd_soc_component_update_bits(comp, MCHP_PDMC_MR,
 624                                       MCHP_PDMC_MR_OSR_MASK |
 625                                       MCHP_PDMC_MR_SINCORDER_MASK |
 626                                       MCHP_PDMC_MR_SINC_OSR_MASK |
 627                                       MCHP_PDMC_MR_CHUNK_MASK, mr_val);
 628
 629         snd_soc_component_write(comp, MCHP_PDMC_CFGR, cfgr_val);
 630
 631         return 0;
 632 }
 633
 634 static void mchp_pdmc_noise_filter_workaround(struct mchp_pdmc *dd)
 635 {
 636         u32 tmp, steps = 16;
 637
 638         /*
 639          * PDMC doesn't wait for microphones' startup time thus the acquisition
 640          * may start before the microphones are ready leading to poc noises at
 641          * the beginning of capture. To avoid this, we need to wait 50ms (in
 642          * normal startup procedure) or 150 ms (worst case after resume from sleep
 643          * states) after microphones are enabled and then clear the FIFOs (by
 644          * reading the RHR 16 times) and possible interrupts before continuing.
 645          * Also, for this to work the DMA needs to be started after interrupts
 646          * are enabled.
 647          */
 648         usleep_range(dd->startup_delay_us, dd->startup_delay_us + 5);
 649
 650         while (steps--)
 651                 regmap_read(dd->regmap, MCHP_PDMC_RHR, &tmp);
 652
 653         /* Clear interrupts. */
 654         regmap_read(dd->regmap, MCHP_PDMC_ISR, &tmp);
 655 }
 656
 657 static int mchp_pdmc_trigger(struct snd_pcm_substream *substream,
 658                              int cmd, struct snd_soc_dai *dai)
 659 {
 660         struct mchp_pdmc *dd = snd_soc_dai_get_drvdata(dai);
 661         struct snd_soc_component *cpu = dai->component;
 662 #ifdef DEBUG
 663         u32 val;
 664 #endif
 665
 666         switch (cmd) {
 667         case SNDRV_PCM_TRIGGER_RESUME:
 668         case SNDRV_PCM_TRIGGER_START:
 669         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
 670                 snd_soc_component_update_bits(cpu, MCHP_PDMC_MR,
 671                                               MCHP_PDMC_MR_PDMCEN_MASK,
 672                                               dd->pdmcen);
 673
 674                 mchp_pdmc_noise_filter_workaround(dd);
 675
 676                 /* Enable interrupts. */
 677                 regmap_write(dd->regmap, MCHP_PDMC_IER, dd->suspend_irq |
 678                              MCHP_PDMC_IR_RXOVR | MCHP_PDMC_IR_RXUDR);
 679                 dd->suspend_irq = 0;
 680                 break;
 681         case SNDRV_PCM_TRIGGER_SUSPEND:
 682                 regmap_read(dd->regmap, MCHP_PDMC_IMR, &dd->suspend_irq);
 683                 fallthrough;
 684         case SNDRV_PCM_TRIGGER_STOP:
 685                 /* Disable overrun and underrun error interrupts */
 686                 regmap_write(dd->regmap, MCHP_PDMC_IDR, dd->suspend_irq |
 687                              MCHP_PDMC_IR_RXOVR | MCHP_PDMC_IR_RXUDR);
 688                 fallthrough;
 689         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
 690                 snd_soc_component_update_bits(cpu, MCHP_PDMC_MR,
 691                                               MCHP_PDMC_MR_PDMCEN_MASK, 0);
 692                 break;
 693         default:
 694                 return -EINVAL;
 695         }
 696
 697 #ifdef DEBUG
 698         regmap_read(dd->regmap, MCHP_PDMC_MR, &val);
 699         dev_dbg(dd->dev, "MR (0x%02x): 0x%08x\n", MCHP_PDMC_MR, val);
 700         regmap_read(dd->regmap, MCHP_PDMC_CFGR, &val);
 701         dev_dbg(dd->dev, "CFGR (0x%02x): 0x%08x\n", MCHP_PDMC_CFGR, val);
 702         regmap_read(dd->regmap, MCHP_PDMC_IMR, &val);
 703         dev_dbg(dd->dev, "IMR (0x%02x): 0x%08x\n", MCHP_PDMC_IMR, val);
 704 #endif
 705
 706         return 0;
 707 }
 708
 709 static const struct snd_soc_dai_ops mchp_pdmc_dai_ops = {
 710         .set_fmt        = mchp_pdmc_set_fmt,
 711         .startup        = mchp_pdmc_startup,
 712         .hw_params      = mchp_pdmc_hw_params,
 713         .trigger        = mchp_pdmc_trigger,
 714 };
 715
 716 static int mchp_pdmc_add_chmap_ctls(struct snd_pcm *pcm, struct mchp_pdmc *dd)
 717 {
 718         struct mchp_pdmc_chmap *info;
 719         struct snd_kcontrol_new knew = {
 720                 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
 721                 .access = SNDRV_CTL_ELEM_ACCESS_READWRITE |
 722                         SNDRV_CTL_ELEM_ACCESS_TLV_READ |
 723                         SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK,
 724                 .info = mchp_pdmc_chmap_ctl_info,
 725                 .get = mchp_pdmc_chmap_ctl_get,
 726                 .put = mchp_pdmc_chmap_ctl_put,
 727                 .tlv.c = mchp_pdmc_chmap_ctl_tlv,
 728         };
 729         int err;
 730
 731         if (WARN_ON(pcm->streams[SNDRV_PCM_STREAM_CAPTURE].chmap_kctl))
 732                 return -EBUSY;
 733         info = kzalloc(sizeof(*info), GFP_KERNEL);
 734         if (!info)
 735                 return -ENOMEM;
 736         info->pcm = pcm;
 737         info->dd = dd;
 738         info->chmap = mchp_pdmc_std_chmaps;
 739         knew.name = "Capture Channel Map";
 740         knew.device = pcm->device;
 741         knew.count = pcm->streams[SNDRV_PCM_STREAM_CAPTURE].substream_count;
 742         info->kctl = snd_ctl_new1(&knew, info);
 743         if (!info->kctl) {
 744                 kfree(info);
 745                 return -ENOMEM;
 746         }
 747         info->kctl->private_free = mchp_pdmc_chmap_ctl_private_free;
 748         err = snd_ctl_add(pcm->card, info->kctl);
 749         if (err < 0)
 750                 return err;
 751         pcm->streams[SNDRV_PCM_STREAM_CAPTURE].chmap_kctl = info->kctl;
 752         return 0;
 753 }
 754
 755 static int mchp_pdmc_pcm_new(struct snd_soc_pcm_runtime *rtd,
 756                              struct snd_soc_dai *dai)
 757 {
 758         struct mchp_pdmc *dd = snd_soc_dai_get_drvdata(dai);
 759         int ret;
 760
 761         ret = mchp_pdmc_add_chmap_ctls(rtd->pcm, dd);
 762         if (ret < 0)
 763                 dev_err(dd->dev, "failed to add channel map controls: %d\n", ret);
 764
 765         return ret;
 766 }
 767
 768 static struct snd_soc_dai_driver mchp_pdmc_dai = {
 769         .probe  = mchp_pdmc_dai_probe,
 770         .capture = {
 771                 .stream_name    = "Capture",
 772                 .channels_min   = 1,
 773                 .channels_max   = 4,
 774                 .rate_min       = 8000,
 775                 .rate_max       = 192000,
 776                 .rates          = SNDRV_PCM_RATE_KNOT,
 777                 .formats        = SNDRV_PCM_FMTBIT_S24_LE,
 778         },
 779         .ops = &mchp_pdmc_dai_ops,
 780         .pcm_new = &mchp_pdmc_pcm_new,
 781 };
 782
 783 /* PDMC interrupt handler */
 784 static irqreturn_t mchp_pdmc_interrupt(int irq, void *dev_id)
 785 {
 786         struct mchp_pdmc *dd = dev_id;
 787         u32 isr, msr, pending;
 788         irqreturn_t ret = IRQ_NONE;
 789
 790         regmap_read(dd->regmap, MCHP_PDMC_ISR, &isr);
 791         regmap_read(dd->regmap, MCHP_PDMC_IMR, &msr);
 792
 793         pending = isr & msr;
 794         dev_dbg(dd->dev, "ISR (0x%02x): 0x%08x, IMR (0x%02x): 0x%08x, pending: 0x%08x\n",
 795                 MCHP_PDMC_ISR, isr, MCHP_PDMC_IMR, msr, pending);
 796         if (!pending)
 797                 return IRQ_NONE;
 798
 799         if (pending & MCHP_PDMC_IR_RXUDR) {
 800                 dev_warn(dd->dev, "underrun detected\n");
 801                 regmap_write(dd->regmap, MCHP_PDMC_IDR, MCHP_PDMC_IR_RXUDR);
 802                 ret = IRQ_HANDLED;
 803         }
 804         if (pending & MCHP_PDMC_IR_RXOVR) {
 805                 dev_warn(dd->dev, "overrun detected\n");
 806                 regmap_write(dd->regmap, MCHP_PDMC_IDR, MCHP_PDMC_IR_RXOVR);
 807                 ret = IRQ_HANDLED;
 808         }
 809
 810         return ret;
 811 }
 812
 813 /* regmap configuration */
 814 static bool mchp_pdmc_readable_reg(struct device *dev, unsigned int reg)
 815 {
 816         switch (reg) {
 817         case MCHP_PDMC_MR:
 818         case MCHP_PDMC_CFGR:
 819         case MCHP_PDMC_IMR:
 820         case MCHP_PDMC_ISR:
 821         case MCHP_PDMC_RHR:
 822         case MCHP_PDMC_VER:
 823                 return true;
 824         default:
 825                 return false;
 826         }
 827 }
 828
 829 static bool mchp_pdmc_writeable_reg(struct device *dev, unsigned int reg)
 830 {
 831         switch (reg) {
 832         case MCHP_PDMC_CR:
 833         case MCHP_PDMC_MR:
 834         case MCHP_PDMC_CFGR:
 835         case MCHP_PDMC_IER:
 836         case MCHP_PDMC_IDR:
 837                 return true;
 838         default:
 839                 return false;
 840         }
 841 }
 842
 843 static bool mchp_pdmc_volatile_reg(struct device *dev, unsigned int reg)
 844 {
 845         switch (reg) {
 846         case MCHP_PDMC_ISR:
 847         case MCHP_PDMC_RHR:
 848                 return true;
 849         default:
 850                 return false;
 851         }
 852 }
 853
 854 static bool mchp_pdmc_precious_reg(struct device *dev, unsigned int reg)
 855 {
 856         switch (reg) {
 857         case MCHP_PDMC_RHR:
 858         case MCHP_PDMC_ISR:
 859                 return true;
 860         default:
 861                 return false;
 862         }
 863 }
 864
 865 static const struct regmap_config mchp_pdmc_regmap_config = {
 866         .reg_bits       = 32,
 867         .reg_stride     = 4,
 868         .val_bits       = 32,
 869         .max_register   = MCHP_PDMC_VER,
 870         .readable_reg   = mchp_pdmc_readable_reg,
 871         .writeable_reg  = mchp_pdmc_writeable_reg,
 872         .precious_reg   = mchp_pdmc_precious_reg,
 873         .volatile_reg   = mchp_pdmc_volatile_reg,
 874         .cache_type     = REGCACHE_FLAT,
 875 };
 876
 877 static int mchp_pdmc_dt_init(struct mchp_pdmc *dd)
 878 {
 879         struct device_node *np = dd->dev->of_node;
 880         bool mic_ch[MCHP_PDMC_DS_NO][MCHP_PDMC_EDGE_NO] = {0};
 881         int i;
 882         int ret;
 883
 884         if (!np) {
 885                 dev_err(dd->dev, "device node not found\n");
 886                 return -EINVAL;
 887         }
 888
 889         dd->mic_no = of_property_count_u32_elems(np, "microchip,mic-pos");
 890         if (dd->mic_no < 0) {
 891                 dev_err(dd->dev, "failed to get microchip,mic-pos: %d",
 892                         dd->mic_no);
 893                 return dd->mic_no;
 894         }
 895         if (!dd->mic_no || dd->mic_no % 2 ||
 896             dd->mic_no / 2 > MCHP_PDMC_MAX_CHANNELS) {
 897                 dev_err(dd->dev, "invalid array length for microchip,mic-pos: %d",
 898                         dd->mic_no);
 899                 return -EINVAL;
 900         }
 901
 902         dd->mic_no /= 2;
 903
 904         dev_info(dd->dev, "%d PDM microphones declared\n", dd->mic_no);
 905
 906         /*
 907          * by default, we consider the order of microphones in
 908          * microchip,mic-pos to be the same with the channel mapping;
 909          * 1st microphone channel 0, 2nd microphone channel 1, etc.
 910          */
 911         for (i = 0; i < dd->mic_no; i++) {
 912                 int ds;
 913                 int edge;
 914
 915                 ret = of_property_read_u32_index(np, "microchip,mic-pos", i * 2,
 916                                                  &ds);
 917                 if (ret) {
 918                         dev_err(dd->dev,
 919                                 "failed to get value no %d value from microchip,mic-pos: %d",
 920                                 i * 2, ret);
 921                         return ret;
 922                 }
 923                 if (ds >= MCHP_PDMC_DS_NO) {
 924                         dev_err(dd->dev,
 925                                 "invalid DS index in microchip,mic-pos array: %d",
 926                                 ds);
 927                         return -EINVAL;
 928                 }
 929
 930                 ret = of_property_read_u32_index(np, "microchip,mic-pos", i * 2 + 1,
 931                                                  &edge);
 932                 if (ret) {
 933                         dev_err(dd->dev,
 934                                 "failed to get value no %d value from microchip,mic-pos: %d",
 935                                 i * 2 + 1, ret);
 936                         return ret;
 937                 }
 938
 939                 if (edge != MCHP_PDMC_CLK_POSITIVE &&
 940                     edge != MCHP_PDMC_CLK_NEGATIVE) {
 941                         dev_err(dd->dev,
 942                                 "invalid edge in microchip,mic-pos array: %d", edge);
 943                         return -EINVAL;
 944                 }
 945                 if (mic_ch[ds][edge]) {
 946                         dev_err(dd->dev,
 947                                 "duplicated mic (DS %d, edge %d) in microchip,mic-pos array",
 948                                 ds, edge);
 949                         return -EINVAL;
 950                 }
 951                 mic_ch[ds][edge] = true;
 952                 dd->channel_mic_map[i].ds_pos = ds;
 953                 dd->channel_mic_map[i].clk_edge = edge;
 954         }
 955
 956         dd->startup_delay_us = 150000;
 957         of_property_read_u32(np, "microchip,startup-delay-us", &dd->startup_delay_us);
 958
 959         return 0;
 960 }
 961
 962 /* used to clean the channel index found on RHR's MSB */
 963 static int mchp_pdmc_process(struct snd_pcm_substream *substream,
 964                              int channel, unsigned long hwoff,
 965                              void *buf, unsigned long bytes)
 966 {
 967         struct snd_pcm_runtime *runtime = substream->runtime;
 968         u8 *dma_ptr = runtime->dma_area + hwoff +
 969                       channel * (runtime->dma_bytes / runtime->channels);
 970         u8 *dma_ptr_end = dma_ptr + bytes;
 971         unsigned int sample_size = samples_to_bytes(runtime, 1);
 972
 973         for (; dma_ptr < dma_ptr_end; dma_ptr += sample_size)
 974                 *dma_ptr = 0;
 975
 976         return 0;
 977 }
 978
 979 static struct snd_dmaengine_pcm_config mchp_pdmc_config = {
 980         .process = mchp_pdmc_process,
 981         .prepare_slave_config = snd_dmaengine_pcm_prepare_slave_config,
 982 };
 983
 984 static int mchp_pdmc_runtime_suspend(struct device *dev)
 985 {
 986         struct mchp_pdmc *dd = dev_get_drvdata(dev);
 987
 988         regcache_cache_only(dd->regmap, true);
 989
 990         clk_disable_unprepare(dd->gclk);
 991         clk_disable_unprepare(dd->pclk);
 992
 993         return 0;
 994 }
 995
 996 static int mchp_pdmc_runtime_resume(struct device *dev)
 997 {
 998         struct mchp_pdmc *dd = dev_get_drvdata(dev);
 999         int ret;
1000
1001         ret = clk_prepare_enable(dd->pclk);
1002         if (ret) {
1003                 dev_err(dd->dev,
1004                         "failed to enable the peripheral clock: %d\n", ret);
1005                 return ret;
1006         }
1007         ret = clk_prepare_enable(dd->gclk);
1008         if (ret) {
1009                 dev_err(dd->dev,
1010                         "failed to enable generic clock: %d\n", ret);
1011                 goto disable_pclk;
1012         }
1013
1014         regcache_cache_only(dd->regmap, false);
1015         regcache_mark_dirty(dd->regmap);
1016         ret = regcache_sync(dd->regmap);
1017         if (ret) {
1018                 regcache_cache_only(dd->regmap, true);
1019                 clk_disable_unprepare(dd->gclk);
1020 disable_pclk:
1021                 clk_disable_unprepare(dd->pclk);
1022         }
1023
1024         return ret;
1025 }
1026
1027 static int mchp_pdmc_probe(struct platform_device *pdev)
1028 {
1029         struct device *dev = &pdev->dev;
1030         struct mchp_pdmc *dd;
1031         struct resource *res;
1032         void __iomem *io_base;
1033         u32 version;
1034         int irq;
1035         int ret;
1036
1037         dd = devm_kzalloc(dev, sizeof(*dd), GFP_KERNEL);
1038         if (!dd)
1039                 return -ENOMEM;
1040
1041         dd->dev = &pdev->dev;
1042         ret = mchp_pdmc_dt_init(dd);
1043         if (ret < 0)
1044                 return ret;
1045
1046         irq = platform_get_irq(pdev, 0);
1047         if (irq < 0)
1048                 return irq;
1049
1050         dd->pclk = devm_clk_get(dev, "pclk");
1051         if (IS_ERR(dd->pclk)) {
1052                 ret = PTR_ERR(dd->pclk);
1053                 dev_err(dev, "failed to get peripheral clock: %d\n", ret);
1054                 return ret;
1055         }
1056
1057         dd->gclk = devm_clk_get(dev, "gclk");
1058         if (IS_ERR(dd->gclk)) {
1059                 ret = PTR_ERR(dd->gclk);
1060                 dev_err(dev, "failed to get GCK: %d\n", ret);
1061                 return ret;
1062         }
1063
1064         io_base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
1065         if (IS_ERR(io_base)) {
1066                 ret = PTR_ERR(io_base);
1067                 dev_err(dev, "failed to remap register memory: %d\n", ret);
1068                 return ret;
1069         }
1070
1071         dd->regmap = devm_regmap_init_mmio(dev, io_base,
1072                                            &mchp_pdmc_regmap_config);
1073         if (IS_ERR(dd->regmap)) {
1074                 ret = PTR_ERR(dd->regmap);
1075                 dev_err(dev, "failed to init register map: %d\n", ret);
1076                 return ret;
1077         }
1078
1079         ret = devm_request_irq(dev, irq, mchp_pdmc_interrupt, 0,
1080                                dev_name(&pdev->dev), dd);
1081         if (ret < 0) {
1082                 dev_err(dev, "can't register ISR for IRQ %u (ret=%i)\n",
1083                         irq, ret);
1084                 return ret;
1085         }
1086
1087         /* by default audio filter is enabled and the SINC Filter order
1088          * will be set to the recommended value, 3
1089          */
1090         dd->audio_filter_en = true;
1091         dd->sinc_order = 3;
1092
1093         dd->addr.addr = (dma_addr_t)res->start + MCHP_PDMC_RHR;
1094         platform_set_drvdata(pdev, dd);
1095
1096         pm_runtime_enable(dd->dev);
1097         if (!pm_runtime_enabled(dd->dev)) {
1098                 ret = mchp_pdmc_runtime_resume(dd->dev);
1099                 if (ret)
1100                         return ret;
1101         }
1102
1103         /* register platform */
1104         ret = devm_snd_dmaengine_pcm_register(dev, &mchp_pdmc_config, 0);
1105         if (ret) {
1106                 dev_err(dev, "could not register platform: %d\n", ret);
1107                 goto pm_runtime_suspend;
1108         }
1109
1110         ret = devm_snd_soc_register_component(dev, &mchp_pdmc_dai_component,
1111                                               &mchp_pdmc_dai, 1);
1112         if (ret) {
1113                 dev_err(dev, "could not register CPU DAI: %d\n", ret);
1114                 goto pm_runtime_suspend;
1115         }
1116
1117         /* print IP version */
1118         regmap_read(dd->regmap, MCHP_PDMC_VER, &version);
1119         dev_info(dd->dev, "hw version: %#lx\n",
1120                  version & MCHP_PDMC_VER_VERSION);
1121
1122         return 0;
1123
1124 pm_runtime_suspend:
1125         if (!pm_runtime_status_suspended(dd->dev))
1126                 mchp_pdmc_runtime_suspend(dd->dev);
1127         pm_runtime_disable(dd->dev);
1128
1129         return ret;
1130 }
1131
1132 static void mchp_pdmc_remove(struct platform_device *pdev)
1133 {
1134         struct mchp_pdmc *dd = platform_get_drvdata(pdev);
1135
1136         if (!pm_runtime_status_suspended(dd->dev))
1137                 mchp_pdmc_runtime_suspend(dd->dev);
1138
1139         pm_runtime_disable(dd->dev);
1140 }
1141
1142 static const struct of_device_id mchp_pdmc_of_match[] = {
1143         {
1144                 .compatible = "microchip,sama7g5-pdmc",
1145         }, {
1146                 /* sentinel */
1147         }
1148 };
1149 MODULE_DEVICE_TABLE(of, mchp_pdmc_of_match);
1150
1151 static const struct dev_pm_ops mchp_pdmc_pm_ops = {
1152         SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, pm_runtime_force_resume)
1153         RUNTIME_PM_OPS(mchp_pdmc_runtime_suspend, mchp_pdmc_runtime_resume,
1154                        NULL)
1155 };
1156
1157 static struct platform_driver mchp_pdmc_driver = {
1158         .driver = {
1159                 .name           = "mchp-pdmc",
1160                 .of_match_table = of_match_ptr(mchp_pdmc_of_match),
1161                 .pm             = pm_ptr(&mchp_pdmc_pm_ops),
1162         },
1163         .probe  = mchp_pdmc_probe,
1164         .remove_new = mchp_pdmc_remove,
1165 };
1166 module_platform_driver(mchp_pdmc_driver);
1167
1168 MODULE_DESCRIPTION("Microchip PDMC driver under ALSA SoC architecture");
1169 MODULE_AUTHOR("Codrin Ciubotariu <[email protected]>");
1170 MODULE_LICENSE("GPL v2");