]> Git Repo - linux.git/blob - drivers/gpu/drm/sun4i/sun4i_tv.c
Merge tag 'amd-drm-next-6.5-2023-06-09' of https://gitlab.freedesktop.org/agd5f/linux...
[linux.git] / drivers / gpu / drm / sun4i / sun4i_tv.c
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  * Copyright (C) 2015 Free Electrons
4  * Copyright (C) 2015 NextThing Co
5  *
6  * Maxime Ripard <[email protected]>
7  */
8
9 #include <linux/clk.h>
10 #include <linux/component.h>
11 #include <linux/module.h>
12 #include <linux/of_address.h>
13 #include <linux/platform_device.h>
14 #include <linux/regmap.h>
15 #include <linux/reset.h>
16
17 #include <drm/drm_atomic.h>
18 #include <drm/drm_atomic_helper.h>
19 #include <drm/drm_of.h>
20 #include <drm/drm_panel.h>
21 #include <drm/drm_print.h>
22 #include <drm/drm_probe_helper.h>
23 #include <drm/drm_simple_kms_helper.h>
24
25 #include "sun4i_crtc.h"
26 #include "sun4i_drv.h"
27 #include "sunxi_engine.h"
28
29 #define SUN4I_TVE_EN_REG                0x000
30 #define SUN4I_TVE_EN_DAC_MAP_MASK               GENMASK(19, 4)
31 #define SUN4I_TVE_EN_DAC_MAP(dac, out)          (((out) & 0xf) << (dac + 1) * 4)
32 #define SUN4I_TVE_EN_ENABLE                     BIT(0)
33
34 #define SUN4I_TVE_CFG0_REG              0x004
35 #define SUN4I_TVE_CFG0_DAC_CONTROL_54M          BIT(26)
36 #define SUN4I_TVE_CFG0_CORE_DATAPATH_54M        BIT(25)
37 #define SUN4I_TVE_CFG0_CORE_CONTROL_54M         BIT(24)
38 #define SUN4I_TVE_CFG0_YC_EN                    BIT(17)
39 #define SUN4I_TVE_CFG0_COMP_EN                  BIT(16)
40 #define SUN4I_TVE_CFG0_RES(x)                   ((x) & 0xf)
41 #define SUN4I_TVE_CFG0_RES_480i                 SUN4I_TVE_CFG0_RES(0)
42 #define SUN4I_TVE_CFG0_RES_576i                 SUN4I_TVE_CFG0_RES(1)
43
44 #define SUN4I_TVE_DAC0_REG              0x008
45 #define SUN4I_TVE_DAC0_CLOCK_INVERT             BIT(24)
46 #define SUN4I_TVE_DAC0_LUMA(x)                  (((x) & 3) << 20)
47 #define SUN4I_TVE_DAC0_LUMA_0_4                 SUN4I_TVE_DAC0_LUMA(3)
48 #define SUN4I_TVE_DAC0_CHROMA(x)                (((x) & 3) << 18)
49 #define SUN4I_TVE_DAC0_CHROMA_0_75              SUN4I_TVE_DAC0_CHROMA(3)
50 #define SUN4I_TVE_DAC0_INTERNAL_DAC(x)          (((x) & 3) << 16)
51 #define SUN4I_TVE_DAC0_INTERNAL_DAC_37_5_OHMS   SUN4I_TVE_DAC0_INTERNAL_DAC(3)
52 #define SUN4I_TVE_DAC0_DAC_EN(dac)              BIT(dac)
53
54 #define SUN4I_TVE_NOTCH_REG             0x00c
55 #define SUN4I_TVE_NOTCH_DAC0_TO_DAC_DLY(dac, x) ((4 - (x)) << (dac * 3))
56
57 #define SUN4I_TVE_CHROMA_FREQ_REG       0x010
58
59 #define SUN4I_TVE_PORCH_REG             0x014
60 #define SUN4I_TVE_PORCH_BACK(x)                 ((x) << 16)
61 #define SUN4I_TVE_PORCH_FRONT(x)                (x)
62
63 #define SUN4I_TVE_LINE_REG              0x01c
64 #define SUN4I_TVE_LINE_FIRST(x)                 ((x) << 16)
65 #define SUN4I_TVE_LINE_NUMBER(x)                (x)
66
67 #define SUN4I_TVE_LEVEL_REG             0x020
68 #define SUN4I_TVE_LEVEL_BLANK(x)                ((x) << 16)
69 #define SUN4I_TVE_LEVEL_BLACK(x)                (x)
70
71 #define SUN4I_TVE_DAC1_REG              0x024
72 #define SUN4I_TVE_DAC1_AMPLITUDE(dac, x)        ((x) << (dac * 8))
73
74 #define SUN4I_TVE_DETECT_STA_REG        0x038
75 #define SUN4I_TVE_DETECT_STA_DAC(dac)           BIT((dac * 8))
76 #define SUN4I_TVE_DETECT_STA_UNCONNECTED                0
77 #define SUN4I_TVE_DETECT_STA_CONNECTED                  1
78 #define SUN4I_TVE_DETECT_STA_GROUND                     2
79
80 #define SUN4I_TVE_CB_CR_LVL_REG         0x10c
81 #define SUN4I_TVE_CB_CR_LVL_CR_BURST(x)         ((x) << 8)
82 #define SUN4I_TVE_CB_CR_LVL_CB_BURST(x)         (x)
83
84 #define SUN4I_TVE_TINT_BURST_PHASE_REG  0x110
85 #define SUN4I_TVE_TINT_BURST_PHASE_CHROMA(x)    (x)
86
87 #define SUN4I_TVE_BURST_WIDTH_REG       0x114
88 #define SUN4I_TVE_BURST_WIDTH_BREEZEWAY(x)      ((x) << 16)
89 #define SUN4I_TVE_BURST_WIDTH_BURST_WIDTH(x)    ((x) << 8)
90 #define SUN4I_TVE_BURST_WIDTH_HSYNC_WIDTH(x)    (x)
91
92 #define SUN4I_TVE_CB_CR_GAIN_REG        0x118
93 #define SUN4I_TVE_CB_CR_GAIN_CR(x)              ((x) << 8)
94 #define SUN4I_TVE_CB_CR_GAIN_CB(x)              (x)
95
96 #define SUN4I_TVE_SYNC_VBI_REG          0x11c
97 #define SUN4I_TVE_SYNC_VBI_SYNC(x)              ((x) << 16)
98 #define SUN4I_TVE_SYNC_VBI_VBLANK(x)            (x)
99
100 #define SUN4I_TVE_ACTIVE_LINE_REG       0x124
101 #define SUN4I_TVE_ACTIVE_LINE(x)                (x)
102
103 #define SUN4I_TVE_CHROMA_REG            0x128
104 #define SUN4I_TVE_CHROMA_COMP_GAIN(x)           ((x) & 3)
105 #define SUN4I_TVE_CHROMA_COMP_GAIN_50           SUN4I_TVE_CHROMA_COMP_GAIN(2)
106
107 #define SUN4I_TVE_12C_REG               0x12c
108 #define SUN4I_TVE_12C_NOTCH_WIDTH_WIDE          BIT(8)
109 #define SUN4I_TVE_12C_COMP_YUV_EN               BIT(0)
110
111 #define SUN4I_TVE_RESYNC_REG            0x130
112 #define SUN4I_TVE_RESYNC_FIELD                  BIT(31)
113 #define SUN4I_TVE_RESYNC_LINE(x)                ((x) << 16)
114 #define SUN4I_TVE_RESYNC_PIXEL(x)               (x)
115
116 #define SUN4I_TVE_SLAVE_REG             0x134
117
118 #define SUN4I_TVE_WSS_DATA2_REG         0x244
119
120 struct color_gains {
121         u16     cb;
122         u16     cr;
123 };
124
125 struct burst_levels {
126         u16     cb;
127         u16     cr;
128 };
129
130 struct video_levels {
131         u16     black;
132         u16     blank;
133 };
134
135 struct resync_parameters {
136         bool    field;
137         u16     line;
138         u16     pixel;
139 };
140
141 struct tv_mode {
142         char            *name;
143
144         unsigned int    tv_mode;
145
146         u32             mode;
147         u32             chroma_freq;
148         u16             back_porch;
149         u16             front_porch;
150         u16             vblank_level;
151
152         bool            yc_en;
153         bool            dac3_en;
154         bool            dac_bit25_en;
155
156         const struct color_gains        *color_gains;
157         const struct burst_levels       *burst_levels;
158         const struct video_levels       *video_levels;
159         const struct resync_parameters  *resync_params;
160 };
161
162 struct sun4i_tv {
163         struct drm_connector    connector;
164         struct drm_encoder      encoder;
165
166         struct clk              *clk;
167         struct regmap           *regs;
168         struct reset_control    *reset;
169
170         struct sun4i_drv        *drv;
171 };
172
173 static const struct video_levels ntsc_video_levels = {
174         .black = 282,   .blank = 240,
175 };
176
177 static const struct video_levels pal_video_levels = {
178         .black = 252,   .blank = 252,
179 };
180
181 static const struct burst_levels ntsc_burst_levels = {
182         .cb = 79,       .cr = 0,
183 };
184
185 static const struct burst_levels pal_burst_levels = {
186         .cb = 40,       .cr = 40,
187 };
188
189 static const struct color_gains ntsc_color_gains = {
190         .cb = 160,      .cr = 160,
191 };
192
193 static const struct color_gains pal_color_gains = {
194         .cb = 224,      .cr = 224,
195 };
196
197 static const struct resync_parameters ntsc_resync_parameters = {
198         .field = false, .line = 14,     .pixel = 12,
199 };
200
201 static const struct resync_parameters pal_resync_parameters = {
202         .field = true,  .line = 13,     .pixel = 12,
203 };
204
205 static const struct tv_mode tv_modes[] = {
206         {
207                 .tv_mode        = DRM_MODE_TV_MODE_NTSC,
208                 .mode           = SUN4I_TVE_CFG0_RES_480i,
209                 .chroma_freq    = 0x21f07c1f,
210                 .yc_en          = true,
211                 .dac3_en        = true,
212                 .dac_bit25_en   = true,
213
214                 .back_porch     = 118,
215                 .front_porch    = 32,
216
217                 .vblank_level   = 240,
218
219                 .color_gains    = &ntsc_color_gains,
220                 .burst_levels   = &ntsc_burst_levels,
221                 .video_levels   = &ntsc_video_levels,
222                 .resync_params  = &ntsc_resync_parameters,
223         },
224         {
225                 .tv_mode        = DRM_MODE_TV_MODE_PAL,
226                 .mode           = SUN4I_TVE_CFG0_RES_576i,
227                 .chroma_freq    = 0x2a098acb,
228
229                 .back_porch     = 138,
230                 .front_porch    = 24,
231
232                 .vblank_level   = 252,
233
234                 .color_gains    = &pal_color_gains,
235                 .burst_levels   = &pal_burst_levels,
236                 .video_levels   = &pal_video_levels,
237                 .resync_params  = &pal_resync_parameters,
238         },
239 };
240
241 static inline struct sun4i_tv *
242 drm_encoder_to_sun4i_tv(struct drm_encoder *encoder)
243 {
244         return container_of(encoder, struct sun4i_tv,
245                             encoder);
246 }
247
248 static const struct tv_mode *
249 sun4i_tv_find_tv_by_mode(unsigned int mode)
250 {
251         int i;
252
253         for (i = 0; i < ARRAY_SIZE(tv_modes); i++) {
254                 const struct tv_mode *tv_mode = &tv_modes[i];
255
256                 if (tv_mode->tv_mode == mode)
257                         return tv_mode;
258         }
259
260         return NULL;
261 }
262
263 static void sun4i_tv_disable(struct drm_encoder *encoder,
264                             struct drm_atomic_state *state)
265 {
266         struct sun4i_tv *tv = drm_encoder_to_sun4i_tv(encoder);
267         struct sun4i_crtc *crtc = drm_crtc_to_sun4i_crtc(encoder->crtc);
268
269         DRM_DEBUG_DRIVER("Disabling the TV Output\n");
270
271         regmap_update_bits(tv->regs, SUN4I_TVE_EN_REG,
272                            SUN4I_TVE_EN_ENABLE,
273                            0);
274
275         sunxi_engine_disable_color_correction(crtc->engine);
276 }
277
278 static void sun4i_tv_enable(struct drm_encoder *encoder,
279                             struct drm_atomic_state *state)
280 {
281         struct sun4i_tv *tv = drm_encoder_to_sun4i_tv(encoder);
282         struct sun4i_crtc *crtc = drm_crtc_to_sun4i_crtc(encoder->crtc);
283         struct drm_crtc_state *crtc_state =
284                 drm_atomic_get_new_crtc_state(state, encoder->crtc);
285         struct drm_display_mode *mode = &crtc_state->mode;
286         struct drm_connector *connector = &tv->connector;
287         struct drm_connector_state *conn_state =
288                 drm_atomic_get_new_connector_state(state, connector);
289         const struct tv_mode *tv_mode =
290                 sun4i_tv_find_tv_by_mode(conn_state->tv.mode);
291
292         DRM_DEBUG_DRIVER("Enabling the TV Output\n");
293
294         /* Enable and map the DAC to the output */
295         regmap_update_bits(tv->regs, SUN4I_TVE_EN_REG,
296                            SUN4I_TVE_EN_DAC_MAP_MASK,
297                            SUN4I_TVE_EN_DAC_MAP(0, 1) |
298                            SUN4I_TVE_EN_DAC_MAP(1, 2) |
299                            SUN4I_TVE_EN_DAC_MAP(2, 3) |
300                            SUN4I_TVE_EN_DAC_MAP(3, 4));
301
302         /* Set PAL settings */
303         regmap_write(tv->regs, SUN4I_TVE_CFG0_REG,
304                      tv_mode->mode |
305                      (tv_mode->yc_en ? SUN4I_TVE_CFG0_YC_EN : 0) |
306                      SUN4I_TVE_CFG0_COMP_EN |
307                      SUN4I_TVE_CFG0_DAC_CONTROL_54M |
308                      SUN4I_TVE_CFG0_CORE_DATAPATH_54M |
309                      SUN4I_TVE_CFG0_CORE_CONTROL_54M);
310
311         /* Configure the DAC for a composite output */
312         regmap_write(tv->regs, SUN4I_TVE_DAC0_REG,
313                      SUN4I_TVE_DAC0_DAC_EN(0) |
314                      (tv_mode->dac3_en ? SUN4I_TVE_DAC0_DAC_EN(3) : 0) |
315                      SUN4I_TVE_DAC0_INTERNAL_DAC_37_5_OHMS |
316                      SUN4I_TVE_DAC0_CHROMA_0_75 |
317                      SUN4I_TVE_DAC0_LUMA_0_4 |
318                      SUN4I_TVE_DAC0_CLOCK_INVERT |
319                      (tv_mode->dac_bit25_en ? BIT(25) : 0) |
320                      BIT(30));
321
322         /* Configure the sample delay between DAC0 and the other DAC */
323         regmap_write(tv->regs, SUN4I_TVE_NOTCH_REG,
324                      SUN4I_TVE_NOTCH_DAC0_TO_DAC_DLY(1, 0) |
325                      SUN4I_TVE_NOTCH_DAC0_TO_DAC_DLY(2, 0));
326
327         regmap_write(tv->regs, SUN4I_TVE_CHROMA_FREQ_REG,
328                      tv_mode->chroma_freq);
329
330         /* Set the front and back porch */
331         regmap_write(tv->regs, SUN4I_TVE_PORCH_REG,
332                      SUN4I_TVE_PORCH_BACK(tv_mode->back_porch) |
333                      SUN4I_TVE_PORCH_FRONT(tv_mode->front_porch));
334
335         /* Set the lines setup */
336         regmap_write(tv->regs, SUN4I_TVE_LINE_REG,
337                      SUN4I_TVE_LINE_FIRST(22) |
338                      SUN4I_TVE_LINE_NUMBER(mode->vtotal));
339
340         regmap_write(tv->regs, SUN4I_TVE_LEVEL_REG,
341                      SUN4I_TVE_LEVEL_BLANK(tv_mode->video_levels->blank) |
342                      SUN4I_TVE_LEVEL_BLACK(tv_mode->video_levels->black));
343
344         regmap_write(tv->regs, SUN4I_TVE_DAC1_REG,
345                      SUN4I_TVE_DAC1_AMPLITUDE(0, 0x18) |
346                      SUN4I_TVE_DAC1_AMPLITUDE(1, 0x18) |
347                      SUN4I_TVE_DAC1_AMPLITUDE(2, 0x18) |
348                      SUN4I_TVE_DAC1_AMPLITUDE(3, 0x18));
349
350         regmap_write(tv->regs, SUN4I_TVE_CB_CR_LVL_REG,
351                      SUN4I_TVE_CB_CR_LVL_CB_BURST(tv_mode->burst_levels->cb) |
352                      SUN4I_TVE_CB_CR_LVL_CR_BURST(tv_mode->burst_levels->cr));
353
354         /* Set burst width for a composite output */
355         regmap_write(tv->regs, SUN4I_TVE_BURST_WIDTH_REG,
356                      SUN4I_TVE_BURST_WIDTH_HSYNC_WIDTH(126) |
357                      SUN4I_TVE_BURST_WIDTH_BURST_WIDTH(68) |
358                      SUN4I_TVE_BURST_WIDTH_BREEZEWAY(22));
359
360         regmap_write(tv->regs, SUN4I_TVE_CB_CR_GAIN_REG,
361                      SUN4I_TVE_CB_CR_GAIN_CB(tv_mode->color_gains->cb) |
362                      SUN4I_TVE_CB_CR_GAIN_CR(tv_mode->color_gains->cr));
363
364         regmap_write(tv->regs, SUN4I_TVE_SYNC_VBI_REG,
365                      SUN4I_TVE_SYNC_VBI_SYNC(0x10) |
366                      SUN4I_TVE_SYNC_VBI_VBLANK(tv_mode->vblank_level));
367
368         regmap_write(tv->regs, SUN4I_TVE_ACTIVE_LINE_REG,
369                      SUN4I_TVE_ACTIVE_LINE(1440));
370
371         /* Set composite chroma gain to 50 % */
372         regmap_write(tv->regs, SUN4I_TVE_CHROMA_REG,
373                      SUN4I_TVE_CHROMA_COMP_GAIN_50);
374
375         regmap_write(tv->regs, SUN4I_TVE_12C_REG,
376                      SUN4I_TVE_12C_COMP_YUV_EN |
377                      SUN4I_TVE_12C_NOTCH_WIDTH_WIDE);
378
379         regmap_write(tv->regs, SUN4I_TVE_RESYNC_REG,
380                      SUN4I_TVE_RESYNC_PIXEL(tv_mode->resync_params->pixel) |
381                      SUN4I_TVE_RESYNC_LINE(tv_mode->resync_params->line) |
382                      (tv_mode->resync_params->field ?
383                       SUN4I_TVE_RESYNC_FIELD : 0));
384
385         regmap_write(tv->regs, SUN4I_TVE_SLAVE_REG, 0);
386
387         sunxi_engine_apply_color_correction(crtc->engine);
388
389         regmap_update_bits(tv->regs, SUN4I_TVE_EN_REG,
390                            SUN4I_TVE_EN_ENABLE,
391                            SUN4I_TVE_EN_ENABLE);
392 }
393
394 static const struct drm_encoder_helper_funcs sun4i_tv_helper_funcs = {
395         .atomic_disable = sun4i_tv_disable,
396         .atomic_enable  = sun4i_tv_enable,
397 };
398
399 static const struct drm_connector_helper_funcs sun4i_tv_comp_connector_helper_funcs = {
400         .atomic_check   = drm_atomic_helper_connector_tv_check,
401         .get_modes      = drm_connector_helper_tv_get_modes,
402 };
403
404 static void sun4i_tv_connector_reset(struct drm_connector *connector)
405 {
406         drm_atomic_helper_connector_reset(connector);
407         drm_atomic_helper_connector_tv_reset(connector);
408 }
409
410 static const struct drm_connector_funcs sun4i_tv_comp_connector_funcs = {
411         .fill_modes             = drm_helper_probe_single_connector_modes,
412         .destroy                = drm_connector_cleanup,
413         .reset                  = sun4i_tv_connector_reset,
414         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
415         .atomic_destroy_state   = drm_atomic_helper_connector_destroy_state,
416 };
417
418 static const struct regmap_config sun4i_tv_regmap_config = {
419         .reg_bits       = 32,
420         .val_bits       = 32,
421         .reg_stride     = 4,
422         .max_register   = SUN4I_TVE_WSS_DATA2_REG,
423         .name           = "tv-encoder",
424 };
425
426 static int sun4i_tv_bind(struct device *dev, struct device *master,
427                          void *data)
428 {
429         struct platform_device *pdev = to_platform_device(dev);
430         struct drm_device *drm = data;
431         struct sun4i_drv *drv = drm->dev_private;
432         struct sun4i_tv *tv;
433         void __iomem *regs;
434         int ret;
435
436         tv = devm_kzalloc(dev, sizeof(*tv), GFP_KERNEL);
437         if (!tv)
438                 return -ENOMEM;
439         tv->drv = drv;
440         dev_set_drvdata(dev, tv);
441
442         regs = devm_platform_ioremap_resource(pdev, 0);
443         if (IS_ERR(regs)) {
444                 dev_err(dev, "Couldn't map the TV encoder registers\n");
445                 return PTR_ERR(regs);
446         }
447
448         tv->regs = devm_regmap_init_mmio(dev, regs,
449                                          &sun4i_tv_regmap_config);
450         if (IS_ERR(tv->regs)) {
451                 dev_err(dev, "Couldn't create the TV encoder regmap\n");
452                 return PTR_ERR(tv->regs);
453         }
454
455         tv->reset = devm_reset_control_get(dev, NULL);
456         if (IS_ERR(tv->reset)) {
457                 dev_err(dev, "Couldn't get our reset line\n");
458                 return PTR_ERR(tv->reset);
459         }
460
461         ret = reset_control_deassert(tv->reset);
462         if (ret) {
463                 dev_err(dev, "Couldn't deassert our reset line\n");
464                 return ret;
465         }
466
467         tv->clk = devm_clk_get(dev, NULL);
468         if (IS_ERR(tv->clk)) {
469                 dev_err(dev, "Couldn't get the TV encoder clock\n");
470                 ret = PTR_ERR(tv->clk);
471                 goto err_assert_reset;
472         }
473         clk_prepare_enable(tv->clk);
474
475         drm_encoder_helper_add(&tv->encoder,
476                                &sun4i_tv_helper_funcs);
477         ret = drm_simple_encoder_init(drm, &tv->encoder,
478                                       DRM_MODE_ENCODER_TVDAC);
479         if (ret) {
480                 dev_err(dev, "Couldn't initialise the TV encoder\n");
481                 goto err_disable_clk;
482         }
483
484         tv->encoder.possible_crtcs = drm_of_find_possible_crtcs(drm,
485                                                                 dev->of_node);
486         if (!tv->encoder.possible_crtcs) {
487                 ret = -EPROBE_DEFER;
488                 goto err_disable_clk;
489         }
490
491         drm_connector_helper_add(&tv->connector,
492                                  &sun4i_tv_comp_connector_helper_funcs);
493         ret = drm_connector_init(drm, &tv->connector,
494                                  &sun4i_tv_comp_connector_funcs,
495                                  DRM_MODE_CONNECTOR_Composite);
496         if (ret) {
497                 dev_err(dev,
498                         "Couldn't initialise the Composite connector\n");
499                 goto err_cleanup_encoder;
500         }
501         tv->connector.interlace_allowed = true;
502
503         drm_connector_attach_encoder(&tv->connector, &tv->encoder);
504
505         ret = drm_mode_create_tv_properties(drm,
506                                             BIT(DRM_MODE_TV_MODE_NTSC) |
507                                             BIT(DRM_MODE_TV_MODE_PAL));
508         if (ret)
509                 goto err_cleanup_connector;
510
511         drm_object_attach_property(&tv->connector.base,
512                                    drm->mode_config.tv_mode_property,
513                                    DRM_MODE_TV_MODE_NTSC);
514
515         return 0;
516
517 err_cleanup_connector:
518         drm_connector_cleanup(&tv->connector);
519 err_cleanup_encoder:
520         drm_encoder_cleanup(&tv->encoder);
521 err_disable_clk:
522         clk_disable_unprepare(tv->clk);
523 err_assert_reset:
524         reset_control_assert(tv->reset);
525         return ret;
526 }
527
528 static void sun4i_tv_unbind(struct device *dev, struct device *master,
529                             void *data)
530 {
531         struct sun4i_tv *tv = dev_get_drvdata(dev);
532
533         drm_connector_cleanup(&tv->connector);
534         drm_encoder_cleanup(&tv->encoder);
535         clk_disable_unprepare(tv->clk);
536         reset_control_assert(tv->reset);
537 }
538
539 static const struct component_ops sun4i_tv_ops = {
540         .bind   = sun4i_tv_bind,
541         .unbind = sun4i_tv_unbind,
542 };
543
544 static int sun4i_tv_probe(struct platform_device *pdev)
545 {
546         return component_add(&pdev->dev, &sun4i_tv_ops);
547 }
548
549 static int sun4i_tv_remove(struct platform_device *pdev)
550 {
551         component_del(&pdev->dev, &sun4i_tv_ops);
552
553         return 0;
554 }
555
556 static const struct of_device_id sun4i_tv_of_table[] = {
557         { .compatible = "allwinner,sun4i-a10-tv-encoder" },
558         { }
559 };
560 MODULE_DEVICE_TABLE(of, sun4i_tv_of_table);
561
562 static struct platform_driver sun4i_tv_platform_driver = {
563         .probe          = sun4i_tv_probe,
564         .remove         = sun4i_tv_remove,
565         .driver         = {
566                 .name           = "sun4i-tve",
567                 .of_match_table = sun4i_tv_of_table,
568         },
569 };
570 module_platform_driver(sun4i_tv_platform_driver);
571
572 MODULE_AUTHOR("Maxime Ripard <[email protected]>");
573 MODULE_DESCRIPTION("Allwinner A10 TV Encoder Driver");
574 MODULE_LICENSE("GPL");
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