1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2020 Unisoc Inc.
6 #include <linux/component.h>
7 #include <linux/delay.h>
8 #include <linux/dma-buf.h>
10 #include <linux/module.h>
12 #include <linux/of_address.h>
13 #include <linux/of_device.h>
14 #include <linux/of_graph.h>
15 #include <linux/of_irq.h>
16 #include <linux/wait.h>
17 #include <linux/workqueue.h>
19 #include <drm/drm_atomic_helper.h>
20 #include <drm/drm_blend.h>
21 #include <drm/drm_fb_dma_helper.h>
22 #include <drm/drm_framebuffer.h>
23 #include <drm/drm_gem_dma_helper.h>
24 #include <drm/drm_gem_framebuffer_helper.h>
30 /* Global control registers */
31 #define REG_DPU_CTRL 0x04
32 #define REG_DPU_CFG0 0x08
33 #define REG_PANEL_SIZE 0x20
34 #define REG_BLEND_SIZE 0x24
35 #define REG_BG_COLOR 0x2C
37 /* Layer0 control registers */
38 #define REG_LAY_BASE_ADDR0 0x30
39 #define REG_LAY_BASE_ADDR1 0x34
40 #define REG_LAY_BASE_ADDR2 0x38
41 #define REG_LAY_CTRL 0x40
42 #define REG_LAY_SIZE 0x44
43 #define REG_LAY_PITCH 0x48
44 #define REG_LAY_POS 0x4C
45 #define REG_LAY_ALPHA 0x50
46 #define REG_LAY_CROP_START 0x5C
48 /* Interrupt control registers */
49 #define REG_DPU_INT_EN 0x1E0
50 #define REG_DPU_INT_CLR 0x1E4
51 #define REG_DPU_INT_STS 0x1E8
53 /* DPI control registers */
54 #define REG_DPI_CTRL 0x1F0
55 #define REG_DPI_H_TIMING 0x1F4
56 #define REG_DPI_V_TIMING 0x1F8
58 /* MMU control registers */
59 #define REG_MMU_EN 0x800
60 #define REG_MMU_VPN_RANGE 0x80C
61 #define REG_MMU_PPN1 0x83C
62 #define REG_MMU_RANGE1 0x840
63 #define REG_MMU_PPN2 0x844
64 #define REG_MMU_RANGE2 0x848
66 /* Global control bits */
67 #define BIT_DPU_RUN BIT(0)
68 #define BIT_DPU_STOP BIT(1)
69 #define BIT_DPU_REG_UPDATE BIT(2)
70 #define BIT_DPU_IF_EDPI BIT(0)
72 /* Layer control bits */
73 #define BIT_DPU_LAY_EN BIT(0)
74 #define BIT_DPU_LAY_LAYER_ALPHA (0x01 << 2)
75 #define BIT_DPU_LAY_COMBO_ALPHA (0x02 << 2)
76 #define BIT_DPU_LAY_FORMAT_YUV422_2PLANE (0x00 << 4)
77 #define BIT_DPU_LAY_FORMAT_YUV420_2PLANE (0x01 << 4)
78 #define BIT_DPU_LAY_FORMAT_YUV420_3PLANE (0x02 << 4)
79 #define BIT_DPU_LAY_FORMAT_ARGB8888 (0x03 << 4)
80 #define BIT_DPU_LAY_FORMAT_RGB565 (0x04 << 4)
81 #define BIT_DPU_LAY_DATA_ENDIAN_B0B1B2B3 (0x00 << 8)
82 #define BIT_DPU_LAY_DATA_ENDIAN_B3B2B1B0 (0x01 << 8)
83 #define BIT_DPU_LAY_NO_SWITCH (0x00 << 10)
84 #define BIT_DPU_LAY_RB_OR_UV_SWITCH (0x01 << 10)
85 #define BIT_DPU_LAY_MODE_BLEND_NORMAL (0x00 << 16)
86 #define BIT_DPU_LAY_MODE_BLEND_PREMULT (0x01 << 16)
87 #define BIT_DPU_LAY_ROTATION_0 (0x00 << 20)
88 #define BIT_DPU_LAY_ROTATION_90 (0x01 << 20)
89 #define BIT_DPU_LAY_ROTATION_180 (0x02 << 20)
90 #define BIT_DPU_LAY_ROTATION_270 (0x03 << 20)
91 #define BIT_DPU_LAY_ROTATION_0_M (0x04 << 20)
92 #define BIT_DPU_LAY_ROTATION_90_M (0x05 << 20)
93 #define BIT_DPU_LAY_ROTATION_180_M (0x06 << 20)
94 #define BIT_DPU_LAY_ROTATION_270_M (0x07 << 20)
96 /* Interrupt control & status bits */
97 #define BIT_DPU_INT_DONE BIT(0)
98 #define BIT_DPU_INT_TE BIT(1)
99 #define BIT_DPU_INT_ERR BIT(2)
100 #define BIT_DPU_INT_UPDATE_DONE BIT(4)
101 #define BIT_DPU_INT_VSYNC BIT(5)
103 /* DPI control bits */
104 #define BIT_DPU_EDPI_TE_EN BIT(8)
105 #define BIT_DPU_EDPI_FROM_EXTERNAL_PAD BIT(10)
106 #define BIT_DPU_DPI_HALT_EN BIT(16)
108 static const u32 layer_fmts[] = {
127 struct drm_plane base;
130 static int dpu_wait_stop_done(struct sprd_dpu *dpu)
132 struct dpu_context *ctx = &dpu->ctx;
138 rc = wait_event_interruptible_timeout(ctx->wait_queue, ctx->evt_stop,
139 msecs_to_jiffies(500));
140 ctx->evt_stop = false;
145 drm_err(dpu->drm, "dpu wait for stop done time out!\n");
152 static int dpu_wait_update_done(struct sprd_dpu *dpu)
154 struct dpu_context *ctx = &dpu->ctx;
157 ctx->evt_update = false;
159 rc = wait_event_interruptible_timeout(ctx->wait_queue, ctx->evt_update,
160 msecs_to_jiffies(500));
163 drm_err(dpu->drm, "dpu wait for reg update done time out!\n");
170 static u32 drm_format_to_dpu(struct drm_framebuffer *fb)
174 switch (fb->format->format) {
175 case DRM_FORMAT_BGRA8888:
176 /* BGRA8888 -> ARGB8888 */
177 format |= BIT_DPU_LAY_DATA_ENDIAN_B3B2B1B0;
178 format |= BIT_DPU_LAY_FORMAT_ARGB8888;
180 case DRM_FORMAT_RGBX8888:
181 case DRM_FORMAT_RGBA8888:
182 /* RGBA8888 -> ABGR8888 */
183 format |= BIT_DPU_LAY_DATA_ENDIAN_B3B2B1B0;
185 case DRM_FORMAT_ABGR8888:
187 format |= BIT_DPU_LAY_RB_OR_UV_SWITCH;
189 case DRM_FORMAT_ARGB8888:
190 format |= BIT_DPU_LAY_FORMAT_ARGB8888;
192 case DRM_FORMAT_XBGR8888:
194 format |= BIT_DPU_LAY_RB_OR_UV_SWITCH;
196 case DRM_FORMAT_XRGB8888:
197 format |= BIT_DPU_LAY_FORMAT_ARGB8888;
199 case DRM_FORMAT_BGR565:
201 format |= BIT_DPU_LAY_RB_OR_UV_SWITCH;
203 case DRM_FORMAT_RGB565:
204 format |= BIT_DPU_LAY_FORMAT_RGB565;
206 case DRM_FORMAT_NV12:
208 format |= BIT_DPU_LAY_FORMAT_YUV420_2PLANE;
210 format |= BIT_DPU_LAY_DATA_ENDIAN_B0B1B2B3;
212 format |= BIT_DPU_LAY_NO_SWITCH;
214 case DRM_FORMAT_NV21:
216 format |= BIT_DPU_LAY_FORMAT_YUV420_2PLANE;
218 format |= BIT_DPU_LAY_DATA_ENDIAN_B0B1B2B3;
220 format |= BIT_DPU_LAY_RB_OR_UV_SWITCH;
222 case DRM_FORMAT_NV16:
224 format |= BIT_DPU_LAY_FORMAT_YUV422_2PLANE;
226 format |= BIT_DPU_LAY_DATA_ENDIAN_B3B2B1B0;
228 format |= BIT_DPU_LAY_RB_OR_UV_SWITCH;
230 case DRM_FORMAT_NV61:
232 format |= BIT_DPU_LAY_FORMAT_YUV422_2PLANE;
234 format |= BIT_DPU_LAY_DATA_ENDIAN_B0B1B2B3;
236 format |= BIT_DPU_LAY_NO_SWITCH;
238 case DRM_FORMAT_YUV420:
239 format |= BIT_DPU_LAY_FORMAT_YUV420_3PLANE;
241 format |= BIT_DPU_LAY_DATA_ENDIAN_B0B1B2B3;
243 format |= BIT_DPU_LAY_NO_SWITCH;
245 case DRM_FORMAT_YVU420:
246 format |= BIT_DPU_LAY_FORMAT_YUV420_3PLANE;
248 format |= BIT_DPU_LAY_DATA_ENDIAN_B0B1B2B3;
250 format |= BIT_DPU_LAY_RB_OR_UV_SWITCH;
259 static u32 drm_rotation_to_dpu(struct drm_plane_state *state)
263 switch (state->rotation) {
265 case DRM_MODE_ROTATE_0:
266 rotation = BIT_DPU_LAY_ROTATION_0;
268 case DRM_MODE_ROTATE_90:
269 rotation = BIT_DPU_LAY_ROTATION_90;
271 case DRM_MODE_ROTATE_180:
272 rotation = BIT_DPU_LAY_ROTATION_180;
274 case DRM_MODE_ROTATE_270:
275 rotation = BIT_DPU_LAY_ROTATION_270;
277 case DRM_MODE_REFLECT_Y:
278 rotation = BIT_DPU_LAY_ROTATION_180_M;
280 case (DRM_MODE_REFLECT_Y | DRM_MODE_ROTATE_90):
281 rotation = BIT_DPU_LAY_ROTATION_90_M;
283 case DRM_MODE_REFLECT_X:
284 rotation = BIT_DPU_LAY_ROTATION_0_M;
286 case (DRM_MODE_REFLECT_X | DRM_MODE_ROTATE_90):
287 rotation = BIT_DPU_LAY_ROTATION_270_M;
294 static u32 drm_blend_to_dpu(struct drm_plane_state *state)
298 switch (state->pixel_blend_mode) {
299 case DRM_MODE_BLEND_COVERAGE:
300 /* alpha mode select - combo alpha */
301 blend |= BIT_DPU_LAY_COMBO_ALPHA;
303 blend |= BIT_DPU_LAY_MODE_BLEND_NORMAL;
305 case DRM_MODE_BLEND_PREMULTI:
306 /* alpha mode select - combo alpha */
307 blend |= BIT_DPU_LAY_COMBO_ALPHA;
309 blend |= BIT_DPU_LAY_MODE_BLEND_PREMULT;
311 case DRM_MODE_BLEND_PIXEL_NONE:
313 /* don't do blending, maybe RGBX */
314 /* alpha mode select - layer alpha */
315 blend |= BIT_DPU_LAY_LAYER_ALPHA;
322 static void sprd_dpu_layer(struct sprd_dpu *dpu, struct drm_plane_state *state)
324 struct dpu_context *ctx = &dpu->ctx;
325 struct drm_gem_dma_object *dma_obj;
326 struct drm_framebuffer *fb = state->fb;
327 u32 addr, size, offset, pitch, blend, format, rotation;
328 u32 src_x = state->src_x >> 16;
329 u32 src_y = state->src_y >> 16;
330 u32 src_w = state->src_w >> 16;
331 u32 src_h = state->src_h >> 16;
332 u32 dst_x = state->crtc_x;
333 u32 dst_y = state->crtc_y;
334 u32 alpha = state->alpha;
335 u32 index = state->zpos;
338 offset = (dst_x & 0xffff) | (dst_y << 16);
339 size = (src_w & 0xffff) | (src_h << 16);
341 for (i = 0; i < fb->format->num_planes; i++) {
342 dma_obj = drm_fb_dma_get_gem_obj(fb, i);
343 addr = dma_obj->dma_addr + fb->offsets[i];
346 layer_reg_wr(ctx, REG_LAY_BASE_ADDR0, addr, index);
348 layer_reg_wr(ctx, REG_LAY_BASE_ADDR1, addr, index);
350 layer_reg_wr(ctx, REG_LAY_BASE_ADDR2, addr, index);
353 if (fb->format->num_planes == 3) {
354 /* UV pitch is 1/2 of Y pitch */
355 pitch = (fb->pitches[0] / fb->format->cpp[0]) |
356 (fb->pitches[0] / fb->format->cpp[0] << 15);
358 pitch = fb->pitches[0] / fb->format->cpp[0];
361 layer_reg_wr(ctx, REG_LAY_POS, offset, index);
362 layer_reg_wr(ctx, REG_LAY_SIZE, size, index);
363 layer_reg_wr(ctx, REG_LAY_CROP_START,
364 src_y << 16 | src_x, index);
365 layer_reg_wr(ctx, REG_LAY_ALPHA, alpha, index);
366 layer_reg_wr(ctx, REG_LAY_PITCH, pitch, index);
368 format = drm_format_to_dpu(fb);
369 blend = drm_blend_to_dpu(state);
370 rotation = drm_rotation_to_dpu(state);
372 layer_reg_wr(ctx, REG_LAY_CTRL, BIT_DPU_LAY_EN |
379 static void sprd_dpu_flip(struct sprd_dpu *dpu)
381 struct dpu_context *ctx = &dpu->ctx;
384 * Make sure the dpu is in stop status. DPU has no shadow
385 * registers in EDPI mode. So the config registers can only be
386 * updated in the rising edge of DPU_RUN bit.
388 if (ctx->if_type == SPRD_DPU_IF_EDPI)
389 dpu_wait_stop_done(dpu);
391 /* update trigger and wait */
392 if (ctx->if_type == SPRD_DPU_IF_DPI) {
394 dpu_reg_set(ctx, REG_DPU_CTRL, BIT_DPU_REG_UPDATE);
395 dpu_wait_update_done(dpu);
398 dpu_reg_set(ctx, REG_DPU_INT_EN, BIT_DPU_INT_ERR);
399 } else if (ctx->if_type == SPRD_DPU_IF_EDPI) {
400 dpu_reg_set(ctx, REG_DPU_CTRL, BIT_DPU_RUN);
402 ctx->stopped = false;
406 static void sprd_dpu_init(struct sprd_dpu *dpu)
408 struct dpu_context *ctx = &dpu->ctx;
411 writel(0x00, ctx->base + REG_BG_COLOR);
412 writel(0x00, ctx->base + REG_MMU_EN);
413 writel(0x00, ctx->base + REG_MMU_PPN1);
414 writel(0xffff, ctx->base + REG_MMU_RANGE1);
415 writel(0x00, ctx->base + REG_MMU_PPN2);
416 writel(0xffff, ctx->base + REG_MMU_RANGE2);
417 writel(0x1ffff, ctx->base + REG_MMU_VPN_RANGE);
419 if (ctx->if_type == SPRD_DPU_IF_DPI) {
420 /* use dpi as interface */
421 dpu_reg_clr(ctx, REG_DPU_CFG0, BIT_DPU_IF_EDPI);
422 /* disable Halt function for SPRD DSI */
423 dpu_reg_clr(ctx, REG_DPI_CTRL, BIT_DPU_DPI_HALT_EN);
424 /* select te from external pad */
425 dpu_reg_set(ctx, REG_DPI_CTRL, BIT_DPU_EDPI_FROM_EXTERNAL_PAD);
427 /* enable dpu update done INT */
428 int_mask |= BIT_DPU_INT_UPDATE_DONE;
429 /* enable dpu done INT */
430 int_mask |= BIT_DPU_INT_DONE;
431 /* enable dpu dpi vsync */
432 int_mask |= BIT_DPU_INT_VSYNC;
433 /* enable dpu TE INT */
434 int_mask |= BIT_DPU_INT_TE;
435 /* enable underflow err INT */
436 int_mask |= BIT_DPU_INT_ERR;
437 } else if (ctx->if_type == SPRD_DPU_IF_EDPI) {
438 /* use edpi as interface */
439 dpu_reg_set(ctx, REG_DPU_CFG0, BIT_DPU_IF_EDPI);
440 /* use external te */
441 dpu_reg_set(ctx, REG_DPI_CTRL, BIT_DPU_EDPI_FROM_EXTERNAL_PAD);
443 dpu_reg_set(ctx, REG_DPI_CTRL, BIT_DPU_EDPI_TE_EN);
445 /* enable stop done INT */
446 int_mask |= BIT_DPU_INT_DONE;
448 int_mask |= BIT_DPU_INT_TE;
451 writel(int_mask, ctx->base + REG_DPU_INT_EN);
454 static void sprd_dpu_fini(struct sprd_dpu *dpu)
456 struct dpu_context *ctx = &dpu->ctx;
458 writel(0x00, ctx->base + REG_DPU_INT_EN);
459 writel(0xff, ctx->base + REG_DPU_INT_CLR);
462 static void sprd_dpi_init(struct sprd_dpu *dpu)
464 struct dpu_context *ctx = &dpu->ctx;
468 size = (ctx->vm.vactive << 16) | ctx->vm.hactive;
469 writel(size, ctx->base + REG_PANEL_SIZE);
470 writel(size, ctx->base + REG_BLEND_SIZE);
472 if (ctx->if_type == SPRD_DPU_IF_DPI) {
474 reg_val = ctx->vm.hsync_len << 0 |
475 ctx->vm.hback_porch << 8 |
476 ctx->vm.hfront_porch << 20;
477 writel(reg_val, ctx->base + REG_DPI_H_TIMING);
479 reg_val = ctx->vm.vsync_len << 0 |
480 ctx->vm.vback_porch << 8 |
481 ctx->vm.vfront_porch << 20;
482 writel(reg_val, ctx->base + REG_DPI_V_TIMING);
486 void sprd_dpu_run(struct sprd_dpu *dpu)
488 struct dpu_context *ctx = &dpu->ctx;
490 dpu_reg_set(ctx, REG_DPU_CTRL, BIT_DPU_RUN);
492 ctx->stopped = false;
495 void sprd_dpu_stop(struct sprd_dpu *dpu)
497 struct dpu_context *ctx = &dpu->ctx;
499 if (ctx->if_type == SPRD_DPU_IF_DPI)
500 dpu_reg_set(ctx, REG_DPU_CTRL, BIT_DPU_STOP);
502 dpu_wait_stop_done(dpu);
505 static int sprd_plane_atomic_check(struct drm_plane *plane,
506 struct drm_atomic_state *state)
508 struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state,
510 struct drm_crtc_state *crtc_state;
513 if (!plane_state->fb || !plane_state->crtc)
516 fmt = drm_format_to_dpu(plane_state->fb);
520 crtc_state = drm_atomic_get_crtc_state(plane_state->state, plane_state->crtc);
521 if (IS_ERR(crtc_state))
522 return PTR_ERR(crtc_state);
524 return drm_atomic_helper_check_plane_state(plane_state, crtc_state,
525 DRM_PLANE_NO_SCALING,
526 DRM_PLANE_NO_SCALING,
530 static void sprd_plane_atomic_update(struct drm_plane *drm_plane,
531 struct drm_atomic_state *state)
533 struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state,
535 struct sprd_dpu *dpu = to_sprd_crtc(new_state->crtc);
537 /* start configure dpu layers */
538 sprd_dpu_layer(dpu, new_state);
541 static void sprd_plane_atomic_disable(struct drm_plane *drm_plane,
542 struct drm_atomic_state *state)
544 struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state,
546 struct sprd_dpu *dpu = to_sprd_crtc(old_state->crtc);
548 layer_reg_wr(&dpu->ctx, REG_LAY_CTRL, 0x00, old_state->zpos);
551 static void sprd_plane_create_properties(struct sprd_plane *plane, int index)
553 unsigned int supported_modes = BIT(DRM_MODE_BLEND_PIXEL_NONE) |
554 BIT(DRM_MODE_BLEND_PREMULTI) |
555 BIT(DRM_MODE_BLEND_COVERAGE);
557 /* create rotation property */
558 drm_plane_create_rotation_property(&plane->base,
560 DRM_MODE_ROTATE_MASK |
561 DRM_MODE_REFLECT_MASK);
563 /* create alpha property */
564 drm_plane_create_alpha_property(&plane->base);
566 /* create blend mode property */
567 drm_plane_create_blend_mode_property(&plane->base, supported_modes);
569 /* create zpos property */
570 drm_plane_create_zpos_immutable_property(&plane->base, index);
573 static const struct drm_plane_helper_funcs sprd_plane_helper_funcs = {
574 .atomic_check = sprd_plane_atomic_check,
575 .atomic_update = sprd_plane_atomic_update,
576 .atomic_disable = sprd_plane_atomic_disable,
579 static const struct drm_plane_funcs sprd_plane_funcs = {
580 .update_plane = drm_atomic_helper_update_plane,
581 .disable_plane = drm_atomic_helper_disable_plane,
582 .destroy = drm_plane_cleanup,
583 .reset = drm_atomic_helper_plane_reset,
584 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
585 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
588 static struct sprd_plane *sprd_planes_init(struct drm_device *drm)
590 struct sprd_plane *plane, *primary;
591 enum drm_plane_type plane_type;
594 for (i = 0; i < 6; i++) {
595 plane_type = (i == 0) ? DRM_PLANE_TYPE_PRIMARY :
596 DRM_PLANE_TYPE_OVERLAY;
598 plane = drmm_universal_plane_alloc(drm, struct sprd_plane, base,
599 1, &sprd_plane_funcs,
600 layer_fmts, ARRAY_SIZE(layer_fmts),
601 NULL, plane_type, NULL);
603 drm_err(drm, "failed to init drm plane: %d\n", i);
607 drm_plane_helper_add(&plane->base, &sprd_plane_helper_funcs);
609 sprd_plane_create_properties(plane, i);
618 static void sprd_crtc_mode_set_nofb(struct drm_crtc *crtc)
620 struct sprd_dpu *dpu = to_sprd_crtc(crtc);
621 struct drm_display_mode *mode = &crtc->state->adjusted_mode;
622 struct drm_encoder *encoder;
623 struct sprd_dsi *dsi;
625 drm_display_mode_to_videomode(mode, &dpu->ctx.vm);
627 drm_for_each_encoder_mask(encoder, crtc->dev,
628 crtc->state->encoder_mask) {
629 dsi = encoder_to_dsi(encoder);
631 if (dsi->slave->mode_flags & MIPI_DSI_MODE_VIDEO)
632 dpu->ctx.if_type = SPRD_DPU_IF_DPI;
634 dpu->ctx.if_type = SPRD_DPU_IF_EDPI;
640 static void sprd_crtc_atomic_enable(struct drm_crtc *crtc,
641 struct drm_atomic_state *state)
643 struct sprd_dpu *dpu = to_sprd_crtc(crtc);
647 drm_crtc_vblank_on(&dpu->base);
650 static void sprd_crtc_atomic_disable(struct drm_crtc *crtc,
651 struct drm_atomic_state *state)
653 struct sprd_dpu *dpu = to_sprd_crtc(crtc);
654 struct drm_device *drm = dpu->base.dev;
656 drm_crtc_vblank_off(&dpu->base);
660 spin_lock_irq(&drm->event_lock);
661 if (crtc->state->event) {
662 drm_crtc_send_vblank_event(crtc, crtc->state->event);
663 crtc->state->event = NULL;
665 spin_unlock_irq(&drm->event_lock);
668 static void sprd_crtc_atomic_flush(struct drm_crtc *crtc,
669 struct drm_atomic_state *state)
672 struct sprd_dpu *dpu = to_sprd_crtc(crtc);
673 struct drm_device *drm = dpu->base.dev;
677 spin_lock_irq(&drm->event_lock);
678 if (crtc->state->event) {
679 drm_crtc_send_vblank_event(crtc, crtc->state->event);
680 crtc->state->event = NULL;
682 spin_unlock_irq(&drm->event_lock);
685 static int sprd_crtc_enable_vblank(struct drm_crtc *crtc)
687 struct sprd_dpu *dpu = to_sprd_crtc(crtc);
689 dpu_reg_set(&dpu->ctx, REG_DPU_INT_EN, BIT_DPU_INT_VSYNC);
694 static void sprd_crtc_disable_vblank(struct drm_crtc *crtc)
696 struct sprd_dpu *dpu = to_sprd_crtc(crtc);
698 dpu_reg_clr(&dpu->ctx, REG_DPU_INT_EN, BIT_DPU_INT_VSYNC);
701 static const struct drm_crtc_helper_funcs sprd_crtc_helper_funcs = {
702 .mode_set_nofb = sprd_crtc_mode_set_nofb,
703 .atomic_flush = sprd_crtc_atomic_flush,
704 .atomic_enable = sprd_crtc_atomic_enable,
705 .atomic_disable = sprd_crtc_atomic_disable,
708 static const struct drm_crtc_funcs sprd_crtc_funcs = {
709 .destroy = drm_crtc_cleanup,
710 .set_config = drm_atomic_helper_set_config,
711 .page_flip = drm_atomic_helper_page_flip,
712 .reset = drm_atomic_helper_crtc_reset,
713 .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
714 .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
715 .enable_vblank = sprd_crtc_enable_vblank,
716 .disable_vblank = sprd_crtc_disable_vblank,
719 static struct sprd_dpu *sprd_crtc_init(struct drm_device *drm,
720 struct drm_plane *primary, struct device *dev)
722 struct device_node *port;
723 struct sprd_dpu *dpu;
725 dpu = drmm_crtc_alloc_with_planes(drm, struct sprd_dpu, base,
727 &sprd_crtc_funcs, NULL);
729 drm_err(drm, "failed to init crtc\n");
732 drm_crtc_helper_add(&dpu->base, &sprd_crtc_helper_funcs);
735 * set crtc port so that drm_of_find_possible_crtcs call works
737 port = of_graph_get_port_by_id(dev->of_node, 0);
739 drm_err(drm, "failed to found crtc output port for %s\n",
740 dev->of_node->full_name);
741 return ERR_PTR(-EINVAL);
743 dpu->base.port = port;
749 static irqreturn_t sprd_dpu_isr(int irq, void *data)
751 struct sprd_dpu *dpu = data;
752 struct dpu_context *ctx = &dpu->ctx;
753 u32 reg_val, int_mask = 0;
755 reg_val = readl(ctx->base + REG_DPU_INT_STS);
757 /* disable err interrupt */
758 if (reg_val & BIT_DPU_INT_ERR) {
759 int_mask |= BIT_DPU_INT_ERR;
760 drm_warn(dpu->drm, "Warning: dpu underflow!\n");
763 /* dpu update done isr */
764 if (reg_val & BIT_DPU_INT_UPDATE_DONE) {
765 ctx->evt_update = true;
766 wake_up_interruptible_all(&ctx->wait_queue);
769 /* dpu stop done isr */
770 if (reg_val & BIT_DPU_INT_DONE) {
771 ctx->evt_stop = true;
772 wake_up_interruptible_all(&ctx->wait_queue);
775 if (reg_val & BIT_DPU_INT_VSYNC)
776 drm_crtc_handle_vblank(&dpu->base);
778 writel(reg_val, ctx->base + REG_DPU_INT_CLR);
779 dpu_reg_clr(ctx, REG_DPU_INT_EN, int_mask);
784 static int sprd_dpu_context_init(struct sprd_dpu *dpu,
787 struct platform_device *pdev = to_platform_device(dev);
788 struct dpu_context *ctx = &dpu->ctx;
789 struct resource *res;
792 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
794 dev_err(dev, "failed to get I/O resource\n");
798 ctx->base = devm_ioremap(dev, res->start, resource_size(res));
800 dev_err(dev, "failed to map dpu registers\n");
804 ctx->irq = platform_get_irq(pdev, 0);
808 /* disable and clear interrupts before register dpu IRQ. */
809 writel(0x00, ctx->base + REG_DPU_INT_EN);
810 writel(0xff, ctx->base + REG_DPU_INT_CLR);
812 ret = devm_request_irq(dev, ctx->irq, sprd_dpu_isr,
813 IRQF_TRIGGER_NONE, "DPU", dpu);
815 dev_err(dev, "failed to register dpu irq handler\n");
819 init_waitqueue_head(&ctx->wait_queue);
824 static int sprd_dpu_bind(struct device *dev, struct device *master, void *data)
826 struct drm_device *drm = data;
827 struct sprd_dpu *dpu;
828 struct sprd_plane *plane;
831 plane = sprd_planes_init(drm);
833 return PTR_ERR(plane);
835 dpu = sprd_crtc_init(drm, &plane->base, dev);
840 dev_set_drvdata(dev, dpu);
842 ret = sprd_dpu_context_init(dpu, dev);
849 static const struct component_ops dpu_component_ops = {
850 .bind = sprd_dpu_bind,
853 static const struct of_device_id dpu_match_table[] = {
854 { .compatible = "sprd,sharkl3-dpu" },
857 MODULE_DEVICE_TABLE(of, dpu_match_table);
859 static int sprd_dpu_probe(struct platform_device *pdev)
861 return component_add(&pdev->dev, &dpu_component_ops);
864 static int sprd_dpu_remove(struct platform_device *pdev)
866 component_del(&pdev->dev, &dpu_component_ops);
871 struct platform_driver sprd_dpu_driver = {
872 .probe = sprd_dpu_probe,
873 .remove = sprd_dpu_remove,
875 .name = "sprd-dpu-drv",
876 .of_match_table = dpu_match_table,
882 MODULE_DESCRIPTION("Unisoc Display Controller Driver");
883 MODULE_LICENSE("GPL v2");