2 * Copyright 2007-8 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
27 #include <linux/pci.h>
29 #include <drm/drm_device.h>
30 #include <drm/radeon_drm.h>
35 #include "atom-bits.h"
36 #include "radeon_asic.h"
37 #include "radeon_atombios.h"
38 #include "radeon_legacy_encoders.h"
40 union atom_supported_devices {
41 struct _ATOM_SUPPORTED_DEVICES_INFO info;
42 struct _ATOM_SUPPORTED_DEVICES_INFO_2 info_2;
43 struct _ATOM_SUPPORTED_DEVICES_INFO_2d1 info_2d1;
46 static void radeon_lookup_i2c_gpio_quirks(struct radeon_device *rdev,
47 ATOM_GPIO_I2C_ASSIGMENT *gpio,
50 /* r4xx mask is technically not used by the hw, so patch in the legacy mask bits */
51 if ((rdev->family == CHIP_R420) ||
52 (rdev->family == CHIP_R423) ||
53 (rdev->family == CHIP_RV410)) {
54 if ((le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x0018) ||
55 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x0019) ||
56 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x001a)) {
57 gpio->ucClkMaskShift = 0x19;
58 gpio->ucDataMaskShift = 0x18;
62 /* some evergreen boards have bad data for this entry */
63 if (ASIC_IS_DCE4(rdev)) {
65 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1936) &&
66 (gpio->sucI2cId.ucAccess == 0)) {
67 gpio->sucI2cId.ucAccess = 0x97;
68 gpio->ucDataMaskShift = 8;
69 gpio->ucDataEnShift = 8;
70 gpio->ucDataY_Shift = 8;
71 gpio->ucDataA_Shift = 8;
75 /* some DCE3 boards have bad data for this entry */
76 if (ASIC_IS_DCE3(rdev)) {
78 (le16_to_cpu(gpio->usClkMaskRegisterIndex) == 0x1fda) &&
79 (gpio->sucI2cId.ucAccess == 0x94))
80 gpio->sucI2cId.ucAccess = 0x14;
84 static struct radeon_i2c_bus_rec radeon_get_bus_rec_for_i2c_gpio(ATOM_GPIO_I2C_ASSIGMENT *gpio)
86 struct radeon_i2c_bus_rec i2c;
88 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
90 i2c.mask_clk_reg = le16_to_cpu(gpio->usClkMaskRegisterIndex) * 4;
91 i2c.mask_data_reg = le16_to_cpu(gpio->usDataMaskRegisterIndex) * 4;
92 i2c.en_clk_reg = le16_to_cpu(gpio->usClkEnRegisterIndex) * 4;
93 i2c.en_data_reg = le16_to_cpu(gpio->usDataEnRegisterIndex) * 4;
94 i2c.y_clk_reg = le16_to_cpu(gpio->usClkY_RegisterIndex) * 4;
95 i2c.y_data_reg = le16_to_cpu(gpio->usDataY_RegisterIndex) * 4;
96 i2c.a_clk_reg = le16_to_cpu(gpio->usClkA_RegisterIndex) * 4;
97 i2c.a_data_reg = le16_to_cpu(gpio->usDataA_RegisterIndex) * 4;
98 i2c.mask_clk_mask = (1 << gpio->ucClkMaskShift);
99 i2c.mask_data_mask = (1 << gpio->ucDataMaskShift);
100 i2c.en_clk_mask = (1 << gpio->ucClkEnShift);
101 i2c.en_data_mask = (1 << gpio->ucDataEnShift);
102 i2c.y_clk_mask = (1 << gpio->ucClkY_Shift);
103 i2c.y_data_mask = (1 << gpio->ucDataY_Shift);
104 i2c.a_clk_mask = (1 << gpio->ucClkA_Shift);
105 i2c.a_data_mask = (1 << gpio->ucDataA_Shift);
107 if (gpio->sucI2cId.sbfAccess.bfHW_Capable)
108 i2c.hw_capable = true;
110 i2c.hw_capable = false;
112 if (gpio->sucI2cId.ucAccess == 0xa0)
117 i2c.i2c_id = gpio->sucI2cId.ucAccess;
119 if (i2c.mask_clk_reg)
127 static struct radeon_i2c_bus_rec radeon_lookup_i2c_gpio(struct radeon_device *rdev,
130 struct atom_context *ctx = rdev->mode_info.atom_context;
131 ATOM_GPIO_I2C_ASSIGMENT *gpio;
132 struct radeon_i2c_bus_rec i2c;
133 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
134 struct _ATOM_GPIO_I2C_INFO *i2c_info;
135 uint16_t data_offset, size;
138 memset(&i2c, 0, sizeof(struct radeon_i2c_bus_rec));
141 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
142 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
144 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
145 sizeof(ATOM_GPIO_I2C_ASSIGMENT);
147 gpio = &i2c_info->asGPIO_Info[0];
148 for (i = 0; i < num_indices; i++) {
150 radeon_lookup_i2c_gpio_quirks(rdev, gpio, i);
152 if (gpio->sucI2cId.ucAccess == id) {
153 i2c = radeon_get_bus_rec_for_i2c_gpio(gpio);
156 gpio = (ATOM_GPIO_I2C_ASSIGMENT *)
157 ((u8 *)gpio + sizeof(ATOM_GPIO_I2C_ASSIGMENT));
164 void radeon_atombios_i2c_init(struct radeon_device *rdev)
166 struct atom_context *ctx = rdev->mode_info.atom_context;
167 ATOM_GPIO_I2C_ASSIGMENT *gpio;
168 struct radeon_i2c_bus_rec i2c;
169 int index = GetIndexIntoMasterTable(DATA, GPIO_I2C_Info);
170 struct _ATOM_GPIO_I2C_INFO *i2c_info;
171 uint16_t data_offset, size;
175 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
176 i2c_info = (struct _ATOM_GPIO_I2C_INFO *)(ctx->bios + data_offset);
178 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
179 sizeof(ATOM_GPIO_I2C_ASSIGMENT);
181 gpio = &i2c_info->asGPIO_Info[0];
182 for (i = 0; i < num_indices; i++) {
183 radeon_lookup_i2c_gpio_quirks(rdev, gpio, i);
185 i2c = radeon_get_bus_rec_for_i2c_gpio(gpio);
188 sprintf(stmp, "0x%x", i2c.i2c_id);
189 rdev->i2c_bus[i] = radeon_i2c_create(rdev->ddev, &i2c, stmp);
191 gpio = (ATOM_GPIO_I2C_ASSIGMENT *)
192 ((u8 *)gpio + sizeof(ATOM_GPIO_I2C_ASSIGMENT));
197 struct radeon_gpio_rec radeon_atombios_lookup_gpio(struct radeon_device *rdev,
200 struct atom_context *ctx = rdev->mode_info.atom_context;
201 struct radeon_gpio_rec gpio;
202 int index = GetIndexIntoMasterTable(DATA, GPIO_Pin_LUT);
203 struct _ATOM_GPIO_PIN_LUT *gpio_info;
204 ATOM_GPIO_PIN_ASSIGNMENT *pin;
205 u16 data_offset, size;
208 memset(&gpio, 0, sizeof(struct radeon_gpio_rec));
211 if (atom_parse_data_header(ctx, index, &size, NULL, NULL, &data_offset)) {
212 gpio_info = (struct _ATOM_GPIO_PIN_LUT *)(ctx->bios + data_offset);
214 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
215 sizeof(ATOM_GPIO_PIN_ASSIGNMENT);
217 pin = gpio_info->asGPIO_Pin;
218 for (i = 0; i < num_indices; i++) {
219 if (id == pin->ucGPIO_ID) {
220 gpio.id = pin->ucGPIO_ID;
221 gpio.reg = le16_to_cpu(pin->usGpioPin_AIndex) * 4;
222 gpio.shift = pin->ucGpioPinBitShift;
223 gpio.mask = (1 << pin->ucGpioPinBitShift);
227 pin = (ATOM_GPIO_PIN_ASSIGNMENT *)
228 ((u8 *)pin + sizeof(ATOM_GPIO_PIN_ASSIGNMENT));
235 static struct radeon_hpd radeon_atom_get_hpd_info_from_gpio(struct radeon_device *rdev,
236 struct radeon_gpio_rec *gpio)
238 struct radeon_hpd hpd;
241 memset(&hpd, 0, sizeof(struct radeon_hpd));
243 if (ASIC_IS_DCE6(rdev))
244 reg = SI_DC_GPIO_HPD_A;
245 else if (ASIC_IS_DCE4(rdev))
246 reg = EVERGREEN_DC_GPIO_HPD_A;
248 reg = AVIVO_DC_GPIO_HPD_A;
251 if (gpio->reg == reg) {
254 hpd.hpd = RADEON_HPD_1;
257 hpd.hpd = RADEON_HPD_2;
260 hpd.hpd = RADEON_HPD_3;
263 hpd.hpd = RADEON_HPD_4;
266 hpd.hpd = RADEON_HPD_5;
269 hpd.hpd = RADEON_HPD_6;
272 hpd.hpd = RADEON_HPD_NONE;
276 hpd.hpd = RADEON_HPD_NONE;
280 static bool radeon_atom_apply_quirks(struct drm_device *dev,
281 uint32_t supported_device,
283 struct radeon_i2c_bus_rec *i2c_bus,
285 struct radeon_hpd *hpd)
287 struct pci_dev *pdev = to_pci_dev(dev->dev);
289 /* Asus M2A-VM HDMI board lists the DVI port as HDMI */
290 if ((pdev->device == 0x791e) &&
291 (pdev->subsystem_vendor == 0x1043) &&
292 (pdev->subsystem_device == 0x826d)) {
293 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
294 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
295 *connector_type = DRM_MODE_CONNECTOR_DVID;
298 /* Asrock RS600 board lists the DVI port as HDMI */
299 if ((pdev->device == 0x7941) &&
300 (pdev->subsystem_vendor == 0x1849) &&
301 (pdev->subsystem_device == 0x7941)) {
302 if ((*connector_type == DRM_MODE_CONNECTOR_HDMIA) &&
303 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
304 *connector_type = DRM_MODE_CONNECTOR_DVID;
307 /* MSI K9A2GM V2/V3 board has no HDMI or DVI */
308 if ((pdev->device == 0x796e) &&
309 (pdev->subsystem_vendor == 0x1462) &&
310 (pdev->subsystem_device == 0x7302)) {
311 if ((supported_device == ATOM_DEVICE_DFP2_SUPPORT) ||
312 (supported_device == ATOM_DEVICE_DFP3_SUPPORT))
316 /* a-bit f-i90hd - ciaranm on #radeonhd - this board has no DVI */
317 if ((pdev->device == 0x7941) &&
318 (pdev->subsystem_vendor == 0x147b) &&
319 (pdev->subsystem_device == 0x2412)) {
320 if (*connector_type == DRM_MODE_CONNECTOR_DVII)
324 /* Falcon NW laptop lists vga ddc line for LVDS */
325 if ((pdev->device == 0x5653) &&
326 (pdev->subsystem_vendor == 0x1462) &&
327 (pdev->subsystem_device == 0x0291)) {
328 if (*connector_type == DRM_MODE_CONNECTOR_LVDS) {
329 i2c_bus->valid = false;
334 /* HIS X1300 is DVI+VGA, not DVI+DVI */
335 if ((pdev->device == 0x7146) &&
336 (pdev->subsystem_vendor == 0x17af) &&
337 (pdev->subsystem_device == 0x2058)) {
338 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
342 /* Gigabyte X1300 is DVI+VGA, not DVI+DVI */
343 if ((pdev->device == 0x7142) &&
344 (pdev->subsystem_vendor == 0x1458) &&
345 (pdev->subsystem_device == 0x2134)) {
346 if (supported_device == ATOM_DEVICE_DFP1_SUPPORT)
352 if ((pdev->device == 0x71C5) &&
353 (pdev->subsystem_vendor == 0x106b) &&
354 (pdev->subsystem_device == 0x0080)) {
355 if ((supported_device == ATOM_DEVICE_CRT1_SUPPORT) ||
356 (supported_device == ATOM_DEVICE_DFP2_SUPPORT))
358 if (supported_device == ATOM_DEVICE_CRT2_SUPPORT)
362 /* mac rv630, rv730, others */
363 if ((supported_device == ATOM_DEVICE_TV1_SUPPORT) &&
364 (*connector_type == DRM_MODE_CONNECTOR_DVII)) {
365 *connector_type = DRM_MODE_CONNECTOR_9PinDIN;
366 *line_mux = CONNECTOR_7PIN_DIN_ENUM_ID1;
369 /* ASUS HD 3600 XT board lists the DVI port as HDMI */
370 if ((pdev->device == 0x9598) &&
371 (pdev->subsystem_vendor == 0x1043) &&
372 (pdev->subsystem_device == 0x01da)) {
373 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
374 *connector_type = DRM_MODE_CONNECTOR_DVII;
378 /* ASUS HD 3600 board lists the DVI port as HDMI */
379 if ((pdev->device == 0x9598) &&
380 (pdev->subsystem_vendor == 0x1043) &&
381 (pdev->subsystem_device == 0x01e4)) {
382 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
383 *connector_type = DRM_MODE_CONNECTOR_DVII;
387 /* ASUS HD 3450 board lists the DVI port as HDMI */
388 if ((pdev->device == 0x95C5) &&
389 (pdev->subsystem_vendor == 0x1043) &&
390 (pdev->subsystem_device == 0x01e2)) {
391 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
392 *connector_type = DRM_MODE_CONNECTOR_DVII;
396 /* some BIOSes seem to report DAC on HDMI - usually this is a board with
397 * HDMI + VGA reporting as HDMI
399 if (*connector_type == DRM_MODE_CONNECTOR_HDMIA) {
400 if (supported_device & (ATOM_DEVICE_CRT_SUPPORT)) {
401 *connector_type = DRM_MODE_CONNECTOR_VGA;
406 /* Acer laptop (Acer TravelMate 5730/5730G) has an HDMI port
407 * on the laptop and a DVI port on the docking station and
408 * both share the same encoder, hpd pin, and ddc line.
409 * So while the bios table is technically correct,
410 * we drop the DVI port here since xrandr has no concept of
411 * encoders and will try and drive both connectors
412 * with different crtcs which isn't possible on the hardware
413 * side and leaves no crtcs for LVDS or VGA.
415 if (((pdev->device == 0x95c4) || (pdev->device == 0x9591)) &&
416 (pdev->subsystem_vendor == 0x1025) &&
417 (pdev->subsystem_device == 0x013c)) {
418 if ((*connector_type == DRM_MODE_CONNECTOR_DVII) &&
419 (supported_device == ATOM_DEVICE_DFP1_SUPPORT)) {
420 /* actually it's a DVI-D port not DVI-I */
421 *connector_type = DRM_MODE_CONNECTOR_DVID;
426 /* XFX Pine Group device rv730 reports no VGA DDC lines
427 * even though they are wired up to record 0x93
429 if ((pdev->device == 0x9498) &&
430 (pdev->subsystem_vendor == 0x1682) &&
431 (pdev->subsystem_device == 0x2452) &&
432 (i2c_bus->valid == false) &&
433 !(supported_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))) {
434 struct radeon_device *rdev = dev->dev_private;
435 *i2c_bus = radeon_lookup_i2c_gpio(rdev, 0x93);
438 /* Fujitsu D3003-S2 board lists DVI-I as DVI-D and VGA */
439 if (((pdev->device == 0x9802) ||
440 (pdev->device == 0x9805) ||
441 (pdev->device == 0x9806)) &&
442 (pdev->subsystem_vendor == 0x1734) &&
443 (pdev->subsystem_device == 0x11bd)) {
444 if (*connector_type == DRM_MODE_CONNECTOR_VGA) {
445 *connector_type = DRM_MODE_CONNECTOR_DVII;
447 } else if (*connector_type == DRM_MODE_CONNECTOR_DVID) {
448 *connector_type = DRM_MODE_CONNECTOR_DVII;
455 static const int supported_devices_connector_convert[] = {
456 DRM_MODE_CONNECTOR_Unknown,
457 DRM_MODE_CONNECTOR_VGA,
458 DRM_MODE_CONNECTOR_DVII,
459 DRM_MODE_CONNECTOR_DVID,
460 DRM_MODE_CONNECTOR_DVIA,
461 DRM_MODE_CONNECTOR_SVIDEO,
462 DRM_MODE_CONNECTOR_Composite,
463 DRM_MODE_CONNECTOR_LVDS,
464 DRM_MODE_CONNECTOR_Unknown,
465 DRM_MODE_CONNECTOR_Unknown,
466 DRM_MODE_CONNECTOR_HDMIA,
467 DRM_MODE_CONNECTOR_HDMIB,
468 DRM_MODE_CONNECTOR_Unknown,
469 DRM_MODE_CONNECTOR_Unknown,
470 DRM_MODE_CONNECTOR_9PinDIN,
471 DRM_MODE_CONNECTOR_DisplayPort
474 static const uint16_t supported_devices_connector_object_id_convert[] = {
475 CONNECTOR_OBJECT_ID_NONE,
476 CONNECTOR_OBJECT_ID_VGA,
477 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I, /* not all boards support DL */
478 CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D, /* not all boards support DL */
479 CONNECTOR_OBJECT_ID_VGA, /* technically DVI-A */
480 CONNECTOR_OBJECT_ID_COMPOSITE,
481 CONNECTOR_OBJECT_ID_SVIDEO,
482 CONNECTOR_OBJECT_ID_LVDS,
483 CONNECTOR_OBJECT_ID_9PIN_DIN,
484 CONNECTOR_OBJECT_ID_9PIN_DIN,
485 CONNECTOR_OBJECT_ID_DISPLAYPORT,
486 CONNECTOR_OBJECT_ID_HDMI_TYPE_A,
487 CONNECTOR_OBJECT_ID_HDMI_TYPE_B,
488 CONNECTOR_OBJECT_ID_SVIDEO
491 static const int object_connector_convert[] = {
492 DRM_MODE_CONNECTOR_Unknown,
493 DRM_MODE_CONNECTOR_DVII,
494 DRM_MODE_CONNECTOR_DVII,
495 DRM_MODE_CONNECTOR_DVID,
496 DRM_MODE_CONNECTOR_DVID,
497 DRM_MODE_CONNECTOR_VGA,
498 DRM_MODE_CONNECTOR_Composite,
499 DRM_MODE_CONNECTOR_SVIDEO,
500 DRM_MODE_CONNECTOR_Unknown,
501 DRM_MODE_CONNECTOR_Unknown,
502 DRM_MODE_CONNECTOR_9PinDIN,
503 DRM_MODE_CONNECTOR_Unknown,
504 DRM_MODE_CONNECTOR_HDMIA,
505 DRM_MODE_CONNECTOR_HDMIB,
506 DRM_MODE_CONNECTOR_LVDS,
507 DRM_MODE_CONNECTOR_9PinDIN,
508 DRM_MODE_CONNECTOR_Unknown,
509 DRM_MODE_CONNECTOR_Unknown,
510 DRM_MODE_CONNECTOR_Unknown,
511 DRM_MODE_CONNECTOR_DisplayPort,
512 DRM_MODE_CONNECTOR_eDP,
513 DRM_MODE_CONNECTOR_Unknown
516 bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev)
518 struct radeon_device *rdev = dev->dev_private;
519 struct radeon_mode_info *mode_info = &rdev->mode_info;
520 struct atom_context *ctx = mode_info->atom_context;
521 int index = GetIndexIntoMasterTable(DATA, Object_Header);
522 u16 size, data_offset;
524 ATOM_CONNECTOR_OBJECT_TABLE *con_obj;
525 ATOM_ENCODER_OBJECT_TABLE *enc_obj;
526 ATOM_OBJECT_TABLE *router_obj;
527 ATOM_DISPLAY_OBJECT_PATH_TABLE *path_obj;
528 ATOM_OBJECT_HEADER *obj_header;
529 int i, j, k, path_size, device_support;
531 u16 igp_lane_info, conn_id, connector_object_id;
532 struct radeon_i2c_bus_rec ddc_bus;
533 struct radeon_router router;
534 struct radeon_gpio_rec gpio;
535 struct radeon_hpd hpd;
537 if (!atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset))
543 obj_header = (ATOM_OBJECT_HEADER *) (ctx->bios + data_offset);
544 path_obj = (ATOM_DISPLAY_OBJECT_PATH_TABLE *)
545 (ctx->bios + data_offset +
546 le16_to_cpu(obj_header->usDisplayPathTableOffset));
547 con_obj = (ATOM_CONNECTOR_OBJECT_TABLE *)
548 (ctx->bios + data_offset +
549 le16_to_cpu(obj_header->usConnectorObjectTableOffset));
550 enc_obj = (ATOM_ENCODER_OBJECT_TABLE *)
551 (ctx->bios + data_offset +
552 le16_to_cpu(obj_header->usEncoderObjectTableOffset));
553 router_obj = (ATOM_OBJECT_TABLE *)
554 (ctx->bios + data_offset +
555 le16_to_cpu(obj_header->usRouterObjectTableOffset));
556 device_support = le16_to_cpu(obj_header->usDeviceSupport);
559 for (i = 0; i < path_obj->ucNumOfDispPath; i++) {
560 uint8_t *addr = (uint8_t *) path_obj->asDispPath;
561 ATOM_DISPLAY_OBJECT_PATH *path;
563 path = (ATOM_DISPLAY_OBJECT_PATH *) addr;
564 path_size += le16_to_cpu(path->usSize);
566 if (device_support & le16_to_cpu(path->usDeviceTag)) {
567 uint8_t con_obj_id, con_obj_num;
570 (le16_to_cpu(path->usConnObjectId) & OBJECT_ID_MASK)
573 (le16_to_cpu(path->usConnObjectId) & ENUM_ID_MASK)
576 /* TODO CV support */
577 if (le16_to_cpu(path->usDeviceTag) ==
578 ATOM_DEVICE_CV_SUPPORT)
582 if ((rdev->flags & RADEON_IS_IGP) &&
584 CONNECTOR_OBJECT_ID_PCIE_CONNECTOR)) {
585 uint16_t igp_offset = 0;
586 ATOM_INTEGRATED_SYSTEM_INFO_V2 *igp_obj;
589 GetIndexIntoMasterTable(DATA,
590 IntegratedSystemInfo);
592 if (atom_parse_data_header(ctx, index, &size, &frev,
593 &crev, &igp_offset)) {
597 (ATOM_INTEGRATED_SYSTEM_INFO_V2
598 *) (ctx->bios + igp_offset);
601 uint32_t slot_config, ct;
603 if (con_obj_num == 1)
612 ct = (slot_config >> 16) & 0xff;
614 object_connector_convert
616 connector_object_id = ct;
618 slot_config & 0xffff;
626 object_connector_convert[con_obj_id];
627 connector_object_id = con_obj_id;
632 object_connector_convert[con_obj_id];
633 connector_object_id = con_obj_id;
636 if (connector_type == DRM_MODE_CONNECTOR_Unknown)
639 router.ddc_valid = false;
640 router.cd_valid = false;
641 for (j = 0; j < ((le16_to_cpu(path->usSize) - 8) / 2); j++) {
642 uint8_t grph_obj_type =
643 (le16_to_cpu(path->usGraphicObjIds[j]) &
644 OBJECT_TYPE_MASK) >> OBJECT_TYPE_SHIFT;
646 if (grph_obj_type == GRAPH_OBJECT_TYPE_ENCODER) {
647 for (k = 0; k < enc_obj->ucNumberOfObjects; k++) {
648 u16 encoder_obj = le16_to_cpu(enc_obj->asObjects[k].usObjectID);
649 if (le16_to_cpu(path->usGraphicObjIds[j]) == encoder_obj) {
650 ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
651 (ctx->bios + data_offset +
652 le16_to_cpu(enc_obj->asObjects[k].usRecordOffset));
653 ATOM_ENCODER_CAP_RECORD *cap_record;
656 while (record->ucRecordSize > 0 &&
657 record->ucRecordType > 0 &&
658 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
659 switch (record->ucRecordType) {
660 case ATOM_ENCODER_CAP_RECORD_TYPE:
661 cap_record =(ATOM_ENCODER_CAP_RECORD *)
663 caps = le16_to_cpu(cap_record->usEncoderCap);
666 record = (ATOM_COMMON_RECORD_HEADER *)
667 ((char *)record + record->ucRecordSize);
669 radeon_add_atom_encoder(dev,
677 } else if (grph_obj_type == GRAPH_OBJECT_TYPE_ROUTER) {
678 for (k = 0; k < router_obj->ucNumberOfObjects; k++) {
679 u16 router_obj_id = le16_to_cpu(router_obj->asObjects[k].usObjectID);
680 if (le16_to_cpu(path->usGraphicObjIds[j]) == router_obj_id) {
681 ATOM_COMMON_RECORD_HEADER *record = (ATOM_COMMON_RECORD_HEADER *)
682 (ctx->bios + data_offset +
683 le16_to_cpu(router_obj->asObjects[k].usRecordOffset));
684 ATOM_I2C_RECORD *i2c_record;
685 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
686 ATOM_ROUTER_DDC_PATH_SELECT_RECORD *ddc_path;
687 ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *cd_path;
688 ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *router_src_dst_table =
689 (ATOM_SRC_DST_TABLE_FOR_ONE_OBJECT *)
690 (ctx->bios + data_offset +
691 le16_to_cpu(router_obj->asObjects[k].usSrcDstTableOffset));
692 u8 *num_dst_objs = (u8 *)
693 ((u8 *)router_src_dst_table + 1 +
694 (router_src_dst_table->ucNumberOfSrc * 2));
695 u16 *dst_objs = (u16 *)(num_dst_objs + 1);
698 router.router_id = router_obj_id;
699 for (enum_id = 0; enum_id < (*num_dst_objs); enum_id++) {
700 if (le16_to_cpu(path->usConnObjectId) ==
701 le16_to_cpu(dst_objs[enum_id]))
705 while (record->ucRecordSize > 0 &&
706 record->ucRecordType > 0 &&
707 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
708 switch (record->ucRecordType) {
709 case ATOM_I2C_RECORD_TYPE:
714 (ATOM_I2C_ID_CONFIG_ACCESS *)
715 &i2c_record->sucI2cId;
717 radeon_lookup_i2c_gpio(rdev,
720 router.i2c_addr = i2c_record->ucI2CAddr >> 1;
722 case ATOM_ROUTER_DDC_PATH_SELECT_RECORD_TYPE:
723 ddc_path = (ATOM_ROUTER_DDC_PATH_SELECT_RECORD *)
725 router.ddc_valid = true;
726 router.ddc_mux_type = ddc_path->ucMuxType;
727 router.ddc_mux_control_pin = ddc_path->ucMuxControlPin;
728 router.ddc_mux_state = ddc_path->ucMuxState[enum_id];
730 case ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD_TYPE:
731 cd_path = (ATOM_ROUTER_DATA_CLOCK_PATH_SELECT_RECORD *)
733 router.cd_valid = true;
734 router.cd_mux_type = cd_path->ucMuxType;
735 router.cd_mux_control_pin = cd_path->ucMuxControlPin;
736 router.cd_mux_state = cd_path->ucMuxState[enum_id];
739 record = (ATOM_COMMON_RECORD_HEADER *)
740 ((char *)record + record->ucRecordSize);
747 /* look up gpio for ddc, hpd */
748 ddc_bus.valid = false;
749 hpd.hpd = RADEON_HPD_NONE;
750 if ((le16_to_cpu(path->usDeviceTag) &
751 (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) == 0) {
752 for (j = 0; j < con_obj->ucNumberOfObjects; j++) {
753 if (le16_to_cpu(path->usConnObjectId) ==
754 le16_to_cpu(con_obj->asObjects[j].
756 ATOM_COMMON_RECORD_HEADER
758 (ATOM_COMMON_RECORD_HEADER
760 (ctx->bios + data_offset +
761 le16_to_cpu(con_obj->
764 ATOM_I2C_RECORD *i2c_record;
765 ATOM_HPD_INT_RECORD *hpd_record;
766 ATOM_I2C_ID_CONFIG_ACCESS *i2c_config;
768 while (record->ucRecordSize > 0 &&
769 record->ucRecordType > 0 &&
770 record->ucRecordType <= ATOM_MAX_OBJECT_RECORD_NUMBER) {
771 switch (record->ucRecordType) {
772 case ATOM_I2C_RECORD_TYPE:
777 (ATOM_I2C_ID_CONFIG_ACCESS *)
778 &i2c_record->sucI2cId;
779 ddc_bus = radeon_lookup_i2c_gpio(rdev,
783 case ATOM_HPD_INT_RECORD_TYPE:
785 (ATOM_HPD_INT_RECORD *)
787 gpio = radeon_atombios_lookup_gpio(rdev,
788 hpd_record->ucHPDIntGPIOID);
789 hpd = radeon_atom_get_hpd_info_from_gpio(rdev, &gpio);
790 hpd.plugged_state = hpd_record->ucPlugged_PinState;
794 (ATOM_COMMON_RECORD_HEADER
805 /* needed for aux chan transactions */
806 ddc_bus.hpd = hpd.hpd;
808 conn_id = le16_to_cpu(path->usConnObjectId);
810 if (!radeon_atom_apply_quirks
811 (dev, le16_to_cpu(path->usDeviceTag), &connector_type,
812 &ddc_bus, &conn_id, &hpd))
815 radeon_add_atom_connector(dev,
819 connector_type, &ddc_bus,
828 radeon_link_encoder_connector(dev);
832 static uint16_t atombios_get_connector_object_id(struct drm_device *dev,
836 struct radeon_device *rdev = dev->dev_private;
838 if (rdev->flags & RADEON_IS_IGP) {
839 return supported_devices_connector_object_id_convert
841 } else if (((connector_type == DRM_MODE_CONNECTOR_DVII) ||
842 (connector_type == DRM_MODE_CONNECTOR_DVID)) &&
843 (devices & ATOM_DEVICE_DFP2_SUPPORT)) {
844 struct radeon_mode_info *mode_info = &rdev->mode_info;
845 struct atom_context *ctx = mode_info->atom_context;
846 int index = GetIndexIntoMasterTable(DATA, XTMDS_Info);
847 uint16_t size, data_offset;
849 ATOM_XTMDS_INFO *xtmds;
851 if (atom_parse_data_header(ctx, index, &size, &frev, &crev, &data_offset)) {
852 xtmds = (ATOM_XTMDS_INFO *)(ctx->bios + data_offset);
854 if (xtmds->ucSupportedLink & ATOM_XTMDS_SUPPORTED_DUALLINK) {
855 if (connector_type == DRM_MODE_CONNECTOR_DVII)
856 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_I;
858 return CONNECTOR_OBJECT_ID_DUAL_LINK_DVI_D;
860 if (connector_type == DRM_MODE_CONNECTOR_DVII)
861 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_I;
863 return CONNECTOR_OBJECT_ID_SINGLE_LINK_DVI_D;
866 return supported_devices_connector_object_id_convert
869 return supported_devices_connector_object_id_convert
874 struct bios_connector {
879 struct radeon_i2c_bus_rec ddc_bus;
880 struct radeon_hpd hpd;
883 bool radeon_get_atom_connector_info_from_supported_devices_table(struct
887 struct radeon_device *rdev = dev->dev_private;
888 struct radeon_mode_info *mode_info = &rdev->mode_info;
889 struct atom_context *ctx = mode_info->atom_context;
890 int index = GetIndexIntoMasterTable(DATA, SupportedDevicesInfo);
891 uint16_t size, data_offset;
893 uint16_t device_support;
895 union atom_supported_devices *supported_devices;
896 int i, j, max_device;
897 struct bios_connector *bios_connectors;
898 size_t bc_size = sizeof(*bios_connectors) * ATOM_MAX_SUPPORTED_DEVICE;
899 struct radeon_router router;
901 router.ddc_valid = false;
902 router.cd_valid = false;
904 bios_connectors = kzalloc(bc_size, GFP_KERNEL);
905 if (!bios_connectors)
908 if (!atom_parse_data_header(ctx, index, &size, &frev, &crev,
910 kfree(bios_connectors);
915 (union atom_supported_devices *)(ctx->bios + data_offset);
917 device_support = le16_to_cpu(supported_devices->info.usDeviceSupport);
920 max_device = ATOM_MAX_SUPPORTED_DEVICE;
922 max_device = ATOM_MAX_SUPPORTED_DEVICE_INFO;
924 for (i = 0; i < max_device; i++) {
925 ATOM_CONNECTOR_INFO_I2C ci =
926 supported_devices->info.asConnInfo[i];
928 bios_connectors[i].valid = false;
930 if (!(device_support & (1 << i))) {
934 if (i == ATOM_DEVICE_CV_INDEX) {
935 DRM_DEBUG_KMS("Skipping Component Video\n");
939 bios_connectors[i].connector_type =
940 supported_devices_connector_convert[ci.sucConnectorInfo.
944 if (bios_connectors[i].connector_type ==
945 DRM_MODE_CONNECTOR_Unknown)
948 dac = ci.sucConnectorInfo.sbfAccess.bfAssociatedDAC;
950 bios_connectors[i].line_mux =
951 ci.sucI2cId.ucAccess;
953 /* give tv unique connector ids */
954 if (i == ATOM_DEVICE_TV1_INDEX) {
955 bios_connectors[i].ddc_bus.valid = false;
956 bios_connectors[i].line_mux = 50;
957 } else if (i == ATOM_DEVICE_TV2_INDEX) {
958 bios_connectors[i].ddc_bus.valid = false;
959 bios_connectors[i].line_mux = 51;
960 } else if (i == ATOM_DEVICE_CV_INDEX) {
961 bios_connectors[i].ddc_bus.valid = false;
962 bios_connectors[i].line_mux = 52;
964 bios_connectors[i].ddc_bus =
965 radeon_lookup_i2c_gpio(rdev,
966 bios_connectors[i].line_mux);
968 if ((crev > 1) && (frev > 1)) {
969 u8 isb = supported_devices->info_2d1.asIntSrcInfo[i].ucIntSrcBitmap;
972 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
975 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
978 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
982 if (i == ATOM_DEVICE_DFP1_INDEX)
983 bios_connectors[i].hpd.hpd = RADEON_HPD_1;
984 else if (i == ATOM_DEVICE_DFP2_INDEX)
985 bios_connectors[i].hpd.hpd = RADEON_HPD_2;
987 bios_connectors[i].hpd.hpd = RADEON_HPD_NONE;
990 /* Always set the connector type to VGA for CRT1/CRT2. if they are
991 * shared with a DVI port, we'll pick up the DVI connector when we
992 * merge the outputs. Some bioses incorrectly list VGA ports as DVI.
994 if (i == ATOM_DEVICE_CRT1_INDEX || i == ATOM_DEVICE_CRT2_INDEX)
995 bios_connectors[i].connector_type =
996 DRM_MODE_CONNECTOR_VGA;
998 if (!radeon_atom_apply_quirks
999 (dev, (1 << i), &bios_connectors[i].connector_type,
1000 &bios_connectors[i].ddc_bus, &bios_connectors[i].line_mux,
1001 &bios_connectors[i].hpd))
1004 bios_connectors[i].valid = true;
1005 bios_connectors[i].devices = (1 << i);
1007 if (ASIC_IS_AVIVO(rdev) || radeon_r4xx_atom)
1008 radeon_add_atom_encoder(dev,
1009 radeon_get_encoder_enum(dev,
1015 radeon_add_legacy_encoder(dev,
1016 radeon_get_encoder_enum(dev,
1022 /* combine shared connectors */
1023 for (i = 0; i < max_device; i++) {
1024 if (bios_connectors[i].valid) {
1025 for (j = 0; j < max_device; j++) {
1026 if (bios_connectors[j].valid && (i != j)) {
1027 if (bios_connectors[i].line_mux ==
1028 bios_connectors[j].line_mux) {
1029 /* make sure not to combine LVDS */
1030 if (bios_connectors[i].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1031 bios_connectors[i].line_mux = 53;
1032 bios_connectors[i].ddc_bus.valid = false;
1035 if (bios_connectors[j].devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1036 bios_connectors[j].line_mux = 53;
1037 bios_connectors[j].ddc_bus.valid = false;
1040 /* combine analog and digital for DVI-I */
1041 if (((bios_connectors[i].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
1042 (bios_connectors[j].devices & (ATOM_DEVICE_CRT_SUPPORT))) ||
1043 ((bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT)) &&
1044 (bios_connectors[i].devices & (ATOM_DEVICE_CRT_SUPPORT)))) {
1045 bios_connectors[i].devices |=
1046 bios_connectors[j].devices;
1047 bios_connectors[i].connector_type =
1048 DRM_MODE_CONNECTOR_DVII;
1049 if (bios_connectors[j].devices & (ATOM_DEVICE_DFP_SUPPORT))
1050 bios_connectors[i].hpd =
1051 bios_connectors[j].hpd;
1052 bios_connectors[j].valid = false;
1060 /* add the connectors */
1061 for (i = 0; i < max_device; i++) {
1062 if (bios_connectors[i].valid) {
1063 uint16_t connector_object_id =
1064 atombios_get_connector_object_id(dev,
1065 bios_connectors[i].connector_type,
1066 bios_connectors[i].devices);
1067 radeon_add_atom_connector(dev,
1068 bios_connectors[i].line_mux,
1069 bios_connectors[i].devices,
1072 &bios_connectors[i].ddc_bus,
1074 connector_object_id,
1075 &bios_connectors[i].hpd,
1080 radeon_link_encoder_connector(dev);
1082 kfree(bios_connectors);
1086 union firmware_info {
1087 ATOM_FIRMWARE_INFO info;
1088 ATOM_FIRMWARE_INFO_V1_2 info_12;
1089 ATOM_FIRMWARE_INFO_V1_3 info_13;
1090 ATOM_FIRMWARE_INFO_V1_4 info_14;
1091 ATOM_FIRMWARE_INFO_V2_1 info_21;
1092 ATOM_FIRMWARE_INFO_V2_2 info_22;
1096 struct _ATOM_INTEGRATED_SYSTEM_INFO info;
1097 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
1098 struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 info_6;
1099 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_7 info_7;
1100 struct _ATOM_INTEGRATED_SYSTEM_INFO_V1_8 info_8;
1103 static void radeon_atombios_get_dentist_vco_freq(struct radeon_device *rdev)
1105 struct radeon_mode_info *mode_info = &rdev->mode_info;
1106 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1107 union igp_info *igp_info;
1111 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1112 &frev, &crev, &data_offset)) {
1113 igp_info = (union igp_info *)(mode_info->atom_context->bios +
1115 rdev->clock.vco_freq =
1116 le32_to_cpu(igp_info->info_6.ulDentistVCOFreq);
1120 bool radeon_atom_get_clock_info(struct drm_device *dev)
1122 struct radeon_device *rdev = dev->dev_private;
1123 struct radeon_mode_info *mode_info = &rdev->mode_info;
1124 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
1125 union firmware_info *firmware_info;
1127 struct radeon_pll *p1pll = &rdev->clock.p1pll;
1128 struct radeon_pll *p2pll = &rdev->clock.p2pll;
1129 struct radeon_pll *dcpll = &rdev->clock.dcpll;
1130 struct radeon_pll *spll = &rdev->clock.spll;
1131 struct radeon_pll *mpll = &rdev->clock.mpll;
1132 uint16_t data_offset;
1134 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1135 &frev, &crev, &data_offset)) {
1137 (union firmware_info *)(mode_info->atom_context->bios +
1140 p1pll->reference_freq =
1141 le16_to_cpu(firmware_info->info.usReferenceClock);
1142 p1pll->reference_div = 0;
1144 if ((frev < 2) && (crev < 2))
1145 p1pll->pll_out_min =
1146 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Output);
1148 p1pll->pll_out_min =
1149 le32_to_cpu(firmware_info->info_12.ulMinPixelClockPLL_Output);
1150 p1pll->pll_out_max =
1151 le32_to_cpu(firmware_info->info.ulMaxPixelClockPLL_Output);
1153 if (((frev < 2) && (crev >= 4)) || (frev >= 2)) {
1154 p1pll->lcd_pll_out_min =
1155 le16_to_cpu(firmware_info->info_14.usLcdMinPixelClockPLL_Output) * 100;
1156 if (p1pll->lcd_pll_out_min == 0)
1157 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
1158 p1pll->lcd_pll_out_max =
1159 le16_to_cpu(firmware_info->info_14.usLcdMaxPixelClockPLL_Output) * 100;
1160 if (p1pll->lcd_pll_out_max == 0)
1161 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
1163 p1pll->lcd_pll_out_min = p1pll->pll_out_min;
1164 p1pll->lcd_pll_out_max = p1pll->pll_out_max;
1167 if (p1pll->pll_out_min == 0) {
1168 if (ASIC_IS_AVIVO(rdev))
1169 p1pll->pll_out_min = 64800;
1171 p1pll->pll_out_min = 20000;
1175 le16_to_cpu(firmware_info->info.usMinPixelClockPLL_Input);
1177 le16_to_cpu(firmware_info->info.usMaxPixelClockPLL_Input);
1182 if (ASIC_IS_DCE4(rdev))
1183 spll->reference_freq =
1184 le16_to_cpu(firmware_info->info_21.usCoreReferenceClock);
1186 spll->reference_freq =
1187 le16_to_cpu(firmware_info->info.usReferenceClock);
1188 spll->reference_div = 0;
1191 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Output);
1193 le32_to_cpu(firmware_info->info.ulMaxEngineClockPLL_Output);
1196 if (spll->pll_out_min == 0) {
1197 if (ASIC_IS_AVIVO(rdev))
1198 spll->pll_out_min = 64800;
1200 spll->pll_out_min = 20000;
1204 le16_to_cpu(firmware_info->info.usMinEngineClockPLL_Input);
1206 le16_to_cpu(firmware_info->info.usMaxEngineClockPLL_Input);
1209 if (ASIC_IS_DCE4(rdev))
1210 mpll->reference_freq =
1211 le16_to_cpu(firmware_info->info_21.usMemoryReferenceClock);
1213 mpll->reference_freq =
1214 le16_to_cpu(firmware_info->info.usReferenceClock);
1215 mpll->reference_div = 0;
1218 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Output);
1220 le32_to_cpu(firmware_info->info.ulMaxMemoryClockPLL_Output);
1223 if (mpll->pll_out_min == 0) {
1224 if (ASIC_IS_AVIVO(rdev))
1225 mpll->pll_out_min = 64800;
1227 mpll->pll_out_min = 20000;
1231 le16_to_cpu(firmware_info->info.usMinMemoryClockPLL_Input);
1233 le16_to_cpu(firmware_info->info.usMaxMemoryClockPLL_Input);
1235 rdev->clock.default_sclk =
1236 le32_to_cpu(firmware_info->info.ulDefaultEngineClock);
1237 rdev->clock.default_mclk =
1238 le32_to_cpu(firmware_info->info.ulDefaultMemoryClock);
1240 if (ASIC_IS_DCE4(rdev)) {
1241 rdev->clock.default_dispclk =
1242 le32_to_cpu(firmware_info->info_21.ulDefaultDispEngineClkFreq);
1243 if (rdev->clock.default_dispclk == 0) {
1244 if (ASIC_IS_DCE6(rdev))
1245 rdev->clock.default_dispclk = 60000; /* 600 Mhz */
1246 else if (ASIC_IS_DCE5(rdev))
1247 rdev->clock.default_dispclk = 54000; /* 540 Mhz */
1249 rdev->clock.default_dispclk = 60000; /* 600 Mhz */
1251 /* set a reasonable default for DP */
1252 if (ASIC_IS_DCE6(rdev) && (rdev->clock.default_dispclk < 53900)) {
1253 DRM_INFO("Changing default dispclk from %dMhz to 600Mhz\n",
1254 rdev->clock.default_dispclk / 100);
1255 rdev->clock.default_dispclk = 60000;
1257 rdev->clock.dp_extclk =
1258 le16_to_cpu(firmware_info->info_21.usUniphyDPModeExtClkFreq);
1259 rdev->clock.current_dispclk = rdev->clock.default_dispclk;
1263 rdev->clock.max_pixel_clock = le16_to_cpu(firmware_info->info.usMaxPixelClock);
1264 if (rdev->clock.max_pixel_clock == 0)
1265 rdev->clock.max_pixel_clock = 40000;
1267 /* not technically a clock, but... */
1268 rdev->mode_info.firmware_flags =
1269 le16_to_cpu(firmware_info->info.usFirmwareCapability.susAccess);
1271 if (ASIC_IS_DCE8(rdev))
1272 rdev->clock.vco_freq =
1273 le32_to_cpu(firmware_info->info_22.ulGPUPLL_OutputFreq);
1274 else if (ASIC_IS_DCE5(rdev))
1275 rdev->clock.vco_freq = rdev->clock.current_dispclk;
1276 else if (ASIC_IS_DCE41(rdev))
1277 radeon_atombios_get_dentist_vco_freq(rdev);
1279 rdev->clock.vco_freq = rdev->clock.current_dispclk;
1281 if (rdev->clock.vco_freq == 0)
1282 rdev->clock.vco_freq = 360000; /* 3.6 GHz */
1290 bool radeon_atombios_sideport_present(struct radeon_device *rdev)
1292 struct radeon_mode_info *mode_info = &rdev->mode_info;
1293 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1294 union igp_info *igp_info;
1298 /* sideport is AMD only */
1299 if (rdev->family == CHIP_RS600)
1302 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1303 &frev, &crev, &data_offset)) {
1304 igp_info = (union igp_info *)(mode_info->atom_context->bios +
1308 if (le32_to_cpu(igp_info->info.ulBootUpMemoryClock))
1312 if (le32_to_cpu(igp_info->info_2.ulBootUpSidePortClock))
1316 DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
1323 bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
1324 struct radeon_encoder_int_tmds *tmds)
1326 struct drm_device *dev = encoder->base.dev;
1327 struct radeon_device *rdev = dev->dev_private;
1328 struct radeon_mode_info *mode_info = &rdev->mode_info;
1329 int index = GetIndexIntoMasterTable(DATA, TMDS_Info);
1330 uint16_t data_offset;
1331 struct _ATOM_TMDS_INFO *tmds_info;
1336 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1337 &frev, &crev, &data_offset)) {
1339 (struct _ATOM_TMDS_INFO *)(mode_info->atom_context->bios +
1342 maxfreq = le16_to_cpu(tmds_info->usMaxFrequency);
1343 for (i = 0; i < 4; i++) {
1344 tmds->tmds_pll[i].freq =
1345 le16_to_cpu(tmds_info->asMiscInfo[i].usFrequency);
1346 tmds->tmds_pll[i].value =
1347 tmds_info->asMiscInfo[i].ucPLL_ChargePump & 0x3f;
1348 tmds->tmds_pll[i].value |=
1349 (tmds_info->asMiscInfo[i].
1350 ucPLL_VCO_Gain & 0x3f) << 6;
1351 tmds->tmds_pll[i].value |=
1352 (tmds_info->asMiscInfo[i].
1353 ucPLL_DutyCycle & 0xf) << 12;
1354 tmds->tmds_pll[i].value |=
1355 (tmds_info->asMiscInfo[i].
1356 ucPLL_VoltageSwing & 0xf) << 16;
1358 DRM_DEBUG_KMS("TMDS PLL From ATOMBIOS %u %x\n",
1359 tmds->tmds_pll[i].freq,
1360 tmds->tmds_pll[i].value);
1362 if (maxfreq == tmds->tmds_pll[i].freq) {
1363 tmds->tmds_pll[i].freq = 0xffffffff;
1372 bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev,
1373 struct radeon_atom_ss *ss,
1376 struct radeon_mode_info *mode_info = &rdev->mode_info;
1377 int index = GetIndexIntoMasterTable(DATA, PPLL_SS_Info);
1378 uint16_t data_offset, size;
1379 struct _ATOM_SPREAD_SPECTRUM_INFO *ss_info;
1380 struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT *ss_assign;
1384 memset(ss, 0, sizeof(struct radeon_atom_ss));
1385 if (atom_parse_data_header(mode_info->atom_context, index, &size,
1386 &frev, &crev, &data_offset)) {
1388 (struct _ATOM_SPREAD_SPECTRUM_INFO *)(mode_info->atom_context->bios + data_offset);
1390 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1391 sizeof(ATOM_SPREAD_SPECTRUM_ASSIGNMENT);
1392 ss_assign = (struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT*)
1393 ((u8 *)&ss_info->asSS_Info[0]);
1394 for (i = 0; i < num_indices; i++) {
1395 if (ss_assign->ucSS_Id == id) {
1397 le16_to_cpu(ss_assign->usSpreadSpectrumPercentage);
1398 ss->type = ss_assign->ucSpreadSpectrumType;
1399 ss->step = ss_assign->ucSS_Step;
1400 ss->delay = ss_assign->ucSS_Delay;
1401 ss->range = ss_assign->ucSS_Range;
1402 ss->refdiv = ss_assign->ucRecommendedRef_Div;
1405 ss_assign = (struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT*)
1406 ((u8 *)ss_assign + sizeof(struct _ATOM_SPREAD_SPECTRUM_ASSIGNMENT));
1412 static void radeon_atombios_get_igp_ss_overrides(struct radeon_device *rdev,
1413 struct radeon_atom_ss *ss,
1416 struct radeon_mode_info *mode_info = &rdev->mode_info;
1417 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1418 u16 data_offset, size;
1419 union igp_info *igp_info;
1421 u16 percentage = 0, rate = 0;
1423 /* get any igp specific overrides */
1424 if (atom_parse_data_header(mode_info->atom_context, index, &size,
1425 &frev, &crev, &data_offset)) {
1426 igp_info = (union igp_info *)
1427 (mode_info->atom_context->bios + data_offset);
1431 case ASIC_INTERNAL_SS_ON_TMDS:
1432 percentage = le16_to_cpu(igp_info->info_6.usDVISSPercentage);
1433 rate = le16_to_cpu(igp_info->info_6.usDVISSpreadRateIn10Hz);
1435 case ASIC_INTERNAL_SS_ON_HDMI:
1436 percentage = le16_to_cpu(igp_info->info_6.usHDMISSPercentage);
1437 rate = le16_to_cpu(igp_info->info_6.usHDMISSpreadRateIn10Hz);
1439 case ASIC_INTERNAL_SS_ON_LVDS:
1440 percentage = le16_to_cpu(igp_info->info_6.usLvdsSSPercentage);
1441 rate = le16_to_cpu(igp_info->info_6.usLvdsSSpreadRateIn10Hz);
1447 case ASIC_INTERNAL_SS_ON_TMDS:
1448 percentage = le16_to_cpu(igp_info->info_7.usDVISSPercentage);
1449 rate = le16_to_cpu(igp_info->info_7.usDVISSpreadRateIn10Hz);
1451 case ASIC_INTERNAL_SS_ON_HDMI:
1452 percentage = le16_to_cpu(igp_info->info_7.usHDMISSPercentage);
1453 rate = le16_to_cpu(igp_info->info_7.usHDMISSpreadRateIn10Hz);
1455 case ASIC_INTERNAL_SS_ON_LVDS:
1456 percentage = le16_to_cpu(igp_info->info_7.usLvdsSSPercentage);
1457 rate = le16_to_cpu(igp_info->info_7.usLvdsSSpreadRateIn10Hz);
1463 case ASIC_INTERNAL_SS_ON_TMDS:
1464 percentage = le16_to_cpu(igp_info->info_8.usDVISSPercentage);
1465 rate = le16_to_cpu(igp_info->info_8.usDVISSpreadRateIn10Hz);
1467 case ASIC_INTERNAL_SS_ON_HDMI:
1468 percentage = le16_to_cpu(igp_info->info_8.usHDMISSPercentage);
1469 rate = le16_to_cpu(igp_info->info_8.usHDMISSpreadRateIn10Hz);
1471 case ASIC_INTERNAL_SS_ON_LVDS:
1472 percentage = le16_to_cpu(igp_info->info_8.usLvdsSSPercentage);
1473 rate = le16_to_cpu(igp_info->info_8.usLvdsSSpreadRateIn10Hz);
1478 DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
1482 ss->percentage = percentage;
1488 union asic_ss_info {
1489 struct _ATOM_ASIC_INTERNAL_SS_INFO info;
1490 struct _ATOM_ASIC_INTERNAL_SS_INFO_V2 info_2;
1491 struct _ATOM_ASIC_INTERNAL_SS_INFO_V3 info_3;
1494 union asic_ss_assignment {
1495 struct _ATOM_ASIC_SS_ASSIGNMENT v1;
1496 struct _ATOM_ASIC_SS_ASSIGNMENT_V2 v2;
1497 struct _ATOM_ASIC_SS_ASSIGNMENT_V3 v3;
1500 bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev,
1501 struct radeon_atom_ss *ss,
1504 struct radeon_mode_info *mode_info = &rdev->mode_info;
1505 int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info);
1506 uint16_t data_offset, size;
1507 union asic_ss_info *ss_info;
1508 union asic_ss_assignment *ss_assign;
1512 if (id == ASIC_INTERNAL_MEMORY_SS) {
1513 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_MEMORY_CLOCK_SS_SUPPORT))
1516 if (id == ASIC_INTERNAL_ENGINE_SS) {
1517 if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_ENGINE_CLOCK_SS_SUPPORT))
1521 memset(ss, 0, sizeof(struct radeon_atom_ss));
1522 if (atom_parse_data_header(mode_info->atom_context, index, &size,
1523 &frev, &crev, &data_offset)) {
1526 (union asic_ss_info *)(mode_info->atom_context->bios + data_offset);
1530 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1531 sizeof(ATOM_ASIC_SS_ASSIGNMENT);
1533 ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info.asSpreadSpectrum[0]);
1534 for (i = 0; i < num_indices; i++) {
1535 if ((ss_assign->v1.ucClockIndication == id) &&
1536 (clock <= le32_to_cpu(ss_assign->v1.ulTargetClockRange))) {
1538 le16_to_cpu(ss_assign->v1.usSpreadSpectrumPercentage);
1539 ss->type = ss_assign->v1.ucSpreadSpectrumMode;
1540 ss->rate = le16_to_cpu(ss_assign->v1.usSpreadRateInKhz);
1541 ss->percentage_divider = 100;
1544 ss_assign = (union asic_ss_assignment *)
1545 ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT));
1549 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1550 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2);
1551 ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info_2.asSpreadSpectrum[0]);
1552 for (i = 0; i < num_indices; i++) {
1553 if ((ss_assign->v2.ucClockIndication == id) &&
1554 (clock <= le32_to_cpu(ss_assign->v2.ulTargetClockRange))) {
1556 le16_to_cpu(ss_assign->v2.usSpreadSpectrumPercentage);
1557 ss->type = ss_assign->v2.ucSpreadSpectrumMode;
1558 ss->rate = le16_to_cpu(ss_assign->v2.usSpreadRateIn10Hz);
1559 ss->percentage_divider = 100;
1561 ((id == ASIC_INTERNAL_ENGINE_SS) ||
1562 (id == ASIC_INTERNAL_MEMORY_SS)))
1566 ss_assign = (union asic_ss_assignment *)
1567 ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT_V2));
1571 num_indices = (size - sizeof(ATOM_COMMON_TABLE_HEADER)) /
1572 sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3);
1573 ss_assign = (union asic_ss_assignment *)((u8 *)&ss_info->info_3.asSpreadSpectrum[0]);
1574 for (i = 0; i < num_indices; i++) {
1575 if ((ss_assign->v3.ucClockIndication == id) &&
1576 (clock <= le32_to_cpu(ss_assign->v3.ulTargetClockRange))) {
1578 le16_to_cpu(ss_assign->v3.usSpreadSpectrumPercentage);
1579 ss->type = ss_assign->v3.ucSpreadSpectrumMode;
1580 ss->rate = le16_to_cpu(ss_assign->v3.usSpreadRateIn10Hz);
1581 if (ss_assign->v3.ucSpreadSpectrumMode &
1582 SS_MODE_V3_PERCENTAGE_DIV_BY_1000_MASK)
1583 ss->percentage_divider = 1000;
1585 ss->percentage_divider = 100;
1586 if ((id == ASIC_INTERNAL_ENGINE_SS) ||
1587 (id == ASIC_INTERNAL_MEMORY_SS))
1589 if (rdev->flags & RADEON_IS_IGP)
1590 radeon_atombios_get_igp_ss_overrides(rdev, ss, id);
1593 ss_assign = (union asic_ss_assignment *)
1594 ((u8 *)ss_assign + sizeof(ATOM_ASIC_SS_ASSIGNMENT_V3));
1598 DRM_ERROR("Unsupported ASIC_InternalSS_Info table: %d %d\n", frev, crev);
1607 struct _ATOM_LVDS_INFO info;
1608 struct _ATOM_LVDS_INFO_V12 info_12;
1611 struct radeon_encoder_atom_dig *radeon_atombios_get_lvds_info(struct
1615 struct drm_device *dev = encoder->base.dev;
1616 struct radeon_device *rdev = dev->dev_private;
1617 struct radeon_mode_info *mode_info = &rdev->mode_info;
1618 int index = GetIndexIntoMasterTable(DATA, LVDS_Info);
1619 uint16_t data_offset, misc;
1620 union lvds_info *lvds_info;
1622 struct radeon_encoder_atom_dig *lvds = NULL;
1623 int encoder_enum = (encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
1625 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1626 &frev, &crev, &data_offset)) {
1628 (union lvds_info *)(mode_info->atom_context->bios + data_offset);
1630 kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
1635 lvds->native_mode.clock =
1636 le16_to_cpu(lvds_info->info.sLCDTiming.usPixClk) * 10;
1637 lvds->native_mode.hdisplay =
1638 le16_to_cpu(lvds_info->info.sLCDTiming.usHActive);
1639 lvds->native_mode.vdisplay =
1640 le16_to_cpu(lvds_info->info.sLCDTiming.usVActive);
1641 lvds->native_mode.htotal = lvds->native_mode.hdisplay +
1642 le16_to_cpu(lvds_info->info.sLCDTiming.usHBlanking_Time);
1643 lvds->native_mode.hsync_start = lvds->native_mode.hdisplay +
1644 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncOffset);
1645 lvds->native_mode.hsync_end = lvds->native_mode.hsync_start +
1646 le16_to_cpu(lvds_info->info.sLCDTiming.usHSyncWidth);
1647 lvds->native_mode.vtotal = lvds->native_mode.vdisplay +
1648 le16_to_cpu(lvds_info->info.sLCDTiming.usVBlanking_Time);
1649 lvds->native_mode.vsync_start = lvds->native_mode.vdisplay +
1650 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncOffset);
1651 lvds->native_mode.vsync_end = lvds->native_mode.vsync_start +
1652 le16_to_cpu(lvds_info->info.sLCDTiming.usVSyncWidth);
1653 lvds->panel_pwr_delay =
1654 le16_to_cpu(lvds_info->info.usOffDelayInMs);
1655 lvds->lcd_misc = lvds_info->info.ucLVDS_Misc;
1657 misc = le16_to_cpu(lvds_info->info.sLCDTiming.susModeMiscInfo.usAccess);
1658 if (misc & ATOM_VSYNC_POLARITY)
1659 lvds->native_mode.flags |= DRM_MODE_FLAG_NVSYNC;
1660 if (misc & ATOM_HSYNC_POLARITY)
1661 lvds->native_mode.flags |= DRM_MODE_FLAG_NHSYNC;
1662 if (misc & ATOM_COMPOSITESYNC)
1663 lvds->native_mode.flags |= DRM_MODE_FLAG_CSYNC;
1664 if (misc & ATOM_INTERLACE)
1665 lvds->native_mode.flags |= DRM_MODE_FLAG_INTERLACE;
1666 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1667 lvds->native_mode.flags |= DRM_MODE_FLAG_DBLSCAN;
1669 lvds->native_mode.width_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageHSize);
1670 lvds->native_mode.height_mm = le16_to_cpu(lvds_info->info.sLCDTiming.usImageVSize);
1672 /* set crtc values */
1673 drm_mode_set_crtcinfo(&lvds->native_mode, CRTC_INTERLACE_HALVE_V);
1675 lvds->lcd_ss_id = lvds_info->info.ucSS_Id;
1677 encoder->native_mode = lvds->native_mode;
1679 if (encoder_enum == 2)
1682 lvds->linkb = false;
1684 /* parse the lcd record table */
1685 if (le16_to_cpu(lvds_info->info.usModePatchTableOffset)) {
1686 ATOM_FAKE_EDID_PATCH_RECORD *fake_edid_record;
1687 ATOM_PANEL_RESOLUTION_PATCH_RECORD *panel_res_record;
1688 bool bad_record = false;
1691 if ((frev == 1) && (crev < 2))
1693 record = (u8 *)(mode_info->atom_context->bios +
1694 le16_to_cpu(lvds_info->info.usModePatchTableOffset));
1697 record = (u8 *)(mode_info->atom_context->bios +
1699 le16_to_cpu(lvds_info->info.usModePatchTableOffset));
1700 while (*record != ATOM_RECORD_END_TYPE) {
1702 case LCD_MODE_PATCH_RECORD_MODE_TYPE:
1703 record += sizeof(ATOM_PATCH_RECORD_MODE);
1705 case LCD_RTS_RECORD_TYPE:
1706 record += sizeof(ATOM_LCD_RTS_RECORD);
1708 case LCD_CAP_RECORD_TYPE:
1709 record += sizeof(ATOM_LCD_MODE_CONTROL_CAP);
1711 case LCD_FAKE_EDID_PATCH_RECORD_TYPE:
1712 fake_edid_record = (ATOM_FAKE_EDID_PATCH_RECORD *)record;
1713 if (fake_edid_record->ucFakeEDIDLength) {
1716 max((int)EDID_LENGTH, (int)fake_edid_record->ucFakeEDIDLength);
1717 edid = kmalloc(edid_size, GFP_KERNEL);
1719 memcpy((u8 *)edid, (u8 *)&fake_edid_record->ucFakeEDIDString[0],
1720 fake_edid_record->ucFakeEDIDLength);
1722 if (drm_edid_is_valid(edid)) {
1723 rdev->mode_info.bios_hardcoded_edid = edid;
1724 rdev->mode_info.bios_hardcoded_edid_size = edid_size;
1729 record += fake_edid_record->ucFakeEDIDLength ?
1730 struct_size(fake_edid_record,
1732 fake_edid_record->ucFakeEDIDLength) :
1733 /* empty fake edid record must be 3 bytes long */
1734 sizeof(ATOM_FAKE_EDID_PATCH_RECORD) + 1;
1736 case LCD_PANEL_RESOLUTION_RECORD_TYPE:
1737 panel_res_record = (ATOM_PANEL_RESOLUTION_PATCH_RECORD *)record;
1738 lvds->native_mode.width_mm = panel_res_record->usHSize;
1739 lvds->native_mode.height_mm = panel_res_record->usVSize;
1740 record += sizeof(ATOM_PANEL_RESOLUTION_PATCH_RECORD);
1743 DRM_ERROR("Bad LCD record %d\n", *record);
1755 struct radeon_encoder_primary_dac *
1756 radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder)
1758 struct drm_device *dev = encoder->base.dev;
1759 struct radeon_device *rdev = dev->dev_private;
1760 struct radeon_mode_info *mode_info = &rdev->mode_info;
1761 int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1762 uint16_t data_offset;
1763 struct _COMPASSIONATE_DATA *dac_info;
1766 struct radeon_encoder_primary_dac *p_dac = NULL;
1768 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1769 &frev, &crev, &data_offset)) {
1770 dac_info = (struct _COMPASSIONATE_DATA *)
1771 (mode_info->atom_context->bios + data_offset);
1773 p_dac = kzalloc(sizeof(struct radeon_encoder_primary_dac), GFP_KERNEL);
1778 bg = dac_info->ucDAC1_BG_Adjustment;
1779 dac = dac_info->ucDAC1_DAC_Adjustment;
1780 p_dac->ps2_pdac_adj = (bg << 8) | (dac);
1786 bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index,
1787 struct drm_display_mode *mode)
1789 struct radeon_mode_info *mode_info = &rdev->mode_info;
1790 ATOM_ANALOG_TV_INFO *tv_info;
1791 ATOM_ANALOG_TV_INFO_V1_2 *tv_info_v1_2;
1792 ATOM_DTD_FORMAT *dtd_timings;
1793 int data_index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1795 u16 data_offset, misc;
1797 if (!atom_parse_data_header(mode_info->atom_context, data_index, NULL,
1798 &frev, &crev, &data_offset))
1803 tv_info = (ATOM_ANALOG_TV_INFO *)(mode_info->atom_context->bios + data_offset);
1804 if (index >= MAX_SUPPORTED_TV_TIMING)
1807 mode->crtc_htotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Total);
1808 mode->crtc_hdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_Disp);
1809 mode->crtc_hsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart);
1810 mode->crtc_hsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncStart) +
1811 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_H_SyncWidth);
1813 mode->crtc_vtotal = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Total);
1814 mode->crtc_vdisplay = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_Disp);
1815 mode->crtc_vsync_start = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart);
1816 mode->crtc_vsync_end = le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncStart) +
1817 le16_to_cpu(tv_info->aModeTimings[index].usCRTC_V_SyncWidth);
1820 misc = le16_to_cpu(tv_info->aModeTimings[index].susModeMiscInfo.usAccess);
1821 if (misc & ATOM_VSYNC_POLARITY)
1822 mode->flags |= DRM_MODE_FLAG_NVSYNC;
1823 if (misc & ATOM_HSYNC_POLARITY)
1824 mode->flags |= DRM_MODE_FLAG_NHSYNC;
1825 if (misc & ATOM_COMPOSITESYNC)
1826 mode->flags |= DRM_MODE_FLAG_CSYNC;
1827 if (misc & ATOM_INTERLACE)
1828 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1829 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1830 mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1832 mode->crtc_clock = mode->clock =
1833 le16_to_cpu(tv_info->aModeTimings[index].usPixelClock) * 10;
1836 /* PAL timings appear to have wrong values for totals */
1837 mode->crtc_htotal -= 1;
1838 mode->crtc_vtotal -= 1;
1842 tv_info_v1_2 = (ATOM_ANALOG_TV_INFO_V1_2 *)(mode_info->atom_context->bios + data_offset);
1843 if (index >= MAX_SUPPORTED_TV_TIMING_V1_2)
1846 dtd_timings = &tv_info_v1_2->aModeTimings[index];
1847 mode->crtc_htotal = le16_to_cpu(dtd_timings->usHActive) +
1848 le16_to_cpu(dtd_timings->usHBlanking_Time);
1849 mode->crtc_hdisplay = le16_to_cpu(dtd_timings->usHActive);
1850 mode->crtc_hsync_start = le16_to_cpu(dtd_timings->usHActive) +
1851 le16_to_cpu(dtd_timings->usHSyncOffset);
1852 mode->crtc_hsync_end = mode->crtc_hsync_start +
1853 le16_to_cpu(dtd_timings->usHSyncWidth);
1855 mode->crtc_vtotal = le16_to_cpu(dtd_timings->usVActive) +
1856 le16_to_cpu(dtd_timings->usVBlanking_Time);
1857 mode->crtc_vdisplay = le16_to_cpu(dtd_timings->usVActive);
1858 mode->crtc_vsync_start = le16_to_cpu(dtd_timings->usVActive) +
1859 le16_to_cpu(dtd_timings->usVSyncOffset);
1860 mode->crtc_vsync_end = mode->crtc_vsync_start +
1861 le16_to_cpu(dtd_timings->usVSyncWidth);
1864 misc = le16_to_cpu(dtd_timings->susModeMiscInfo.usAccess);
1865 if (misc & ATOM_VSYNC_POLARITY)
1866 mode->flags |= DRM_MODE_FLAG_NVSYNC;
1867 if (misc & ATOM_HSYNC_POLARITY)
1868 mode->flags |= DRM_MODE_FLAG_NHSYNC;
1869 if (misc & ATOM_COMPOSITESYNC)
1870 mode->flags |= DRM_MODE_FLAG_CSYNC;
1871 if (misc & ATOM_INTERLACE)
1872 mode->flags |= DRM_MODE_FLAG_INTERLACE;
1873 if (misc & ATOM_DOUBLE_CLOCK_MODE)
1874 mode->flags |= DRM_MODE_FLAG_DBLSCAN;
1876 mode->crtc_clock = mode->clock =
1877 le16_to_cpu(dtd_timings->usPixClk) * 10;
1884 radeon_atombios_get_tv_info(struct radeon_device *rdev)
1886 struct radeon_mode_info *mode_info = &rdev->mode_info;
1887 int index = GetIndexIntoMasterTable(DATA, AnalogTV_Info);
1888 uint16_t data_offset;
1890 struct _ATOM_ANALOG_TV_INFO *tv_info;
1891 enum radeon_tv_std tv_std = TV_STD_NTSC;
1893 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1894 &frev, &crev, &data_offset)) {
1896 tv_info = (struct _ATOM_ANALOG_TV_INFO *)
1897 (mode_info->atom_context->bios + data_offset);
1899 switch (tv_info->ucTV_BootUpDefaultStandard) {
1901 tv_std = TV_STD_NTSC;
1902 DRM_DEBUG_KMS("Default TV standard: NTSC\n");
1905 tv_std = TV_STD_NTSC_J;
1906 DRM_DEBUG_KMS("Default TV standard: NTSC-J\n");
1909 tv_std = TV_STD_PAL;
1910 DRM_DEBUG_KMS("Default TV standard: PAL\n");
1913 tv_std = TV_STD_PAL_M;
1914 DRM_DEBUG_KMS("Default TV standard: PAL-M\n");
1917 tv_std = TV_STD_PAL_N;
1918 DRM_DEBUG_KMS("Default TV standard: PAL-N\n");
1921 tv_std = TV_STD_PAL_CN;
1922 DRM_DEBUG_KMS("Default TV standard: PAL-CN\n");
1925 tv_std = TV_STD_PAL_60;
1926 DRM_DEBUG_KMS("Default TV standard: PAL-60\n");
1929 tv_std = TV_STD_SECAM;
1930 DRM_DEBUG_KMS("Default TV standard: SECAM\n");
1933 tv_std = TV_STD_NTSC;
1934 DRM_DEBUG_KMS("Unknown TV standard; defaulting to NTSC\n");
1941 struct radeon_encoder_tv_dac *
1942 radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder)
1944 struct drm_device *dev = encoder->base.dev;
1945 struct radeon_device *rdev = dev->dev_private;
1946 struct radeon_mode_info *mode_info = &rdev->mode_info;
1947 int index = GetIndexIntoMasterTable(DATA, CompassionateData);
1948 uint16_t data_offset;
1949 struct _COMPASSIONATE_DATA *dac_info;
1952 struct radeon_encoder_tv_dac *tv_dac = NULL;
1954 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1955 &frev, &crev, &data_offset)) {
1957 dac_info = (struct _COMPASSIONATE_DATA *)
1958 (mode_info->atom_context->bios + data_offset);
1960 tv_dac = kzalloc(sizeof(struct radeon_encoder_tv_dac), GFP_KERNEL);
1965 bg = dac_info->ucDAC2_CRT2_BG_Adjustment;
1966 dac = dac_info->ucDAC2_CRT2_DAC_Adjustment;
1967 tv_dac->ps2_tvdac_adj = (bg << 16) | (dac << 20);
1969 bg = dac_info->ucDAC2_PAL_BG_Adjustment;
1970 dac = dac_info->ucDAC2_PAL_DAC_Adjustment;
1971 tv_dac->pal_tvdac_adj = (bg << 16) | (dac << 20);
1973 bg = dac_info->ucDAC2_NTSC_BG_Adjustment;
1974 dac = dac_info->ucDAC2_NTSC_DAC_Adjustment;
1975 tv_dac->ntsc_tvdac_adj = (bg << 16) | (dac << 20);
1977 tv_dac->tv_std = radeon_atombios_get_tv_info(rdev);
1982 static const char *thermal_controller_names[] = {
1993 static const char *pp_lib_thermal_controller_names[] = {
2016 struct _ATOM_POWERPLAY_INFO info;
2017 struct _ATOM_POWERPLAY_INFO_V2 info_2;
2018 struct _ATOM_POWERPLAY_INFO_V3 info_3;
2019 struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
2020 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
2021 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
2024 union pplib_clock_info {
2025 struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
2026 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
2027 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
2028 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
2029 struct _ATOM_PPLIB_SI_CLOCK_INFO si;
2030 struct _ATOM_PPLIB_CI_CLOCK_INFO ci;
2033 union pplib_power_state {
2034 struct _ATOM_PPLIB_STATE v1;
2035 struct _ATOM_PPLIB_STATE_V2 v2;
2038 static void radeon_atombios_parse_misc_flags_1_3(struct radeon_device *rdev,
2040 u32 misc, u32 misc2)
2042 rdev->pm.power_state[state_index].misc = misc;
2043 rdev->pm.power_state[state_index].misc2 = misc2;
2044 /* order matters! */
2045 if (misc & ATOM_PM_MISCINFO_POWER_SAVING_MODE)
2046 rdev->pm.power_state[state_index].type =
2047 POWER_STATE_TYPE_POWERSAVE;
2048 if (misc & ATOM_PM_MISCINFO_DEFAULT_DC_STATE_ENTRY_TRUE)
2049 rdev->pm.power_state[state_index].type =
2050 POWER_STATE_TYPE_BATTERY;
2051 if (misc & ATOM_PM_MISCINFO_DEFAULT_LOW_DC_STATE_ENTRY_TRUE)
2052 rdev->pm.power_state[state_index].type =
2053 POWER_STATE_TYPE_BATTERY;
2054 if (misc & ATOM_PM_MISCINFO_LOAD_BALANCE_EN)
2055 rdev->pm.power_state[state_index].type =
2056 POWER_STATE_TYPE_BALANCED;
2057 if (misc & ATOM_PM_MISCINFO_3D_ACCELERATION_EN) {
2058 rdev->pm.power_state[state_index].type =
2059 POWER_STATE_TYPE_PERFORMANCE;
2060 rdev->pm.power_state[state_index].flags &=
2061 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2063 if (misc2 & ATOM_PM_MISCINFO2_SYSTEM_AC_LITE_MODE)
2064 rdev->pm.power_state[state_index].type =
2065 POWER_STATE_TYPE_BALANCED;
2066 if (misc & ATOM_PM_MISCINFO_DRIVER_DEFAULT_MODE) {
2067 rdev->pm.power_state[state_index].type =
2068 POWER_STATE_TYPE_DEFAULT;
2069 rdev->pm.default_power_state_index = state_index;
2070 rdev->pm.power_state[state_index].default_clock_mode =
2071 &rdev->pm.power_state[state_index].clock_info[0];
2072 } else if (state_index == 0) {
2073 rdev->pm.power_state[state_index].clock_info[0].flags |=
2074 RADEON_PM_MODE_NO_DISPLAY;
2078 static int radeon_atombios_parse_power_table_1_3(struct radeon_device *rdev)
2080 struct radeon_mode_info *mode_info = &rdev->mode_info;
2081 u32 misc, misc2 = 0;
2082 int num_modes = 0, i;
2083 int state_index = 0;
2084 struct radeon_i2c_bus_rec i2c_bus;
2085 union power_info *power_info;
2086 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2090 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2091 &frev, &crev, &data_offset))
2093 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2095 /* add the i2c bus for thermal/fan chip */
2096 if ((power_info->info.ucOverdriveThermalController > 0) &&
2097 (power_info->info.ucOverdriveThermalController < ARRAY_SIZE(thermal_controller_names))) {
2098 DRM_INFO("Possible %s thermal controller at 0x%02x\n",
2099 thermal_controller_names[power_info->info.ucOverdriveThermalController],
2100 power_info->info.ucOverdriveControllerAddress >> 1);
2101 i2c_bus = radeon_lookup_i2c_gpio(rdev, power_info->info.ucOverdriveI2cLine);
2102 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2103 if (rdev->pm.i2c_bus) {
2104 struct i2c_board_info info = { };
2105 const char *name = thermal_controller_names[power_info->info.
2106 ucOverdriveThermalController];
2107 info.addr = power_info->info.ucOverdriveControllerAddress >> 1;
2108 strlcpy(info.type, name, sizeof(info.type));
2109 i2c_new_client_device(&rdev->pm.i2c_bus->adapter, &info);
2112 num_modes = power_info->info.ucNumOfPowerModeEntries;
2113 if (num_modes > ATOM_MAX_NUMBEROF_POWER_BLOCK)
2114 num_modes = ATOM_MAX_NUMBEROF_POWER_BLOCK;
2117 rdev->pm.power_state = kcalloc(num_modes,
2118 sizeof(struct radeon_power_state),
2120 if (!rdev->pm.power_state)
2122 /* last mode is usually default, array is low to high */
2123 for (i = 0; i < num_modes; i++) {
2124 /* avoid memory leaks from invalid modes or unknown frev. */
2125 if (!rdev->pm.power_state[state_index].clock_info) {
2126 rdev->pm.power_state[state_index].clock_info =
2127 kzalloc(sizeof(struct radeon_pm_clock_info),
2130 if (!rdev->pm.power_state[state_index].clock_info)
2132 rdev->pm.power_state[state_index].num_clock_modes = 1;
2133 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2136 rdev->pm.power_state[state_index].clock_info[0].mclk =
2137 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usMemoryClock);
2138 rdev->pm.power_state[state_index].clock_info[0].sclk =
2139 le16_to_cpu(power_info->info.asPowerPlayInfo[i].usEngineClock);
2140 /* skip invalid modes */
2141 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2142 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2144 rdev->pm.power_state[state_index].pcie_lanes =
2145 power_info->info.asPowerPlayInfo[i].ucNumPciELanes;
2146 misc = le32_to_cpu(power_info->info.asPowerPlayInfo[i].ulMiscInfo);
2147 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2148 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2149 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2151 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2152 radeon_atombios_lookup_gpio(rdev,
2153 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex);
2154 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2155 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2158 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2160 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2161 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2163 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2164 power_info->info.asPowerPlayInfo[i].ucVoltageDropIndex;
2166 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2167 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, 0);
2171 rdev->pm.power_state[state_index].clock_info[0].mclk =
2172 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMemoryClock);
2173 rdev->pm.power_state[state_index].clock_info[0].sclk =
2174 le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulEngineClock);
2175 /* skip invalid modes */
2176 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2177 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2179 rdev->pm.power_state[state_index].pcie_lanes =
2180 power_info->info_2.asPowerPlayInfo[i].ucNumPciELanes;
2181 misc = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo);
2182 misc2 = le32_to_cpu(power_info->info_2.asPowerPlayInfo[i].ulMiscInfo2);
2183 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2184 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2185 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2187 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2188 radeon_atombios_lookup_gpio(rdev,
2189 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex);
2190 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2191 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2194 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2196 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2197 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2199 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2200 power_info->info_2.asPowerPlayInfo[i].ucVoltageDropIndex;
2202 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2203 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2);
2207 rdev->pm.power_state[state_index].clock_info[0].mclk =
2208 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMemoryClock);
2209 rdev->pm.power_state[state_index].clock_info[0].sclk =
2210 le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulEngineClock);
2211 /* skip invalid modes */
2212 if ((rdev->pm.power_state[state_index].clock_info[0].mclk == 0) ||
2213 (rdev->pm.power_state[state_index].clock_info[0].sclk == 0))
2215 rdev->pm.power_state[state_index].pcie_lanes =
2216 power_info->info_3.asPowerPlayInfo[i].ucNumPciELanes;
2217 misc = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo);
2218 misc2 = le32_to_cpu(power_info->info_3.asPowerPlayInfo[i].ulMiscInfo2);
2219 if ((misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_SUPPORT) ||
2220 (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)) {
2221 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2223 rdev->pm.power_state[state_index].clock_info[0].voltage.gpio =
2224 radeon_atombios_lookup_gpio(rdev,
2225 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex);
2226 if (misc & ATOM_PM_MISCINFO_VOLTAGE_DROP_ACTIVE_HIGH)
2227 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2230 rdev->pm.power_state[state_index].clock_info[0].voltage.active_high =
2232 } else if (misc & ATOM_PM_MISCINFO_PROGRAM_VOLTAGE) {
2233 rdev->pm.power_state[state_index].clock_info[0].voltage.type =
2235 rdev->pm.power_state[state_index].clock_info[0].voltage.vddc_id =
2236 power_info->info_3.asPowerPlayInfo[i].ucVoltageDropIndex;
2237 if (misc2 & ATOM_PM_MISCINFO2_VDDCI_DYNAMIC_VOLTAGE_EN) {
2238 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_enabled =
2240 rdev->pm.power_state[state_index].clock_info[0].voltage.vddci_id =
2241 power_info->info_3.asPowerPlayInfo[i].ucVDDCI_VoltageDropIndex;
2244 rdev->pm.power_state[state_index].flags = RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2245 radeon_atombios_parse_misc_flags_1_3(rdev, state_index, misc, misc2);
2251 /* free any unused clock_info allocation. */
2252 if (state_index && state_index < num_modes) {
2253 kfree(rdev->pm.power_state[state_index].clock_info);
2254 rdev->pm.power_state[state_index].clock_info = NULL;
2257 /* last mode is usually default */
2258 if (state_index && rdev->pm.default_power_state_index == -1) {
2259 rdev->pm.power_state[state_index - 1].type =
2260 POWER_STATE_TYPE_DEFAULT;
2261 rdev->pm.default_power_state_index = state_index - 1;
2262 rdev->pm.power_state[state_index - 1].default_clock_mode =
2263 &rdev->pm.power_state[state_index - 1].clock_info[0];
2264 rdev->pm.power_state[state_index - 1].flags &=
2265 ~RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2266 rdev->pm.power_state[state_index - 1].misc = 0;
2267 rdev->pm.power_state[state_index - 1].misc2 = 0;
2272 static void radeon_atombios_add_pplib_thermal_controller(struct radeon_device *rdev,
2273 ATOM_PPLIB_THERMALCONTROLLER *controller)
2275 struct radeon_i2c_bus_rec i2c_bus;
2277 /* add the i2c bus for thermal/fan chip */
2278 if (controller->ucType > 0) {
2279 if (controller->ucFanParameters & ATOM_PP_FANPARAMETERS_NOFAN)
2280 rdev->pm.no_fan = true;
2281 rdev->pm.fan_pulses_per_revolution =
2282 controller->ucFanParameters & ATOM_PP_FANPARAMETERS_TACHOMETER_PULSES_PER_REVOLUTION_MASK;
2283 if (rdev->pm.fan_pulses_per_revolution) {
2284 rdev->pm.fan_min_rpm = controller->ucFanMinRPM;
2285 rdev->pm.fan_max_rpm = controller->ucFanMaxRPM;
2287 if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV6xx) {
2288 DRM_INFO("Internal thermal controller %s fan control\n",
2289 (controller->ucFanParameters &
2290 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2291 rdev->pm.int_thermal_type = THERMAL_TYPE_RV6XX;
2292 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_RV770) {
2293 DRM_INFO("Internal thermal controller %s fan control\n",
2294 (controller->ucFanParameters &
2295 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2296 rdev->pm.int_thermal_type = THERMAL_TYPE_RV770;
2297 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_EVERGREEN) {
2298 DRM_INFO("Internal thermal controller %s fan control\n",
2299 (controller->ucFanParameters &
2300 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2301 rdev->pm.int_thermal_type = THERMAL_TYPE_EVERGREEN;
2302 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_SUMO) {
2303 DRM_INFO("Internal thermal controller %s fan control\n",
2304 (controller->ucFanParameters &
2305 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2306 rdev->pm.int_thermal_type = THERMAL_TYPE_SUMO;
2307 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_NISLANDS) {
2308 DRM_INFO("Internal thermal controller %s fan control\n",
2309 (controller->ucFanParameters &
2310 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2311 rdev->pm.int_thermal_type = THERMAL_TYPE_NI;
2312 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_SISLANDS) {
2313 DRM_INFO("Internal thermal controller %s fan control\n",
2314 (controller->ucFanParameters &
2315 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2316 rdev->pm.int_thermal_type = THERMAL_TYPE_SI;
2317 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_CISLANDS) {
2318 DRM_INFO("Internal thermal controller %s fan control\n",
2319 (controller->ucFanParameters &
2320 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2321 rdev->pm.int_thermal_type = THERMAL_TYPE_CI;
2322 } else if (controller->ucType == ATOM_PP_THERMALCONTROLLER_KAVERI) {
2323 DRM_INFO("Internal thermal controller %s fan control\n",
2324 (controller->ucFanParameters &
2325 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2326 rdev->pm.int_thermal_type = THERMAL_TYPE_KV;
2327 } else if (controller->ucType ==
2328 ATOM_PP_THERMALCONTROLLER_EXTERNAL_GPIO) {
2329 DRM_INFO("External GPIO thermal controller %s fan control\n",
2330 (controller->ucFanParameters &
2331 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2332 rdev->pm.int_thermal_type = THERMAL_TYPE_EXTERNAL_GPIO;
2333 } else if (controller->ucType ==
2334 ATOM_PP_THERMALCONTROLLER_ADT7473_WITH_INTERNAL) {
2335 DRM_INFO("ADT7473 with internal thermal controller %s fan control\n",
2336 (controller->ucFanParameters &
2337 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2338 rdev->pm.int_thermal_type = THERMAL_TYPE_ADT7473_WITH_INTERNAL;
2339 } else if (controller->ucType ==
2340 ATOM_PP_THERMALCONTROLLER_EMC2103_WITH_INTERNAL) {
2341 DRM_INFO("EMC2103 with internal thermal controller %s fan control\n",
2342 (controller->ucFanParameters &
2343 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2344 rdev->pm.int_thermal_type = THERMAL_TYPE_EMC2103_WITH_INTERNAL;
2345 } else if (controller->ucType < ARRAY_SIZE(pp_lib_thermal_controller_names)) {
2346 DRM_INFO("Possible %s thermal controller at 0x%02x %s fan control\n",
2347 pp_lib_thermal_controller_names[controller->ucType],
2348 controller->ucI2cAddress >> 1,
2349 (controller->ucFanParameters &
2350 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2351 rdev->pm.int_thermal_type = THERMAL_TYPE_EXTERNAL;
2352 i2c_bus = radeon_lookup_i2c_gpio(rdev, controller->ucI2cLine);
2353 rdev->pm.i2c_bus = radeon_i2c_lookup(rdev, &i2c_bus);
2354 if (rdev->pm.i2c_bus) {
2355 struct i2c_board_info info = { };
2356 const char *name = pp_lib_thermal_controller_names[controller->ucType];
2357 info.addr = controller->ucI2cAddress >> 1;
2358 strlcpy(info.type, name, sizeof(info.type));
2359 i2c_new_client_device(&rdev->pm.i2c_bus->adapter, &info);
2362 DRM_INFO("Unknown thermal controller type %d at 0x%02x %s fan control\n",
2364 controller->ucI2cAddress >> 1,
2365 (controller->ucFanParameters &
2366 ATOM_PP_FANPARAMETERS_NOFAN) ? "without" : "with");
2371 void radeon_atombios_get_default_voltages(struct radeon_device *rdev,
2372 u16 *vddc, u16 *vddci, u16 *mvdd)
2374 struct radeon_mode_info *mode_info = &rdev->mode_info;
2375 int index = GetIndexIntoMasterTable(DATA, FirmwareInfo);
2378 union firmware_info *firmware_info;
2384 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
2385 &frev, &crev, &data_offset)) {
2387 (union firmware_info *)(mode_info->atom_context->bios +
2389 *vddc = le16_to_cpu(firmware_info->info_14.usBootUpVDDCVoltage);
2390 if ((frev == 2) && (crev >= 2)) {
2391 *vddci = le16_to_cpu(firmware_info->info_22.usBootUpVDDCIVoltage);
2392 *mvdd = le16_to_cpu(firmware_info->info_22.usBootUpMVDDCVoltage);
2397 static void radeon_atombios_parse_pplib_non_clock_info(struct radeon_device *rdev,
2398 int state_index, int mode_index,
2399 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info)
2402 u32 misc = le32_to_cpu(non_clock_info->ulCapsAndSettings);
2403 u32 misc2 = le16_to_cpu(non_clock_info->usClassification);
2404 u16 vddc, vddci, mvdd;
2406 radeon_atombios_get_default_voltages(rdev, &vddc, &vddci, &mvdd);
2408 rdev->pm.power_state[state_index].misc = misc;
2409 rdev->pm.power_state[state_index].misc2 = misc2;
2410 rdev->pm.power_state[state_index].pcie_lanes =
2411 ((misc & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >>
2412 ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT) + 1;
2413 switch (misc2 & ATOM_PPLIB_CLASSIFICATION_UI_MASK) {
2414 case ATOM_PPLIB_CLASSIFICATION_UI_BATTERY:
2415 rdev->pm.power_state[state_index].type =
2416 POWER_STATE_TYPE_BATTERY;
2418 case ATOM_PPLIB_CLASSIFICATION_UI_BALANCED:
2419 rdev->pm.power_state[state_index].type =
2420 POWER_STATE_TYPE_BALANCED;
2422 case ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE:
2423 rdev->pm.power_state[state_index].type =
2424 POWER_STATE_TYPE_PERFORMANCE;
2426 case ATOM_PPLIB_CLASSIFICATION_UI_NONE:
2427 if (misc2 & ATOM_PPLIB_CLASSIFICATION_3DPERFORMANCE)
2428 rdev->pm.power_state[state_index].type =
2429 POWER_STATE_TYPE_PERFORMANCE;
2432 rdev->pm.power_state[state_index].flags = 0;
2433 if (misc & ATOM_PPLIB_SINGLE_DISPLAY_ONLY)
2434 rdev->pm.power_state[state_index].flags |=
2435 RADEON_PM_STATE_SINGLE_DISPLAY_ONLY;
2436 if (misc2 & ATOM_PPLIB_CLASSIFICATION_BOOT) {
2437 rdev->pm.power_state[state_index].type =
2438 POWER_STATE_TYPE_DEFAULT;
2439 rdev->pm.default_power_state_index = state_index;
2440 rdev->pm.power_state[state_index].default_clock_mode =
2441 &rdev->pm.power_state[state_index].clock_info[mode_index - 1];
2442 if ((rdev->family >= CHIP_BARTS) && !(rdev->flags & RADEON_IS_IGP)) {
2443 /* NI chips post without MC ucode, so default clocks are strobe mode only */
2444 rdev->pm.default_sclk = rdev->pm.power_state[state_index].clock_info[0].sclk;
2445 rdev->pm.default_mclk = rdev->pm.power_state[state_index].clock_info[0].mclk;
2446 rdev->pm.default_vddc = rdev->pm.power_state[state_index].clock_info[0].voltage.voltage;
2447 rdev->pm.default_vddci = rdev->pm.power_state[state_index].clock_info[0].voltage.vddci;
2451 if (ASIC_IS_DCE4(rdev))
2452 radeon_atom_get_max_voltage(rdev,
2453 SET_VOLTAGE_TYPE_ASIC_VDDCI,
2455 /* patch the table values with the default sclk/mclk from firmware info */
2456 for (j = 0; j < mode_index; j++) {
2457 rdev->pm.power_state[state_index].clock_info[j].mclk =
2458 rdev->clock.default_mclk;
2459 rdev->pm.power_state[state_index].clock_info[j].sclk =
2460 rdev->clock.default_sclk;
2462 rdev->pm.power_state[state_index].clock_info[j].voltage.voltage =
2465 rdev->pm.power_state[state_index].clock_info[j].voltage.vddci =
2472 static bool radeon_atombios_parse_pplib_clock_info(struct radeon_device *rdev,
2473 int state_index, int mode_index,
2474 union pplib_clock_info *clock_info)
2479 if (rdev->flags & RADEON_IS_IGP) {
2480 if (rdev->family >= CHIP_PALM) {
2481 sclk = le16_to_cpu(clock_info->sumo.usEngineClockLow);
2482 sclk |= clock_info->sumo.ucEngineClockHigh << 16;
2483 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2485 sclk = le16_to_cpu(clock_info->rs780.usLowEngineClockLow);
2486 sclk |= clock_info->rs780.ucLowEngineClockHigh << 16;
2487 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2489 } else if (rdev->family >= CHIP_BONAIRE) {
2490 sclk = le16_to_cpu(clock_info->ci.usEngineClockLow);
2491 sclk |= clock_info->ci.ucEngineClockHigh << 16;
2492 mclk = le16_to_cpu(clock_info->ci.usMemoryClockLow);
2493 mclk |= clock_info->ci.ucMemoryClockHigh << 16;
2494 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2495 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2496 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2498 } else if (rdev->family >= CHIP_TAHITI) {
2499 sclk = le16_to_cpu(clock_info->si.usEngineClockLow);
2500 sclk |= clock_info->si.ucEngineClockHigh << 16;
2501 mclk = le16_to_cpu(clock_info->si.usMemoryClockLow);
2502 mclk |= clock_info->si.ucMemoryClockHigh << 16;
2503 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2504 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2505 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2507 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2508 le16_to_cpu(clock_info->si.usVDDC);
2509 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.vddci =
2510 le16_to_cpu(clock_info->si.usVDDCI);
2511 } else if (rdev->family >= CHIP_CEDAR) {
2512 sclk = le16_to_cpu(clock_info->evergreen.usEngineClockLow);
2513 sclk |= clock_info->evergreen.ucEngineClockHigh << 16;
2514 mclk = le16_to_cpu(clock_info->evergreen.usMemoryClockLow);
2515 mclk |= clock_info->evergreen.ucMemoryClockHigh << 16;
2516 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2517 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2518 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2520 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2521 le16_to_cpu(clock_info->evergreen.usVDDC);
2522 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.vddci =
2523 le16_to_cpu(clock_info->evergreen.usVDDCI);
2525 sclk = le16_to_cpu(clock_info->r600.usEngineClockLow);
2526 sclk |= clock_info->r600.ucEngineClockHigh << 16;
2527 mclk = le16_to_cpu(clock_info->r600.usMemoryClockLow);
2528 mclk |= clock_info->r600.ucMemoryClockHigh << 16;
2529 rdev->pm.power_state[state_index].clock_info[mode_index].mclk = mclk;
2530 rdev->pm.power_state[state_index].clock_info[mode_index].sclk = sclk;
2531 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.type =
2533 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage =
2534 le16_to_cpu(clock_info->r600.usVDDC);
2537 /* patch up vddc if necessary */
2538 switch (rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage) {
2539 case ATOM_VIRTUAL_VOLTAGE_ID0:
2540 case ATOM_VIRTUAL_VOLTAGE_ID1:
2541 case ATOM_VIRTUAL_VOLTAGE_ID2:
2542 case ATOM_VIRTUAL_VOLTAGE_ID3:
2543 case ATOM_VIRTUAL_VOLTAGE_ID4:
2544 case ATOM_VIRTUAL_VOLTAGE_ID5:
2545 case ATOM_VIRTUAL_VOLTAGE_ID6:
2546 case ATOM_VIRTUAL_VOLTAGE_ID7:
2547 if (radeon_atom_get_max_vddc(rdev, VOLTAGE_TYPE_VDDC,
2548 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage,
2550 rdev->pm.power_state[state_index].clock_info[mode_index].voltage.voltage = vddc;
2556 if (rdev->flags & RADEON_IS_IGP) {
2557 /* skip invalid modes */
2558 if (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0)
2561 /* skip invalid modes */
2562 if ((rdev->pm.power_state[state_index].clock_info[mode_index].mclk == 0) ||
2563 (rdev->pm.power_state[state_index].clock_info[mode_index].sclk == 0))
2569 static int radeon_atombios_parse_power_table_4_5(struct radeon_device *rdev)
2571 struct radeon_mode_info *mode_info = &rdev->mode_info;
2572 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
2573 union pplib_power_state *power_state;
2575 int state_index = 0, mode_index = 0;
2576 union pplib_clock_info *clock_info;
2578 union power_info *power_info;
2579 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2583 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2584 &frev, &crev, &data_offset))
2586 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2588 radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController);
2589 if (power_info->pplib.ucNumStates == 0)
2591 rdev->pm.power_state = kcalloc(power_info->pplib.ucNumStates,
2592 sizeof(struct radeon_power_state),
2594 if (!rdev->pm.power_state)
2596 /* first mode is usually default, followed by low to high */
2597 for (i = 0; i < power_info->pplib.ucNumStates; i++) {
2599 power_state = (union pplib_power_state *)
2600 (mode_info->atom_context->bios + data_offset +
2601 le16_to_cpu(power_info->pplib.usStateArrayOffset) +
2602 i * power_info->pplib.ucStateEntrySize);
2603 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
2604 (mode_info->atom_context->bios + data_offset +
2605 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset) +
2606 (power_state->v1.ucNonClockStateIndex *
2607 power_info->pplib.ucNonClockSize));
2608 rdev->pm.power_state[i].clock_info =
2609 kcalloc((power_info->pplib.ucStateEntrySize - 1) ?
2610 (power_info->pplib.ucStateEntrySize - 1) : 1,
2611 sizeof(struct radeon_pm_clock_info),
2613 if (!rdev->pm.power_state[i].clock_info)
2615 if (power_info->pplib.ucStateEntrySize - 1) {
2616 for (j = 0; j < (power_info->pplib.ucStateEntrySize - 1); j++) {
2617 clock_info = (union pplib_clock_info *)
2618 (mode_info->atom_context->bios + data_offset +
2619 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset) +
2620 (power_state->v1.ucClockStateIndices[j] *
2621 power_info->pplib.ucClockInfoSize));
2622 valid = radeon_atombios_parse_pplib_clock_info(rdev,
2623 state_index, mode_index,
2629 rdev->pm.power_state[state_index].clock_info[0].mclk =
2630 rdev->clock.default_mclk;
2631 rdev->pm.power_state[state_index].clock_info[0].sclk =
2632 rdev->clock.default_sclk;
2635 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
2637 radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index,
2642 /* if multiple clock modes, mark the lowest as no display */
2643 for (i = 0; i < state_index; i++) {
2644 if (rdev->pm.power_state[i].num_clock_modes > 1)
2645 rdev->pm.power_state[i].clock_info[0].flags |=
2646 RADEON_PM_MODE_NO_DISPLAY;
2648 /* first mode is usually default */
2649 if (rdev->pm.default_power_state_index == -1) {
2650 rdev->pm.power_state[0].type =
2651 POWER_STATE_TYPE_DEFAULT;
2652 rdev->pm.default_power_state_index = 0;
2653 rdev->pm.power_state[0].default_clock_mode =
2654 &rdev->pm.power_state[0].clock_info[0];
2659 static int radeon_atombios_parse_power_table_6(struct radeon_device *rdev)
2661 struct radeon_mode_info *mode_info = &rdev->mode_info;
2662 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
2663 union pplib_power_state *power_state;
2664 int i, j, non_clock_array_index, clock_array_index;
2665 int state_index = 0, mode_index = 0;
2666 union pplib_clock_info *clock_info;
2667 struct _StateArray *state_array;
2668 struct _ClockInfoArray *clock_info_array;
2669 struct _NonClockInfoArray *non_clock_info_array;
2671 union power_info *power_info;
2672 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2675 u8 *power_state_offset;
2677 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
2678 &frev, &crev, &data_offset))
2680 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
2682 radeon_atombios_add_pplib_thermal_controller(rdev, &power_info->pplib.sThermalController);
2683 state_array = (struct _StateArray *)
2684 (mode_info->atom_context->bios + data_offset +
2685 le16_to_cpu(power_info->pplib.usStateArrayOffset));
2686 clock_info_array = (struct _ClockInfoArray *)
2687 (mode_info->atom_context->bios + data_offset +
2688 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
2689 non_clock_info_array = (struct _NonClockInfoArray *)
2690 (mode_info->atom_context->bios + data_offset +
2691 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
2692 if (state_array->ucNumEntries == 0)
2694 rdev->pm.power_state = kcalloc(state_array->ucNumEntries,
2695 sizeof(struct radeon_power_state),
2697 if (!rdev->pm.power_state)
2699 power_state_offset = (u8 *)state_array->states;
2700 for (i = 0; i < state_array->ucNumEntries; i++) {
2702 power_state = (union pplib_power_state *)power_state_offset;
2703 non_clock_array_index = power_state->v2.nonClockInfoIndex;
2704 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
2705 &non_clock_info_array->nonClockInfo[non_clock_array_index];
2706 rdev->pm.power_state[i].clock_info =
2707 kcalloc(power_state->v2.ucNumDPMLevels ?
2708 power_state->v2.ucNumDPMLevels : 1,
2709 sizeof(struct radeon_pm_clock_info),
2711 if (!rdev->pm.power_state[i].clock_info)
2713 if (power_state->v2.ucNumDPMLevels) {
2714 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
2715 clock_array_index = power_state->v2.clockInfoIndex[j];
2716 clock_info = (union pplib_clock_info *)
2717 &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize];
2718 valid = radeon_atombios_parse_pplib_clock_info(rdev,
2719 state_index, mode_index,
2725 rdev->pm.power_state[state_index].clock_info[0].mclk =
2726 rdev->clock.default_mclk;
2727 rdev->pm.power_state[state_index].clock_info[0].sclk =
2728 rdev->clock.default_sclk;
2731 rdev->pm.power_state[state_index].num_clock_modes = mode_index;
2733 radeon_atombios_parse_pplib_non_clock_info(rdev, state_index, mode_index,
2737 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
2739 /* if multiple clock modes, mark the lowest as no display */
2740 for (i = 0; i < state_index; i++) {
2741 if (rdev->pm.power_state[i].num_clock_modes > 1)
2742 rdev->pm.power_state[i].clock_info[0].flags |=
2743 RADEON_PM_MODE_NO_DISPLAY;
2745 /* first mode is usually default */
2746 if (rdev->pm.default_power_state_index == -1) {
2747 rdev->pm.power_state[0].type =
2748 POWER_STATE_TYPE_DEFAULT;
2749 rdev->pm.default_power_state_index = 0;
2750 rdev->pm.power_state[0].default_clock_mode =
2751 &rdev->pm.power_state[0].clock_info[0];
2756 void radeon_atombios_get_power_modes(struct radeon_device *rdev)
2758 struct radeon_mode_info *mode_info = &rdev->mode_info;
2759 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
2762 int state_index = 0;
2764 rdev->pm.default_power_state_index = -1;
2766 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
2767 &frev, &crev, &data_offset)) {
2772 state_index = radeon_atombios_parse_power_table_1_3(rdev);
2776 state_index = radeon_atombios_parse_power_table_4_5(rdev);
2779 state_index = radeon_atombios_parse_power_table_6(rdev);
2786 if (state_index == 0) {
2787 rdev->pm.power_state = kzalloc(sizeof(struct radeon_power_state), GFP_KERNEL);
2788 if (rdev->pm.power_state) {
2789 rdev->pm.power_state[0].clock_info =
2791 sizeof(struct radeon_pm_clock_info),
2793 if (rdev->pm.power_state[0].clock_info) {
2794 /* add the default mode */
2795 rdev->pm.power_state[state_index].type =
2796 POWER_STATE_TYPE_DEFAULT;
2797 rdev->pm.power_state[state_index].num_clock_modes = 1;
2798 rdev->pm.power_state[state_index].clock_info[0].mclk = rdev->clock.default_mclk;
2799 rdev->pm.power_state[state_index].clock_info[0].sclk = rdev->clock.default_sclk;
2800 rdev->pm.power_state[state_index].default_clock_mode =
2801 &rdev->pm.power_state[state_index].clock_info[0];
2802 rdev->pm.power_state[state_index].clock_info[0].voltage.type = VOLTAGE_NONE;
2803 rdev->pm.power_state[state_index].pcie_lanes = 16;
2804 rdev->pm.default_power_state_index = state_index;
2805 rdev->pm.power_state[state_index].flags = 0;
2811 rdev->pm.num_power_states = state_index;
2813 rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
2814 rdev->pm.current_clock_mode_index = 0;
2815 if (rdev->pm.default_power_state_index >= 0)
2816 rdev->pm.current_vddc =
2817 rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
2819 rdev->pm.current_vddc = 0;
2822 union get_clock_dividers {
2823 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS v1;
2824 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V2 v2;
2825 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V3 v3;
2826 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V4 v4;
2827 struct _COMPUTE_MEMORY_ENGINE_PLL_PARAMETERS_V5 v5;
2828 struct _COMPUTE_GPU_CLOCK_INPUT_PARAMETERS_V1_6 v6_in;
2829 struct _COMPUTE_GPU_CLOCK_OUTPUT_PARAMETERS_V1_6 v6_out;
2832 int radeon_atom_get_clock_dividers(struct radeon_device *rdev,
2836 struct atom_clock_dividers *dividers)
2838 union get_clock_dividers args;
2839 int index = GetIndexIntoMasterTable(COMMAND, ComputeMemoryEnginePLL);
2842 memset(&args, 0, sizeof(args));
2843 memset(dividers, 0, sizeof(struct atom_clock_dividers));
2845 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2851 args.v1.ucAction = clock_type;
2852 args.v1.ulClock = cpu_to_le32(clock); /* 10 khz */
2854 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2856 dividers->post_div = args.v1.ucPostDiv;
2857 dividers->fb_div = args.v1.ucFbDiv;
2858 dividers->enable_post_div = true;
2863 /* r6xx, r7xx, evergreen, ni, si */
2864 if (rdev->family <= CHIP_RV770) {
2865 args.v2.ucAction = clock_type;
2866 args.v2.ulClock = cpu_to_le32(clock); /* 10 khz */
2868 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2870 dividers->post_div = args.v2.ucPostDiv;
2871 dividers->fb_div = le16_to_cpu(args.v2.usFbDiv);
2872 dividers->ref_div = args.v2.ucAction;
2873 if (rdev->family == CHIP_RV770) {
2874 dividers->enable_post_div = (le32_to_cpu(args.v2.ulClock) & (1 << 24)) ?
2876 dividers->vco_mode = (le32_to_cpu(args.v2.ulClock) & (1 << 25)) ? 1 : 0;
2878 dividers->enable_post_div = (dividers->fb_div & 1) ? true : false;
2880 if (clock_type == COMPUTE_ENGINE_PLL_PARAM) {
2881 args.v3.ulClockParams = cpu_to_le32((clock_type << 24) | clock);
2883 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2885 dividers->post_div = args.v3.ucPostDiv;
2886 dividers->enable_post_div = (args.v3.ucCntlFlag &
2887 ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN) ? true : false;
2888 dividers->enable_dithen = (args.v3.ucCntlFlag &
2889 ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE) ? false : true;
2890 dividers->whole_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDiv);
2891 dividers->frac_fb_div = le16_to_cpu(args.v3.ulFbDiv.usFbDivFrac);
2892 dividers->ref_div = args.v3.ucRefDiv;
2893 dividers->vco_mode = (args.v3.ucCntlFlag &
2894 ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE) ? 1 : 0;
2896 /* for SI we use ComputeMemoryClockParam for memory plls */
2897 if (rdev->family >= CHIP_TAHITI)
2899 args.v5.ulClockParams = cpu_to_le32((clock_type << 24) | clock);
2901 args.v5.ucInputFlag = ATOM_PLL_INPUT_FLAG_PLL_STROBE_MODE_EN;
2903 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2905 dividers->post_div = args.v5.ucPostDiv;
2906 dividers->enable_post_div = (args.v5.ucCntlFlag &
2907 ATOM_PLL_CNTL_FLAG_PLL_POST_DIV_EN) ? true : false;
2908 dividers->enable_dithen = (args.v5.ucCntlFlag &
2909 ATOM_PLL_CNTL_FLAG_FRACTION_DISABLE) ? false : true;
2910 dividers->whole_fb_div = le16_to_cpu(args.v5.ulFbDiv.usFbDiv);
2911 dividers->frac_fb_div = le16_to_cpu(args.v5.ulFbDiv.usFbDivFrac);
2912 dividers->ref_div = args.v5.ucRefDiv;
2913 dividers->vco_mode = (args.v5.ucCntlFlag &
2914 ATOM_PLL_CNTL_FLAG_MPLL_VCO_MODE) ? 1 : 0;
2920 args.v4.ulClock = cpu_to_le32(clock); /* 10 khz */
2922 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2924 dividers->post_divider = dividers->post_div = args.v4.ucPostDiv;
2925 dividers->real_clock = le32_to_cpu(args.v4.ulClock);
2929 /* COMPUTE_GPUCLK_INPUT_FLAG_DEFAULT_GPUCLK, COMPUTE_GPUCLK_INPUT_FLAG_SCLK */
2930 args.v6_in.ulClock.ulComputeClockFlag = clock_type;
2931 args.v6_in.ulClock.ulClockFreq = cpu_to_le32(clock); /* 10 khz */
2933 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2935 dividers->whole_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDiv);
2936 dividers->frac_fb_div = le16_to_cpu(args.v6_out.ulFbDiv.usFbDivFrac);
2937 dividers->ref_div = args.v6_out.ucPllRefDiv;
2938 dividers->post_div = args.v6_out.ucPllPostDiv;
2939 dividers->flags = args.v6_out.ucPllCntlFlag;
2940 dividers->real_clock = le32_to_cpu(args.v6_out.ulClock.ulClock);
2941 dividers->post_divider = args.v6_out.ulClock.ucPostDiv;
2949 int radeon_atom_get_memory_pll_dividers(struct radeon_device *rdev,
2952 struct atom_mpll_param *mpll_param)
2954 COMPUTE_MEMORY_CLOCK_PARAM_PARAMETERS_V2_1 args;
2955 int index = GetIndexIntoMasterTable(COMMAND, ComputeMemoryClockParam);
2958 memset(&args, 0, sizeof(args));
2959 memset(mpll_param, 0, sizeof(struct atom_mpll_param));
2961 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2969 args.ulClock = cpu_to_le32(clock); /* 10 khz */
2970 args.ucInputFlag = 0;
2972 args.ucInputFlag |= MPLL_INPUT_FLAG_STROBE_MODE_EN;
2974 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2976 mpll_param->clkfrac = le16_to_cpu(args.ulFbDiv.usFbDivFrac);
2977 mpll_param->clkf = le16_to_cpu(args.ulFbDiv.usFbDiv);
2978 mpll_param->post_div = args.ucPostDiv;
2979 mpll_param->dll_speed = args.ucDllSpeed;
2980 mpll_param->bwcntl = args.ucBWCntl;
2981 mpll_param->vco_mode =
2982 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_VCO_MODE_MASK);
2983 mpll_param->yclk_sel =
2984 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_BYPASS_DQ_PLL) ? 1 : 0;
2986 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_QDR_ENABLE) ? 1 : 0;
2987 mpll_param->half_rate =
2988 (args.ucPllCntlFlag & MPLL_CNTL_FLAG_AD_HALF_RATE) ? 1 : 0;
3000 void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable)
3002 DYNAMIC_CLOCK_GATING_PS_ALLOCATION args;
3003 int index = GetIndexIntoMasterTable(COMMAND, DynamicClockGating);
3005 args.ucEnable = enable;
3007 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3010 uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev)
3012 GET_ENGINE_CLOCK_PS_ALLOCATION args;
3013 int index = GetIndexIntoMasterTable(COMMAND, GetEngineClock);
3015 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3016 return le32_to_cpu(args.ulReturnEngineClock);
3019 uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev)
3021 GET_MEMORY_CLOCK_PS_ALLOCATION args;
3022 int index = GetIndexIntoMasterTable(COMMAND, GetMemoryClock);
3024 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3025 return le32_to_cpu(args.ulReturnMemoryClock);
3028 void radeon_atom_set_engine_clock(struct radeon_device *rdev,
3031 SET_ENGINE_CLOCK_PS_ALLOCATION args;
3032 int index = GetIndexIntoMasterTable(COMMAND, SetEngineClock);
3034 args.ulTargetEngineClock = cpu_to_le32(eng_clock); /* 10 khz */
3036 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3039 void radeon_atom_set_memory_clock(struct radeon_device *rdev,
3042 SET_MEMORY_CLOCK_PS_ALLOCATION args;
3043 int index = GetIndexIntoMasterTable(COMMAND, SetMemoryClock);
3045 if (rdev->flags & RADEON_IS_IGP)
3048 args.ulTargetMemoryClock = cpu_to_le32(mem_clock); /* 10 khz */
3050 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3053 void radeon_atom_set_engine_dram_timings(struct radeon_device *rdev,
3054 u32 eng_clock, u32 mem_clock)
3056 SET_ENGINE_CLOCK_PS_ALLOCATION args;
3057 int index = GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings);
3060 memset(&args, 0, sizeof(args));
3062 tmp = eng_clock & SET_CLOCK_FREQ_MASK;
3063 tmp |= (COMPUTE_ENGINE_PLL_PARAM << 24);
3065 args.ulTargetEngineClock = cpu_to_le32(tmp);
3067 args.sReserved.ulClock = cpu_to_le32(mem_clock & SET_CLOCK_FREQ_MASK);
3069 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3072 void radeon_atom_update_memory_dll(struct radeon_device *rdev,
3076 int index = GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings);
3078 args = cpu_to_le32(mem_clock); /* 10 khz */
3080 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3083 void radeon_atom_set_ac_timing(struct radeon_device *rdev,
3086 SET_MEMORY_CLOCK_PS_ALLOCATION args;
3087 int index = GetIndexIntoMasterTable(COMMAND, DynamicMemorySettings);
3088 u32 tmp = mem_clock | (COMPUTE_MEMORY_PLL_PARAM << 24);
3090 args.ulTargetMemoryClock = cpu_to_le32(tmp); /* 10 khz */
3092 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3096 struct _SET_VOLTAGE_PS_ALLOCATION alloc;
3097 struct _SET_VOLTAGE_PARAMETERS v1;
3098 struct _SET_VOLTAGE_PARAMETERS_V2 v2;
3099 struct _SET_VOLTAGE_PARAMETERS_V1_3 v3;
3102 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type)
3104 union set_voltage args;
3105 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
3106 u8 frev, crev, volt_index = voltage_level;
3108 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
3111 /* 0xff01 is a flag rather then an actual voltage */
3112 if (voltage_level == 0xff01)
3117 args.v1.ucVoltageType = voltage_type;
3118 args.v1.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_ALL_SOURCE;
3119 args.v1.ucVoltageIndex = volt_index;
3122 args.v2.ucVoltageType = voltage_type;
3123 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_SET_VOLTAGE;
3124 args.v2.usVoltageLevel = cpu_to_le16(voltage_level);
3127 args.v3.ucVoltageType = voltage_type;
3128 args.v3.ucVoltageMode = ATOM_SET_VOLTAGE;
3129 args.v3.usVoltageLevel = cpu_to_le16(voltage_level);
3132 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3136 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3139 int radeon_atom_get_max_vddc(struct radeon_device *rdev, u8 voltage_type,
3140 u16 voltage_id, u16 *voltage)
3142 union set_voltage args;
3143 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
3146 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
3153 args.v2.ucVoltageType = SET_VOLTAGE_GET_MAX_VOLTAGE;
3154 args.v2.ucVoltageMode = 0;
3155 args.v2.usVoltageLevel = 0;
3157 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3159 *voltage = le16_to_cpu(args.v2.usVoltageLevel);
3162 args.v3.ucVoltageType = voltage_type;
3163 args.v3.ucVoltageMode = ATOM_GET_VOLTAGE_LEVEL;
3164 args.v3.usVoltageLevel = cpu_to_le16(voltage_id);
3166 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3168 *voltage = le16_to_cpu(args.v3.usVoltageLevel);
3171 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3178 int radeon_atom_get_leakage_vddc_based_on_leakage_idx(struct radeon_device *rdev,
3182 return radeon_atom_get_max_vddc(rdev, VOLTAGE_TYPE_VDDC, leakage_idx, voltage);
3185 int radeon_atom_get_leakage_id_from_vbios(struct radeon_device *rdev,
3188 union set_voltage args;
3189 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
3192 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
3198 args.v3.ucVoltageType = 0;
3199 args.v3.ucVoltageMode = ATOM_GET_LEAKAGE_ID;
3200 args.v3.usVoltageLevel = 0;
3202 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3204 *leakage_id = le16_to_cpu(args.v3.usVoltageLevel);
3207 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3214 int radeon_atom_get_leakage_vddc_based_on_leakage_params(struct radeon_device *rdev,
3215 u16 *vddc, u16 *vddci,
3216 u16 virtual_voltage_id,
3217 u16 vbios_voltage_id)
3219 int index = GetIndexIntoMasterTable(DATA, ASIC_ProfilingInfo);
3221 u16 data_offset, size;
3223 ATOM_ASIC_PROFILING_INFO_V2_1 *profile;
3224 u16 *leakage_bin, *vddc_id_buf, *vddc_buf, *vddci_id_buf, *vddci_buf;
3229 if (!atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3230 &frev, &crev, &data_offset))
3233 profile = (ATOM_ASIC_PROFILING_INFO_V2_1 *)
3234 (rdev->mode_info.atom_context->bios + data_offset);
3242 if (size < sizeof(ATOM_ASIC_PROFILING_INFO_V2_1))
3244 leakage_bin = (u16 *)
3245 (rdev->mode_info.atom_context->bios + data_offset +
3246 le16_to_cpu(profile->usLeakageBinArrayOffset));
3247 vddc_id_buf = (u16 *)
3248 (rdev->mode_info.atom_context->bios + data_offset +
3249 le16_to_cpu(profile->usElbVDDC_IdArrayOffset));
3251 (rdev->mode_info.atom_context->bios + data_offset +
3252 le16_to_cpu(profile->usElbVDDC_LevelArrayOffset));
3253 vddci_id_buf = (u16 *)
3254 (rdev->mode_info.atom_context->bios + data_offset +
3255 le16_to_cpu(profile->usElbVDDCI_IdArrayOffset));
3257 (rdev->mode_info.atom_context->bios + data_offset +
3258 le16_to_cpu(profile->usElbVDDCI_LevelArrayOffset));
3260 if (profile->ucElbVDDC_Num > 0) {
3261 for (i = 0; i < profile->ucElbVDDC_Num; i++) {
3262 if (vddc_id_buf[i] == virtual_voltage_id) {
3263 for (j = 0; j < profile->ucLeakageBinNum; j++) {
3264 if (vbios_voltage_id <= leakage_bin[j]) {
3265 *vddc = vddc_buf[j * profile->ucElbVDDC_Num + i];
3273 if (profile->ucElbVDDCI_Num > 0) {
3274 for (i = 0; i < profile->ucElbVDDCI_Num; i++) {
3275 if (vddci_id_buf[i] == virtual_voltage_id) {
3276 for (j = 0; j < profile->ucLeakageBinNum; j++) {
3277 if (vbios_voltage_id <= leakage_bin[j]) {
3278 *vddci = vddci_buf[j * profile->ucElbVDDCI_Num + i];
3288 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3293 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3300 union get_voltage_info {
3301 struct _GET_VOLTAGE_INFO_INPUT_PARAMETER_V1_2 in;
3302 struct _GET_EVV_VOLTAGE_INFO_OUTPUT_PARAMETER_V1_2 evv_out;
3305 int radeon_atom_get_voltage_evv(struct radeon_device *rdev,
3306 u16 virtual_voltage_id,
3309 int index = GetIndexIntoMasterTable(COMMAND, GetVoltageInfo);
3311 u32 count = rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count;
3312 union get_voltage_info args;
3314 for (entry_id = 0; entry_id < count; entry_id++) {
3315 if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[entry_id].v ==
3320 if (entry_id >= count)
3323 args.in.ucVoltageType = VOLTAGE_TYPE_VDDC;
3324 args.in.ucVoltageMode = ATOM_GET_VOLTAGE_EVV_VOLTAGE;
3325 args.in.usVoltageLevel = cpu_to_le16(virtual_voltage_id);
3326 args.in.ulSCLKFreq =
3327 cpu_to_le32(rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[entry_id].clk);
3329 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3331 *voltage = le16_to_cpu(args.evv_out.usVoltageLevel);
3336 int radeon_atom_get_voltage_gpio_settings(struct radeon_device *rdev,
3337 u16 voltage_level, u8 voltage_type,
3338 u32 *gpio_value, u32 *gpio_mask)
3340 union set_voltage args;
3341 int index = GetIndexIntoMasterTable(COMMAND, SetVoltage);
3344 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
3351 args.v2.ucVoltageType = voltage_type;
3352 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_GET_GPIOMASK;
3353 args.v2.usVoltageLevel = cpu_to_le16(voltage_level);
3355 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3357 *gpio_mask = le32_to_cpu(*(u32 *)&args.v2);
3359 args.v2.ucVoltageType = voltage_type;
3360 args.v2.ucVoltageMode = SET_ASIC_VOLTAGE_MODE_GET_GPIOVAL;
3361 args.v2.usVoltageLevel = cpu_to_le16(voltage_level);
3363 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
3365 *gpio_value = le32_to_cpu(*(u32 *)&args.v2);
3368 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3375 union voltage_object_info {
3376 struct _ATOM_VOLTAGE_OBJECT_INFO v1;
3377 struct _ATOM_VOLTAGE_OBJECT_INFO_V2 v2;
3378 struct _ATOM_VOLTAGE_OBJECT_INFO_V3_1 v3;
3381 union voltage_object {
3382 struct _ATOM_VOLTAGE_OBJECT v1;
3383 struct _ATOM_VOLTAGE_OBJECT_V2 v2;
3384 union _ATOM_VOLTAGE_OBJECT_V3 v3;
3387 static ATOM_VOLTAGE_OBJECT *atom_lookup_voltage_object_v1(ATOM_VOLTAGE_OBJECT_INFO *v1,
3390 u32 size = le16_to_cpu(v1->sHeader.usStructureSize);
3391 u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO, asVoltageObj[0]);
3392 u8 *start = (u8 *)v1;
3394 while (offset < size) {
3395 ATOM_VOLTAGE_OBJECT *vo = (ATOM_VOLTAGE_OBJECT *)(start + offset);
3396 if (vo->ucVoltageType == voltage_type)
3398 offset += offsetof(ATOM_VOLTAGE_OBJECT, asFormula.ucVIDAdjustEntries) +
3399 vo->asFormula.ucNumOfVoltageEntries;
3404 static ATOM_VOLTAGE_OBJECT_V2 *atom_lookup_voltage_object_v2(ATOM_VOLTAGE_OBJECT_INFO_V2 *v2,
3407 u32 size = le16_to_cpu(v2->sHeader.usStructureSize);
3408 u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO_V2, asVoltageObj[0]);
3409 u8 *start = (u8*)v2;
3411 while (offset < size) {
3412 ATOM_VOLTAGE_OBJECT_V2 *vo = (ATOM_VOLTAGE_OBJECT_V2 *)(start + offset);
3413 if (vo->ucVoltageType == voltage_type)
3415 offset += offsetof(ATOM_VOLTAGE_OBJECT_V2, asFormula.asVIDAdjustEntries) +
3416 (vo->asFormula.ucNumOfVoltageEntries * sizeof(VOLTAGE_LUT_ENTRY));
3421 static ATOM_VOLTAGE_OBJECT_V3 *atom_lookup_voltage_object_v3(ATOM_VOLTAGE_OBJECT_INFO_V3_1 *v3,
3422 u8 voltage_type, u8 voltage_mode)
3424 u32 size = le16_to_cpu(v3->sHeader.usStructureSize);
3425 u32 offset = offsetof(ATOM_VOLTAGE_OBJECT_INFO_V3_1, asVoltageObj[0]);
3426 u8 *start = (u8*)v3;
3428 while (offset < size) {
3429 ATOM_VOLTAGE_OBJECT_V3 *vo = (ATOM_VOLTAGE_OBJECT_V3 *)(start + offset);
3430 if ((vo->asGpioVoltageObj.sHeader.ucVoltageType == voltage_type) &&
3431 (vo->asGpioVoltageObj.sHeader.ucVoltageMode == voltage_mode))
3433 offset += le16_to_cpu(vo->asGpioVoltageObj.sHeader.usSize);
3439 radeon_atom_is_voltage_gpio(struct radeon_device *rdev,
3440 u8 voltage_type, u8 voltage_mode)
3442 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3444 u16 data_offset, size;
3445 union voltage_object_info *voltage_info;
3446 union voltage_object *voltage_object = NULL;
3448 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3449 &frev, &crev, &data_offset)) {
3450 voltage_info = (union voltage_object_info *)
3451 (rdev->mode_info.atom_context->bios + data_offset);
3458 voltage_object = (union voltage_object *)
3459 atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type);
3460 if (voltage_object &&
3461 (voltage_object->v1.asControl.ucVoltageControlId == VOLTAGE_CONTROLLED_BY_GPIO))
3465 voltage_object = (union voltage_object *)
3466 atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type);
3467 if (voltage_object &&
3468 (voltage_object->v2.asControl.ucVoltageControlId == VOLTAGE_CONTROLLED_BY_GPIO))
3472 DRM_ERROR("unknown voltage object table\n");
3479 if (atom_lookup_voltage_object_v3(&voltage_info->v3,
3480 voltage_type, voltage_mode))
3484 DRM_ERROR("unknown voltage object table\n");
3489 DRM_ERROR("unknown voltage object table\n");
3497 int radeon_atom_get_svi2_info(struct radeon_device *rdev,
3499 u8 *svd_gpio_id, u8 *svc_gpio_id)
3501 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3503 u16 data_offset, size;
3504 union voltage_object_info *voltage_info;
3505 union voltage_object *voltage_object = NULL;
3507 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3508 &frev, &crev, &data_offset)) {
3509 voltage_info = (union voltage_object_info *)
3510 (rdev->mode_info.atom_context->bios + data_offset);
3516 voltage_object = (union voltage_object *)
3517 atom_lookup_voltage_object_v3(&voltage_info->v3,
3520 if (voltage_object) {
3521 *svd_gpio_id = voltage_object->v3.asSVID2Obj.ucSVDGpioId;
3522 *svc_gpio_id = voltage_object->v3.asSVID2Obj.ucSVCGpioId;
3528 DRM_ERROR("unknown voltage object table\n");
3533 DRM_ERROR("unknown voltage object table\n");
3541 int radeon_atom_get_max_voltage(struct radeon_device *rdev,
3542 u8 voltage_type, u16 *max_voltage)
3544 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3546 u16 data_offset, size;
3547 union voltage_object_info *voltage_info;
3548 union voltage_object *voltage_object = NULL;
3550 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3551 &frev, &crev, &data_offset)) {
3552 voltage_info = (union voltage_object_info *)
3553 (rdev->mode_info.atom_context->bios + data_offset);
3557 voltage_object = (union voltage_object *)
3558 atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type);
3559 if (voltage_object) {
3560 ATOM_VOLTAGE_FORMULA *formula =
3561 &voltage_object->v1.asFormula;
3562 if (formula->ucFlag & 1)
3564 le16_to_cpu(formula->usVoltageBaseLevel) +
3565 formula->ucNumOfVoltageEntries / 2 *
3566 le16_to_cpu(formula->usVoltageStep);
3569 le16_to_cpu(formula->usVoltageBaseLevel) +
3570 (formula->ucNumOfVoltageEntries - 1) *
3571 le16_to_cpu(formula->usVoltageStep);
3576 voltage_object = (union voltage_object *)
3577 atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type);
3578 if (voltage_object) {
3579 ATOM_VOLTAGE_FORMULA_V2 *formula =
3580 &voltage_object->v2.asFormula;
3581 if (formula->ucNumOfVoltageEntries) {
3582 VOLTAGE_LUT_ENTRY *lut = (VOLTAGE_LUT_ENTRY *)
3583 ((u8 *)&formula->asVIDAdjustEntries[0] +
3584 (sizeof(VOLTAGE_LUT_ENTRY) * (formula->ucNumOfVoltageEntries - 1)));
3586 le16_to_cpu(lut->usVoltageValue);
3592 DRM_ERROR("unknown voltage object table\n");
3600 int radeon_atom_get_min_voltage(struct radeon_device *rdev,
3601 u8 voltage_type, u16 *min_voltage)
3603 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3605 u16 data_offset, size;
3606 union voltage_object_info *voltage_info;
3607 union voltage_object *voltage_object = NULL;
3609 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3610 &frev, &crev, &data_offset)) {
3611 voltage_info = (union voltage_object_info *)
3612 (rdev->mode_info.atom_context->bios + data_offset);
3616 voltage_object = (union voltage_object *)
3617 atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type);
3618 if (voltage_object) {
3619 ATOM_VOLTAGE_FORMULA *formula =
3620 &voltage_object->v1.asFormula;
3622 le16_to_cpu(formula->usVoltageBaseLevel);
3627 voltage_object = (union voltage_object *)
3628 atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type);
3629 if (voltage_object) {
3630 ATOM_VOLTAGE_FORMULA_V2 *formula =
3631 &voltage_object->v2.asFormula;
3632 if (formula->ucNumOfVoltageEntries) {
3634 le16_to_cpu(formula->asVIDAdjustEntries[
3642 DRM_ERROR("unknown voltage object table\n");
3650 int radeon_atom_get_voltage_step(struct radeon_device *rdev,
3651 u8 voltage_type, u16 *voltage_step)
3653 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3655 u16 data_offset, size;
3656 union voltage_object_info *voltage_info;
3657 union voltage_object *voltage_object = NULL;
3659 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3660 &frev, &crev, &data_offset)) {
3661 voltage_info = (union voltage_object_info *)
3662 (rdev->mode_info.atom_context->bios + data_offset);
3666 voltage_object = (union voltage_object *)
3667 atom_lookup_voltage_object_v1(&voltage_info->v1, voltage_type);
3668 if (voltage_object) {
3669 ATOM_VOLTAGE_FORMULA *formula =
3670 &voltage_object->v1.asFormula;
3671 if (formula->ucFlag & 1)
3673 (le16_to_cpu(formula->usVoltageStep) + 1) / 2;
3676 le16_to_cpu(formula->usVoltageStep);
3683 DRM_ERROR("unknown voltage object table\n");
3691 int radeon_atom_round_to_true_voltage(struct radeon_device *rdev,
3693 u16 nominal_voltage,
3696 u16 min_voltage, max_voltage, voltage_step;
3698 if (radeon_atom_get_max_voltage(rdev, voltage_type, &max_voltage))
3700 if (radeon_atom_get_min_voltage(rdev, voltage_type, &min_voltage))
3702 if (radeon_atom_get_voltage_step(rdev, voltage_type, &voltage_step))
3705 if (nominal_voltage <= min_voltage)
3706 *true_voltage = min_voltage;
3707 else if (nominal_voltage >= max_voltage)
3708 *true_voltage = max_voltage;
3710 *true_voltage = min_voltage +
3711 ((nominal_voltage - min_voltage) / voltage_step) *
3717 int radeon_atom_get_voltage_table(struct radeon_device *rdev,
3718 u8 voltage_type, u8 voltage_mode,
3719 struct atom_voltage_table *voltage_table)
3721 int index = GetIndexIntoMasterTable(DATA, VoltageObjectInfo);
3723 u16 data_offset, size;
3725 union voltage_object_info *voltage_info;
3726 union voltage_object *voltage_object = NULL;
3728 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3729 &frev, &crev, &data_offset)) {
3730 voltage_info = (union voltage_object_info *)
3731 (rdev->mode_info.atom_context->bios + data_offset);
3738 DRM_ERROR("old table version %d, %d\n", frev, crev);
3741 voltage_object = (union voltage_object *)
3742 atom_lookup_voltage_object_v2(&voltage_info->v2, voltage_type);
3743 if (voltage_object) {
3744 ATOM_VOLTAGE_FORMULA_V2 *formula =
3745 &voltage_object->v2.asFormula;
3746 VOLTAGE_LUT_ENTRY *lut;
3747 if (formula->ucNumOfVoltageEntries > MAX_VOLTAGE_ENTRIES)
3749 lut = &formula->asVIDAdjustEntries[0];
3750 for (i = 0; i < formula->ucNumOfVoltageEntries; i++) {
3751 voltage_table->entries[i].value =
3752 le16_to_cpu(lut->usVoltageValue);
3753 ret = radeon_atom_get_voltage_gpio_settings(rdev,
3754 voltage_table->entries[i].value,
3756 &voltage_table->entries[i].smio_low,
3757 &voltage_table->mask_low);
3760 lut = (VOLTAGE_LUT_ENTRY *)
3761 ((u8 *)lut + sizeof(VOLTAGE_LUT_ENTRY));
3763 voltage_table->count = formula->ucNumOfVoltageEntries;
3768 DRM_ERROR("unknown voltage object table\n");
3775 voltage_object = (union voltage_object *)
3776 atom_lookup_voltage_object_v3(&voltage_info->v3,
3777 voltage_type, voltage_mode);
3778 if (voltage_object) {
3779 ATOM_GPIO_VOLTAGE_OBJECT_V3 *gpio =
3780 &voltage_object->v3.asGpioVoltageObj;
3781 VOLTAGE_LUT_ENTRY_V2 *lut;
3782 if (gpio->ucGpioEntryNum > MAX_VOLTAGE_ENTRIES)
3784 lut = &gpio->asVolGpioLut[0];
3785 for (i = 0; i < gpio->ucGpioEntryNum; i++) {
3786 voltage_table->entries[i].value =
3787 le16_to_cpu(lut->usVoltageValue);
3788 voltage_table->entries[i].smio_low =
3789 le32_to_cpu(lut->ulVoltageId);
3790 lut = (VOLTAGE_LUT_ENTRY_V2 *)
3791 ((u8 *)lut + sizeof(VOLTAGE_LUT_ENTRY_V2));
3793 voltage_table->mask_low = le32_to_cpu(gpio->ulGpioMaskVal);
3794 voltage_table->count = gpio->ucGpioEntryNum;
3795 voltage_table->phase_delay = gpio->ucPhaseDelay;
3800 DRM_ERROR("unknown voltage object table\n");
3805 DRM_ERROR("unknown voltage object table\n");
3813 struct _ATOM_VRAM_INFO_V3 v1_3;
3814 struct _ATOM_VRAM_INFO_V4 v1_4;
3815 struct _ATOM_VRAM_INFO_HEADER_V2_1 v2_1;
3818 int radeon_atom_get_memory_info(struct radeon_device *rdev,
3819 u8 module_index, struct atom_memory_info *mem_info)
3821 int index = GetIndexIntoMasterTable(DATA, VRAM_Info);
3823 u16 data_offset, size;
3824 union vram_info *vram_info;
3826 memset(mem_info, 0, sizeof(struct atom_memory_info));
3828 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3829 &frev, &crev, &data_offset)) {
3830 vram_info = (union vram_info *)
3831 (rdev->mode_info.atom_context->bios + data_offset);
3837 if (module_index < vram_info->v1_3.ucNumOfVRAMModule) {
3838 ATOM_VRAM_MODULE_V3 *vram_module =
3839 (ATOM_VRAM_MODULE_V3 *)vram_info->v1_3.aVramInfo;
3841 for (i = 0; i < module_index; i++) {
3842 if (le16_to_cpu(vram_module->usSize) == 0)
3844 vram_module = (ATOM_VRAM_MODULE_V3 *)
3845 ((u8 *)vram_module + le16_to_cpu(vram_module->usSize));
3847 mem_info->mem_vendor = vram_module->asMemory.ucMemoryVenderID & 0xf;
3848 mem_info->mem_type = vram_module->asMemory.ucMemoryType & 0xf0;
3853 /* r7xx, evergreen */
3854 if (module_index < vram_info->v1_4.ucNumOfVRAMModule) {
3855 ATOM_VRAM_MODULE_V4 *vram_module =
3856 (ATOM_VRAM_MODULE_V4 *)vram_info->v1_4.aVramInfo;
3858 for (i = 0; i < module_index; i++) {
3859 if (le16_to_cpu(vram_module->usModuleSize) == 0)
3861 vram_module = (ATOM_VRAM_MODULE_V4 *)
3862 ((u8 *)vram_module + le16_to_cpu(vram_module->usModuleSize));
3864 mem_info->mem_vendor = vram_module->ucMemoryVenderID & 0xf;
3865 mem_info->mem_type = vram_module->ucMemoryType & 0xf0;
3870 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3878 if (module_index < vram_info->v2_1.ucNumOfVRAMModule) {
3879 ATOM_VRAM_MODULE_V7 *vram_module =
3880 (ATOM_VRAM_MODULE_V7 *)vram_info->v2_1.aVramInfo;
3882 for (i = 0; i < module_index; i++) {
3883 if (le16_to_cpu(vram_module->usModuleSize) == 0)
3885 vram_module = (ATOM_VRAM_MODULE_V7 *)
3886 ((u8 *)vram_module + le16_to_cpu(vram_module->usModuleSize));
3888 mem_info->mem_vendor = vram_module->ucMemoryVenderID & 0xf;
3889 mem_info->mem_type = vram_module->ucMemoryType & 0xf0;
3894 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3899 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3907 int radeon_atom_get_mclk_range_table(struct radeon_device *rdev,
3908 bool gddr5, u8 module_index,
3909 struct atom_memory_clock_range_table *mclk_range_table)
3911 int index = GetIndexIntoMasterTable(DATA, VRAM_Info);
3913 u16 data_offset, size;
3914 union vram_info *vram_info;
3915 u32 mem_timing_size = gddr5 ?
3916 sizeof(ATOM_MEMORY_TIMING_FORMAT_V2) : sizeof(ATOM_MEMORY_TIMING_FORMAT);
3918 memset(mclk_range_table, 0, sizeof(struct atom_memory_clock_range_table));
3920 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3921 &frev, &crev, &data_offset)) {
3922 vram_info = (union vram_info *)
3923 (rdev->mode_info.atom_context->bios + data_offset);
3928 DRM_ERROR("old table version %d, %d\n", frev, crev);
3931 /* r7xx, evergreen */
3932 if (module_index < vram_info->v1_4.ucNumOfVRAMModule) {
3933 ATOM_VRAM_MODULE_V4 *vram_module =
3934 (ATOM_VRAM_MODULE_V4 *)vram_info->v1_4.aVramInfo;
3935 ATOM_MEMORY_TIMING_FORMAT *format;
3937 for (i = 0; i < module_index; i++) {
3938 if (le16_to_cpu(vram_module->usModuleSize) == 0)
3940 vram_module = (ATOM_VRAM_MODULE_V4 *)
3941 ((u8 *)vram_module + le16_to_cpu(vram_module->usModuleSize));
3943 mclk_range_table->num_entries = (u8)
3944 ((le16_to_cpu(vram_module->usModuleSize) - offsetof(ATOM_VRAM_MODULE_V4, asMemTiming)) /
3946 format = &vram_module->asMemTiming[0];
3947 for (i = 0; i < mclk_range_table->num_entries; i++) {
3948 mclk_range_table->mclk[i] = le32_to_cpu(format->ulClkRange);
3949 format = (ATOM_MEMORY_TIMING_FORMAT *)
3950 ((u8 *)format + mem_timing_size);
3956 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3961 DRM_ERROR("new table version %d, %d\n", frev, crev);
3964 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
3972 #define MEM_ID_MASK 0xff000000
3973 #define MEM_ID_SHIFT 24
3974 #define CLOCK_RANGE_MASK 0x00ffffff
3975 #define CLOCK_RANGE_SHIFT 0
3976 #define LOW_NIBBLE_MASK 0xf
3977 #define DATA_EQU_PREV 0
3978 #define DATA_FROM_TABLE 4
3980 int radeon_atom_init_mc_reg_table(struct radeon_device *rdev,
3982 struct atom_mc_reg_table *reg_table)
3984 int index = GetIndexIntoMasterTable(DATA, VRAM_Info);
3985 u8 frev, crev, num_entries, t_mem_id, num_ranges = 0;
3987 u16 data_offset, size;
3988 union vram_info *vram_info;
3990 memset(reg_table, 0, sizeof(struct atom_mc_reg_table));
3992 if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
3993 &frev, &crev, &data_offset)) {
3994 vram_info = (union vram_info *)
3995 (rdev->mode_info.atom_context->bios + data_offset);
3998 DRM_ERROR("old table version %d, %d\n", frev, crev);
4003 if (module_index < vram_info->v2_1.ucNumOfVRAMModule) {
4004 ATOM_INIT_REG_BLOCK *reg_block =
4005 (ATOM_INIT_REG_BLOCK *)
4006 ((u8 *)vram_info + le16_to_cpu(vram_info->v2_1.usMemClkPatchTblOffset));
4007 ATOM_MEMORY_SETTING_DATA_BLOCK *reg_data =
4008 (ATOM_MEMORY_SETTING_DATA_BLOCK *)
4009 ((u8 *)reg_block + (2 * sizeof(u16)) +
4010 le16_to_cpu(reg_block->usRegIndexTblSize));
4011 ATOM_INIT_REG_INDEX_FORMAT *format = ®_block->asRegIndexBuf[0];
4012 num_entries = (u8)((le16_to_cpu(reg_block->usRegIndexTblSize)) /
4013 sizeof(ATOM_INIT_REG_INDEX_FORMAT)) - 1;
4014 if (num_entries > VBIOS_MC_REGISTER_ARRAY_SIZE)
4016 while (i < num_entries) {
4017 if (format->ucPreRegDataLength & ACCESS_PLACEHOLDER)
4019 reg_table->mc_reg_address[i].s1 =
4020 (u16)(le16_to_cpu(format->usRegIndex));
4021 reg_table->mc_reg_address[i].pre_reg_data =
4022 (u8)(format->ucPreRegDataLength);
4024 format = (ATOM_INIT_REG_INDEX_FORMAT *)
4025 ((u8 *)format + sizeof(ATOM_INIT_REG_INDEX_FORMAT));
4027 reg_table->last = i;
4028 while ((le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK) &&
4029 (num_ranges < VBIOS_MAX_AC_TIMING_ENTRIES)) {
4030 t_mem_id = (u8)((le32_to_cpu(*(u32 *)reg_data) & MEM_ID_MASK)
4032 if (module_index == t_mem_id) {
4033 reg_table->mc_reg_table_entry[num_ranges].mclk_max =
4034 (u32)((le32_to_cpu(*(u32 *)reg_data) & CLOCK_RANGE_MASK)
4035 >> CLOCK_RANGE_SHIFT);
4036 for (i = 0, j = 1; i < reg_table->last; i++) {
4037 if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_FROM_TABLE) {
4038 reg_table->mc_reg_table_entry[num_ranges].mc_data[i] =
4039 (u32)le32_to_cpu(*((u32 *)reg_data + j));
4041 } else if ((reg_table->mc_reg_address[i].pre_reg_data & LOW_NIBBLE_MASK) == DATA_EQU_PREV) {
4042 reg_table->mc_reg_table_entry[num_ranges].mc_data[i] =
4043 reg_table->mc_reg_table_entry[num_ranges].mc_data[i - 1];
4048 reg_data = (ATOM_MEMORY_SETTING_DATA_BLOCK *)
4049 ((u8 *)reg_data + le16_to_cpu(reg_block->usRegDataBlkSize));
4051 if (le32_to_cpu(*(u32 *)reg_data) != END_OF_REG_DATA_BLOCK)
4053 reg_table->num_entries = num_ranges;
4058 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
4063 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
4071 void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev)
4073 struct radeon_device *rdev = dev->dev_private;
4074 uint32_t bios_2_scratch, bios_6_scratch;
4076 if (rdev->family >= CHIP_R600) {
4077 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
4078 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
4080 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
4081 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
4084 /* let the bios control the backlight */
4085 bios_2_scratch &= ~ATOM_S2_VRI_BRIGHT_ENABLE;
4087 /* tell the bios not to handle mode switching */
4088 bios_6_scratch |= ATOM_S6_ACC_BLOCK_DISPLAY_SWITCH;
4090 /* clear the vbios dpms state */
4091 if (ASIC_IS_DCE4(rdev))
4092 bios_2_scratch &= ~ATOM_S2_DEVICE_DPMS_STATE;
4094 if (rdev->family >= CHIP_R600) {
4095 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
4096 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
4098 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
4099 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
4104 void radeon_save_bios_scratch_regs(struct radeon_device *rdev)
4106 uint32_t scratch_reg;
4109 if (rdev->family >= CHIP_R600)
4110 scratch_reg = R600_BIOS_0_SCRATCH;
4112 scratch_reg = RADEON_BIOS_0_SCRATCH;
4114 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
4115 rdev->bios_scratch[i] = RREG32(scratch_reg + (i * 4));
4118 void radeon_restore_bios_scratch_regs(struct radeon_device *rdev)
4120 uint32_t scratch_reg;
4123 if (rdev->family >= CHIP_R600)
4124 scratch_reg = R600_BIOS_0_SCRATCH;
4126 scratch_reg = RADEON_BIOS_0_SCRATCH;
4128 for (i = 0; i < RADEON_BIOS_NUM_SCRATCH; i++)
4129 WREG32(scratch_reg + (i * 4), rdev->bios_scratch[i]);
4132 void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock)
4134 struct drm_device *dev = encoder->dev;
4135 struct radeon_device *rdev = dev->dev_private;
4136 uint32_t bios_6_scratch;
4138 if (rdev->family >= CHIP_R600)
4139 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
4141 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
4144 bios_6_scratch |= ATOM_S6_CRITICAL_STATE;
4145 bios_6_scratch &= ~ATOM_S6_ACC_MODE;
4147 bios_6_scratch &= ~ATOM_S6_CRITICAL_STATE;
4148 bios_6_scratch |= ATOM_S6_ACC_MODE;
4151 if (rdev->family >= CHIP_R600)
4152 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
4154 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
4157 /* at some point we may want to break this out into individual functions */
4159 radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
4160 struct drm_encoder *encoder,
4163 struct drm_device *dev = connector->dev;
4164 struct radeon_device *rdev = dev->dev_private;
4165 struct radeon_connector *radeon_connector =
4166 to_radeon_connector(connector);
4167 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
4168 uint32_t bios_0_scratch, bios_3_scratch, bios_6_scratch;
4170 if (rdev->family >= CHIP_R600) {
4171 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
4172 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
4173 bios_6_scratch = RREG32(R600_BIOS_6_SCRATCH);
4175 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
4176 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
4177 bios_6_scratch = RREG32(RADEON_BIOS_6_SCRATCH);
4180 if ((radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) &&
4181 (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT)) {
4183 DRM_DEBUG_KMS("TV1 connected\n");
4184 bios_3_scratch |= ATOM_S3_TV1_ACTIVE;
4185 bios_6_scratch |= ATOM_S6_ACC_REQ_TV1;
4187 DRM_DEBUG_KMS("TV1 disconnected\n");
4188 bios_0_scratch &= ~ATOM_S0_TV1_MASK;
4189 bios_3_scratch &= ~ATOM_S3_TV1_ACTIVE;
4190 bios_6_scratch &= ~ATOM_S6_ACC_REQ_TV1;
4193 if ((radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) &&
4194 (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT)) {
4196 DRM_DEBUG_KMS("CV connected\n");
4197 bios_3_scratch |= ATOM_S3_CV_ACTIVE;
4198 bios_6_scratch |= ATOM_S6_ACC_REQ_CV;
4200 DRM_DEBUG_KMS("CV disconnected\n");
4201 bios_0_scratch &= ~ATOM_S0_CV_MASK;
4202 bios_3_scratch &= ~ATOM_S3_CV_ACTIVE;
4203 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CV;
4206 if ((radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) &&
4207 (radeon_connector->devices & ATOM_DEVICE_LCD1_SUPPORT)) {
4209 DRM_DEBUG_KMS("LCD1 connected\n");
4210 bios_0_scratch |= ATOM_S0_LCD1;
4211 bios_3_scratch |= ATOM_S3_LCD1_ACTIVE;
4212 bios_6_scratch |= ATOM_S6_ACC_REQ_LCD1;
4214 DRM_DEBUG_KMS("LCD1 disconnected\n");
4215 bios_0_scratch &= ~ATOM_S0_LCD1;
4216 bios_3_scratch &= ~ATOM_S3_LCD1_ACTIVE;
4217 bios_6_scratch &= ~ATOM_S6_ACC_REQ_LCD1;
4220 if ((radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) &&
4221 (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)) {
4223 DRM_DEBUG_KMS("CRT1 connected\n");
4224 bios_0_scratch |= ATOM_S0_CRT1_COLOR;
4225 bios_3_scratch |= ATOM_S3_CRT1_ACTIVE;
4226 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT1;
4228 DRM_DEBUG_KMS("CRT1 disconnected\n");
4229 bios_0_scratch &= ~ATOM_S0_CRT1_MASK;
4230 bios_3_scratch &= ~ATOM_S3_CRT1_ACTIVE;
4231 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT1;
4234 if ((radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) &&
4235 (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)) {
4237 DRM_DEBUG_KMS("CRT2 connected\n");
4238 bios_0_scratch |= ATOM_S0_CRT2_COLOR;
4239 bios_3_scratch |= ATOM_S3_CRT2_ACTIVE;
4240 bios_6_scratch |= ATOM_S6_ACC_REQ_CRT2;
4242 DRM_DEBUG_KMS("CRT2 disconnected\n");
4243 bios_0_scratch &= ~ATOM_S0_CRT2_MASK;
4244 bios_3_scratch &= ~ATOM_S3_CRT2_ACTIVE;
4245 bios_6_scratch &= ~ATOM_S6_ACC_REQ_CRT2;
4248 if ((radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) &&
4249 (radeon_connector->devices & ATOM_DEVICE_DFP1_SUPPORT)) {
4251 DRM_DEBUG_KMS("DFP1 connected\n");
4252 bios_0_scratch |= ATOM_S0_DFP1;
4253 bios_3_scratch |= ATOM_S3_DFP1_ACTIVE;
4254 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP1;
4256 DRM_DEBUG_KMS("DFP1 disconnected\n");
4257 bios_0_scratch &= ~ATOM_S0_DFP1;
4258 bios_3_scratch &= ~ATOM_S3_DFP1_ACTIVE;
4259 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP1;
4262 if ((radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) &&
4263 (radeon_connector->devices & ATOM_DEVICE_DFP2_SUPPORT)) {
4265 DRM_DEBUG_KMS("DFP2 connected\n");
4266 bios_0_scratch |= ATOM_S0_DFP2;
4267 bios_3_scratch |= ATOM_S3_DFP2_ACTIVE;
4268 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP2;
4270 DRM_DEBUG_KMS("DFP2 disconnected\n");
4271 bios_0_scratch &= ~ATOM_S0_DFP2;
4272 bios_3_scratch &= ~ATOM_S3_DFP2_ACTIVE;
4273 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP2;
4276 if ((radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) &&
4277 (radeon_connector->devices & ATOM_DEVICE_DFP3_SUPPORT)) {
4279 DRM_DEBUG_KMS("DFP3 connected\n");
4280 bios_0_scratch |= ATOM_S0_DFP3;
4281 bios_3_scratch |= ATOM_S3_DFP3_ACTIVE;
4282 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP3;
4284 DRM_DEBUG_KMS("DFP3 disconnected\n");
4285 bios_0_scratch &= ~ATOM_S0_DFP3;
4286 bios_3_scratch &= ~ATOM_S3_DFP3_ACTIVE;
4287 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP3;
4290 if ((radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) &&
4291 (radeon_connector->devices & ATOM_DEVICE_DFP4_SUPPORT)) {
4293 DRM_DEBUG_KMS("DFP4 connected\n");
4294 bios_0_scratch |= ATOM_S0_DFP4;
4295 bios_3_scratch |= ATOM_S3_DFP4_ACTIVE;
4296 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP4;
4298 DRM_DEBUG_KMS("DFP4 disconnected\n");
4299 bios_0_scratch &= ~ATOM_S0_DFP4;
4300 bios_3_scratch &= ~ATOM_S3_DFP4_ACTIVE;
4301 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP4;
4304 if ((radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) &&
4305 (radeon_connector->devices & ATOM_DEVICE_DFP5_SUPPORT)) {
4307 DRM_DEBUG_KMS("DFP5 connected\n");
4308 bios_0_scratch |= ATOM_S0_DFP5;
4309 bios_3_scratch |= ATOM_S3_DFP5_ACTIVE;
4310 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP5;
4312 DRM_DEBUG_KMS("DFP5 disconnected\n");
4313 bios_0_scratch &= ~ATOM_S0_DFP5;
4314 bios_3_scratch &= ~ATOM_S3_DFP5_ACTIVE;
4315 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP5;
4318 if ((radeon_encoder->devices & ATOM_DEVICE_DFP6_SUPPORT) &&
4319 (radeon_connector->devices & ATOM_DEVICE_DFP6_SUPPORT)) {
4321 DRM_DEBUG_KMS("DFP6 connected\n");
4322 bios_0_scratch |= ATOM_S0_DFP6;
4323 bios_3_scratch |= ATOM_S3_DFP6_ACTIVE;
4324 bios_6_scratch |= ATOM_S6_ACC_REQ_DFP6;
4326 DRM_DEBUG_KMS("DFP6 disconnected\n");
4327 bios_0_scratch &= ~ATOM_S0_DFP6;
4328 bios_3_scratch &= ~ATOM_S3_DFP6_ACTIVE;
4329 bios_6_scratch &= ~ATOM_S6_ACC_REQ_DFP6;
4333 if (rdev->family >= CHIP_R600) {
4334 WREG32(R600_BIOS_0_SCRATCH, bios_0_scratch);
4335 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
4336 WREG32(R600_BIOS_6_SCRATCH, bios_6_scratch);
4338 WREG32(RADEON_BIOS_0_SCRATCH, bios_0_scratch);
4339 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
4340 WREG32(RADEON_BIOS_6_SCRATCH, bios_6_scratch);
4345 radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc)
4347 struct drm_device *dev = encoder->dev;
4348 struct radeon_device *rdev = dev->dev_private;
4349 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
4350 uint32_t bios_3_scratch;
4352 if (ASIC_IS_DCE4(rdev))
4355 if (rdev->family >= CHIP_R600)
4356 bios_3_scratch = RREG32(R600_BIOS_3_SCRATCH);
4358 bios_3_scratch = RREG32(RADEON_BIOS_3_SCRATCH);
4360 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
4361 bios_3_scratch &= ~ATOM_S3_TV1_CRTC_ACTIVE;
4362 bios_3_scratch |= (crtc << 18);
4364 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
4365 bios_3_scratch &= ~ATOM_S3_CV_CRTC_ACTIVE;
4366 bios_3_scratch |= (crtc << 24);
4368 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
4369 bios_3_scratch &= ~ATOM_S3_CRT1_CRTC_ACTIVE;
4370 bios_3_scratch |= (crtc << 16);
4372 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
4373 bios_3_scratch &= ~ATOM_S3_CRT2_CRTC_ACTIVE;
4374 bios_3_scratch |= (crtc << 20);
4376 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
4377 bios_3_scratch &= ~ATOM_S3_LCD1_CRTC_ACTIVE;
4378 bios_3_scratch |= (crtc << 17);
4380 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
4381 bios_3_scratch &= ~ATOM_S3_DFP1_CRTC_ACTIVE;
4382 bios_3_scratch |= (crtc << 19);
4384 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
4385 bios_3_scratch &= ~ATOM_S3_DFP2_CRTC_ACTIVE;
4386 bios_3_scratch |= (crtc << 23);
4388 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
4389 bios_3_scratch &= ~ATOM_S3_DFP3_CRTC_ACTIVE;
4390 bios_3_scratch |= (crtc << 25);
4393 if (rdev->family >= CHIP_R600)
4394 WREG32(R600_BIOS_3_SCRATCH, bios_3_scratch);
4396 WREG32(RADEON_BIOS_3_SCRATCH, bios_3_scratch);
4400 radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on)
4402 struct drm_device *dev = encoder->dev;
4403 struct radeon_device *rdev = dev->dev_private;
4404 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
4405 uint32_t bios_2_scratch;
4407 if (ASIC_IS_DCE4(rdev))
4410 if (rdev->family >= CHIP_R600)
4411 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
4413 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
4415 if (radeon_encoder->devices & ATOM_DEVICE_TV1_SUPPORT) {
4417 bios_2_scratch &= ~ATOM_S2_TV1_DPMS_STATE;
4419 bios_2_scratch |= ATOM_S2_TV1_DPMS_STATE;
4421 if (radeon_encoder->devices & ATOM_DEVICE_CV_SUPPORT) {
4423 bios_2_scratch &= ~ATOM_S2_CV_DPMS_STATE;
4425 bios_2_scratch |= ATOM_S2_CV_DPMS_STATE;
4427 if (radeon_encoder->devices & ATOM_DEVICE_CRT1_SUPPORT) {
4429 bios_2_scratch &= ~ATOM_S2_CRT1_DPMS_STATE;
4431 bios_2_scratch |= ATOM_S2_CRT1_DPMS_STATE;
4433 if (radeon_encoder->devices & ATOM_DEVICE_CRT2_SUPPORT) {
4435 bios_2_scratch &= ~ATOM_S2_CRT2_DPMS_STATE;
4437 bios_2_scratch |= ATOM_S2_CRT2_DPMS_STATE;
4439 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
4441 bios_2_scratch &= ~ATOM_S2_LCD1_DPMS_STATE;
4443 bios_2_scratch |= ATOM_S2_LCD1_DPMS_STATE;
4445 if (radeon_encoder->devices & ATOM_DEVICE_DFP1_SUPPORT) {
4447 bios_2_scratch &= ~ATOM_S2_DFP1_DPMS_STATE;
4449 bios_2_scratch |= ATOM_S2_DFP1_DPMS_STATE;
4451 if (radeon_encoder->devices & ATOM_DEVICE_DFP2_SUPPORT) {
4453 bios_2_scratch &= ~ATOM_S2_DFP2_DPMS_STATE;
4455 bios_2_scratch |= ATOM_S2_DFP2_DPMS_STATE;
4457 if (radeon_encoder->devices & ATOM_DEVICE_DFP3_SUPPORT) {
4459 bios_2_scratch &= ~ATOM_S2_DFP3_DPMS_STATE;
4461 bios_2_scratch |= ATOM_S2_DFP3_DPMS_STATE;
4463 if (radeon_encoder->devices & ATOM_DEVICE_DFP4_SUPPORT) {
4465 bios_2_scratch &= ~ATOM_S2_DFP4_DPMS_STATE;
4467 bios_2_scratch |= ATOM_S2_DFP4_DPMS_STATE;
4469 if (radeon_encoder->devices & ATOM_DEVICE_DFP5_SUPPORT) {
4471 bios_2_scratch &= ~ATOM_S2_DFP5_DPMS_STATE;
4473 bios_2_scratch |= ATOM_S2_DFP5_DPMS_STATE;
4476 if (rdev->family >= CHIP_R600)
4477 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
4479 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);