drivers/gpu/drm/msm/hdmi/hdmi_bridge.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2013 Red Hat
   4  * Author: Rob Clark <[email protected]>
   5  */
   6
   7 #include <linux/delay.h>
   8 #include <drm/drm_bridge_connector.h>
   9 #include <drm/drm_edid.h>
  10
  11 #include "msm_kms.h"
  12 #include "hdmi.h"
  13
  14 void msm_hdmi_bridge_destroy(struct drm_bridge *bridge)
  15 {
  16         struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge);
  17
  18         msm_hdmi_hpd_disable(hdmi_bridge);
  19         drm_bridge_remove(bridge);
  20 }
  21
  22 static void msm_hdmi_power_on(struct drm_bridge *bridge)
  23 {
  24         struct drm_device *dev = bridge->dev;
  25         struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge);
  26         struct hdmi *hdmi = hdmi_bridge->hdmi;
  27         const struct hdmi_platform_config *config = hdmi->config;
  28         int i, ret;
  29
  30         pm_runtime_get_sync(&hdmi->pdev->dev);
  31
  32         ret = regulator_bulk_enable(config->pwr_reg_cnt, hdmi->pwr_regs);
  33         if (ret)
  34                 DRM_DEV_ERROR(dev->dev, "failed to enable pwr regulator: %d\n", ret);
  35
  36         if (config->pwr_clk_cnt > 0) {
  37                 DBG("pixclock: %lu", hdmi->pixclock);
  38                 ret = clk_set_rate(hdmi->pwr_clks[0], hdmi->pixclock);
  39                 if (ret) {
  40                         DRM_DEV_ERROR(dev->dev, "failed to set pixel clk: %s (%d)\n",
  41                                         config->pwr_clk_names[0], ret);
  42                 }
  43         }
  44
  45         for (i = 0; i < config->pwr_clk_cnt; i++) {
  46                 ret = clk_prepare_enable(hdmi->pwr_clks[i]);
  47                 if (ret) {
  48                         DRM_DEV_ERROR(dev->dev, "failed to enable pwr clk: %s (%d)\n",
  49                                         config->pwr_clk_names[i], ret);
  50                 }
  51         }
  52 }
  53
  54 static void power_off(struct drm_bridge *bridge)
  55 {
  56         struct drm_device *dev = bridge->dev;
  57         struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge);
  58         struct hdmi *hdmi = hdmi_bridge->hdmi;
  59         const struct hdmi_platform_config *config = hdmi->config;
  60         int i, ret;
  61
  62         /* TODO do we need to wait for final vblank somewhere before
  63          * cutting the clocks?
  64          */
  65         mdelay(16 + 4);
  66
  67         for (i = 0; i < config->pwr_clk_cnt; i++)
  68                 clk_disable_unprepare(hdmi->pwr_clks[i]);
  69
  70         ret = regulator_bulk_disable(config->pwr_reg_cnt, hdmi->pwr_regs);
  71         if (ret)
  72                 DRM_DEV_ERROR(dev->dev, "failed to disable pwr regulator: %d\n", ret);
  73
  74         pm_runtime_put(&hdmi->pdev->dev);
  75 }
  76
  77 #define AVI_IFRAME_LINE_NUMBER 1
  78
  79 static void msm_hdmi_config_avi_infoframe(struct hdmi *hdmi)
  80 {
  81         struct drm_crtc *crtc = hdmi->encoder->crtc;
  82         const struct drm_display_mode *mode = &crtc->state->adjusted_mode;
  83         union hdmi_infoframe frame;
  84         u8 buffer[HDMI_INFOFRAME_SIZE(AVI)];
  85         u32 val;
  86         int len;
  87
  88         drm_hdmi_avi_infoframe_from_display_mode(&frame.avi,
  89                                                  hdmi->connector, mode);
  90
  91         len = hdmi_infoframe_pack(&frame, buffer, sizeof(buffer));
  92         if (len < 0) {
  93                 DRM_DEV_ERROR(&hdmi->pdev->dev,
  94                         "failed to configure avi infoframe\n");
  95                 return;
  96         }
  97
  98         /*
  99          * the AVI_INFOx registers don't map exactly to how the AVI infoframes
 100          * are packed according to the spec. The checksum from the header is
 101          * written to the LSB byte of AVI_INFO0 and the version is written to
 102          * the third byte from the LSB of AVI_INFO3
 103          */
 104         hdmi_write(hdmi, REG_HDMI_AVI_INFO(0),
 105                    buffer[3] |
 106                    buffer[4] << 8 |
 107                    buffer[5] << 16 |
 108                    buffer[6] << 24);
 109
 110         hdmi_write(hdmi, REG_HDMI_AVI_INFO(1),
 111                    buffer[7] |
 112                    buffer[8] << 8 |
 113                    buffer[9] << 16 |
 114                    buffer[10] << 24);
 115
 116         hdmi_write(hdmi, REG_HDMI_AVI_INFO(2),
 117                    buffer[11] |
 118                    buffer[12] << 8 |
 119                    buffer[13] << 16 |
 120                    buffer[14] << 24);
 121
 122         hdmi_write(hdmi, REG_HDMI_AVI_INFO(3),
 123                    buffer[15] |
 124                    buffer[16] << 8 |
 125                    buffer[1] << 24);
 126
 127         hdmi_write(hdmi, REG_HDMI_INFOFRAME_CTRL0,
 128                    HDMI_INFOFRAME_CTRL0_AVI_SEND |
 129                    HDMI_INFOFRAME_CTRL0_AVI_CONT);
 130
 131         val = hdmi_read(hdmi, REG_HDMI_INFOFRAME_CTRL1);
 132         val &= ~HDMI_INFOFRAME_CTRL1_AVI_INFO_LINE__MASK;
 133         val |= HDMI_INFOFRAME_CTRL1_AVI_INFO_LINE(AVI_IFRAME_LINE_NUMBER);
 134         hdmi_write(hdmi, REG_HDMI_INFOFRAME_CTRL1, val);
 135 }
 136
 137 static void msm_hdmi_bridge_pre_enable(struct drm_bridge *bridge)
 138 {
 139         struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge);
 140         struct hdmi *hdmi = hdmi_bridge->hdmi;
 141         struct hdmi_phy *phy = hdmi->phy;
 142
 143         DBG("power up");
 144
 145         if (!hdmi->power_on) {
 146                 msm_hdmi_phy_resource_enable(phy);
 147                 msm_hdmi_power_on(bridge);
 148                 hdmi->power_on = true;
 149                 if (hdmi->hdmi_mode) {
 150                         msm_hdmi_config_avi_infoframe(hdmi);
 151                         msm_hdmi_audio_update(hdmi);
 152                 }
 153         }
 154
 155         msm_hdmi_phy_powerup(phy, hdmi->pixclock);
 156
 157         msm_hdmi_set_mode(hdmi, true);
 158
 159         if (hdmi->hdcp_ctrl)
 160                 msm_hdmi_hdcp_on(hdmi->hdcp_ctrl);
 161 }
 162
 163 static void msm_hdmi_bridge_post_disable(struct drm_bridge *bridge)
 164 {
 165         struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge);
 166         struct hdmi *hdmi = hdmi_bridge->hdmi;
 167         struct hdmi_phy *phy = hdmi->phy;
 168
 169         if (hdmi->hdcp_ctrl)
 170                 msm_hdmi_hdcp_off(hdmi->hdcp_ctrl);
 171
 172         DBG("power down");
 173         msm_hdmi_set_mode(hdmi, false);
 174
 175         msm_hdmi_phy_powerdown(phy);
 176
 177         if (hdmi->power_on) {
 178                 power_off(bridge);
 179                 hdmi->power_on = false;
 180                 if (hdmi->hdmi_mode)
 181                         msm_hdmi_audio_update(hdmi);
 182                 msm_hdmi_phy_resource_disable(phy);
 183         }
 184 }
 185
 186 static void msm_hdmi_bridge_mode_set(struct drm_bridge *bridge,
 187                  const struct drm_display_mode *mode,
 188                  const struct drm_display_mode *adjusted_mode)
 189 {
 190         struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge);
 191         struct hdmi *hdmi = hdmi_bridge->hdmi;
 192         int hstart, hend, vstart, vend;
 193         uint32_t frame_ctrl;
 194
 195         mode = adjusted_mode;
 196
 197         hdmi->pixclock = mode->clock * 1000;
 198
 199         hstart = mode->htotal - mode->hsync_start;
 200         hend   = mode->htotal - mode->hsync_start + mode->hdisplay;
 201
 202         vstart = mode->vtotal - mode->vsync_start - 1;
 203         vend   = mode->vtotal - mode->vsync_start + mode->vdisplay - 1;
 204
 205         DBG("htotal=%d, vtotal=%d, hstart=%d, hend=%d, vstart=%d, vend=%d",
 206                         mode->htotal, mode->vtotal, hstart, hend, vstart, vend);
 207
 208         hdmi_write(hdmi, REG_HDMI_TOTAL,
 209                         HDMI_TOTAL_H_TOTAL(mode->htotal - 1) |
 210                         HDMI_TOTAL_V_TOTAL(mode->vtotal - 1));
 211
 212         hdmi_write(hdmi, REG_HDMI_ACTIVE_HSYNC,
 213                         HDMI_ACTIVE_HSYNC_START(hstart) |
 214                         HDMI_ACTIVE_HSYNC_END(hend));
 215         hdmi_write(hdmi, REG_HDMI_ACTIVE_VSYNC,
 216                         HDMI_ACTIVE_VSYNC_START(vstart) |
 217                         HDMI_ACTIVE_VSYNC_END(vend));
 218
 219         if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
 220                 hdmi_write(hdmi, REG_HDMI_VSYNC_TOTAL_F2,
 221                                 HDMI_VSYNC_TOTAL_F2_V_TOTAL(mode->vtotal));
 222                 hdmi_write(hdmi, REG_HDMI_VSYNC_ACTIVE_F2,
 223                                 HDMI_VSYNC_ACTIVE_F2_START(vstart + 1) |
 224                                 HDMI_VSYNC_ACTIVE_F2_END(vend + 1));
 225         } else {
 226                 hdmi_write(hdmi, REG_HDMI_VSYNC_TOTAL_F2,
 227                                 HDMI_VSYNC_TOTAL_F2_V_TOTAL(0));
 228                 hdmi_write(hdmi, REG_HDMI_VSYNC_ACTIVE_F2,
 229                                 HDMI_VSYNC_ACTIVE_F2_START(0) |
 230                                 HDMI_VSYNC_ACTIVE_F2_END(0));
 231         }
 232
 233         frame_ctrl = 0;
 234         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
 235                 frame_ctrl |= HDMI_FRAME_CTRL_HSYNC_LOW;
 236         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
 237                 frame_ctrl |= HDMI_FRAME_CTRL_VSYNC_LOW;
 238         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
 239                 frame_ctrl |= HDMI_FRAME_CTRL_INTERLACED_EN;
 240         DBG("frame_ctrl=%08x", frame_ctrl);
 241         hdmi_write(hdmi, REG_HDMI_FRAME_CTRL, frame_ctrl);
 242
 243         if (hdmi->hdmi_mode)
 244                 msm_hdmi_audio_update(hdmi);
 245 }
 246
 247 static struct edid *msm_hdmi_bridge_get_edid(struct drm_bridge *bridge,
 248                 struct drm_connector *connector)
 249 {
 250         struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge);
 251         struct hdmi *hdmi = hdmi_bridge->hdmi;
 252         struct edid *edid;
 253         uint32_t hdmi_ctrl;
 254
 255         hdmi_ctrl = hdmi_read(hdmi, REG_HDMI_CTRL);
 256         hdmi_write(hdmi, REG_HDMI_CTRL, hdmi_ctrl | HDMI_CTRL_ENABLE);
 257
 258         edid = drm_get_edid(connector, hdmi->i2c);
 259
 260         hdmi_write(hdmi, REG_HDMI_CTRL, hdmi_ctrl);
 261
 262         hdmi->hdmi_mode = drm_detect_hdmi_monitor(edid);
 263
 264         return edid;
 265 }
 266
 267 static enum drm_mode_status msm_hdmi_bridge_mode_valid(struct drm_bridge *bridge,
 268                 const struct drm_display_info *info,
 269                 const struct drm_display_mode *mode)
 270 {
 271         struct hdmi_bridge *hdmi_bridge = to_hdmi_bridge(bridge);
 272         struct hdmi *hdmi = hdmi_bridge->hdmi;
 273         const struct hdmi_platform_config *config = hdmi->config;
 274         struct msm_drm_private *priv = bridge->dev->dev_private;
 275         struct msm_kms *kms = priv->kms;
 276         long actual, requested;
 277
 278         requested = 1000 * mode->clock;
 279
 280         /* for mdp5/apq8074, we manage our own pixel clk (as opposed to
 281          * mdp4/dtv stuff where pixel clk is assigned to mdp/encoder
 282          * instead):
 283          */
 284         if (kms->funcs->round_pixclk)
 285                 actual = kms->funcs->round_pixclk(kms,
 286                         requested, hdmi_bridge->hdmi->encoder);
 287         else if (config->pwr_clk_cnt > 0)
 288                 actual = clk_round_rate(hdmi->pwr_clks[0], requested);
 289         else
 290                 actual = requested;
 291
 292         DBG("requested=%ld, actual=%ld", requested, actual);
 293
 294         if (actual != requested)
 295                 return MODE_CLOCK_RANGE;
 296
 297         return 0;
 298 }
 299
 300 static const struct drm_bridge_funcs msm_hdmi_bridge_funcs = {
 301                 .pre_enable = msm_hdmi_bridge_pre_enable,
 302                 .post_disable = msm_hdmi_bridge_post_disable,
 303                 .mode_set = msm_hdmi_bridge_mode_set,
 304                 .mode_valid = msm_hdmi_bridge_mode_valid,
 305                 .get_edid = msm_hdmi_bridge_get_edid,
 306                 .detect = msm_hdmi_bridge_detect,
 307 };
 308
 309 static void
 310 msm_hdmi_hotplug_work(struct work_struct *work)
 311 {
 312         struct hdmi_bridge *hdmi_bridge =
 313                 container_of(work, struct hdmi_bridge, hpd_work);
 314         struct drm_bridge *bridge = &hdmi_bridge->base;
 315
 316         drm_bridge_hpd_notify(bridge, drm_bridge_detect(bridge));
 317 }
 318
 319 /* initialize bridge */
 320 struct drm_bridge *msm_hdmi_bridge_init(struct hdmi *hdmi)
 321 {
 322         struct drm_bridge *bridge = NULL;
 323         struct hdmi_bridge *hdmi_bridge;
 324         int ret;
 325
 326         hdmi_bridge = devm_kzalloc(hdmi->dev->dev,
 327                         sizeof(*hdmi_bridge), GFP_KERNEL);
 328         if (!hdmi_bridge) {
 329                 ret = -ENOMEM;
 330                 goto fail;
 331         }
 332
 333         hdmi_bridge->hdmi = hdmi;
 334         INIT_WORK(&hdmi_bridge->hpd_work, msm_hdmi_hotplug_work);
 335
 336         bridge = &hdmi_bridge->base;
 337         bridge->funcs = &msm_hdmi_bridge_funcs;
 338         bridge->ddc = hdmi->i2c;
 339         bridge->type = DRM_MODE_CONNECTOR_HDMIA;
 340         bridge->ops = DRM_BRIDGE_OP_HPD |
 341                 DRM_BRIDGE_OP_DETECT |
 342                 DRM_BRIDGE_OP_EDID;
 343
 344         drm_bridge_add(bridge);
 345
 346         ret = drm_bridge_attach(hdmi->encoder, bridge, NULL, DRM_BRIDGE_ATTACH_NO_CONNECTOR);
 347         if (ret)
 348                 goto fail;
 349
 350         return bridge;
 351
 352 fail:
 353         if (bridge)
 354                 msm_hdmi_bridge_destroy(bridge);
 355
 356         return ERR_PTR(ret);
 357 }