drivers/gpu/drm/msm/dsi/dsi_phy_20nm.xml.h

   1 #ifndef DSI_PHY_20NM_XML
   2 #define DSI_PHY_20NM_XML
   3
   4 /* Autogenerated file, DO NOT EDIT manually!
   5
   6 This file was generated by the rules-ng-ng headergen tool in this git repository:
   7 http://github.com/freedreno/envytools/
   8 git clone https://github.com/freedreno/envytools.git
   9
  10 The rules-ng-ng source files this header was generated from are:
  11 - /home/robclark/src/mesa/mesa/src/freedreno/registers/msm.xml                   (    944 bytes, from 2022-07-23 20:21:46)
  12 - /home/robclark/src/mesa/mesa/src/freedreno/registers/freedreno_copyright.xml   (   1572 bytes, from 2022-07-23 20:21:46)
  13 - /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp4.xml              (  20912 bytes, from 2022-03-08 17:40:42)
  14 - /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp_common.xml        (   2849 bytes, from 2022-03-08 17:40:42)
  15 - /home/robclark/src/mesa/mesa/src/freedreno/registers/mdp/mdp5.xml              (  37461 bytes, from 2022-03-08 17:40:42)
  16 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi.xml               (  18746 bytes, from 2022-04-28 17:29:36)
  17 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_v2.xml        (   3236 bytes, from 2022-03-08 17:40:42)
  18 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm_8960.xml (   4935 bytes, from 2022-03-08 17:40:42)
  19 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_28nm.xml      (   7004 bytes, from 2022-03-08 17:40:42)
  20 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_20nm.xml      (   3712 bytes, from 2022-03-08 17:40:42)
  21 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_14nm.xml      (   5381 bytes, from 2022-03-08 17:40:42)
  22 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_10nm.xml      (   4499 bytes, from 2022-03-08 17:40:42)
  23 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/dsi_phy_7nm.xml       (  11007 bytes, from 2022-03-08 17:40:42)
  24 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/sfpb.xml              (    602 bytes, from 2022-03-08 17:40:42)
  25 - /home/robclark/src/mesa/mesa/src/freedreno/registers/dsi/mmss_cc.xml           (   1686 bytes, from 2022-03-08 17:40:42)
  26 - /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/qfprom.xml           (    600 bytes, from 2022-03-08 17:40:42)
  27 - /home/robclark/src/mesa/mesa/src/freedreno/registers/hdmi/hdmi.xml             (  42350 bytes, from 2022-09-20 17:45:56)
  28 - /home/robclark/src/mesa/mesa/src/freedreno/registers/edp/edp.xml               (  10416 bytes, from 2022-03-08 17:40:42)
  29
  30 Copyright (C) 2013-2022 by the following authors:
  31 - Rob Clark <[email protected]> (robclark)
  32 - Ilia Mirkin <[email protected]> (imirkin)
  33
  34 Permission is hereby granted, free of charge, to any person obtaining
  35 a copy of this software and associated documentation files (the
  36 "Software"), to deal in the Software without restriction, including
  37 without limitation the rights to use, copy, modify, merge, publish,
  38 distribute, sublicense, and/or sell copies of the Software, and to
  39 permit persons to whom the Software is furnished to do so, subject to
  40 the following conditions:
  41
  42 The above copyright notice and this permission notice (including the
  43 next paragraph) shall be included in all copies or substantial
  44 portions of the Software.
  45
  46 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  47 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  48 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  49 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  50 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  51 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  52 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  53 */
  54
  55
  56 static inline uint32_t REG_DSI_20nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x40*i0; }
  57
  58 static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_0(uint32_t i0) { return 0x00000000 + 0x40*i0; }
  59
  60 static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_1(uint32_t i0) { return 0x00000004 + 0x40*i0; }
  61
  62 static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_2(uint32_t i0) { return 0x00000008 + 0x40*i0; }
  63
  64 static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_3(uint32_t i0) { return 0x0000000c + 0x40*i0; }
  65
  66 static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_4(uint32_t i0) { return 0x00000010 + 0x40*i0; }
  67
  68 static inline uint32_t REG_DSI_20nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x00000014 + 0x40*i0; }
  69
  70 static inline uint32_t REG_DSI_20nm_PHY_LN_DEBUG_SEL(uint32_t i0) { return 0x00000018 + 0x40*i0; }
  71
  72 static inline uint32_t REG_DSI_20nm_PHY_LN_TEST_STR_0(uint32_t i0) { return 0x0000001c + 0x40*i0; }
  73
  74 static inline uint32_t REG_DSI_20nm_PHY_LN_TEST_STR_1(uint32_t i0) { return 0x00000020 + 0x40*i0; }
  75
  76 #define REG_DSI_20nm_PHY_LNCK_CFG_0                             0x00000100
  77
  78 #define REG_DSI_20nm_PHY_LNCK_CFG_1                             0x00000104
  79
  80 #define REG_DSI_20nm_PHY_LNCK_CFG_2                             0x00000108
  81
  82 #define REG_DSI_20nm_PHY_LNCK_CFG_3                             0x0000010c
  83
  84 #define REG_DSI_20nm_PHY_LNCK_CFG_4                             0x00000110
  85
  86 #define REG_DSI_20nm_PHY_LNCK_TEST_DATAPATH                     0x00000114
  87
  88 #define REG_DSI_20nm_PHY_LNCK_DEBUG_SEL                         0x00000118
  89
  90 #define REG_DSI_20nm_PHY_LNCK_TEST_STR0                         0x0000011c
  91
  92 #define REG_DSI_20nm_PHY_LNCK_TEST_STR1                         0x00000120
  93
  94 #define REG_DSI_20nm_PHY_TIMING_CTRL_0                          0x00000140
  95 #define DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO__MASK               0x000000ff
  96 #define DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT              0
  97 static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO(uint32_t val)
  98 {
  99         return ((val) << DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO__MASK;
 100 }
 101
 102 #define REG_DSI_20nm_PHY_TIMING_CTRL_1                          0x00000144
 103 #define DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK              0x000000ff
 104 #define DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT             0
 105 static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL(uint32_t val)
 106 {
 107         return ((val) << DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK;
 108 }
 109
 110 #define REG_DSI_20nm_PHY_TIMING_CTRL_2                          0x00000148
 111 #define DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK            0x000000ff
 112 #define DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT           0
 113 static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE(uint32_t val)
 114 {
 115         return ((val) << DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK;
 116 }
 117
 118 #define REG_DSI_20nm_PHY_TIMING_CTRL_3                          0x0000014c
 119 #define DSI_20nm_PHY_TIMING_CTRL_3_CLK_ZERO_8                   0x00000001
 120
 121 #define REG_DSI_20nm_PHY_TIMING_CTRL_4                          0x00000150
 122 #define DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT__MASK                0x000000ff
 123 #define DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT               0
 124 static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT(uint32_t val)
 125 {
 126         return ((val) << DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT__MASK;
 127 }
 128
 129 #define REG_DSI_20nm_PHY_TIMING_CTRL_5                          0x00000154
 130 #define DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO__MASK                0x000000ff
 131 #define DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT               0
 132 static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO(uint32_t val)
 133 {
 134         return ((val) << DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO__MASK;
 135 }
 136
 137 #define REG_DSI_20nm_PHY_TIMING_CTRL_6                          0x00000158
 138 #define DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE__MASK             0x000000ff
 139 #define DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT            0
 140 static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE(uint32_t val)
 141 {
 142         return ((val) << DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE__MASK;
 143 }
 144
 145 #define REG_DSI_20nm_PHY_TIMING_CTRL_7                          0x0000015c
 146 #define DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL__MASK               0x000000ff
 147 #define DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT              0
 148 static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL(uint32_t val)
 149 {
 150         return ((val) << DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL__MASK;
 151 }
 152
 153 #define REG_DSI_20nm_PHY_TIMING_CTRL_8                          0x00000160
 154 #define DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST__MASK                0x000000ff
 155 #define DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST__SHIFT               0
 156 static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST(uint32_t val)
 157 {
 158         return ((val) << DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST__MASK;
 159 }
 160
 161 #define REG_DSI_20nm_PHY_TIMING_CTRL_9                          0x00000164
 162 #define DSI_20nm_PHY_TIMING_CTRL_9_TA_GO__MASK                  0x00000007
 163 #define DSI_20nm_PHY_TIMING_CTRL_9_TA_GO__SHIFT                 0
 164 static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_9_TA_GO(uint32_t val)
 165 {
 166         return ((val) << DSI_20nm_PHY_TIMING_CTRL_9_TA_GO__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_9_TA_GO__MASK;
 167 }
 168 #define DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE__MASK                0x00000070
 169 #define DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE__SHIFT               4
 170 static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE(uint32_t val)
 171 {
 172         return ((val) << DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE__MASK;
 173 }
 174
 175 #define REG_DSI_20nm_PHY_TIMING_CTRL_10                         0x00000168
 176 #define DSI_20nm_PHY_TIMING_CTRL_10_TA_GET__MASK                0x00000007
 177 #define DSI_20nm_PHY_TIMING_CTRL_10_TA_GET__SHIFT               0
 178 static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_10_TA_GET(uint32_t val)
 179 {
 180         return ((val) << DSI_20nm_PHY_TIMING_CTRL_10_TA_GET__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_10_TA_GET__MASK;
 181 }
 182
 183 #define REG_DSI_20nm_PHY_TIMING_CTRL_11                         0x0000016c
 184 #define DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK             0x000000ff
 185 #define DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT            0
 186 static inline uint32_t DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD(uint32_t val)
 187 {
 188         return ((val) << DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT) & DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK;
 189 }
 190
 191 #define REG_DSI_20nm_PHY_CTRL_0                                 0x00000170
 192
 193 #define REG_DSI_20nm_PHY_CTRL_1                                 0x00000174
 194
 195 #define REG_DSI_20nm_PHY_CTRL_2                                 0x00000178
 196
 197 #define REG_DSI_20nm_PHY_CTRL_3                                 0x0000017c
 198
 199 #define REG_DSI_20nm_PHY_CTRL_4                                 0x00000180
 200
 201 #define REG_DSI_20nm_PHY_STRENGTH_0                             0x00000184
 202
 203 #define REG_DSI_20nm_PHY_STRENGTH_1                             0x00000188
 204
 205 #define REG_DSI_20nm_PHY_BIST_CTRL_0                            0x000001b4
 206
 207 #define REG_DSI_20nm_PHY_BIST_CTRL_1                            0x000001b8
 208
 209 #define REG_DSI_20nm_PHY_BIST_CTRL_2                            0x000001bc
 210
 211 #define REG_DSI_20nm_PHY_BIST_CTRL_3                            0x000001c0
 212
 213 #define REG_DSI_20nm_PHY_BIST_CTRL_4                            0x000001c4
 214
 215 #define REG_DSI_20nm_PHY_BIST_CTRL_5                            0x000001c8
 216
 217 #define REG_DSI_20nm_PHY_GLBL_TEST_CTRL                         0x000001d4
 218 #define DSI_20nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL               0x00000001
 219
 220 #define REG_DSI_20nm_PHY_LDO_CNTRL                              0x000001dc
 221
 222 #define REG_DSI_20nm_PHY_REGULATOR_CTRL_0                       0x00000000
 223
 224 #define REG_DSI_20nm_PHY_REGULATOR_CTRL_1                       0x00000004
 225
 226 #define REG_DSI_20nm_PHY_REGULATOR_CTRL_2                       0x00000008
 227
 228 #define REG_DSI_20nm_PHY_REGULATOR_CTRL_3                       0x0000000c
 229
 230 #define REG_DSI_20nm_PHY_REGULATOR_CTRL_4                       0x00000010
 231
 232 #define REG_DSI_20nm_PHY_REGULATOR_CTRL_5                       0x00000014
 233
 234 #define REG_DSI_20nm_PHY_REGULATOR_CAL_PWR_CFG                  0x00000018
 235
 236
 237 #endif /* DSI_PHY_20NM_XML */