drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2013 Red Hat
   4  * Copyright (c) 2014-2018, The Linux Foundation. All rights reserved.
   5  * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
   6  *
   7  * Author: Rob Clark <[email protected]>
   8  */
   9
  10 #define pr_fmt(fmt)     "[drm:%s:%d] " fmt, __func__, __LINE__
  11
  12 #include <linux/debugfs.h>
  13 #include <linux/dma-buf.h>
  14 #include <linux/of_irq.h>
  15 #include <linux/pm_opp.h>
  16
  17 #include <drm/drm_crtc.h>
  18 #include <drm/drm_file.h>
  19 #include <drm/drm_framebuffer.h>
  20 #include <drm/drm_vblank.h>
  21 #include <drm/drm_writeback.h>
  22
  23 #include "msm_drv.h"
  24 #include "msm_mmu.h"
  25 #include "msm_gem.h"
  26 #include "disp/msm_disp_snapshot.h"
  27
  28 #include "dpu_core_irq.h"
  29 #include "dpu_crtc.h"
  30 #include "dpu_encoder.h"
  31 #include "dpu_formats.h"
  32 #include "dpu_hw_vbif.h"
  33 #include "dpu_kms.h"
  34 #include "dpu_plane.h"
  35 #include "dpu_vbif.h"
  36 #include "dpu_writeback.h"
  37
  38 #define CREATE_TRACE_POINTS
  39 #include "dpu_trace.h"
  40
  41 /*
  42  * To enable overall DRM driver logging
  43  * # echo 0x2 > /sys/module/drm/parameters/debug
  44  *
  45  * To enable DRM driver h/w logging
  46  * # echo <mask> > /sys/kernel/debug/dri/0/debug/hw_log_mask
  47  *
  48  * See dpu_hw_mdss.h for h/w logging mask definitions (search for DPU_DBG_MASK_)
  49  */
  50 #define DPU_DEBUGFS_DIR "msm_dpu"
  51 #define DPU_DEBUGFS_HWMASKNAME "hw_log_mask"
  52
  53 static int dpu_kms_hw_init(struct msm_kms *kms);
  54 static void _dpu_kms_mmu_destroy(struct dpu_kms *dpu_kms);
  55
  56 #ifdef CONFIG_DEBUG_FS
  57 static int _dpu_danger_signal_status(struct seq_file *s,
  58                 bool danger_status)
  59 {
  60         struct dpu_kms *kms = (struct dpu_kms *)s->private;
  61         struct dpu_danger_safe_status status;
  62         int i;
  63
  64         if (!kms->hw_mdp) {
  65                 DPU_ERROR("invalid arg(s)\n");
  66                 return 0;
  67         }
  68
  69         memset(&status, 0, sizeof(struct dpu_danger_safe_status));
  70
  71         pm_runtime_get_sync(&kms->pdev->dev);
  72         if (danger_status) {
  73                 seq_puts(s, "\nDanger signal status:\n");
  74                 if (kms->hw_mdp->ops.get_danger_status)
  75                         kms->hw_mdp->ops.get_danger_status(kms->hw_mdp,
  76                                         &status);
  77         } else {
  78                 seq_puts(s, "\nSafe signal status:\n");
  79                 if (kms->hw_mdp->ops.get_safe_status)
  80                         kms->hw_mdp->ops.get_safe_status(kms->hw_mdp,
  81                                         &status);
  82         }
  83         pm_runtime_put_sync(&kms->pdev->dev);
  84
  85         seq_printf(s, "MDP     :  0x%x\n", status.mdp);
  86
  87         for (i = SSPP_VIG0; i < SSPP_MAX; i++)
  88                 seq_printf(s, "SSPP%d   :  0x%x  \n", i - SSPP_VIG0,
  89                                 status.sspp[i]);
  90         seq_puts(s, "\n");
  91
  92         return 0;
  93 }
  94
  95 static int dpu_debugfs_danger_stats_show(struct seq_file *s, void *v)
  96 {
  97         return _dpu_danger_signal_status(s, true);
  98 }
  99 DEFINE_SHOW_ATTRIBUTE(dpu_debugfs_danger_stats);
 100
 101 static int dpu_debugfs_safe_stats_show(struct seq_file *s, void *v)
 102 {
 103         return _dpu_danger_signal_status(s, false);
 104 }
 105 DEFINE_SHOW_ATTRIBUTE(dpu_debugfs_safe_stats);
 106
 107 static ssize_t _dpu_plane_danger_read(struct file *file,
 108                         char __user *buff, size_t count, loff_t *ppos)
 109 {
 110         struct dpu_kms *kms = file->private_data;
 111         int len;
 112         char buf[40];
 113
 114         len = scnprintf(buf, sizeof(buf), "%d\n", !kms->has_danger_ctrl);
 115
 116         return simple_read_from_buffer(buff, count, ppos, buf, len);
 117 }
 118
 119 static void _dpu_plane_set_danger_state(struct dpu_kms *kms, bool enable)
 120 {
 121         struct drm_plane *plane;
 122
 123         drm_for_each_plane(plane, kms->dev) {
 124                 if (plane->fb && plane->state) {
 125                         dpu_plane_danger_signal_ctrl(plane, enable);
 126                         DPU_DEBUG("plane:%d img:%dx%d ",
 127                                 plane->base.id, plane->fb->width,
 128                                 plane->fb->height);
 129                         DPU_DEBUG("src[%d,%d,%d,%d] dst[%d,%d,%d,%d]\n",
 130                                 plane->state->src_x >> 16,
 131                                 plane->state->src_y >> 16,
 132                                 plane->state->src_w >> 16,
 133                                 plane->state->src_h >> 16,
 134                                 plane->state->crtc_x, plane->state->crtc_y,
 135                                 plane->state->crtc_w, plane->state->crtc_h);
 136                 } else {
 137                         DPU_DEBUG("Inactive plane:%d\n", plane->base.id);
 138                 }
 139         }
 140 }
 141
 142 static ssize_t _dpu_plane_danger_write(struct file *file,
 143                     const char __user *user_buf, size_t count, loff_t *ppos)
 144 {
 145         struct dpu_kms *kms = file->private_data;
 146         int disable_panic;
 147         int ret;
 148
 149         ret = kstrtouint_from_user(user_buf, count, 0, &disable_panic);
 150         if (ret)
 151                 return ret;
 152
 153         if (disable_panic) {
 154                 /* Disable panic signal for all active pipes */
 155                 DPU_DEBUG("Disabling danger:\n");
 156                 _dpu_plane_set_danger_state(kms, false);
 157                 kms->has_danger_ctrl = false;
 158         } else {
 159                 /* Enable panic signal for all active pipes */
 160                 DPU_DEBUG("Enabling danger:\n");
 161                 kms->has_danger_ctrl = true;
 162                 _dpu_plane_set_danger_state(kms, true);
 163         }
 164
 165         return count;
 166 }
 167
 168 static const struct file_operations dpu_plane_danger_enable = {
 169         .open = simple_open,
 170         .read = _dpu_plane_danger_read,
 171         .write = _dpu_plane_danger_write,
 172 };
 173
 174 static void dpu_debugfs_danger_init(struct dpu_kms *dpu_kms,
 175                 struct dentry *parent)
 176 {
 177         struct dentry *entry = debugfs_create_dir("danger", parent);
 178
 179         debugfs_create_file("danger_status", 0600, entry,
 180                         dpu_kms, &dpu_debugfs_danger_stats_fops);
 181         debugfs_create_file("safe_status", 0600, entry,
 182                         dpu_kms, &dpu_debugfs_safe_stats_fops);
 183         debugfs_create_file("disable_danger", 0600, entry,
 184                         dpu_kms, &dpu_plane_danger_enable);
 185
 186 }
 187
 188 /*
 189  * Companion structure for dpu_debugfs_create_regset32.
 190  */
 191 struct dpu_debugfs_regset32 {
 192         uint32_t offset;
 193         uint32_t blk_len;
 194         struct dpu_kms *dpu_kms;
 195 };
 196
 197 static int dpu_regset32_show(struct seq_file *s, void *data)
 198 {
 199         struct dpu_debugfs_regset32 *regset = s->private;
 200         struct dpu_kms *dpu_kms = regset->dpu_kms;
 201         void __iomem *base;
 202         uint32_t i, addr;
 203
 204         if (!dpu_kms->mmio)
 205                 return 0;
 206
 207         base = dpu_kms->mmio + regset->offset;
 208
 209         /* insert padding spaces, if needed */
 210         if (regset->offset & 0xF) {
 211                 seq_printf(s, "[%x]", regset->offset & ~0xF);
 212                 for (i = 0; i < (regset->offset & 0xF); i += 4)
 213                         seq_puts(s, "         ");
 214         }
 215
 216         pm_runtime_get_sync(&dpu_kms->pdev->dev);
 217
 218         /* main register output */
 219         for (i = 0; i < regset->blk_len; i += 4) {
 220                 addr = regset->offset + i;
 221                 if ((addr & 0xF) == 0x0)
 222                         seq_printf(s, i ? "\n[%x]" : "[%x]", addr);
 223                 seq_printf(s, " %08x", readl_relaxed(base + i));
 224         }
 225         seq_puts(s, "\n");
 226         pm_runtime_put_sync(&dpu_kms->pdev->dev);
 227
 228         return 0;
 229 }
 230 DEFINE_SHOW_ATTRIBUTE(dpu_regset32);
 231
 232 void dpu_debugfs_create_regset32(const char *name, umode_t mode,
 233                 void *parent,
 234                 uint32_t offset, uint32_t length, struct dpu_kms *dpu_kms)
 235 {
 236         struct dpu_debugfs_regset32 *regset;
 237
 238         if (WARN_ON(!name || !dpu_kms || !length))
 239                 return;
 240
 241         regset = devm_kzalloc(&dpu_kms->pdev->dev, sizeof(*regset), GFP_KERNEL);
 242         if (!regset)
 243                 return;
 244
 245         /* make sure offset is a multiple of 4 */
 246         regset->offset = round_down(offset, 4);
 247         regset->blk_len = length;
 248         regset->dpu_kms = dpu_kms;
 249
 250         debugfs_create_file(name, mode, parent, regset, &dpu_regset32_fops);
 251 }
 252
 253 static void dpu_debugfs_sspp_init(struct dpu_kms *dpu_kms, struct dentry *debugfs_root)
 254 {
 255         struct dentry *entry = debugfs_create_dir("sspp", debugfs_root);
 256         int i;
 257
 258         if (IS_ERR(entry))
 259                 return;
 260
 261         for (i = SSPP_NONE; i < SSPP_MAX; i++) {
 262                 struct dpu_hw_sspp *hw = dpu_rm_get_sspp(&dpu_kms->rm, i);
 263
 264                 if (!hw)
 265                         continue;
 266
 267                 _dpu_hw_sspp_init_debugfs(hw, dpu_kms, entry);
 268         }
 269 }
 270
 271 static int dpu_kms_debugfs_init(struct msm_kms *kms, struct drm_minor *minor)
 272 {
 273         struct dpu_kms *dpu_kms = to_dpu_kms(kms);
 274         void *p = dpu_hw_util_get_log_mask_ptr();
 275         struct dentry *entry;
 276         struct drm_device *dev;
 277         struct msm_drm_private *priv;
 278         int i;
 279
 280         if (!p)
 281                 return -EINVAL;
 282
 283         /* Only create a set of debugfs for the primary node, ignore render nodes */
 284         if (minor->type != DRM_MINOR_PRIMARY)
 285                 return 0;
 286
 287         dev = dpu_kms->dev;
 288         priv = dev->dev_private;
 289
 290         entry = debugfs_create_dir("debug", minor->debugfs_root);
 291
 292         debugfs_create_x32(DPU_DEBUGFS_HWMASKNAME, 0600, entry, p);
 293
 294         dpu_debugfs_danger_init(dpu_kms, entry);
 295         dpu_debugfs_vbif_init(dpu_kms, entry);
 296         dpu_debugfs_core_irq_init(dpu_kms, entry);
 297         dpu_debugfs_sspp_init(dpu_kms, entry);
 298
 299         for (i = 0; i < ARRAY_SIZE(priv->dp); i++) {
 300                 if (priv->dp[i])
 301                         msm_dp_debugfs_init(priv->dp[i], minor);
 302         }
 303
 304         return dpu_core_perf_debugfs_init(dpu_kms, entry);
 305 }
 306 #endif
 307
 308 /* Global/shared object state funcs */
 309
 310 /*
 311  * This is a helper that returns the private state currently in operation.
 312  * Note that this would return the "old_state" if called in the atomic check
 313  * path, and the "new_state" after the atomic swap has been done.
 314  */
 315 struct dpu_global_state *
 316 dpu_kms_get_existing_global_state(struct dpu_kms *dpu_kms)
 317 {
 318         return to_dpu_global_state(dpu_kms->global_state.state);
 319 }
 320
 321 /*
 322  * This acquires the modeset lock set aside for global state, creates
 323  * a new duplicated private object state.
 324  */
 325 struct dpu_global_state *dpu_kms_get_global_state(struct drm_atomic_state *s)
 326 {
 327         struct msm_drm_private *priv = s->dev->dev_private;
 328         struct dpu_kms *dpu_kms = to_dpu_kms(priv->kms);
 329         struct drm_private_state *priv_state;
 330         int ret;
 331
 332         ret = drm_modeset_lock(&dpu_kms->global_state_lock, s->acquire_ctx);
 333         if (ret)
 334                 return ERR_PTR(ret);
 335
 336         priv_state = drm_atomic_get_private_obj_state(s,
 337                                                 &dpu_kms->global_state);
 338         if (IS_ERR(priv_state))
 339                 return ERR_CAST(priv_state);
 340
 341         return to_dpu_global_state(priv_state);
 342 }
 343
 344 static struct drm_private_state *
 345 dpu_kms_global_duplicate_state(struct drm_private_obj *obj)
 346 {
 347         struct dpu_global_state *state;
 348
 349         state = kmemdup(obj->state, sizeof(*state), GFP_KERNEL);
 350         if (!state)
 351                 return NULL;
 352
 353         __drm_atomic_helper_private_obj_duplicate_state(obj, &state->base);
 354
 355         return &state->base;
 356 }
 357
 358 static void dpu_kms_global_destroy_state(struct drm_private_obj *obj,
 359                                       struct drm_private_state *state)
 360 {
 361         struct dpu_global_state *dpu_state = to_dpu_global_state(state);
 362
 363         kfree(dpu_state);
 364 }
 365
 366 static const struct drm_private_state_funcs dpu_kms_global_state_funcs = {
 367         .atomic_duplicate_state = dpu_kms_global_duplicate_state,
 368         .atomic_destroy_state = dpu_kms_global_destroy_state,
 369 };
 370
 371 static int dpu_kms_global_obj_init(struct dpu_kms *dpu_kms)
 372 {
 373         struct dpu_global_state *state;
 374
 375         drm_modeset_lock_init(&dpu_kms->global_state_lock);
 376
 377         state = kzalloc(sizeof(*state), GFP_KERNEL);
 378         if (!state)
 379                 return -ENOMEM;
 380
 381         drm_atomic_private_obj_init(dpu_kms->dev, &dpu_kms->global_state,
 382                                     &state->base,
 383                                     &dpu_kms_global_state_funcs);
 384         return 0;
 385 }
 386
 387 static int dpu_kms_parse_data_bus_icc_path(struct dpu_kms *dpu_kms)
 388 {
 389         struct icc_path *path0;
 390         struct icc_path *path1;
 391         struct drm_device *dev = dpu_kms->dev;
 392         struct device *dpu_dev = dev->dev;
 393
 394         path0 = msm_icc_get(dpu_dev, "mdp0-mem");
 395         path1 = msm_icc_get(dpu_dev, "mdp1-mem");
 396
 397         if (IS_ERR_OR_NULL(path0))
 398                 return PTR_ERR_OR_ZERO(path0);
 399
 400         dpu_kms->path[0] = path0;
 401         dpu_kms->num_paths = 1;
 402
 403         if (!IS_ERR_OR_NULL(path1)) {
 404                 dpu_kms->path[1] = path1;
 405                 dpu_kms->num_paths++;
 406         }
 407         return 0;
 408 }
 409
 410 static int dpu_kms_enable_vblank(struct msm_kms *kms, struct drm_crtc *crtc)
 411 {
 412         return dpu_crtc_vblank(crtc, true);
 413 }
 414
 415 static void dpu_kms_disable_vblank(struct msm_kms *kms, struct drm_crtc *crtc)
 416 {
 417         dpu_crtc_vblank(crtc, false);
 418 }
 419
 420 static void dpu_kms_enable_commit(struct msm_kms *kms)
 421 {
 422         struct dpu_kms *dpu_kms = to_dpu_kms(kms);
 423         pm_runtime_get_sync(&dpu_kms->pdev->dev);
 424 }
 425
 426 static void dpu_kms_disable_commit(struct msm_kms *kms)
 427 {
 428         struct dpu_kms *dpu_kms = to_dpu_kms(kms);
 429         pm_runtime_put_sync(&dpu_kms->pdev->dev);
 430 }
 431
 432 static void dpu_kms_flush_commit(struct msm_kms *kms, unsigned crtc_mask)
 433 {
 434         struct dpu_kms *dpu_kms = to_dpu_kms(kms);
 435         struct drm_crtc *crtc;
 436
 437         for_each_crtc_mask(dpu_kms->dev, crtc, crtc_mask) {
 438                 if (!crtc->state->active)
 439                         continue;
 440
 441                 trace_dpu_kms_commit(DRMID(crtc));
 442                 dpu_crtc_commit_kickoff(crtc);
 443         }
 444 }
 445
 446 static void dpu_kms_complete_commit(struct msm_kms *kms, unsigned crtc_mask)
 447 {
 448         struct dpu_kms *dpu_kms = to_dpu_kms(kms);
 449         struct drm_crtc *crtc;
 450
 451         DPU_ATRACE_BEGIN("kms_complete_commit");
 452
 453         for_each_crtc_mask(dpu_kms->dev, crtc, crtc_mask)
 454                 dpu_crtc_complete_commit(crtc);
 455
 456         DPU_ATRACE_END("kms_complete_commit");
 457 }
 458
 459 static void dpu_kms_wait_for_commit_done(struct msm_kms *kms,
 460                 struct drm_crtc *crtc)
 461 {
 462         struct drm_encoder *encoder;
 463         struct drm_device *dev;
 464         int ret;
 465
 466         if (!kms || !crtc || !crtc->state) {
 467                 DPU_ERROR("invalid params\n");
 468                 return;
 469         }
 470
 471         dev = crtc->dev;
 472
 473         if (!crtc->state->enable) {
 474                 DPU_DEBUG("[crtc:%d] not enable\n", crtc->base.id);
 475                 return;
 476         }
 477
 478         if (!drm_atomic_crtc_effectively_active(crtc->state)) {
 479                 DPU_DEBUG("[crtc:%d] not active\n", crtc->base.id);
 480                 return;
 481         }
 482
 483         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
 484                 if (encoder->crtc != crtc)
 485                         continue;
 486                 /*
 487                  * Wait for post-flush if necessary to delay before
 488                  * plane_cleanup. For example, wait for vsync in case of video
 489                  * mode panels. This may be a no-op for command mode panels.
 490                  */
 491                 trace_dpu_kms_wait_for_commit_done(DRMID(crtc));
 492                 ret = dpu_encoder_wait_for_event(encoder, MSM_ENC_COMMIT_DONE);
 493                 if (ret && ret != -EWOULDBLOCK) {
 494                         DPU_ERROR("wait for commit done returned %d\n", ret);
 495                         break;
 496                 }
 497         }
 498 }
 499
 500 static void dpu_kms_wait_flush(struct msm_kms *kms, unsigned crtc_mask)
 501 {
 502         struct dpu_kms *dpu_kms = to_dpu_kms(kms);
 503         struct drm_crtc *crtc;
 504
 505         for_each_crtc_mask(dpu_kms->dev, crtc, crtc_mask)
 506                 dpu_kms_wait_for_commit_done(kms, crtc);
 507 }
 508
 509 static int _dpu_kms_initialize_dsi(struct drm_device *dev,
 510                                     struct msm_drm_private *priv,
 511                                     struct dpu_kms *dpu_kms)
 512 {
 513         struct drm_encoder *encoder = NULL;
 514         struct msm_display_info info;
 515         int i, rc = 0;
 516
 517         if (!(priv->dsi[0] || priv->dsi[1]))
 518                 return rc;
 519
 520         /*
 521          * We support following confiurations:
 522          * - Single DSI host (dsi0 or dsi1)
 523          * - Two independent DSI hosts
 524          * - Bonded DSI0 and DSI1 hosts
 525          *
 526          * TODO: Support swapping DSI0 and DSI1 in the bonded setup.
 527          */
 528         for (i = 0; i < ARRAY_SIZE(priv->dsi); i++) {
 529                 int other = (i + 1) % 2;
 530
 531                 if (!priv->dsi[i])
 532                         continue;
 533
 534                 if (msm_dsi_is_bonded_dsi(priv->dsi[i]) &&
 535                     !msm_dsi_is_master_dsi(priv->dsi[i]))
 536                         continue;
 537
 538                 encoder = dpu_encoder_init(dev, DRM_MODE_ENCODER_DSI);
 539                 if (IS_ERR(encoder)) {
 540                         DPU_ERROR("encoder init failed for dsi display\n");
 541                         return PTR_ERR(encoder);
 542                 }
 543
 544                 memset(&info, 0, sizeof(info));
 545                 info.intf_type = encoder->encoder_type;
 546
 547                 rc = msm_dsi_modeset_init(priv->dsi[i], dev, encoder);
 548                 if (rc) {
 549                         DPU_ERROR("modeset_init failed for dsi[%d], rc = %d\n",
 550                                 i, rc);
 551                         break;
 552                 }
 553
 554                 info.h_tile_instance[info.num_of_h_tiles++] = i;
 555                 info.is_cmd_mode = msm_dsi_is_cmd_mode(priv->dsi[i]);
 556
 557                 info.dsc = msm_dsi_get_dsc_config(priv->dsi[i]);
 558
 559                 if (msm_dsi_is_bonded_dsi(priv->dsi[i]) && priv->dsi[other]) {
 560                         rc = msm_dsi_modeset_init(priv->dsi[other], dev, encoder);
 561                         if (rc) {
 562                                 DPU_ERROR("modeset_init failed for dsi[%d], rc = %d\n",
 563                                         other, rc);
 564                                 break;
 565                         }
 566
 567                         info.h_tile_instance[info.num_of_h_tiles++] = other;
 568                 }
 569
 570                 rc = dpu_encoder_setup(dev, encoder, &info);
 571                 if (rc)
 572                         DPU_ERROR("failed to setup DPU encoder %d: rc:%d\n",
 573                                   encoder->base.id, rc);
 574         }
 575
 576         return rc;
 577 }
 578
 579 static int _dpu_kms_initialize_displayport(struct drm_device *dev,
 580                                             struct msm_drm_private *priv,
 581                                             struct dpu_kms *dpu_kms)
 582 {
 583         struct drm_encoder *encoder = NULL;
 584         struct msm_display_info info;
 585         int rc;
 586         int i;
 587
 588         for (i = 0; i < ARRAY_SIZE(priv->dp); i++) {
 589                 if (!priv->dp[i])
 590                         continue;
 591
 592                 encoder = dpu_encoder_init(dev, DRM_MODE_ENCODER_TMDS);
 593                 if (IS_ERR(encoder)) {
 594                         DPU_ERROR("encoder init failed for dsi display\n");
 595                         return PTR_ERR(encoder);
 596                 }
 597
 598                 memset(&info, 0, sizeof(info));
 599                 rc = msm_dp_modeset_init(priv->dp[i], dev, encoder);
 600                 if (rc) {
 601                         DPU_ERROR("modeset_init failed for DP, rc = %d\n", rc);
 602                         drm_encoder_cleanup(encoder);
 603                         return rc;
 604                 }
 605
 606                 info.num_of_h_tiles = 1;
 607                 info.h_tile_instance[0] = i;
 608                 info.intf_type = encoder->encoder_type;
 609                 rc = dpu_encoder_setup(dev, encoder, &info);
 610                 if (rc) {
 611                         DPU_ERROR("failed to setup DPU encoder %d: rc:%d\n",
 612                                   encoder->base.id, rc);
 613                         return rc;
 614                 }
 615         }
 616
 617         return 0;
 618 }
 619
 620 static int _dpu_kms_initialize_writeback(struct drm_device *dev,
 621                 struct msm_drm_private *priv, struct dpu_kms *dpu_kms,
 622                 const u32 *wb_formats, int n_formats)
 623 {
 624         struct drm_encoder *encoder = NULL;
 625         struct msm_display_info info;
 626         int rc;
 627
 628         encoder = dpu_encoder_init(dev, DRM_MODE_ENCODER_VIRTUAL);
 629         if (IS_ERR(encoder)) {
 630                 DPU_ERROR("encoder init failed for dsi display\n");
 631                 return PTR_ERR(encoder);
 632         }
 633
 634         memset(&info, 0, sizeof(info));
 635
 636         rc = dpu_writeback_init(dev, encoder, wb_formats,
 637                         n_formats);
 638         if (rc) {
 639                 DPU_ERROR("dpu_writeback_init, rc = %d\n", rc);
 640                 drm_encoder_cleanup(encoder);
 641                 return rc;
 642         }
 643
 644         info.num_of_h_tiles = 1;
 645         /* use only WB idx 2 instance for DPU */
 646         info.h_tile_instance[0] = WB_2;
 647         info.intf_type = encoder->encoder_type;
 648
 649         rc = dpu_encoder_setup(dev, encoder, &info);
 650         if (rc) {
 651                 DPU_ERROR("failed to setup DPU encoder %d: rc:%d\n",
 652                                   encoder->base.id, rc);
 653                 return rc;
 654         }
 655
 656         return 0;
 657 }
 658
 659 /**
 660  * _dpu_kms_setup_displays - create encoders, bridges and connectors
 661  *                           for underlying displays
 662  * @dev:        Pointer to drm device structure
 663  * @priv:       Pointer to private drm device data
 664  * @dpu_kms:    Pointer to dpu kms structure
 665  * Returns:     Zero on success
 666  */
 667 static int _dpu_kms_setup_displays(struct drm_device *dev,
 668                                     struct msm_drm_private *priv,
 669                                     struct dpu_kms *dpu_kms)
 670 {
 671         int rc = 0;
 672         int i;
 673
 674         rc = _dpu_kms_initialize_dsi(dev, priv, dpu_kms);
 675         if (rc) {
 676                 DPU_ERROR("initialize_dsi failed, rc = %d\n", rc);
 677                 return rc;
 678         }
 679
 680         rc = _dpu_kms_initialize_displayport(dev, priv, dpu_kms);
 681         if (rc) {
 682                 DPU_ERROR("initialize_DP failed, rc = %d\n", rc);
 683                 return rc;
 684         }
 685
 686         /* Since WB isn't a driver check the catalog before initializing */
 687         if (dpu_kms->catalog->wb_count) {
 688                 for (i = 0; i < dpu_kms->catalog->wb_count; i++) {
 689                         if (dpu_kms->catalog->wb[i].id == WB_2) {
 690                                 rc = _dpu_kms_initialize_writeback(dev, priv, dpu_kms,
 691                                                 dpu_kms->catalog->wb[i].format_list,
 692                                                 dpu_kms->catalog->wb[i].num_formats);
 693                                 if (rc) {
 694                                         DPU_ERROR("initialize_WB failed, rc = %d\n", rc);
 695                                         return rc;
 696                                 }
 697                         }
 698                 }
 699         }
 700
 701         return rc;
 702 }
 703
 704 #define MAX_PLANES 20
 705 static int _dpu_kms_drm_obj_init(struct dpu_kms *dpu_kms)
 706 {
 707         struct drm_device *dev;
 708         struct drm_plane *primary_planes[MAX_PLANES], *plane;
 709         struct drm_plane *cursor_planes[MAX_PLANES] = { NULL };
 710         struct drm_crtc *crtc;
 711         struct drm_encoder *encoder;
 712         unsigned int num_encoders;
 713
 714         struct msm_drm_private *priv;
 715         const struct dpu_mdss_cfg *catalog;
 716
 717         int primary_planes_idx = 0, cursor_planes_idx = 0, i, ret;
 718         int max_crtc_count;
 719         dev = dpu_kms->dev;
 720         priv = dev->dev_private;
 721         catalog = dpu_kms->catalog;
 722
 723         /*
 724          * Create encoder and query display drivers to create
 725          * bridges and connectors
 726          */
 727         ret = _dpu_kms_setup_displays(dev, priv, dpu_kms);
 728         if (ret)
 729                 return ret;
 730
 731         num_encoders = 0;
 732         drm_for_each_encoder(encoder, dev)
 733                 num_encoders++;
 734
 735         max_crtc_count = min(catalog->mixer_count, num_encoders);
 736
 737         /* Create the planes, keeping track of one primary/cursor per crtc */
 738         for (i = 0; i < catalog->sspp_count; i++) {
 739                 enum drm_plane_type type;
 740
 741                 if ((catalog->sspp[i].features & BIT(DPU_SSPP_CURSOR))
 742                         && cursor_planes_idx < max_crtc_count)
 743                         type = DRM_PLANE_TYPE_CURSOR;
 744                 else if (primary_planes_idx < max_crtc_count)
 745                         type = DRM_PLANE_TYPE_PRIMARY;
 746                 else
 747                         type = DRM_PLANE_TYPE_OVERLAY;
 748
 749                 DPU_DEBUG("Create plane type %d with features %lx (cur %lx)\n",
 750                           type, catalog->sspp[i].features,
 751                           catalog->sspp[i].features & BIT(DPU_SSPP_CURSOR));
 752
 753                 plane = dpu_plane_init(dev, catalog->sspp[i].id, type,
 754                                        (1UL << max_crtc_count) - 1);
 755                 if (IS_ERR(plane)) {
 756                         DPU_ERROR("dpu_plane_init failed\n");
 757                         ret = PTR_ERR(plane);
 758                         return ret;
 759                 }
 760
 761                 if (type == DRM_PLANE_TYPE_CURSOR)
 762                         cursor_planes[cursor_planes_idx++] = plane;
 763                 else if (type == DRM_PLANE_TYPE_PRIMARY)
 764                         primary_planes[primary_planes_idx++] = plane;
 765         }
 766
 767         max_crtc_count = min(max_crtc_count, primary_planes_idx);
 768
 769         /* Create one CRTC per encoder */
 770         for (i = 0; i < max_crtc_count; i++) {
 771                 crtc = dpu_crtc_init(dev, primary_planes[i], cursor_planes[i]);
 772                 if (IS_ERR(crtc)) {
 773                         ret = PTR_ERR(crtc);
 774                         return ret;
 775                 }
 776                 priv->crtcs[priv->num_crtcs++] = crtc;
 777         }
 778
 779         /* All CRTCs are compatible with all encoders */
 780         drm_for_each_encoder(encoder, dev)
 781                 encoder->possible_crtcs = (1 << priv->num_crtcs) - 1;
 782
 783         return 0;
 784 }
 785
 786 static void _dpu_kms_hw_destroy(struct dpu_kms *dpu_kms)
 787 {
 788         int i;
 789
 790         if (dpu_kms->hw_intr)
 791                 dpu_hw_intr_destroy(dpu_kms->hw_intr);
 792         dpu_kms->hw_intr = NULL;
 793
 794         /* safe to call these more than once during shutdown */
 795         _dpu_kms_mmu_destroy(dpu_kms);
 796
 797         if (dpu_kms->catalog) {
 798                 for (i = 0; i < ARRAY_SIZE(dpu_kms->hw_vbif); i++) {
 799                         if (dpu_kms->hw_vbif[i]) {
 800                                 dpu_hw_vbif_destroy(dpu_kms->hw_vbif[i]);
 801                                 dpu_kms->hw_vbif[i] = NULL;
 802                         }
 803                 }
 804         }
 805
 806         if (dpu_kms->rm_init)
 807                 dpu_rm_destroy(&dpu_kms->rm);
 808         dpu_kms->rm_init = false;
 809
 810         dpu_kms->catalog = NULL;
 811
 812         if (dpu_kms->vbif[VBIF_NRT])
 813                 devm_iounmap(&dpu_kms->pdev->dev, dpu_kms->vbif[VBIF_NRT]);
 814         dpu_kms->vbif[VBIF_NRT] = NULL;
 815
 816         if (dpu_kms->vbif[VBIF_RT])
 817                 devm_iounmap(&dpu_kms->pdev->dev, dpu_kms->vbif[VBIF_RT]);
 818         dpu_kms->vbif[VBIF_RT] = NULL;
 819
 820         if (dpu_kms->hw_mdp)
 821                 dpu_hw_mdp_destroy(dpu_kms->hw_mdp);
 822         dpu_kms->hw_mdp = NULL;
 823
 824         if (dpu_kms->mmio)
 825                 devm_iounmap(&dpu_kms->pdev->dev, dpu_kms->mmio);
 826         dpu_kms->mmio = NULL;
 827 }
 828
 829 static void dpu_kms_destroy(struct msm_kms *kms)
 830 {
 831         struct dpu_kms *dpu_kms;
 832
 833         if (!kms) {
 834                 DPU_ERROR("invalid kms\n");
 835                 return;
 836         }
 837
 838         dpu_kms = to_dpu_kms(kms);
 839
 840         _dpu_kms_hw_destroy(dpu_kms);
 841
 842         msm_kms_destroy(&dpu_kms->base);
 843
 844         if (dpu_kms->rpm_enabled)
 845                 pm_runtime_disable(&dpu_kms->pdev->dev);
 846 }
 847
 848 static int dpu_irq_postinstall(struct msm_kms *kms)
 849 {
 850         struct msm_drm_private *priv;
 851         struct dpu_kms *dpu_kms = to_dpu_kms(kms);
 852         int i;
 853
 854         if (!dpu_kms || !dpu_kms->dev)
 855                 return -EINVAL;
 856
 857         priv = dpu_kms->dev->dev_private;
 858         if (!priv)
 859                 return -EINVAL;
 860
 861         for (i = 0; i < ARRAY_SIZE(priv->dp); i++)
 862                 msm_dp_irq_postinstall(priv->dp[i]);
 863
 864         return 0;
 865 }
 866
 867 static void dpu_kms_mdp_snapshot(struct msm_disp_state *disp_state, struct msm_kms *kms)
 868 {
 869         int i;
 870         struct dpu_kms *dpu_kms;
 871         const struct dpu_mdss_cfg *cat;
 872
 873         dpu_kms = to_dpu_kms(kms);
 874
 875         cat = dpu_kms->catalog;
 876
 877         pm_runtime_get_sync(&dpu_kms->pdev->dev);
 878
 879         /* dump CTL sub-blocks HW regs info */
 880         for (i = 0; i < cat->ctl_count; i++)
 881                 msm_disp_snapshot_add_block(disp_state, cat->ctl[i].len,
 882                                 dpu_kms->mmio + cat->ctl[i].base, "ctl_%d", i);
 883
 884         /* dump DSPP sub-blocks HW regs info */
 885         for (i = 0; i < cat->dspp_count; i++)
 886                 msm_disp_snapshot_add_block(disp_state, cat->dspp[i].len,
 887                                 dpu_kms->mmio + cat->dspp[i].base, "dspp_%d", i);
 888
 889         /* dump INTF sub-blocks HW regs info */
 890         for (i = 0; i < cat->intf_count; i++)
 891                 msm_disp_snapshot_add_block(disp_state, cat->intf[i].len,
 892                                 dpu_kms->mmio + cat->intf[i].base, "intf_%d", i);
 893
 894         /* dump PP sub-blocks HW regs info */
 895         for (i = 0; i < cat->pingpong_count; i++)
 896                 msm_disp_snapshot_add_block(disp_state, cat->pingpong[i].len,
 897                                 dpu_kms->mmio + cat->pingpong[i].base, "pingpong_%d", i);
 898
 899         /* dump SSPP sub-blocks HW regs info */
 900         for (i = 0; i < cat->sspp_count; i++)
 901                 msm_disp_snapshot_add_block(disp_state, cat->sspp[i].len,
 902                                 dpu_kms->mmio + cat->sspp[i].base, "sspp_%d", i);
 903
 904         /* dump LM sub-blocks HW regs info */
 905         for (i = 0; i < cat->mixer_count; i++)
 906                 msm_disp_snapshot_add_block(disp_state, cat->mixer[i].len,
 907                                 dpu_kms->mmio + cat->mixer[i].base, "lm_%d", i);
 908
 909         /* dump WB sub-blocks HW regs info */
 910         for (i = 0; i < cat->wb_count; i++)
 911                 msm_disp_snapshot_add_block(disp_state, cat->wb[i].len,
 912                                 dpu_kms->mmio + cat->wb[i].base, "wb_%d", i);
 913
 914         if (cat->mdp[0].features & BIT(DPU_MDP_PERIPH_0_REMOVED)) {
 915                 msm_disp_snapshot_add_block(disp_state, MDP_PERIPH_TOP0,
 916                                 dpu_kms->mmio + cat->mdp[0].base, "top");
 917                 msm_disp_snapshot_add_block(disp_state, cat->mdp[0].len - MDP_PERIPH_TOP0_END,
 918                                 dpu_kms->mmio + cat->mdp[0].base + MDP_PERIPH_TOP0_END, "top_2");
 919         } else {
 920                 msm_disp_snapshot_add_block(disp_state, cat->mdp[0].len,
 921                                 dpu_kms->mmio + cat->mdp[0].base, "top");
 922         }
 923
 924         /* dump DSC sub-blocks HW regs info */
 925         for (i = 0; i < cat->dsc_count; i++)
 926                 msm_disp_snapshot_add_block(disp_state, cat->dsc[i].len,
 927                                 dpu_kms->mmio + cat->dsc[i].base, "dsc_%d", i);
 928
 929         pm_runtime_put_sync(&dpu_kms->pdev->dev);
 930 }
 931
 932 static const struct msm_kms_funcs kms_funcs = {
 933         .hw_init         = dpu_kms_hw_init,
 934         .irq_preinstall  = dpu_core_irq_preinstall,
 935         .irq_postinstall = dpu_irq_postinstall,
 936         .irq_uninstall   = dpu_core_irq_uninstall,
 937         .irq             = dpu_core_irq,
 938         .enable_commit   = dpu_kms_enable_commit,
 939         .disable_commit  = dpu_kms_disable_commit,
 940         .flush_commit    = dpu_kms_flush_commit,
 941         .wait_flush      = dpu_kms_wait_flush,
 942         .complete_commit = dpu_kms_complete_commit,
 943         .enable_vblank   = dpu_kms_enable_vblank,
 944         .disable_vblank  = dpu_kms_disable_vblank,
 945         .check_modified_format = dpu_format_check_modified_format,
 946         .get_format      = dpu_get_msm_format,
 947         .destroy         = dpu_kms_destroy,
 948         .snapshot        = dpu_kms_mdp_snapshot,
 949 #ifdef CONFIG_DEBUG_FS
 950         .debugfs_init    = dpu_kms_debugfs_init,
 951 #endif
 952 };
 953
 954 static void _dpu_kms_mmu_destroy(struct dpu_kms *dpu_kms)
 955 {
 956         struct msm_mmu *mmu;
 957
 958         if (!dpu_kms->base.aspace)
 959                 return;
 960
 961         mmu = dpu_kms->base.aspace->mmu;
 962
 963         mmu->funcs->detach(mmu);
 964         msm_gem_address_space_put(dpu_kms->base.aspace);
 965
 966         dpu_kms->base.aspace = NULL;
 967 }
 968
 969 static int _dpu_kms_mmu_init(struct dpu_kms *dpu_kms)
 970 {
 971         struct msm_gem_address_space *aspace;
 972
 973         aspace = msm_kms_init_aspace(dpu_kms->dev);
 974         if (IS_ERR(aspace))
 975                 return PTR_ERR(aspace);
 976
 977         dpu_kms->base.aspace = aspace;
 978
 979         return 0;
 980 }
 981
 982 u64 dpu_kms_get_clk_rate(struct dpu_kms *dpu_kms, char *clock_name)
 983 {
 984         struct clk *clk;
 985
 986         clk = msm_clk_bulk_get_clock(dpu_kms->clocks, dpu_kms->num_clocks, clock_name);
 987         if (!clk)
 988                 return -EINVAL;
 989
 990         return clk_get_rate(clk);
 991 }
 992
 993 static int dpu_kms_hw_init(struct msm_kms *kms)
 994 {
 995         struct dpu_kms *dpu_kms;
 996         struct drm_device *dev;
 997         int i, rc = -EINVAL;
 998         u32 core_rev;
 999
1000         if (!kms) {
1001                 DPU_ERROR("invalid kms\n");
1002                 return rc;
1003         }
1004
1005         dpu_kms = to_dpu_kms(kms);
1006         dev = dpu_kms->dev;
1007
1008         rc = dpu_kms_global_obj_init(dpu_kms);
1009         if (rc)
1010                 return rc;
1011
1012         atomic_set(&dpu_kms->bandwidth_ref, 0);
1013
1014         dpu_kms->mmio = msm_ioremap(dpu_kms->pdev, "mdp");
1015         if (IS_ERR(dpu_kms->mmio)) {
1016                 rc = PTR_ERR(dpu_kms->mmio);
1017                 DPU_ERROR("mdp register memory map failed: %d\n", rc);
1018                 dpu_kms->mmio = NULL;
1019                 goto error;
1020         }
1021         DRM_DEBUG("mapped dpu address space @%pK\n", dpu_kms->mmio);
1022
1023         dpu_kms->vbif[VBIF_RT] = msm_ioremap(dpu_kms->pdev, "vbif");
1024         if (IS_ERR(dpu_kms->vbif[VBIF_RT])) {
1025                 rc = PTR_ERR(dpu_kms->vbif[VBIF_RT]);
1026                 DPU_ERROR("vbif register memory map failed: %d\n", rc);
1027                 dpu_kms->vbif[VBIF_RT] = NULL;
1028                 goto error;
1029         }
1030         dpu_kms->vbif[VBIF_NRT] = msm_ioremap_quiet(dpu_kms->pdev, "vbif_nrt");
1031         if (IS_ERR(dpu_kms->vbif[VBIF_NRT])) {
1032                 dpu_kms->vbif[VBIF_NRT] = NULL;
1033                 DPU_DEBUG("VBIF NRT is not defined");
1034         }
1035
1036         dpu_kms->reg_dma = msm_ioremap_quiet(dpu_kms->pdev, "regdma");
1037         if (IS_ERR(dpu_kms->reg_dma)) {
1038                 dpu_kms->reg_dma = NULL;
1039                 DPU_DEBUG("REG_DMA is not defined");
1040         }
1041
1042         dpu_kms_parse_data_bus_icc_path(dpu_kms);
1043
1044         rc = pm_runtime_resume_and_get(&dpu_kms->pdev->dev);
1045         if (rc < 0)
1046                 goto error;
1047
1048         core_rev = readl_relaxed(dpu_kms->mmio + 0x0);
1049
1050         pr_info("dpu hardware revision:0x%x\n", core_rev);
1051
1052         dpu_kms->catalog = of_device_get_match_data(dev->dev);
1053         if (!dpu_kms->catalog) {
1054                 DPU_ERROR("device config not known!\n");
1055                 rc = -EINVAL;
1056                 goto power_error;
1057         }
1058
1059         /*
1060          * Now we need to read the HW catalog and initialize resources such as
1061          * clocks, regulators, GDSC/MMAGIC, ioremap the register ranges etc
1062          */
1063         rc = _dpu_kms_mmu_init(dpu_kms);
1064         if (rc) {
1065                 DPU_ERROR("dpu_kms_mmu_init failed: %d\n", rc);
1066                 goto power_error;
1067         }
1068
1069         rc = dpu_rm_init(&dpu_kms->rm, dpu_kms->catalog, dpu_kms->mmio);
1070         if (rc) {
1071                 DPU_ERROR("rm init failed: %d\n", rc);
1072                 goto power_error;
1073         }
1074
1075         dpu_kms->rm_init = true;
1076
1077         dpu_kms->hw_mdp = dpu_hw_mdptop_init(MDP_TOP, dpu_kms->mmio,
1078                                              dpu_kms->catalog);
1079         if (IS_ERR(dpu_kms->hw_mdp)) {
1080                 rc = PTR_ERR(dpu_kms->hw_mdp);
1081                 DPU_ERROR("failed to get hw_mdp: %d\n", rc);
1082                 dpu_kms->hw_mdp = NULL;
1083                 goto power_error;
1084         }
1085
1086         for (i = 0; i < dpu_kms->catalog->vbif_count; i++) {
1087                 u32 vbif_idx = dpu_kms->catalog->vbif[i].id;
1088
1089                 dpu_kms->hw_vbif[vbif_idx] = dpu_hw_vbif_init(vbif_idx,
1090                                 dpu_kms->vbif[vbif_idx], dpu_kms->catalog);
1091                 if (IS_ERR(dpu_kms->hw_vbif[vbif_idx])) {
1092                         rc = PTR_ERR(dpu_kms->hw_vbif[vbif_idx]);
1093                         DPU_ERROR("failed to init vbif %d: %d\n", vbif_idx, rc);
1094                         dpu_kms->hw_vbif[vbif_idx] = NULL;
1095                         goto power_error;
1096                 }
1097         }
1098
1099         rc = dpu_core_perf_init(&dpu_kms->perf, dev, dpu_kms->catalog,
1100                         msm_clk_bulk_get_clock(dpu_kms->clocks, dpu_kms->num_clocks, "core"));
1101         if (rc) {
1102                 DPU_ERROR("failed to init perf %d\n", rc);
1103                 goto perf_err;
1104         }
1105
1106         dpu_kms->hw_intr = dpu_hw_intr_init(dpu_kms->mmio, dpu_kms->catalog);
1107         if (IS_ERR_OR_NULL(dpu_kms->hw_intr)) {
1108                 rc = PTR_ERR(dpu_kms->hw_intr);
1109                 DPU_ERROR("hw_intr init failed: %d\n", rc);
1110                 dpu_kms->hw_intr = NULL;
1111                 goto hw_intr_init_err;
1112         }
1113
1114         dev->mode_config.min_width = 0;
1115         dev->mode_config.min_height = 0;
1116
1117         /*
1118          * max crtc width is equal to the max mixer width * 2 and max height is
1119          * is 4K
1120          */
1121         dev->mode_config.max_width =
1122                         dpu_kms->catalog->caps->max_mixer_width * 2;
1123         dev->mode_config.max_height = 4096;
1124
1125         dev->max_vblank_count = 0xffffffff;
1126         /* Disable vblank irqs aggressively for power-saving */
1127         dev->vblank_disable_immediate = true;
1128
1129         /*
1130          * _dpu_kms_drm_obj_init should create the DRM related objects
1131          * i.e. CRTCs, planes, encoders, connectors and so forth
1132          */
1133         rc = _dpu_kms_drm_obj_init(dpu_kms);
1134         if (rc) {
1135                 DPU_ERROR("modeset init failed: %d\n", rc);
1136                 goto drm_obj_init_err;
1137         }
1138
1139         dpu_vbif_init_memtypes(dpu_kms);
1140
1141         pm_runtime_put_sync(&dpu_kms->pdev->dev);
1142
1143         return 0;
1144
1145 drm_obj_init_err:
1146         dpu_core_perf_destroy(&dpu_kms->perf);
1147 hw_intr_init_err:
1148 perf_err:
1149 power_error:
1150         pm_runtime_put_sync(&dpu_kms->pdev->dev);
1151 error:
1152         _dpu_kms_hw_destroy(dpu_kms);
1153
1154         return rc;
1155 }
1156
1157 static int dpu_kms_init(struct drm_device *ddev)
1158 {
1159         struct msm_drm_private *priv = ddev->dev_private;
1160         struct device *dev = ddev->dev;
1161         struct platform_device *pdev = to_platform_device(dev);
1162         struct dpu_kms *dpu_kms;
1163         int irq;
1164         struct dev_pm_opp *opp;
1165         int ret = 0;
1166         unsigned long max_freq = ULONG_MAX;
1167
1168         dpu_kms = devm_kzalloc(&pdev->dev, sizeof(*dpu_kms), GFP_KERNEL);
1169         if (!dpu_kms)
1170                 return -ENOMEM;
1171
1172         ret = devm_pm_opp_set_clkname(dev, "core");
1173         if (ret)
1174                 return ret;
1175         /* OPP table is optional */
1176         ret = devm_pm_opp_of_add_table(dev);
1177         if (ret && ret != -ENODEV) {
1178                 dev_err(dev, "invalid OPP table in device tree\n");
1179                 return ret;
1180         }
1181
1182         ret = devm_clk_bulk_get_all(&pdev->dev, &dpu_kms->clocks);
1183         if (ret < 0) {
1184                 DPU_ERROR("failed to parse clocks, ret=%d\n", ret);
1185                 return ret;
1186         }
1187         dpu_kms->num_clocks = ret;
1188
1189         opp = dev_pm_opp_find_freq_floor(dev, &max_freq);
1190         if (!IS_ERR(opp))
1191                 dev_pm_opp_put(opp);
1192
1193         dev_pm_opp_set_rate(dev, max_freq);
1194
1195         ret = msm_kms_init(&dpu_kms->base, &kms_funcs);
1196         if (ret) {
1197                 DPU_ERROR("failed to init kms, ret=%d\n", ret);
1198                 return ret;
1199         }
1200         dpu_kms->dev = ddev;
1201         dpu_kms->pdev = pdev;
1202
1203         pm_runtime_enable(&pdev->dev);
1204         dpu_kms->rpm_enabled = true;
1205
1206         priv->kms = &dpu_kms->base;
1207
1208         irq = irq_of_parse_and_map(dpu_kms->pdev->dev.of_node, 0);
1209         if (!irq) {
1210                 DPU_ERROR("failed to get irq\n");
1211                 return -EINVAL;
1212         }
1213         dpu_kms->base.irq = irq;
1214
1215         return 0;
1216 }
1217
1218 static int dpu_dev_probe(struct platform_device *pdev)
1219 {
1220         return msm_drv_probe(&pdev->dev, dpu_kms_init);
1221 }
1222
1223 static int dpu_dev_remove(struct platform_device *pdev)
1224 {
1225         component_master_del(&pdev->dev, &msm_drm_ops);
1226
1227         return 0;
1228 }
1229
1230 static int __maybe_unused dpu_runtime_suspend(struct device *dev)
1231 {
1232         int i;
1233         struct platform_device *pdev = to_platform_device(dev);
1234         struct msm_drm_private *priv = platform_get_drvdata(pdev);
1235         struct dpu_kms *dpu_kms = to_dpu_kms(priv->kms);
1236
1237         /* Drop the performance state vote */
1238         dev_pm_opp_set_rate(dev, 0);
1239         clk_bulk_disable_unprepare(dpu_kms->num_clocks, dpu_kms->clocks);
1240
1241         for (i = 0; i < dpu_kms->num_paths; i++)
1242                 icc_set_bw(dpu_kms->path[i], 0, 0);
1243
1244         return 0;
1245 }
1246
1247 static int __maybe_unused dpu_runtime_resume(struct device *dev)
1248 {
1249         int rc = -1;
1250         struct platform_device *pdev = to_platform_device(dev);
1251         struct msm_drm_private *priv = platform_get_drvdata(pdev);
1252         struct dpu_kms *dpu_kms = to_dpu_kms(priv->kms);
1253         struct drm_encoder *encoder;
1254         struct drm_device *ddev;
1255
1256         ddev = dpu_kms->dev;
1257
1258         rc = clk_bulk_prepare_enable(dpu_kms->num_clocks, dpu_kms->clocks);
1259         if (rc) {
1260                 DPU_ERROR("clock enable failed rc:%d\n", rc);
1261                 return rc;
1262         }
1263
1264         dpu_vbif_init_memtypes(dpu_kms);
1265
1266         drm_for_each_encoder(encoder, ddev)
1267                 dpu_encoder_virt_runtime_resume(encoder);
1268
1269         return rc;
1270 }
1271
1272 static const struct dev_pm_ops dpu_pm_ops = {
1273         SET_RUNTIME_PM_OPS(dpu_runtime_suspend, dpu_runtime_resume, NULL)
1274         SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1275                                 pm_runtime_force_resume)
1276         .prepare = msm_pm_prepare,
1277         .complete = msm_pm_complete,
1278 };
1279
1280 static const struct of_device_id dpu_dt_match[] = {
1281         { .compatible = "qcom,msm8998-dpu", .data = &dpu_msm8998_cfg, },
1282         { .compatible = "qcom,qcm2290-dpu", .data = &dpu_qcm2290_cfg, },
1283         { .compatible = "qcom,sdm845-dpu", .data = &dpu_sdm845_cfg, },
1284         { .compatible = "qcom,sc7180-dpu", .data = &dpu_sc7180_cfg, },
1285         { .compatible = "qcom,sc7280-dpu", .data = &dpu_sc7280_cfg, },
1286         { .compatible = "qcom,sc8180x-dpu", .data = &dpu_sc8180x_cfg, },
1287         { .compatible = "qcom,sc8280xp-dpu", .data = &dpu_sc8280xp_cfg, },
1288         { .compatible = "qcom,sm6115-dpu", .data = &dpu_sm6115_cfg, },
1289         { .compatible = "qcom,sm8150-dpu", .data = &dpu_sm8150_cfg, },
1290         { .compatible = "qcom,sm8250-dpu", .data = &dpu_sm8250_cfg, },
1291         { .compatible = "qcom,sm8350-dpu", .data = &dpu_sm8350_cfg, },
1292         { .compatible = "qcom,sm8450-dpu", .data = &dpu_sm8450_cfg, },
1293         { .compatible = "qcom,sm8550-dpu", .data = &dpu_sm8550_cfg, },
1294         {}
1295 };
1296 MODULE_DEVICE_TABLE(of, dpu_dt_match);
1297
1298 static struct platform_driver dpu_driver = {
1299         .probe = dpu_dev_probe,
1300         .remove = dpu_dev_remove,
1301         .shutdown = msm_drv_shutdown,
1302         .driver = {
1303                 .name = "msm_dpu",
1304                 .of_match_table = dpu_dt_match,
1305                 .pm = &dpu_pm_ops,
1306         },
1307 };
1308
1309 void __init msm_dpu_register(void)
1310 {
1311         platform_driver_register(&dpu_driver);
1312 }
1313
1314 void __exit msm_dpu_unregister(void)
1315 {
1316         platform_driver_unregister(&dpu_driver);
1317 }