1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2013 Red Hat
6 * Copyright (c) 2014,2017, 2019 The Linux Foundation. All rights reserved.
9 #ifndef __ADRENO_GPU_H__
10 #define __ADRENO_GPU_H__
12 #include <linux/firmware.h>
13 #include <linux/iopoll.h>
17 #include "adreno_common.xml.h"
18 #include "adreno_pm4.xml.h"
20 extern bool snapshot_debugbus;
21 extern bool allow_vram_carveout;
25 ADRENO_FW_SQE = 0, /* a6xx */
27 ADRENO_FW_GMU = 1, /* a6xx */
32 #define ADRENO_QUIRK_TWO_PASS_USE_WFI BIT(0)
33 #define ADRENO_QUIRK_FAULT_DETECT_MASK BIT(1)
34 #define ADRENO_QUIRK_LMLOADKILL_DISABLE BIT(2)
45 #define ADRENO_REV(core, major, minor, patchid) \
46 ((struct adreno_rev){ core, major, minor, patchid })
48 struct adreno_gpu_funcs {
49 struct msm_gpu_funcs base;
50 int (*get_timestamp)(struct msm_gpu *gpu, uint64_t *value);
53 struct adreno_reglist {
58 extern const struct adreno_reglist a615_hwcg[], a630_hwcg[], a640_hwcg[], a650_hwcg[], a660_hwcg[];
61 struct adreno_rev rev;
64 const char *fw[ADRENO_FW_MAX];
67 struct msm_gpu *(*init)(struct drm_device *dev);
70 const struct adreno_reglist *hwcg;
71 u64 address_space_size;
74 const struct adreno_info *adreno_info(struct adreno_rev rev);
78 struct adreno_rev rev;
79 const struct adreno_info *info;
80 uint32_t gmem; /* actual gmem size */
81 uint32_t revn; /* numeric revision name */
83 const struct adreno_gpu_funcs *funcs;
85 /* interesting register offsets to dump: */
86 const unsigned int *registers;
89 * Are we loading fw from legacy path? Prior to addition
90 * of gpu firmware to linux-firmware, the fw files were
91 * placed in toplevel firmware directory, following qcom's
92 * android kernel. But linux-firmware preferred they be
93 * placed in a 'qcom' subdirectory.
95 * For backwards compatibility, we try first to load from
96 * the new path, using request_firmware_direct() to avoid
97 * any potential timeout waiting for usermode helper, then
98 * fall back to the old path (with direct load). And
99 * finally fall back to request_firmware() with the new
100 * path to allow the usermode helper.
103 FW_LOCATION_UNKNOWN = 0,
104 FW_LOCATION_NEW, /* /lib/firmware/qcom/$fwfile */
105 FW_LOCATION_LEGACY, /* /lib/firmware/$fwfile */
110 const struct firmware *fw[ADRENO_FW_MAX];
113 * Register offsets are different between some GPUs.
114 * GPU specific offsets will be exported by GPU specific
115 * code (a3xx_gpu.c) and stored in this common location.
117 const unsigned int *reg_offsets;
119 #define to_adreno_gpu(x) container_of(x, struct adreno_gpu, base)
121 struct adreno_ocmem {
127 /* platform config data (ie. from DT, or pdata) */
128 struct adreno_platform_config {
129 struct adreno_rev rev;
132 #define ADRENO_IDLE_TIMEOUT msecs_to_jiffies(1000)
134 #define spin_until(X) ({ \
135 int __ret = -ETIMEDOUT; \
136 unsigned long __t = jiffies + ADRENO_IDLE_TIMEOUT; \
142 } while (time_before(jiffies, __t)); \
146 bool adreno_cmp_rev(struct adreno_rev rev1, struct adreno_rev rev2);
148 static inline bool adreno_is_a2xx(struct adreno_gpu *gpu)
150 return (gpu->revn < 300);
153 static inline bool adreno_is_a20x(struct adreno_gpu *gpu)
155 return (gpu->revn < 210);
158 static inline bool adreno_is_a225(struct adreno_gpu *gpu)
160 return gpu->revn == 225;
163 static inline bool adreno_is_a305(struct adreno_gpu *gpu)
165 return gpu->revn == 305;
168 static inline bool adreno_is_a306(struct adreno_gpu *gpu)
170 /* yes, 307, because a305c is 306 */
171 return gpu->revn == 307;
174 static inline bool adreno_is_a320(struct adreno_gpu *gpu)
176 return gpu->revn == 320;
179 static inline bool adreno_is_a330(struct adreno_gpu *gpu)
181 return gpu->revn == 330;
184 static inline bool adreno_is_a330v2(struct adreno_gpu *gpu)
186 return adreno_is_a330(gpu) && (gpu->rev.patchid > 0);
189 static inline int adreno_is_a405(struct adreno_gpu *gpu)
191 return gpu->revn == 405;
194 static inline int adreno_is_a420(struct adreno_gpu *gpu)
196 return gpu->revn == 420;
199 static inline int adreno_is_a430(struct adreno_gpu *gpu)
201 return gpu->revn == 430;
204 static inline int adreno_is_a506(struct adreno_gpu *gpu)
206 return gpu->revn == 506;
209 static inline int adreno_is_a508(struct adreno_gpu *gpu)
211 return gpu->revn == 508;
214 static inline int adreno_is_a509(struct adreno_gpu *gpu)
216 return gpu->revn == 509;
219 static inline int adreno_is_a510(struct adreno_gpu *gpu)
221 return gpu->revn == 510;
224 static inline int adreno_is_a512(struct adreno_gpu *gpu)
226 return gpu->revn == 512;
229 static inline int adreno_is_a530(struct adreno_gpu *gpu)
231 return gpu->revn == 530;
234 static inline int adreno_is_a540(struct adreno_gpu *gpu)
236 return gpu->revn == 540;
239 static inline int adreno_is_a618(struct adreno_gpu *gpu)
241 return gpu->revn == 618;
244 static inline int adreno_is_a619(struct adreno_gpu *gpu)
246 return gpu->revn == 619;
249 static inline int adreno_is_a630(struct adreno_gpu *gpu)
251 return gpu->revn == 630;
254 static inline int adreno_is_a640_family(struct adreno_gpu *gpu)
256 return (gpu->revn == 640) || (gpu->revn == 680);
259 static inline int adreno_is_a650(struct adreno_gpu *gpu)
261 return gpu->revn == 650;
264 static inline int adreno_is_7c3(struct adreno_gpu *gpu)
266 /* The order of args is important here to handle ANY_ID correctly */
267 return adreno_cmp_rev(ADRENO_REV(6, 3, 5, ANY_ID), gpu->rev);
270 static inline int adreno_is_a660(struct adreno_gpu *gpu)
272 return gpu->revn == 660;
275 /* check for a615, a616, a618, a619 or any derivatives */
276 static inline int adreno_is_a615_family(struct adreno_gpu *gpu)
278 return gpu->revn == 615 || gpu->revn == 616 || gpu->revn == 618 || gpu->revn == 619;
281 static inline int adreno_is_a660_family(struct adreno_gpu *gpu)
283 return adreno_is_a660(gpu) || adreno_is_7c3(gpu);
286 /* check for a650, a660, or any derivatives */
287 static inline int adreno_is_a650_family(struct adreno_gpu *gpu)
289 return gpu->revn == 650 || gpu->revn == 620 || adreno_is_a660_family(gpu);
292 u64 adreno_private_address_space_size(struct msm_gpu *gpu);
293 int adreno_get_param(struct msm_gpu *gpu, struct msm_file_private *ctx,
294 uint32_t param, uint64_t *value, uint32_t *len);
295 int adreno_set_param(struct msm_gpu *gpu, struct msm_file_private *ctx,
296 uint32_t param, uint64_t value, uint32_t len);
297 const struct firmware *adreno_request_fw(struct adreno_gpu *adreno_gpu,
299 struct drm_gem_object *adreno_fw_create_bo(struct msm_gpu *gpu,
300 const struct firmware *fw, u64 *iova);
301 int adreno_hw_init(struct msm_gpu *gpu);
302 void adreno_recover(struct msm_gpu *gpu);
303 void adreno_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring, u32 reg);
304 bool adreno_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring);
305 #if defined(CONFIG_DEBUG_FS) || defined(CONFIG_DEV_COREDUMP)
306 void adreno_show(struct msm_gpu *gpu, struct msm_gpu_state *state,
307 struct drm_printer *p);
309 void adreno_dump_info(struct msm_gpu *gpu);
310 void adreno_dump(struct msm_gpu *gpu);
311 void adreno_wait_ring(struct msm_ringbuffer *ring, uint32_t ndwords);
312 struct msm_ringbuffer *adreno_active_ring(struct msm_gpu *gpu);
314 int adreno_gpu_ocmem_init(struct device *dev, struct adreno_gpu *adreno_gpu,
315 struct adreno_ocmem *ocmem);
316 void adreno_gpu_ocmem_cleanup(struct adreno_ocmem *ocmem);
318 int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
319 struct adreno_gpu *gpu, const struct adreno_gpu_funcs *funcs,
321 void adreno_gpu_cleanup(struct adreno_gpu *gpu);
322 int adreno_load_fw(struct adreno_gpu *adreno_gpu);
324 void adreno_gpu_state_destroy(struct msm_gpu_state *state);
326 int adreno_gpu_state_get(struct msm_gpu *gpu, struct msm_gpu_state *state);
327 int adreno_gpu_state_put(struct msm_gpu_state *state);
328 void adreno_show_object(struct drm_printer *p, void **ptr, int len,
332 * Common helper function to initialize the default address space for arm-smmu
335 struct msm_gem_address_space *
336 adreno_create_address_space(struct msm_gpu *gpu,
337 struct platform_device *pdev);
339 struct msm_gem_address_space *
340 adreno_iommu_create_address_space(struct msm_gpu *gpu,
341 struct platform_device *pdev,
342 unsigned long quirks);
344 int adreno_fault_handler(struct msm_gpu *gpu, unsigned long iova, int flags,
345 struct adreno_smmu_fault_info *info, const char *block,
348 int adreno_read_speedbin(struct device *dev, u32 *speedbin);
351 * For a5xx and a6xx targets load the zap shader that is used to pull the GPU
354 int adreno_zap_shader_load(struct msm_gpu *gpu, u32 pasid);
356 /* ringbuffer helpers (the parts that are adreno specific) */
359 OUT_PKT0(struct msm_ringbuffer *ring, uint16_t regindx, uint16_t cnt)
361 adreno_wait_ring(ring, cnt+1);
362 OUT_RING(ring, CP_TYPE0_PKT | ((cnt-1) << 16) | (regindx & 0x7FFF));
367 OUT_PKT2(struct msm_ringbuffer *ring)
369 adreno_wait_ring(ring, 1);
370 OUT_RING(ring, CP_TYPE2_PKT);
374 OUT_PKT3(struct msm_ringbuffer *ring, uint8_t opcode, uint16_t cnt)
376 adreno_wait_ring(ring, cnt+1);
377 OUT_RING(ring, CP_TYPE3_PKT | ((cnt-1) << 16) | ((opcode & 0xFF) << 8));
380 static inline u32 PM4_PARITY(u32 val)
382 return (0x9669 >> (0xF & (val ^
383 (val >> 4) ^ (val >> 8) ^ (val >> 12) ^
384 (val >> 16) ^ ((val) >> 20) ^ (val >> 24) ^
388 /* Maximum number of values that can be executed for one opcode */
389 #define TYPE4_MAX_PAYLOAD 127
391 #define PKT4(_reg, _cnt) \
392 (CP_TYPE4_PKT | ((_cnt) << 0) | (PM4_PARITY((_cnt)) << 7) | \
393 (((_reg) & 0x3FFFF) << 8) | (PM4_PARITY((_reg)) << 27))
396 OUT_PKT4(struct msm_ringbuffer *ring, uint16_t regindx, uint16_t cnt)
398 adreno_wait_ring(ring, cnt + 1);
399 OUT_RING(ring, PKT4(regindx, cnt));
403 OUT_PKT7(struct msm_ringbuffer *ring, uint8_t opcode, uint16_t cnt)
405 adreno_wait_ring(ring, cnt + 1);
406 OUT_RING(ring, CP_TYPE7_PKT | (cnt << 0) | (PM4_PARITY(cnt) << 15) |
407 ((opcode & 0x7F) << 16) | (PM4_PARITY(opcode) << 23));
410 struct msm_gpu *a2xx_gpu_init(struct drm_device *dev);
411 struct msm_gpu *a3xx_gpu_init(struct drm_device *dev);
412 struct msm_gpu *a4xx_gpu_init(struct drm_device *dev);
413 struct msm_gpu *a5xx_gpu_init(struct drm_device *dev);
414 struct msm_gpu *a6xx_gpu_init(struct drm_device *dev);
416 static inline uint32_t get_wptr(struct msm_ringbuffer *ring)
418 return (ring->cur - ring->start) % (MSM_GPU_RINGBUFFER_SZ >> 2);
422 * Given a register and a count, return a value to program into
423 * REG_CP_PROTECT_REG(n) - this will block both reads and writes for _len
424 * registers starting at _reg.
426 * The register base needs to be a multiple of the length. If it is not, the
427 * hardware will quietly mask off the bits for you and shift the size. For
428 * example, if you intend the protection to start at 0x07 for a length of 4
429 * (0x07-0x0A) the hardware will actually protect (0x04-0x07) which might
430 * expose registers you intended to protect!
432 #define ADRENO_PROTECT_RW(_reg, _len) \
433 ((1 << 30) | (1 << 29) | \
434 ((ilog2((_len)) & 0x1F) << 24) | (((_reg) << 2) & 0xFFFFF))
437 * Same as above, but allow reads over the range. For areas of mixed use (such
438 * as performance counters) this allows us to protect a much larger range with a
441 #define ADRENO_PROTECT_RDONLY(_reg, _len) \
443 ((ilog2((_len)) & 0x1F) << 24) | (((_reg) << 2) & 0xFFFFF))
446 #define gpu_poll_timeout(gpu, addr, val, cond, interval, timeout) \
447 readl_poll_timeout((gpu)->mmio + ((addr) << 2), val, cond, \
450 #endif /* __ADRENO_GPU_H__ */