]> Git Repo - linux.git/blob - drivers/gpu/drm/msm/adreno/a6xx_gmu.c
Merge tag 'amd-drm-next-6.5-2023-06-09' of https://gitlab.freedesktop.org/agd5f/linux...
[linux.git] / drivers / gpu / drm / msm / adreno / a6xx_gmu.c
1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2017-2019 The Linux Foundation. All rights reserved. */
3
4 #include <linux/clk.h>
5 #include <linux/interconnect.h>
6 #include <linux/pm_domain.h>
7 #include <linux/pm_opp.h>
8 #include <soc/qcom/cmd-db.h>
9 #include <drm/drm_gem.h>
10
11 #include "a6xx_gpu.h"
12 #include "a6xx_gmu.xml.h"
13 #include "msm_gem.h"
14 #include "msm_gpu_trace.h"
15 #include "msm_mmu.h"
16
17 static void a6xx_gmu_fault(struct a6xx_gmu *gmu)
18 {
19         struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
20         struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
21         struct msm_gpu *gpu = &adreno_gpu->base;
22
23         /* FIXME: add a banner here */
24         gmu->hung = true;
25
26         /* Turn off the hangcheck timer while we are resetting */
27         del_timer(&gpu->hangcheck_timer);
28
29         /* Queue the GPU handler because we need to treat this as a recovery */
30         kthread_queue_work(gpu->worker, &gpu->recover_work);
31 }
32
33 static irqreturn_t a6xx_gmu_irq(int irq, void *data)
34 {
35         struct a6xx_gmu *gmu = data;
36         u32 status;
37
38         status = gmu_read(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_STATUS);
39         gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_CLR, status);
40
41         if (status & A6XX_GMU_AO_HOST_INTERRUPT_STATUS_WDOG_BITE) {
42                 dev_err_ratelimited(gmu->dev, "GMU watchdog expired\n");
43
44                 a6xx_gmu_fault(gmu);
45         }
46
47         if (status &  A6XX_GMU_AO_HOST_INTERRUPT_STATUS_HOST_AHB_BUS_ERROR)
48                 dev_err_ratelimited(gmu->dev, "GMU AHB bus error\n");
49
50         if (status & A6XX_GMU_AO_HOST_INTERRUPT_STATUS_FENCE_ERR)
51                 dev_err_ratelimited(gmu->dev, "GMU fence error: 0x%x\n",
52                         gmu_read(gmu, REG_A6XX_GMU_AHB_FENCE_STATUS));
53
54         return IRQ_HANDLED;
55 }
56
57 static irqreturn_t a6xx_hfi_irq(int irq, void *data)
58 {
59         struct a6xx_gmu *gmu = data;
60         u32 status;
61
62         status = gmu_read(gmu, REG_A6XX_GMU_GMU2HOST_INTR_INFO);
63         gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_CLR, status);
64
65         if (status & A6XX_GMU_GMU2HOST_INTR_INFO_CM3_FAULT) {
66                 dev_err_ratelimited(gmu->dev, "GMU firmware fault\n");
67
68                 a6xx_gmu_fault(gmu);
69         }
70
71         return IRQ_HANDLED;
72 }
73
74 bool a6xx_gmu_sptprac_is_on(struct a6xx_gmu *gmu)
75 {
76         u32 val;
77
78         /* This can be called from gpu state code so make sure GMU is valid */
79         if (!gmu->initialized)
80                 return false;
81
82         val = gmu_read(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS);
83
84         return !(val &
85                 (A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SPTPRAC_GDSC_POWER_OFF |
86                 A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_SP_CLOCK_OFF));
87 }
88
89 /* Check to see if the GX rail is still powered */
90 bool a6xx_gmu_gx_is_on(struct a6xx_gmu *gmu)
91 {
92         u32 val;
93
94         /* This can be called from gpu state code so make sure GMU is valid */
95         if (!gmu->initialized)
96                 return false;
97
98         val = gmu_read(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS);
99
100         return !(val &
101                 (A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_GX_HM_GDSC_POWER_OFF |
102                 A6XX_GMU_SPTPRAC_PWR_CLK_STATUS_GX_HM_CLK_OFF));
103 }
104
105 void a6xx_gmu_set_freq(struct msm_gpu *gpu, struct dev_pm_opp *opp,
106                        bool suspended)
107 {
108         struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
109         struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
110         struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
111         u32 perf_index;
112         unsigned long gpu_freq;
113         int ret = 0;
114
115         gpu_freq = dev_pm_opp_get_freq(opp);
116
117         if (gpu_freq == gmu->freq)
118                 return;
119
120         for (perf_index = 0; perf_index < gmu->nr_gpu_freqs - 1; perf_index++)
121                 if (gpu_freq == gmu->gpu_freqs[perf_index])
122                         break;
123
124         gmu->current_perf_index = perf_index;
125         gmu->freq = gmu->gpu_freqs[perf_index];
126
127         trace_msm_gmu_freq_change(gmu->freq, perf_index);
128
129         /*
130          * This can get called from devfreq while the hardware is idle. Don't
131          * bring up the power if it isn't already active. All we're doing here
132          * is updating the frequency so that when we come back online we're at
133          * the right rate.
134          */
135         if (suspended)
136                 return;
137
138         if (!gmu->legacy) {
139                 a6xx_hfi_set_freq(gmu, perf_index);
140                 dev_pm_opp_set_opp(&gpu->pdev->dev, opp);
141                 return;
142         }
143
144         gmu_write(gmu, REG_A6XX_GMU_DCVS_ACK_OPTION, 0);
145
146         gmu_write(gmu, REG_A6XX_GMU_DCVS_PERF_SETTING,
147                         ((3 & 0xf) << 28) | perf_index);
148
149         /*
150          * Send an invalid index as a vote for the bus bandwidth and let the
151          * firmware decide on the right vote
152          */
153         gmu_write(gmu, REG_A6XX_GMU_DCVS_BW_SETTING, 0xff);
154
155         /* Set and clear the OOB for DCVS to trigger the GMU */
156         a6xx_gmu_set_oob(gmu, GMU_OOB_DCVS_SET);
157         a6xx_gmu_clear_oob(gmu, GMU_OOB_DCVS_SET);
158
159         ret = gmu_read(gmu, REG_A6XX_GMU_DCVS_RETURN);
160         if (ret)
161                 dev_err(gmu->dev, "GMU set GPU frequency error: %d\n", ret);
162
163         dev_pm_opp_set_opp(&gpu->pdev->dev, opp);
164 }
165
166 unsigned long a6xx_gmu_get_freq(struct msm_gpu *gpu)
167 {
168         struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu);
169         struct a6xx_gpu *a6xx_gpu = to_a6xx_gpu(adreno_gpu);
170         struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
171
172         return  gmu->freq;
173 }
174
175 static bool a6xx_gmu_check_idle_level(struct a6xx_gmu *gmu)
176 {
177         u32 val;
178         int local = gmu->idle_level;
179
180         /* SPTP and IFPC both report as IFPC */
181         if (gmu->idle_level == GMU_IDLE_STATE_SPTP)
182                 local = GMU_IDLE_STATE_IFPC;
183
184         val = gmu_read(gmu, REG_A6XX_GPU_GMU_CX_GMU_RPMH_POWER_STATE);
185
186         if (val == local) {
187                 if (gmu->idle_level != GMU_IDLE_STATE_IFPC ||
188                         !a6xx_gmu_gx_is_on(gmu))
189                         return true;
190         }
191
192         return false;
193 }
194
195 /* Wait for the GMU to get to its most idle state */
196 int a6xx_gmu_wait_for_idle(struct a6xx_gmu *gmu)
197 {
198         return spin_until(a6xx_gmu_check_idle_level(gmu));
199 }
200
201 static int a6xx_gmu_start(struct a6xx_gmu *gmu)
202 {
203         int ret;
204         u32 val;
205         u32 mask, reset_val;
206
207         val = gmu_read(gmu, REG_A6XX_GMU_CM3_DTCM_START + 0xff8);
208         if (val <= 0x20010004) {
209                 mask = 0xffffffff;
210                 reset_val = 0xbabeface;
211         } else {
212                 mask = 0x1ff;
213                 reset_val = 0x100;
214         }
215
216         gmu_write(gmu, REG_A6XX_GMU_CM3_SYSRESET, 1);
217
218         /* Set the log wptr index
219          * note: downstream saves the value in poweroff and restores it here
220          */
221         gmu_write(gmu, REG_A6XX_GPU_GMU_CX_GMU_PWR_COL_CP_RESP, 0);
222
223         gmu_write(gmu, REG_A6XX_GMU_CM3_SYSRESET, 0);
224
225         ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_CM3_FW_INIT_RESULT, val,
226                 (val & mask) == reset_val, 100, 10000);
227
228         if (ret)
229                 DRM_DEV_ERROR(gmu->dev, "GMU firmware initialization timed out\n");
230
231         return ret;
232 }
233
234 static int a6xx_gmu_hfi_start(struct a6xx_gmu *gmu)
235 {
236         u32 val;
237         int ret;
238
239         gmu_write(gmu, REG_A6XX_GMU_HFI_CTRL_INIT, 1);
240
241         ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_HFI_CTRL_STATUS, val,
242                 val & 1, 100, 10000);
243         if (ret)
244                 DRM_DEV_ERROR(gmu->dev, "Unable to start the HFI queues\n");
245
246         return ret;
247 }
248
249 struct a6xx_gmu_oob_bits {
250         int set, ack, set_new, ack_new, clear, clear_new;
251         const char *name;
252 };
253
254 /* These are the interrupt / ack bits for each OOB request that are set
255  * in a6xx_gmu_set_oob and a6xx_clear_oob
256  */
257 static const struct a6xx_gmu_oob_bits a6xx_gmu_oob_bits[] = {
258         [GMU_OOB_GPU_SET] = {
259                 .name = "GPU_SET",
260                 .set = 16,
261                 .ack = 24,
262                 .set_new = 30,
263                 .ack_new = 31,
264                 .clear = 24,
265                 .clear_new = 31,
266         },
267
268         [GMU_OOB_PERFCOUNTER_SET] = {
269                 .name = "PERFCOUNTER",
270                 .set = 17,
271                 .ack = 25,
272                 .set_new = 28,
273                 .ack_new = 30,
274                 .clear = 25,
275                 .clear_new = 29,
276         },
277
278         [GMU_OOB_BOOT_SLUMBER] = {
279                 .name = "BOOT_SLUMBER",
280                 .set = 22,
281                 .ack = 30,
282                 .clear = 30,
283         },
284
285         [GMU_OOB_DCVS_SET] = {
286                 .name = "GPU_DCVS",
287                 .set = 23,
288                 .ack = 31,
289                 .clear = 31,
290         },
291 };
292
293 /* Trigger a OOB (out of band) request to the GMU */
294 int a6xx_gmu_set_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state)
295 {
296         int ret;
297         u32 val;
298         int request, ack;
299
300         WARN_ON_ONCE(!mutex_is_locked(&gmu->lock));
301
302         if (state >= ARRAY_SIZE(a6xx_gmu_oob_bits))
303                 return -EINVAL;
304
305         if (gmu->legacy) {
306                 request = a6xx_gmu_oob_bits[state].set;
307                 ack = a6xx_gmu_oob_bits[state].ack;
308         } else {
309                 request = a6xx_gmu_oob_bits[state].set_new;
310                 ack = a6xx_gmu_oob_bits[state].ack_new;
311                 if (!request || !ack) {
312                         DRM_DEV_ERROR(gmu->dev,
313                                       "Invalid non-legacy GMU request %s\n",
314                                       a6xx_gmu_oob_bits[state].name);
315                         return -EINVAL;
316                 }
317         }
318
319         /* Trigger the equested OOB operation */
320         gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, 1 << request);
321
322         /* Wait for the acknowledge interrupt */
323         ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_GMU2HOST_INTR_INFO, val,
324                 val & (1 << ack), 100, 10000);
325
326         if (ret)
327                 DRM_DEV_ERROR(gmu->dev,
328                         "Timeout waiting for GMU OOB set %s: 0x%x\n",
329                                 a6xx_gmu_oob_bits[state].name,
330                                 gmu_read(gmu, REG_A6XX_GMU_GMU2HOST_INTR_INFO));
331
332         /* Clear the acknowledge interrupt */
333         gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_CLR, 1 << ack);
334
335         return ret;
336 }
337
338 /* Clear a pending OOB state in the GMU */
339 void a6xx_gmu_clear_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state)
340 {
341         int bit;
342
343         WARN_ON_ONCE(!mutex_is_locked(&gmu->lock));
344
345         if (state >= ARRAY_SIZE(a6xx_gmu_oob_bits))
346                 return;
347
348         if (gmu->legacy)
349                 bit = a6xx_gmu_oob_bits[state].clear;
350         else
351                 bit = a6xx_gmu_oob_bits[state].clear_new;
352
353         gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, 1 << bit);
354 }
355
356 /* Enable CPU control of SPTP power power collapse */
357 static int a6xx_sptprac_enable(struct a6xx_gmu *gmu)
358 {
359         int ret;
360         u32 val;
361
362         if (!gmu->legacy)
363                 return 0;
364
365         gmu_write(gmu, REG_A6XX_GMU_GX_SPTPRAC_POWER_CONTROL, 0x778000);
366
367         ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS, val,
368                 (val & 0x38) == 0x28, 1, 100);
369
370         if (ret) {
371                 DRM_DEV_ERROR(gmu->dev, "Unable to power on SPTPRAC: 0x%x\n",
372                         gmu_read(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS));
373         }
374
375         return 0;
376 }
377
378 /* Disable CPU control of SPTP power power collapse */
379 static void a6xx_sptprac_disable(struct a6xx_gmu *gmu)
380 {
381         u32 val;
382         int ret;
383
384         if (!gmu->legacy)
385                 return;
386
387         /* Make sure retention is on */
388         gmu_rmw(gmu, REG_A6XX_GPU_CC_GX_GDSCR, 0, (1 << 11));
389
390         gmu_write(gmu, REG_A6XX_GMU_GX_SPTPRAC_POWER_CONTROL, 0x778001);
391
392         ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS, val,
393                 (val & 0x04), 100, 10000);
394
395         if (ret)
396                 DRM_DEV_ERROR(gmu->dev, "failed to power off SPTPRAC: 0x%x\n",
397                         gmu_read(gmu, REG_A6XX_GMU_SPTPRAC_PWR_CLK_STATUS));
398 }
399
400 /* Let the GMU know we are starting a boot sequence */
401 static int a6xx_gmu_gfx_rail_on(struct a6xx_gmu *gmu)
402 {
403         u32 vote;
404
405         /* Let the GMU know we are getting ready for boot */
406         gmu_write(gmu, REG_A6XX_GMU_BOOT_SLUMBER_OPTION, 0);
407
408         /* Choose the "default" power level as the highest available */
409         vote = gmu->gx_arc_votes[gmu->nr_gpu_freqs - 1];
410
411         gmu_write(gmu, REG_A6XX_GMU_GX_VOTE_IDX, vote & 0xff);
412         gmu_write(gmu, REG_A6XX_GMU_MX_VOTE_IDX, (vote >> 8) & 0xff);
413
414         /* Let the GMU know the boot sequence has started */
415         return a6xx_gmu_set_oob(gmu, GMU_OOB_BOOT_SLUMBER);
416 }
417
418 /* Let the GMU know that we are about to go into slumber */
419 static int a6xx_gmu_notify_slumber(struct a6xx_gmu *gmu)
420 {
421         int ret;
422
423         /* Disable the power counter so the GMU isn't busy */
424         gmu_write(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_ENABLE, 0);
425
426         /* Disable SPTP_PC if the CPU is responsible for it */
427         if (gmu->idle_level < GMU_IDLE_STATE_SPTP)
428                 a6xx_sptprac_disable(gmu);
429
430         if (!gmu->legacy) {
431                 ret = a6xx_hfi_send_prep_slumber(gmu);
432                 goto out;
433         }
434
435         /* Tell the GMU to get ready to slumber */
436         gmu_write(gmu, REG_A6XX_GMU_BOOT_SLUMBER_OPTION, 1);
437
438         ret = a6xx_gmu_set_oob(gmu, GMU_OOB_BOOT_SLUMBER);
439         a6xx_gmu_clear_oob(gmu, GMU_OOB_BOOT_SLUMBER);
440
441         if (!ret) {
442                 /* Check to see if the GMU really did slumber */
443                 if (gmu_read(gmu, REG_A6XX_GPU_GMU_CX_GMU_RPMH_POWER_STATE)
444                         != 0x0f) {
445                         DRM_DEV_ERROR(gmu->dev, "The GMU did not go into slumber\n");
446                         ret = -ETIMEDOUT;
447                 }
448         }
449
450 out:
451         /* Put fence into allow mode */
452         gmu_write(gmu, REG_A6XX_GMU_AO_AHB_FENCE_CTRL, 0);
453         return ret;
454 }
455
456 static int a6xx_rpmh_start(struct a6xx_gmu *gmu)
457 {
458         int ret;
459         u32 val;
460
461         gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 1 << 1);
462         /* Wait for the register to finish posting */
463         wmb();
464
465         ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_RSCC_CONTROL_ACK, val,
466                 val & (1 << 1), 100, 10000);
467         if (ret) {
468                 DRM_DEV_ERROR(gmu->dev, "Unable to power on the GPU RSC\n");
469                 return ret;
470         }
471
472         ret = gmu_poll_timeout_rscc(gmu, REG_A6XX_RSCC_SEQ_BUSY_DRV0, val,
473                 !val, 100, 10000);
474
475         if (ret) {
476                 DRM_DEV_ERROR(gmu->dev, "GPU RSC sequence stuck while waking up the GPU\n");
477                 return ret;
478         }
479
480         gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 0);
481
482         /* Set up CX GMU counter 0 to count busy ticks */
483         gmu_write(gmu, REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_MASK, 0xff000000);
484         gmu_rmw(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_0, 0xff, 0x20);
485
486         /* Enable the power counter */
487         gmu_write(gmu, REG_A6XX_GMU_CX_GMU_POWER_COUNTER_ENABLE, 1);
488         return 0;
489 }
490
491 static void a6xx_rpmh_stop(struct a6xx_gmu *gmu)
492 {
493         int ret;
494         u32 val;
495
496         gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 1);
497
498         ret = gmu_poll_timeout_rscc(gmu, REG_A6XX_GPU_RSCC_RSC_STATUS0_DRV0,
499                 val, val & (1 << 16), 100, 10000);
500         if (ret)
501                 DRM_DEV_ERROR(gmu->dev, "Unable to power off the GPU RSC\n");
502
503         gmu_write(gmu, REG_A6XX_GMU_RSCC_CONTROL_REQ, 0);
504 }
505
506 static inline void pdc_write(void __iomem *ptr, u32 offset, u32 value)
507 {
508         msm_writel(value, ptr + (offset << 2));
509 }
510
511 static void __iomem *a6xx_gmu_get_mmio(struct platform_device *pdev,
512                 const char *name);
513
514 static void a6xx_gmu_rpmh_init(struct a6xx_gmu *gmu)
515 {
516         struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
517         struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
518         struct platform_device *pdev = to_platform_device(gmu->dev);
519         void __iomem *pdcptr = a6xx_gmu_get_mmio(pdev, "gmu_pdc");
520         void __iomem *seqptr = NULL;
521         uint32_t pdc_address_offset;
522         bool pdc_in_aop = false;
523
524         if (IS_ERR(pdcptr))
525                 goto err;
526
527         if (adreno_is_a650(adreno_gpu) || adreno_is_a660_family(adreno_gpu))
528                 pdc_in_aop = true;
529         else if (adreno_is_a618(adreno_gpu) || adreno_is_a640_family(adreno_gpu))
530                 pdc_address_offset = 0x30090;
531         else if (adreno_is_a619(adreno_gpu))
532                 pdc_address_offset = 0x300a0;
533         else
534                 pdc_address_offset = 0x30080;
535
536         if (!pdc_in_aop) {
537                 seqptr = a6xx_gmu_get_mmio(pdev, "gmu_pdc_seq");
538                 if (IS_ERR(seqptr))
539                         goto err;
540         }
541
542         /* Disable SDE clock gating */
543         gmu_write_rscc(gmu, REG_A6XX_GPU_RSCC_RSC_STATUS0_DRV0, BIT(24));
544
545         /* Setup RSC PDC handshake for sleep and wakeup */
546         gmu_write_rscc(gmu, REG_A6XX_RSCC_PDC_SLAVE_ID_DRV0, 1);
547         gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_DATA, 0);
548         gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR, 0);
549         gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_DATA + 2, 0);
550         gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR + 2, 0);
551         gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_DATA + 4, 0x80000000);
552         gmu_write_rscc(gmu, REG_A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR + 4, 0);
553         gmu_write_rscc(gmu, REG_A6XX_RSCC_OVERRIDE_START_ADDR, 0);
554         gmu_write_rscc(gmu, REG_A6XX_RSCC_PDC_SEQ_START_ADDR, 0x4520);
555         gmu_write_rscc(gmu, REG_A6XX_RSCC_PDC_MATCH_VALUE_LO, 0x4510);
556         gmu_write_rscc(gmu, REG_A6XX_RSCC_PDC_MATCH_VALUE_HI, 0x4514);
557
558         /* Load RSC sequencer uCode for sleep and wakeup */
559         if (adreno_is_a650_family(adreno_gpu)) {
560                 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0, 0xeaaae5a0);
561                 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 1, 0xe1a1ebab);
562                 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 2, 0xa2e0a581);
563                 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 3, 0xecac82e2);
564                 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 4, 0x0020edad);
565         } else {
566                 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0, 0xa7a506a0);
567                 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 1, 0xa1e6a6e7);
568                 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 2, 0xa2e081e1);
569                 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 3, 0xe9a982e2);
570                 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 4, 0x0020e8a8);
571         }
572
573         if (pdc_in_aop)
574                 goto setup_pdc;
575
576         /* Load PDC sequencer uCode for power up and power down sequence */
577         pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0, 0xfebea1e1);
578         pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 1, 0xa5a4a3a2);
579         pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 2, 0x8382a6e0);
580         pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 3, 0xbce3e284);
581         pdc_write(seqptr, REG_A6XX_PDC_GPU_SEQ_MEM_0 + 4, 0x002081fc);
582
583         /* Set TCS commands used by PDC sequence for low power modes */
584         pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD_ENABLE_BANK, 7);
585         pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD_WAIT_FOR_CMPL_BANK, 0);
586         pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CONTROL, 0);
587         pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID, 0x10108);
588         pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR, 0x30010);
589         pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_DATA, 1);
590         pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID + 4, 0x10108);
591         pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR + 4, 0x30000);
592         pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_DATA + 4, 0x0);
593
594         pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_MSGID + 8, 0x10108);
595         pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_ADDR + 8, pdc_address_offset);
596         pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS1_CMD0_DATA + 8, 0x0);
597
598         pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD_ENABLE_BANK, 7);
599         pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD_WAIT_FOR_CMPL_BANK, 0);
600         pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CONTROL, 0);
601         pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID, 0x10108);
602         pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR, 0x30010);
603         pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA, 2);
604
605         pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID + 4, 0x10108);
606         pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR + 4, 0x30000);
607         if (adreno_is_a618(adreno_gpu) || adreno_is_a619(adreno_gpu) ||
608                         adreno_is_a650_family(adreno_gpu))
609                 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 4, 0x2);
610         else
611                 pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 4, 0x3);
612         pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_MSGID + 8, 0x10108);
613         pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_ADDR + 8, pdc_address_offset);
614         pdc_write(pdcptr, REG_A6XX_PDC_GPU_TCS3_CMD0_DATA + 8, 0x3);
615
616         /* Setup GPU PDC */
617 setup_pdc:
618         pdc_write(pdcptr, REG_A6XX_PDC_GPU_SEQ_START_ADDR, 0);
619         pdc_write(pdcptr, REG_A6XX_PDC_GPU_ENABLE_PDC, 0x80000001);
620
621         /* ensure no writes happen before the uCode is fully written */
622         wmb();
623
624         a6xx_rpmh_stop(gmu);
625
626 err:
627         if (!IS_ERR_OR_NULL(pdcptr))
628                 iounmap(pdcptr);
629         if (!IS_ERR_OR_NULL(seqptr))
630                 iounmap(seqptr);
631 }
632
633 /*
634  * The lowest 16 bits of this value are the number of XO clock cycles for main
635  * hysteresis which is set at 0x1680 cycles (300 us).  The higher 16 bits are
636  * for the shorter hysteresis that happens after main - this is 0xa (.5 us)
637  */
638
639 #define GMU_PWR_COL_HYST 0x000a1680
640
641 /* Set up the idle state for the GMU */
642 static void a6xx_gmu_power_config(struct a6xx_gmu *gmu)
643 {
644         /* Disable GMU WB/RB buffer */
645         gmu_write(gmu, REG_A6XX_GMU_SYS_BUS_CONFIG, 0x1);
646         gmu_write(gmu, REG_A6XX_GMU_ICACHE_CONFIG, 0x1);
647         gmu_write(gmu, REG_A6XX_GMU_DCACHE_CONFIG, 0x1);
648
649         gmu_write(gmu, REG_A6XX_GMU_PWR_COL_INTER_FRAME_CTRL, 0x9c40400);
650
651         switch (gmu->idle_level) {
652         case GMU_IDLE_STATE_IFPC:
653                 gmu_write(gmu, REG_A6XX_GMU_PWR_COL_INTER_FRAME_HYST,
654                         GMU_PWR_COL_HYST);
655                 gmu_rmw(gmu, REG_A6XX_GMU_PWR_COL_INTER_FRAME_CTRL, 0,
656                         A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_IFPC_ENABLE |
657                         A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_HM_POWER_COLLAPSE_ENABLE);
658                 fallthrough;
659         case GMU_IDLE_STATE_SPTP:
660                 gmu_write(gmu, REG_A6XX_GMU_PWR_COL_SPTPRAC_HYST,
661                         GMU_PWR_COL_HYST);
662                 gmu_rmw(gmu, REG_A6XX_GMU_PWR_COL_INTER_FRAME_CTRL, 0,
663                         A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_IFPC_ENABLE |
664                         A6XX_GMU_PWR_COL_INTER_FRAME_CTRL_SPTPRAC_POWER_CONTROL_ENABLE);
665         }
666
667         /* Enable RPMh GPU client */
668         gmu_rmw(gmu, REG_A6XX_GMU_RPMH_CTRL, 0,
669                 A6XX_GMU_RPMH_CTRL_RPMH_INTERFACE_ENABLE |
670                 A6XX_GMU_RPMH_CTRL_LLC_VOTE_ENABLE |
671                 A6XX_GMU_RPMH_CTRL_DDR_VOTE_ENABLE |
672                 A6XX_GMU_RPMH_CTRL_MX_VOTE_ENABLE |
673                 A6XX_GMU_RPMH_CTRL_CX_VOTE_ENABLE |
674                 A6XX_GMU_RPMH_CTRL_GFX_VOTE_ENABLE);
675 }
676
677 struct block_header {
678         u32 addr;
679         u32 size;
680         u32 type;
681         u32 value;
682         u32 data[];
683 };
684
685 /* this should be a general kernel helper */
686 static int in_range(u32 addr, u32 start, u32 size)
687 {
688         return addr >= start && addr < start + size;
689 }
690
691 static bool fw_block_mem(struct a6xx_gmu_bo *bo, const struct block_header *blk)
692 {
693         if (!in_range(blk->addr, bo->iova, bo->size))
694                 return false;
695
696         memcpy(bo->virt + blk->addr - bo->iova, blk->data, blk->size);
697         return true;
698 }
699
700 static int a6xx_gmu_fw_load(struct a6xx_gmu *gmu)
701 {
702         struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
703         struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
704         const struct firmware *fw_image = adreno_gpu->fw[ADRENO_FW_GMU];
705         const struct block_header *blk;
706         u32 reg_offset;
707
708         u32 itcm_base = 0x00000000;
709         u32 dtcm_base = 0x00040000;
710
711         if (adreno_is_a650_family(adreno_gpu))
712                 dtcm_base = 0x10004000;
713
714         if (gmu->legacy) {
715                 /* Sanity check the size of the firmware that was loaded */
716                 if (fw_image->size > 0x8000) {
717                         DRM_DEV_ERROR(gmu->dev,
718                                 "GMU firmware is bigger than the available region\n");
719                         return -EINVAL;
720                 }
721
722                 gmu_write_bulk(gmu, REG_A6XX_GMU_CM3_ITCM_START,
723                                (u32*) fw_image->data, fw_image->size);
724                 return 0;
725         }
726
727
728         for (blk = (const struct block_header *) fw_image->data;
729              (const u8*) blk < fw_image->data + fw_image->size;
730              blk = (const struct block_header *) &blk->data[blk->size >> 2]) {
731                 if (blk->size == 0)
732                         continue;
733
734                 if (in_range(blk->addr, itcm_base, SZ_16K)) {
735                         reg_offset = (blk->addr - itcm_base) >> 2;
736                         gmu_write_bulk(gmu,
737                                 REG_A6XX_GMU_CM3_ITCM_START + reg_offset,
738                                 blk->data, blk->size);
739                 } else if (in_range(blk->addr, dtcm_base, SZ_16K)) {
740                         reg_offset = (blk->addr - dtcm_base) >> 2;
741                         gmu_write_bulk(gmu,
742                                 REG_A6XX_GMU_CM3_DTCM_START + reg_offset,
743                                 blk->data, blk->size);
744                 } else if (!fw_block_mem(&gmu->icache, blk) &&
745                            !fw_block_mem(&gmu->dcache, blk) &&
746                            !fw_block_mem(&gmu->dummy, blk)) {
747                         DRM_DEV_ERROR(gmu->dev,
748                                 "failed to match fw block (addr=%.8x size=%d data[0]=%.8x)\n",
749                                 blk->addr, blk->size, blk->data[0]);
750                 }
751         }
752
753         return 0;
754 }
755
756 static int a6xx_gmu_fw_start(struct a6xx_gmu *gmu, unsigned int state)
757 {
758         struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
759         struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
760         int ret;
761         u32 chipid;
762
763         if (adreno_is_a650_family(adreno_gpu)) {
764                 gmu_write(gmu, REG_A6XX_GPU_GMU_CX_GMU_CX_FALNEXT_INTF, 1);
765                 gmu_write(gmu, REG_A6XX_GPU_GMU_CX_GMU_CX_FAL_INTF, 1);
766         }
767
768         if (state == GMU_WARM_BOOT) {
769                 ret = a6xx_rpmh_start(gmu);
770                 if (ret)
771                         return ret;
772         } else {
773                 if (WARN(!adreno_gpu->fw[ADRENO_FW_GMU],
774                         "GMU firmware is not loaded\n"))
775                         return -ENOENT;
776
777                 /* Turn on register retention */
778                 gmu_write(gmu, REG_A6XX_GMU_GENERAL_7, 1);
779
780                 ret = a6xx_rpmh_start(gmu);
781                 if (ret)
782                         return ret;
783
784                 ret = a6xx_gmu_fw_load(gmu);
785                 if (ret)
786                         return ret;
787         }
788
789         gmu_write(gmu, REG_A6XX_GMU_CM3_FW_INIT_RESULT, 0);
790         gmu_write(gmu, REG_A6XX_GMU_CM3_BOOT_CONFIG, 0x02);
791
792         /* Write the iova of the HFI table */
793         gmu_write(gmu, REG_A6XX_GMU_HFI_QTBL_ADDR, gmu->hfi.iova);
794         gmu_write(gmu, REG_A6XX_GMU_HFI_QTBL_INFO, 1);
795
796         gmu_write(gmu, REG_A6XX_GMU_AHB_FENCE_RANGE_0,
797                 (1 << 31) | (0xa << 18) | (0xa0));
798
799         chipid = adreno_gpu->rev.core << 24;
800         chipid |= adreno_gpu->rev.major << 16;
801         chipid |= adreno_gpu->rev.minor << 12;
802         chipid |= adreno_gpu->rev.patchid << 8;
803
804         gmu_write(gmu, REG_A6XX_GMU_HFI_SFR_ADDR, chipid);
805
806         gmu_write(gmu, REG_A6XX_GPU_GMU_CX_GMU_PWR_COL_CP_MSG,
807                   gmu->log.iova | (gmu->log.size / SZ_4K - 1));
808
809         /* Set up the lowest idle level on the GMU */
810         a6xx_gmu_power_config(gmu);
811
812         ret = a6xx_gmu_start(gmu);
813         if (ret)
814                 return ret;
815
816         if (gmu->legacy) {
817                 ret = a6xx_gmu_gfx_rail_on(gmu);
818                 if (ret)
819                         return ret;
820         }
821
822         /* Enable SPTP_PC if the CPU is responsible for it */
823         if (gmu->idle_level < GMU_IDLE_STATE_SPTP) {
824                 ret = a6xx_sptprac_enable(gmu);
825                 if (ret)
826                         return ret;
827         }
828
829         ret = a6xx_gmu_hfi_start(gmu);
830         if (ret)
831                 return ret;
832
833         /* FIXME: Do we need this wmb() here? */
834         wmb();
835
836         return 0;
837 }
838
839 #define A6XX_HFI_IRQ_MASK \
840         (A6XX_GMU_GMU2HOST_INTR_INFO_CM3_FAULT)
841
842 #define A6XX_GMU_IRQ_MASK \
843         (A6XX_GMU_AO_HOST_INTERRUPT_STATUS_WDOG_BITE | \
844          A6XX_GMU_AO_HOST_INTERRUPT_STATUS_HOST_AHB_BUS_ERROR | \
845          A6XX_GMU_AO_HOST_INTERRUPT_STATUS_FENCE_ERR)
846
847 static void a6xx_gmu_irq_disable(struct a6xx_gmu *gmu)
848 {
849         disable_irq(gmu->gmu_irq);
850         disable_irq(gmu->hfi_irq);
851
852         gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_MASK, ~0);
853         gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_MASK, ~0);
854 }
855
856 static void a6xx_gmu_rpmh_off(struct a6xx_gmu *gmu)
857 {
858         u32 val;
859
860         /* Make sure there are no outstanding RPMh votes */
861         gmu_poll_timeout_rscc(gmu, REG_A6XX_RSCC_TCS0_DRV0_STATUS, val,
862                 (val & 1), 100, 10000);
863         gmu_poll_timeout_rscc(gmu, REG_A6XX_RSCC_TCS1_DRV0_STATUS, val,
864                 (val & 1), 100, 10000);
865         gmu_poll_timeout_rscc(gmu, REG_A6XX_RSCC_TCS2_DRV0_STATUS, val,
866                 (val & 1), 100, 10000);
867         gmu_poll_timeout_rscc(gmu, REG_A6XX_RSCC_TCS3_DRV0_STATUS, val,
868                 (val & 1), 100, 1000);
869 }
870
871 #define GBIF_CLIENT_HALT_MASK             BIT(0)
872 #define GBIF_ARB_HALT_MASK                BIT(1)
873
874 static void a6xx_bus_clear_pending_transactions(struct adreno_gpu *adreno_gpu,
875                 bool gx_off)
876 {
877         struct msm_gpu *gpu = &adreno_gpu->base;
878
879         if (!a6xx_has_gbif(adreno_gpu)) {
880                 gpu_write(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL0, 0xf);
881                 spin_until((gpu_read(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL1) &
882                                                                 0xf) == 0xf);
883                 gpu_write(gpu, REG_A6XX_VBIF_XIN_HALT_CTRL0, 0);
884
885                 return;
886         }
887
888         if (gx_off) {
889                 /* Halt the gx side of GBIF */
890                 gpu_write(gpu, REG_A6XX_RBBM_GBIF_HALT, 1);
891                 spin_until(gpu_read(gpu, REG_A6XX_RBBM_GBIF_HALT_ACK) & 1);
892         }
893
894         /* Halt new client requests on GBIF */
895         gpu_write(gpu, REG_A6XX_GBIF_HALT, GBIF_CLIENT_HALT_MASK);
896         spin_until((gpu_read(gpu, REG_A6XX_GBIF_HALT_ACK) &
897                         (GBIF_CLIENT_HALT_MASK)) == GBIF_CLIENT_HALT_MASK);
898
899         /* Halt all AXI requests on GBIF */
900         gpu_write(gpu, REG_A6XX_GBIF_HALT, GBIF_ARB_HALT_MASK);
901         spin_until((gpu_read(gpu,  REG_A6XX_GBIF_HALT_ACK) &
902                         (GBIF_ARB_HALT_MASK)) == GBIF_ARB_HALT_MASK);
903
904         /* The GBIF halt needs to be explicitly cleared */
905         gpu_write(gpu, REG_A6XX_GBIF_HALT, 0x0);
906 }
907
908 /* Force the GMU off in case it isn't responsive */
909 static void a6xx_gmu_force_off(struct a6xx_gmu *gmu)
910 {
911         struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
912         struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
913         struct msm_gpu *gpu = &adreno_gpu->base;
914
915         /* Flush all the queues */
916         a6xx_hfi_stop(gmu);
917
918         /* Stop the interrupts */
919         a6xx_gmu_irq_disable(gmu);
920
921         /* Force off SPTP in case the GMU is managing it */
922         a6xx_sptprac_disable(gmu);
923
924         /* Make sure there are no outstanding RPMh votes */
925         a6xx_gmu_rpmh_off(gmu);
926
927         /* Halt the gmu cm3 core */
928         gmu_write(gmu, REG_A6XX_GMU_CM3_SYSRESET, 1);
929
930         a6xx_bus_clear_pending_transactions(adreno_gpu, true);
931
932         /* Reset GPU core blocks */
933         gpu_write(gpu, REG_A6XX_RBBM_SW_RESET_CMD, 1);
934         udelay(100);
935 }
936
937 static void a6xx_gmu_set_initial_freq(struct msm_gpu *gpu, struct a6xx_gmu *gmu)
938 {
939         struct dev_pm_opp *gpu_opp;
940         unsigned long gpu_freq = gmu->gpu_freqs[gmu->current_perf_index];
941
942         gpu_opp = dev_pm_opp_find_freq_exact(&gpu->pdev->dev, gpu_freq, true);
943         if (IS_ERR(gpu_opp))
944                 return;
945
946         gmu->freq = 0; /* so a6xx_gmu_set_freq() doesn't exit early */
947         a6xx_gmu_set_freq(gpu, gpu_opp, false);
948         dev_pm_opp_put(gpu_opp);
949 }
950
951 static void a6xx_gmu_set_initial_bw(struct msm_gpu *gpu, struct a6xx_gmu *gmu)
952 {
953         struct dev_pm_opp *gpu_opp;
954         unsigned long gpu_freq = gmu->gpu_freqs[gmu->current_perf_index];
955
956         gpu_opp = dev_pm_opp_find_freq_exact(&gpu->pdev->dev, gpu_freq, true);
957         if (IS_ERR(gpu_opp))
958                 return;
959
960         dev_pm_opp_set_opp(&gpu->pdev->dev, gpu_opp);
961         dev_pm_opp_put(gpu_opp);
962 }
963
964 int a6xx_gmu_resume(struct a6xx_gpu *a6xx_gpu)
965 {
966         struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
967         struct msm_gpu *gpu = &adreno_gpu->base;
968         struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
969         int status, ret;
970
971         if (WARN(!gmu->initialized, "The GMU is not set up yet\n"))
972                 return -EINVAL;
973
974         gmu->hung = false;
975
976         /* Turn on the resources */
977         pm_runtime_get_sync(gmu->dev);
978
979         /*
980          * "enable" the GX power domain which won't actually do anything but it
981          * will make sure that the refcounting is correct in case we need to
982          * bring down the GX after a GMU failure
983          */
984         if (!IS_ERR_OR_NULL(gmu->gxpd))
985                 pm_runtime_get_sync(gmu->gxpd);
986
987         /* Use a known rate to bring up the GMU */
988         clk_set_rate(gmu->core_clk, 200000000);
989         clk_set_rate(gmu->hub_clk, 150000000);
990         ret = clk_bulk_prepare_enable(gmu->nr_clocks, gmu->clocks);
991         if (ret) {
992                 pm_runtime_put(gmu->gxpd);
993                 pm_runtime_put(gmu->dev);
994                 return ret;
995         }
996
997         /* Set the bus quota to a reasonable value for boot */
998         a6xx_gmu_set_initial_bw(gpu, gmu);
999
1000         /* Enable the GMU interrupt */
1001         gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_CLR, ~0);
1002         gmu_write(gmu, REG_A6XX_GMU_AO_HOST_INTERRUPT_MASK, ~A6XX_GMU_IRQ_MASK);
1003         enable_irq(gmu->gmu_irq);
1004
1005         /* Check to see if we are doing a cold or warm boot */
1006         status = gmu_read(gmu, REG_A6XX_GMU_GENERAL_7) == 1 ?
1007                 GMU_WARM_BOOT : GMU_COLD_BOOT;
1008
1009         /*
1010          * Warm boot path does not work on newer GPUs
1011          * Presumably this is because icache/dcache regions must be restored
1012          */
1013         if (!gmu->legacy)
1014                 status = GMU_COLD_BOOT;
1015
1016         ret = a6xx_gmu_fw_start(gmu, status);
1017         if (ret)
1018                 goto out;
1019
1020         ret = a6xx_hfi_start(gmu, status);
1021         if (ret)
1022                 goto out;
1023
1024         /*
1025          * Turn on the GMU firmware fault interrupt after we know the boot
1026          * sequence is successful
1027          */
1028         gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_CLR, ~0);
1029         gmu_write(gmu, REG_A6XX_GMU_GMU2HOST_INTR_MASK, ~A6XX_HFI_IRQ_MASK);
1030         enable_irq(gmu->hfi_irq);
1031
1032         /* Set the GPU to the current freq */
1033         a6xx_gmu_set_initial_freq(gpu, gmu);
1034
1035 out:
1036         /* On failure, shut down the GMU to leave it in a good state */
1037         if (ret) {
1038                 disable_irq(gmu->gmu_irq);
1039                 a6xx_rpmh_stop(gmu);
1040                 pm_runtime_put(gmu->gxpd);
1041                 pm_runtime_put(gmu->dev);
1042         }
1043
1044         return ret;
1045 }
1046
1047 bool a6xx_gmu_isidle(struct a6xx_gmu *gmu)
1048 {
1049         u32 reg;
1050
1051         if (!gmu->initialized)
1052                 return true;
1053
1054         reg = gmu_read(gmu, REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS);
1055
1056         if (reg &  A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS_GPUBUSYIGNAHB)
1057                 return false;
1058
1059         return true;
1060 }
1061
1062 /* Gracefully try to shut down the GMU and by extension the GPU */
1063 static void a6xx_gmu_shutdown(struct a6xx_gmu *gmu)
1064 {
1065         struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
1066         struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
1067         u32 val;
1068
1069         /*
1070          * The GMU may still be in slumber unless the GPU started so check and
1071          * skip putting it back into slumber if so
1072          */
1073         val = gmu_read(gmu, REG_A6XX_GPU_GMU_CX_GMU_RPMH_POWER_STATE);
1074
1075         if (val != 0xf) {
1076                 int ret = a6xx_gmu_wait_for_idle(gmu);
1077
1078                 /* If the GMU isn't responding assume it is hung */
1079                 if (ret) {
1080                         a6xx_gmu_force_off(gmu);
1081                         return;
1082                 }
1083
1084                 a6xx_bus_clear_pending_transactions(adreno_gpu, a6xx_gpu->hung);
1085
1086                 /* tell the GMU we want to slumber */
1087                 ret = a6xx_gmu_notify_slumber(gmu);
1088                 if (ret) {
1089                         a6xx_gmu_force_off(gmu);
1090                         return;
1091                 }
1092
1093                 ret = gmu_poll_timeout(gmu,
1094                         REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS, val,
1095                         !(val & A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS_GPUBUSYIGNAHB),
1096                         100, 10000);
1097
1098                 /*
1099                  * Let the user know we failed to slumber but don't worry too
1100                  * much because we are powering down anyway
1101                  */
1102
1103                 if (ret)
1104                         DRM_DEV_ERROR(gmu->dev,
1105                                 "Unable to slumber GMU: status = 0%x/0%x\n",
1106                                 gmu_read(gmu,
1107                                         REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS),
1108                                 gmu_read(gmu,
1109                                         REG_A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS2));
1110         }
1111
1112         /* Turn off HFI */
1113         a6xx_hfi_stop(gmu);
1114
1115         /* Stop the interrupts and mask the hardware */
1116         a6xx_gmu_irq_disable(gmu);
1117
1118         /* Tell RPMh to power off the GPU */
1119         a6xx_rpmh_stop(gmu);
1120 }
1121
1122
1123 int a6xx_gmu_stop(struct a6xx_gpu *a6xx_gpu)
1124 {
1125         struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
1126         struct msm_gpu *gpu = &a6xx_gpu->base.base;
1127
1128         if (!pm_runtime_active(gmu->dev))
1129                 return 0;
1130
1131         /*
1132          * Force the GMU off if we detected a hang, otherwise try to shut it
1133          * down gracefully
1134          */
1135         if (gmu->hung)
1136                 a6xx_gmu_force_off(gmu);
1137         else
1138                 a6xx_gmu_shutdown(gmu);
1139
1140         /* Remove the bus vote */
1141         dev_pm_opp_set_opp(&gpu->pdev->dev, NULL);
1142
1143         /*
1144          * Make sure the GX domain is off before turning off the GMU (CX)
1145          * domain. Usually the GMU does this but only if the shutdown sequence
1146          * was successful
1147          */
1148         if (!IS_ERR_OR_NULL(gmu->gxpd))
1149                 pm_runtime_put_sync(gmu->gxpd);
1150
1151         clk_bulk_disable_unprepare(gmu->nr_clocks, gmu->clocks);
1152
1153         pm_runtime_put_sync(gmu->dev);
1154
1155         return 0;
1156 }
1157
1158 static void a6xx_gmu_memory_free(struct a6xx_gmu *gmu)
1159 {
1160         msm_gem_kernel_put(gmu->hfi.obj, gmu->aspace);
1161         msm_gem_kernel_put(gmu->debug.obj, gmu->aspace);
1162         msm_gem_kernel_put(gmu->icache.obj, gmu->aspace);
1163         msm_gem_kernel_put(gmu->dcache.obj, gmu->aspace);
1164         msm_gem_kernel_put(gmu->dummy.obj, gmu->aspace);
1165         msm_gem_kernel_put(gmu->log.obj, gmu->aspace);
1166
1167         gmu->aspace->mmu->funcs->detach(gmu->aspace->mmu);
1168         msm_gem_address_space_put(gmu->aspace);
1169 }
1170
1171 static int a6xx_gmu_memory_alloc(struct a6xx_gmu *gmu, struct a6xx_gmu_bo *bo,
1172                 size_t size, u64 iova, const char *name)
1173 {
1174         struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
1175         struct drm_device *dev = a6xx_gpu->base.base.dev;
1176         uint32_t flags = MSM_BO_WC;
1177         u64 range_start, range_end;
1178         int ret;
1179
1180         size = PAGE_ALIGN(size);
1181         if (!iova) {
1182                 /* no fixed address - use GMU's uncached range */
1183                 range_start = 0x60000000 + PAGE_SIZE; /* skip dummy page */
1184                 range_end = 0x80000000;
1185         } else {
1186                 /* range for fixed address */
1187                 range_start = iova;
1188                 range_end = iova + size;
1189                 /* use IOMMU_PRIV for icache/dcache */
1190                 flags |= MSM_BO_MAP_PRIV;
1191         }
1192
1193         bo->obj = msm_gem_new(dev, size, flags);
1194         if (IS_ERR(bo->obj))
1195                 return PTR_ERR(bo->obj);
1196
1197         ret = msm_gem_get_and_pin_iova_range(bo->obj, gmu->aspace, &bo->iova,
1198                                              range_start, range_end);
1199         if (ret) {
1200                 drm_gem_object_put(bo->obj);
1201                 return ret;
1202         }
1203
1204         bo->virt = msm_gem_get_vaddr(bo->obj);
1205         bo->size = size;
1206
1207         msm_gem_object_set_name(bo->obj, name);
1208
1209         return 0;
1210 }
1211
1212 static int a6xx_gmu_memory_probe(struct a6xx_gmu *gmu)
1213 {
1214         struct msm_mmu *mmu;
1215
1216         mmu = msm_iommu_new(gmu->dev, 0);
1217         if (!mmu)
1218                 return -ENODEV;
1219         if (IS_ERR(mmu))
1220                 return PTR_ERR(mmu);
1221
1222         gmu->aspace = msm_gem_address_space_create(mmu, "gmu", 0x0, 0x80000000);
1223         if (IS_ERR(gmu->aspace))
1224                 return PTR_ERR(gmu->aspace);
1225
1226         return 0;
1227 }
1228
1229 /* Return the 'arc-level' for the given frequency */
1230 static unsigned int a6xx_gmu_get_arc_level(struct device *dev,
1231                                            unsigned long freq)
1232 {
1233         struct dev_pm_opp *opp;
1234         unsigned int val;
1235
1236         if (!freq)
1237                 return 0;
1238
1239         opp = dev_pm_opp_find_freq_exact(dev, freq, true);
1240         if (IS_ERR(opp))
1241                 return 0;
1242
1243         val = dev_pm_opp_get_level(opp);
1244
1245         dev_pm_opp_put(opp);
1246
1247         return val;
1248 }
1249
1250 static int a6xx_gmu_rpmh_arc_votes_init(struct device *dev, u32 *votes,
1251                 unsigned long *freqs, int freqs_count, const char *id)
1252 {
1253         int i, j;
1254         const u16 *pri, *sec;
1255         size_t pri_count, sec_count;
1256
1257         pri = cmd_db_read_aux_data(id, &pri_count);
1258         if (IS_ERR(pri))
1259                 return PTR_ERR(pri);
1260         /*
1261          * The data comes back as an array of unsigned shorts so adjust the
1262          * count accordingly
1263          */
1264         pri_count >>= 1;
1265         if (!pri_count)
1266                 return -EINVAL;
1267
1268         sec = cmd_db_read_aux_data("mx.lvl", &sec_count);
1269         if (IS_ERR(sec))
1270                 return PTR_ERR(sec);
1271
1272         sec_count >>= 1;
1273         if (!sec_count)
1274                 return -EINVAL;
1275
1276         /* Construct a vote for each frequency */
1277         for (i = 0; i < freqs_count; i++) {
1278                 u8 pindex = 0, sindex = 0;
1279                 unsigned int level = a6xx_gmu_get_arc_level(dev, freqs[i]);
1280
1281                 /* Get the primary index that matches the arc level */
1282                 for (j = 0; j < pri_count; j++) {
1283                         if (pri[j] >= level) {
1284                                 pindex = j;
1285                                 break;
1286                         }
1287                 }
1288
1289                 if (j == pri_count) {
1290                         DRM_DEV_ERROR(dev,
1291                                       "Level %u not found in the RPMh list\n",
1292                                       level);
1293                         DRM_DEV_ERROR(dev, "Available levels:\n");
1294                         for (j = 0; j < pri_count; j++)
1295                                 DRM_DEV_ERROR(dev, "  %u\n", pri[j]);
1296
1297                         return -EINVAL;
1298                 }
1299
1300                 /*
1301                  * Look for a level in in the secondary list that matches. If
1302                  * nothing fits, use the maximum non zero vote
1303                  */
1304
1305                 for (j = 0; j < sec_count; j++) {
1306                         if (sec[j] >= level) {
1307                                 sindex = j;
1308                                 break;
1309                         } else if (sec[j]) {
1310                                 sindex = j;
1311                         }
1312                 }
1313
1314                 /* Construct the vote */
1315                 votes[i] = ((pri[pindex] & 0xffff) << 16) |
1316                         (sindex << 8) | pindex;
1317         }
1318
1319         return 0;
1320 }
1321
1322 /*
1323  * The GMU votes with the RPMh for itself and on behalf of the GPU but we need
1324  * to construct the list of votes on the CPU and send it over. Query the RPMh
1325  * voltage levels and build the votes
1326  */
1327
1328 static int a6xx_gmu_rpmh_votes_init(struct a6xx_gmu *gmu)
1329 {
1330         struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
1331         struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
1332         struct msm_gpu *gpu = &adreno_gpu->base;
1333         int ret;
1334
1335         /* Build the GX votes */
1336         ret = a6xx_gmu_rpmh_arc_votes_init(&gpu->pdev->dev, gmu->gx_arc_votes,
1337                 gmu->gpu_freqs, gmu->nr_gpu_freqs, "gfx.lvl");
1338
1339         /* Build the CX votes */
1340         ret |= a6xx_gmu_rpmh_arc_votes_init(gmu->dev, gmu->cx_arc_votes,
1341                 gmu->gmu_freqs, gmu->nr_gmu_freqs, "cx.lvl");
1342
1343         return ret;
1344 }
1345
1346 static int a6xx_gmu_build_freq_table(struct device *dev, unsigned long *freqs,
1347                 u32 size)
1348 {
1349         int count = dev_pm_opp_get_opp_count(dev);
1350         struct dev_pm_opp *opp;
1351         int i, index = 0;
1352         unsigned long freq = 1;
1353
1354         /*
1355          * The OPP table doesn't contain the "off" frequency level so we need to
1356          * add 1 to the table size to account for it
1357          */
1358
1359         if (WARN(count + 1 > size,
1360                 "The GMU frequency table is being truncated\n"))
1361                 count = size - 1;
1362
1363         /* Set the "off" frequency */
1364         freqs[index++] = 0;
1365
1366         for (i = 0; i < count; i++) {
1367                 opp = dev_pm_opp_find_freq_ceil(dev, &freq);
1368                 if (IS_ERR(opp))
1369                         break;
1370
1371                 dev_pm_opp_put(opp);
1372                 freqs[index++] = freq++;
1373         }
1374
1375         return index;
1376 }
1377
1378 static int a6xx_gmu_pwrlevels_probe(struct a6xx_gmu *gmu)
1379 {
1380         struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
1381         struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
1382         struct msm_gpu *gpu = &adreno_gpu->base;
1383
1384         int ret = 0;
1385
1386         /*
1387          * The GMU handles its own frequency switching so build a list of
1388          * available frequencies to send during initialization
1389          */
1390         ret = devm_pm_opp_of_add_table(gmu->dev);
1391         if (ret) {
1392                 DRM_DEV_ERROR(gmu->dev, "Unable to set the OPP table for the GMU\n");
1393                 return ret;
1394         }
1395
1396         gmu->nr_gmu_freqs = a6xx_gmu_build_freq_table(gmu->dev,
1397                 gmu->gmu_freqs, ARRAY_SIZE(gmu->gmu_freqs));
1398
1399         /*
1400          * The GMU also handles GPU frequency switching so build a list
1401          * from the GPU OPP table
1402          */
1403         gmu->nr_gpu_freqs = a6xx_gmu_build_freq_table(&gpu->pdev->dev,
1404                 gmu->gpu_freqs, ARRAY_SIZE(gmu->gpu_freqs));
1405
1406         gmu->current_perf_index = gmu->nr_gpu_freqs - 1;
1407
1408         /* Build the list of RPMh votes that we'll send to the GMU */
1409         return a6xx_gmu_rpmh_votes_init(gmu);
1410 }
1411
1412 static int a6xx_gmu_clocks_probe(struct a6xx_gmu *gmu)
1413 {
1414         int ret = devm_clk_bulk_get_all(gmu->dev, &gmu->clocks);
1415
1416         if (ret < 1)
1417                 return ret;
1418
1419         gmu->nr_clocks = ret;
1420
1421         gmu->core_clk = msm_clk_bulk_get_clock(gmu->clocks,
1422                 gmu->nr_clocks, "gmu");
1423
1424         gmu->hub_clk = msm_clk_bulk_get_clock(gmu->clocks,
1425                 gmu->nr_clocks, "hub");
1426
1427         return 0;
1428 }
1429
1430 static void __iomem *a6xx_gmu_get_mmio(struct platform_device *pdev,
1431                 const char *name)
1432 {
1433         void __iomem *ret;
1434         struct resource *res = platform_get_resource_byname(pdev,
1435                         IORESOURCE_MEM, name);
1436
1437         if (!res) {
1438                 DRM_DEV_ERROR(&pdev->dev, "Unable to find the %s registers\n", name);
1439                 return ERR_PTR(-EINVAL);
1440         }
1441
1442         ret = ioremap(res->start, resource_size(res));
1443         if (!ret) {
1444                 DRM_DEV_ERROR(&pdev->dev, "Unable to map the %s registers\n", name);
1445                 return ERR_PTR(-EINVAL);
1446         }
1447
1448         return ret;
1449 }
1450
1451 static int a6xx_gmu_get_irq(struct a6xx_gmu *gmu, struct platform_device *pdev,
1452                 const char *name, irq_handler_t handler)
1453 {
1454         int irq, ret;
1455
1456         irq = platform_get_irq_byname(pdev, name);
1457
1458         ret = request_irq(irq, handler, IRQF_TRIGGER_HIGH, name, gmu);
1459         if (ret) {
1460                 DRM_DEV_ERROR(&pdev->dev, "Unable to get interrupt %s %d\n",
1461                               name, ret);
1462                 return ret;
1463         }
1464
1465         disable_irq(irq);
1466
1467         return irq;
1468 }
1469
1470 void a6xx_gmu_remove(struct a6xx_gpu *a6xx_gpu)
1471 {
1472         struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
1473         struct platform_device *pdev = to_platform_device(gmu->dev);
1474
1475         if (!gmu->initialized)
1476                 return;
1477
1478         pm_runtime_force_suspend(gmu->dev);
1479
1480         /*
1481          * Since cxpd is a virt device, the devlink with gmu-dev will be removed
1482          * automatically when we do detach
1483          */
1484         dev_pm_domain_detach(gmu->cxpd, false);
1485
1486         if (!IS_ERR_OR_NULL(gmu->gxpd)) {
1487                 pm_runtime_disable(gmu->gxpd);
1488                 dev_pm_domain_detach(gmu->gxpd, false);
1489         }
1490
1491         iounmap(gmu->mmio);
1492         if (platform_get_resource_byname(pdev, IORESOURCE_MEM, "rscc"))
1493                 iounmap(gmu->rscc);
1494         gmu->mmio = NULL;
1495         gmu->rscc = NULL;
1496
1497         a6xx_gmu_memory_free(gmu);
1498
1499         free_irq(gmu->gmu_irq, gmu);
1500         free_irq(gmu->hfi_irq, gmu);
1501
1502         /* Drop reference taken in of_find_device_by_node */
1503         put_device(gmu->dev);
1504
1505         gmu->initialized = false;
1506 }
1507
1508 static int cxpd_notifier_cb(struct notifier_block *nb,
1509                         unsigned long action, void *data)
1510 {
1511         struct a6xx_gmu *gmu = container_of(nb, struct a6xx_gmu, pd_nb);
1512
1513         if (action == GENPD_NOTIFY_OFF)
1514                 complete_all(&gmu->pd_gate);
1515
1516         return 0;
1517 }
1518
1519 int a6xx_gmu_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node)
1520 {
1521         struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
1522         struct a6xx_gmu *gmu = &a6xx_gpu->gmu;
1523         struct platform_device *pdev = of_find_device_by_node(node);
1524         int ret;
1525
1526         if (!pdev)
1527                 return -ENODEV;
1528
1529         mutex_init(&gmu->lock);
1530
1531         gmu->dev = &pdev->dev;
1532
1533         of_dma_configure(gmu->dev, node, true);
1534
1535         /* Fow now, don't do anything fancy until we get our feet under us */
1536         gmu->idle_level = GMU_IDLE_STATE_ACTIVE;
1537
1538         pm_runtime_enable(gmu->dev);
1539
1540         /* Get the list of clocks */
1541         ret = a6xx_gmu_clocks_probe(gmu);
1542         if (ret)
1543                 goto err_put_device;
1544
1545         ret = a6xx_gmu_memory_probe(gmu);
1546         if (ret)
1547                 goto err_put_device;
1548
1549
1550         /* A660 now requires handling "prealloc requests" in GMU firmware
1551          * For now just hardcode allocations based on the known firmware.
1552          * note: there is no indication that these correspond to "dummy" or
1553          * "debug" regions, but this "guess" allows reusing these BOs which
1554          * are otherwise unused by a660.
1555          */
1556         gmu->dummy.size = SZ_4K;
1557         if (adreno_is_a660_family(adreno_gpu)) {
1558                 ret = a6xx_gmu_memory_alloc(gmu, &gmu->debug, SZ_4K * 7,
1559                                             0x60400000, "debug");
1560                 if (ret)
1561                         goto err_memory;
1562
1563                 gmu->dummy.size = SZ_8K;
1564         }
1565
1566         /* Allocate memory for the GMU dummy page */
1567         ret = a6xx_gmu_memory_alloc(gmu, &gmu->dummy, gmu->dummy.size,
1568                                     0x60000000, "dummy");
1569         if (ret)
1570                 goto err_memory;
1571
1572         /* Note that a650 family also includes a660 family: */
1573         if (adreno_is_a650_family(adreno_gpu)) {
1574                 ret = a6xx_gmu_memory_alloc(gmu, &gmu->icache,
1575                         SZ_16M - SZ_16K, 0x04000, "icache");
1576                 if (ret)
1577                         goto err_memory;
1578         /*
1579          * NOTE: when porting legacy ("pre-650-family") GPUs you may be tempted to add a condition
1580          * to allocate icache/dcache here, as per downstream code flow, but it may not actually be
1581          * necessary. If you omit this step and you don't get random pagefaults, you are likely
1582          * good to go without this!
1583          */
1584         } else if (adreno_is_a640_family(adreno_gpu)) {
1585                 ret = a6xx_gmu_memory_alloc(gmu, &gmu->icache,
1586                         SZ_256K - SZ_16K, 0x04000, "icache");
1587                 if (ret)
1588                         goto err_memory;
1589
1590                 ret = a6xx_gmu_memory_alloc(gmu, &gmu->dcache,
1591                         SZ_256K - SZ_16K, 0x44000, "dcache");
1592                 if (ret)
1593                         goto err_memory;
1594         } else if (adreno_is_a630(adreno_gpu) || adreno_is_a615_family(adreno_gpu)) {
1595                 /* HFI v1, has sptprac */
1596                 gmu->legacy = true;
1597
1598                 /* Allocate memory for the GMU debug region */
1599                 ret = a6xx_gmu_memory_alloc(gmu, &gmu->debug, SZ_16K, 0, "debug");
1600                 if (ret)
1601                         goto err_memory;
1602         }
1603
1604         /* Allocate memory for for the HFI queues */
1605         ret = a6xx_gmu_memory_alloc(gmu, &gmu->hfi, SZ_16K, 0, "hfi");
1606         if (ret)
1607                 goto err_memory;
1608
1609         /* Allocate memory for the GMU log region */
1610         ret = a6xx_gmu_memory_alloc(gmu, &gmu->log, SZ_4K, 0, "log");
1611         if (ret)
1612                 goto err_memory;
1613
1614         /* Map the GMU registers */
1615         gmu->mmio = a6xx_gmu_get_mmio(pdev, "gmu");
1616         if (IS_ERR(gmu->mmio)) {
1617                 ret = PTR_ERR(gmu->mmio);
1618                 goto err_memory;
1619         }
1620
1621         if (adreno_is_a650_family(adreno_gpu)) {
1622                 gmu->rscc = a6xx_gmu_get_mmio(pdev, "rscc");
1623                 if (IS_ERR(gmu->rscc)) {
1624                         ret = -ENODEV;
1625                         goto err_mmio;
1626                 }
1627         } else {
1628                 gmu->rscc = gmu->mmio + 0x23000;
1629         }
1630
1631         /* Get the HFI and GMU interrupts */
1632         gmu->hfi_irq = a6xx_gmu_get_irq(gmu, pdev, "hfi", a6xx_hfi_irq);
1633         gmu->gmu_irq = a6xx_gmu_get_irq(gmu, pdev, "gmu", a6xx_gmu_irq);
1634
1635         if (gmu->hfi_irq < 0 || gmu->gmu_irq < 0) {
1636                 ret = -ENODEV;
1637                 goto err_mmio;
1638         }
1639
1640         gmu->cxpd = dev_pm_domain_attach_by_name(gmu->dev, "cx");
1641         if (IS_ERR(gmu->cxpd)) {
1642                 ret = PTR_ERR(gmu->cxpd);
1643                 goto err_mmio;
1644         }
1645
1646         if (!device_link_add(gmu->dev, gmu->cxpd,
1647                                         DL_FLAG_PM_RUNTIME)) {
1648                 ret = -ENODEV;
1649                 goto detach_cxpd;
1650         }
1651
1652         init_completion(&gmu->pd_gate);
1653         complete_all(&gmu->pd_gate);
1654         gmu->pd_nb.notifier_call = cxpd_notifier_cb;
1655
1656         /*
1657          * Get a link to the GX power domain to reset the GPU in case of GMU
1658          * crash
1659          */
1660         gmu->gxpd = dev_pm_domain_attach_by_name(gmu->dev, "gx");
1661
1662         /* Get the power levels for the GMU and GPU */
1663         a6xx_gmu_pwrlevels_probe(gmu);
1664
1665         /* Set up the HFI queues */
1666         a6xx_hfi_init(gmu);
1667
1668         /* Initialize RPMh */
1669         a6xx_gmu_rpmh_init(gmu);
1670
1671         gmu->initialized = true;
1672
1673         return 0;
1674
1675 detach_cxpd:
1676         dev_pm_domain_detach(gmu->cxpd, false);
1677
1678 err_mmio:
1679         iounmap(gmu->mmio);
1680         if (platform_get_resource_byname(pdev, IORESOURCE_MEM, "rscc"))
1681                 iounmap(gmu->rscc);
1682         free_irq(gmu->gmu_irq, gmu);
1683         free_irq(gmu->hfi_irq, gmu);
1684
1685 err_memory:
1686         a6xx_gmu_memory_free(gmu);
1687 err_put_device:
1688         /* Drop reference taken in of_find_device_by_node */
1689         put_device(gmu->dev);
1690
1691         return ret;
1692 }
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