1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2021 MediaTek Inc.
7 #include <linux/component.h>
8 #include <linux/module.h>
9 #include <linux/of_device.h>
10 #include <linux/of_irq.h>
11 #include <linux/platform_device.h>
12 #include <linux/soc/mediatek/mtk-cmdq.h>
14 #include "mtk_disp_drv.h"
15 #include "mtk_drm_crtc.h"
16 #include "mtk_drm_ddp_comp.h"
17 #include "mtk_drm_drv.h"
19 #define DISP_CCORR_EN 0x0000
20 #define CCORR_EN BIT(0)
21 #define DISP_CCORR_CFG 0x0020
22 #define CCORR_RELAY_MODE BIT(0)
23 #define CCORR_ENGINE_EN BIT(1)
24 #define CCORR_GAMMA_OFF BIT(2)
25 #define CCORR_WGAMUT_SRC_CLIP BIT(3)
26 #define DISP_CCORR_SIZE 0x0030
27 #define DISP_CCORR_COEF_0 0x0080
28 #define DISP_CCORR_COEF_1 0x0084
29 #define DISP_CCORR_COEF_2 0x0088
30 #define DISP_CCORR_COEF_3 0x008C
31 #define DISP_CCORR_COEF_4 0x0090
33 struct mtk_disp_ccorr_data {
38 * struct mtk_disp_ccorr - DISP_CCORR driver structure
39 * @ddp_comp - structure containing type enum and hardware resources
40 * @crtc - associated crtc to report irq events to
42 struct mtk_disp_ccorr {
45 struct cmdq_client_reg cmdq_reg;
46 const struct mtk_disp_ccorr_data *data;
49 int mtk_ccorr_clk_enable(struct device *dev)
51 struct mtk_disp_ccorr *ccorr = dev_get_drvdata(dev);
53 return clk_prepare_enable(ccorr->clk);
56 void mtk_ccorr_clk_disable(struct device *dev)
58 struct mtk_disp_ccorr *ccorr = dev_get_drvdata(dev);
60 clk_disable_unprepare(ccorr->clk);
63 void mtk_ccorr_config(struct device *dev, unsigned int w,
64 unsigned int h, unsigned int vrefresh,
65 unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
67 struct mtk_disp_ccorr *ccorr = dev_get_drvdata(dev);
69 mtk_ddp_write(cmdq_pkt, w << 16 | h, &ccorr->cmdq_reg, ccorr->regs,
71 mtk_ddp_write(cmdq_pkt, CCORR_ENGINE_EN, &ccorr->cmdq_reg, ccorr->regs,
75 void mtk_ccorr_start(struct device *dev)
77 struct mtk_disp_ccorr *ccorr = dev_get_drvdata(dev);
79 writel(CCORR_EN, ccorr->regs + DISP_CCORR_EN);
82 void mtk_ccorr_stop(struct device *dev)
84 struct mtk_disp_ccorr *ccorr = dev_get_drvdata(dev);
86 writel_relaxed(0x0, ccorr->regs + DISP_CCORR_EN);
89 /* Converts a DRM S31.32 value to the HW S1.n format. */
90 static u16 mtk_ctm_s31_32_to_s1_n(u64 in, u32 n)
95 r = in & BIT_ULL(63) ? BIT(n + 1) : 0;
97 if ((in & GENMASK_ULL(62, 33)) > 0) {
98 /* identity value 0x100000000 -> 0x400(mt8183), */
99 /* identity value 0x100000000 -> 0x800(mt8192), */
100 /* if bigger this, set it to max 0x7ff. */
103 /* take the n+1 most important bits. */
104 r |= (in >> (32 - n)) & GENMASK(n, 0);
110 void mtk_ccorr_ctm_set(struct device *dev, struct drm_crtc_state *state)
112 struct mtk_disp_ccorr *ccorr = dev_get_drvdata(dev);
113 struct drm_property_blob *blob = state->ctm;
114 struct drm_color_ctm *ctm;
116 uint16_t coeffs[9] = { 0 };
118 struct cmdq_pkt *cmdq_pkt = NULL;
119 u32 matrix_bits = ccorr->data->matrix_bits;
124 ctm = (struct drm_color_ctm *)blob->data;
127 for (i = 0; i < ARRAY_SIZE(coeffs); i++)
128 coeffs[i] = mtk_ctm_s31_32_to_s1_n(input[i], matrix_bits);
130 mtk_ddp_write(cmdq_pkt, coeffs[0] << 16 | coeffs[1],
131 &ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_COEF_0);
132 mtk_ddp_write(cmdq_pkt, coeffs[2] << 16 | coeffs[3],
133 &ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_COEF_1);
134 mtk_ddp_write(cmdq_pkt, coeffs[4] << 16 | coeffs[5],
135 &ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_COEF_2);
136 mtk_ddp_write(cmdq_pkt, coeffs[6] << 16 | coeffs[7],
137 &ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_COEF_3);
138 mtk_ddp_write(cmdq_pkt, coeffs[8] << 16,
139 &ccorr->cmdq_reg, ccorr->regs, DISP_CCORR_COEF_4);
142 static int mtk_disp_ccorr_bind(struct device *dev, struct device *master,
148 static void mtk_disp_ccorr_unbind(struct device *dev, struct device *master,
153 static const struct component_ops mtk_disp_ccorr_component_ops = {
154 .bind = mtk_disp_ccorr_bind,
155 .unbind = mtk_disp_ccorr_unbind,
158 static int mtk_disp_ccorr_probe(struct platform_device *pdev)
160 struct device *dev = &pdev->dev;
161 struct mtk_disp_ccorr *priv;
162 struct resource *res;
165 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
169 priv->clk = devm_clk_get(dev, NULL);
170 if (IS_ERR(priv->clk)) {
171 dev_err(dev, "failed to get ccorr clk\n");
172 return PTR_ERR(priv->clk);
175 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
176 priv->regs = devm_ioremap_resource(dev, res);
177 if (IS_ERR(priv->regs)) {
178 dev_err(dev, "failed to ioremap ccorr\n");
179 return PTR_ERR(priv->regs);
182 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
183 ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0);
185 dev_dbg(dev, "get mediatek,gce-client-reg fail!\n");
188 priv->data = of_device_get_match_data(dev);
189 platform_set_drvdata(pdev, priv);
191 ret = component_add(dev, &mtk_disp_ccorr_component_ops);
193 dev_err(dev, "Failed to add component: %d\n", ret);
198 static int mtk_disp_ccorr_remove(struct platform_device *pdev)
200 component_del(&pdev->dev, &mtk_disp_ccorr_component_ops);
205 static const struct mtk_disp_ccorr_data mt8183_ccorr_driver_data = {
209 static const struct mtk_disp_ccorr_data mt8192_ccorr_driver_data = {
213 static const struct of_device_id mtk_disp_ccorr_driver_dt_match[] = {
214 { .compatible = "mediatek,mt8183-disp-ccorr",
215 .data = &mt8183_ccorr_driver_data},
216 { .compatible = "mediatek,mt8192-disp-ccorr",
217 .data = &mt8192_ccorr_driver_data},
220 MODULE_DEVICE_TABLE(of, mtk_disp_ccorr_driver_dt_match);
222 struct platform_driver mtk_disp_ccorr_driver = {
223 .probe = mtk_disp_ccorr_probe,
224 .remove = mtk_disp_ccorr_remove,
226 .name = "mediatek-disp-ccorr",
227 .owner = THIS_MODULE,
228 .of_match_table = mtk_disp_ccorr_driver_dt_match,