drivers/gpu/drm/i915/soc/intel_pch.h

   1 /* SPDX-License-Identifier: MIT */
   2 /*
   3  * Copyright 2019 Intel Corporation.
   4  */
   5
   6 #ifndef __INTEL_PCH__
   7 #define __INTEL_PCH__
   8
   9 struct drm_i915_private;
  10
  11 /*
  12  * Sorted by south display engine compatibility.
  13  * If the new PCH comes with a south display engine that is not
  14  * inherited from the latest item, please do not add it to the
  15  * end. Instead, add it right after its "parent" PCH.
  16  */
  17 enum intel_pch {
  18         PCH_NOP = -1,   /* PCH without south display */
  19         PCH_NONE = 0,   /* No PCH present */
  20         PCH_IBX,        /* Ibexpeak PCH */
  21         PCH_CPT,        /* Cougarpoint/Pantherpoint PCH */
  22         PCH_LPT,        /* Lynxpoint/Wildcatpoint PCH */
  23         PCH_SPT,        /* Sunrisepoint/Kaby Lake PCH */
  24         PCH_CNP,        /* Cannon/Comet Lake PCH */
  25         PCH_ICP,        /* Ice Lake/Jasper Lake PCH */
  26         PCH_TGP,        /* Tiger Lake/Mule Creek Canyon PCH */
  27         PCH_ADP,        /* Alder Lake PCH */
  28         PCH_MTP,        /* Meteor Lake PCH */
  29
  30         /* Fake PCHs, functionality handled on the same PCI dev */
  31         PCH_DG1 = 1024,
  32         PCH_DG2,
  33 };
  34
  35 #define INTEL_PCH_DEVICE_ID_MASK                0xff80
  36 #define INTEL_PCH_IBX_DEVICE_ID_TYPE            0x3b00
  37 #define INTEL_PCH_CPT_DEVICE_ID_TYPE            0x1c00
  38 #define INTEL_PCH_PPT_DEVICE_ID_TYPE            0x1e00
  39 #define INTEL_PCH_LPT_DEVICE_ID_TYPE            0x8c00
  40 #define INTEL_PCH_LPT_LP_DEVICE_ID_TYPE         0x9c00
  41 #define INTEL_PCH_WPT_DEVICE_ID_TYPE            0x8c80
  42 #define INTEL_PCH_WPT_LP_DEVICE_ID_TYPE         0x9c80
  43 #define INTEL_PCH_SPT_DEVICE_ID_TYPE            0xA100
  44 #define INTEL_PCH_SPT_LP_DEVICE_ID_TYPE         0x9D00
  45 #define INTEL_PCH_KBP_DEVICE_ID_TYPE            0xA280
  46 #define INTEL_PCH_CNP_DEVICE_ID_TYPE            0xA300
  47 #define INTEL_PCH_CNP_LP_DEVICE_ID_TYPE         0x9D80
  48 #define INTEL_PCH_CMP_DEVICE_ID_TYPE            0x0280
  49 #define INTEL_PCH_CMP2_DEVICE_ID_TYPE           0x0680
  50 #define INTEL_PCH_CMP_V_DEVICE_ID_TYPE          0xA380
  51 #define INTEL_PCH_ICP_DEVICE_ID_TYPE            0x3480
  52 #define INTEL_PCH_ICP2_DEVICE_ID_TYPE           0x3880
  53 #define INTEL_PCH_MCC_DEVICE_ID_TYPE            0x4B00
  54 #define INTEL_PCH_TGP_DEVICE_ID_TYPE            0xA080
  55 #define INTEL_PCH_TGP2_DEVICE_ID_TYPE           0x4380
  56 #define INTEL_PCH_JSP_DEVICE_ID_TYPE            0x4D80
  57 #define INTEL_PCH_ADP_DEVICE_ID_TYPE            0x7A80
  58 #define INTEL_PCH_ADP2_DEVICE_ID_TYPE           0x5180
  59 #define INTEL_PCH_ADP3_DEVICE_ID_TYPE           0x7A00
  60 #define INTEL_PCH_ADP4_DEVICE_ID_TYPE           0x5480
  61 #define INTEL_PCH_MTP_DEVICE_ID_TYPE            0x7E00
  62 #define INTEL_PCH_MTP2_DEVICE_ID_TYPE           0xAE00
  63 #define INTEL_PCH_P2X_DEVICE_ID_TYPE            0x7100
  64 #define INTEL_PCH_P3X_DEVICE_ID_TYPE            0x7000
  65 #define INTEL_PCH_QEMU_DEVICE_ID_TYPE           0x2900 /* qemu q35 has 2918 */
  66
  67 #define INTEL_PCH_TYPE(dev_priv)                ((dev_priv)->pch_type)
  68 #define INTEL_PCH_ID(dev_priv)                  ((dev_priv)->pch_id)
  69 #define HAS_PCH_MTP(dev_priv)                   (INTEL_PCH_TYPE(dev_priv) == PCH_MTP)
  70 #define HAS_PCH_DG2(dev_priv)                   (INTEL_PCH_TYPE(dev_priv) == PCH_DG2)
  71 #define HAS_PCH_ADP(dev_priv)                   (INTEL_PCH_TYPE(dev_priv) == PCH_ADP)
  72 #define HAS_PCH_DG1(dev_priv)                   (INTEL_PCH_TYPE(dev_priv) == PCH_DG1)
  73 #define HAS_PCH_TGP(dev_priv)                   (INTEL_PCH_TYPE(dev_priv) == PCH_TGP)
  74 #define HAS_PCH_ICP(dev_priv)                   (INTEL_PCH_TYPE(dev_priv) == PCH_ICP)
  75 #define HAS_PCH_CNP(dev_priv)                   (INTEL_PCH_TYPE(dev_priv) == PCH_CNP)
  76 #define HAS_PCH_SPT(dev_priv)                   (INTEL_PCH_TYPE(dev_priv) == PCH_SPT)
  77 #define HAS_PCH_LPT(dev_priv)                   (INTEL_PCH_TYPE(dev_priv) == PCH_LPT)
  78 #define HAS_PCH_LPT_LP(dev_priv) \
  79         (INTEL_PCH_ID(dev_priv) == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE || \
  80          INTEL_PCH_ID(dev_priv) == INTEL_PCH_WPT_LP_DEVICE_ID_TYPE)
  81 #define HAS_PCH_LPT_H(dev_priv) \
  82         (INTEL_PCH_ID(dev_priv) == INTEL_PCH_LPT_DEVICE_ID_TYPE || \
  83          INTEL_PCH_ID(dev_priv) == INTEL_PCH_WPT_DEVICE_ID_TYPE)
  84 #define HAS_PCH_CPT(dev_priv)                   (INTEL_PCH_TYPE(dev_priv) == PCH_CPT)
  85 #define HAS_PCH_IBX(dev_priv)                   (INTEL_PCH_TYPE(dev_priv) == PCH_IBX)
  86 #define HAS_PCH_NOP(dev_priv)                   (INTEL_PCH_TYPE(dev_priv) == PCH_NOP)
  87 #define HAS_PCH_SPLIT(dev_priv)                 (INTEL_PCH_TYPE(dev_priv) != PCH_NONE)
  88
  89 void intel_detect_pch(struct drm_i915_private *dev_priv);
  90
  91 #endif /* __INTEL_PCH__ */