drivers/gpu/drm/i915/soc/intel_gmch.c

   1 // SPDX-License-Identifier: MIT
   2 /*
   3  * Copyright © 2023 Intel Corporation
   4  */
   5
   6 #include <linux/pci.h>
   7 #include <linux/pnp.h>
   8
   9 #include <drm/drm_managed.h>
  10 #include <drm/i915_drm.h>
  11
  12 #include "i915_drv.h"
  13 #include "intel_gmch.h"
  14 #include "intel_pci_config.h"
  15
  16 static void intel_gmch_bridge_release(struct drm_device *dev, void *bridge)
  17 {
  18         pci_dev_put(bridge);
  19 }
  20
  21 int intel_gmch_bridge_setup(struct drm_i915_private *i915)
  22 {
  23         int domain = pci_domain_nr(to_pci_dev(i915->drm.dev)->bus);
  24
  25         i915->gmch.pdev = pci_get_domain_bus_and_slot(domain, 0, PCI_DEVFN(0, 0));
  26         if (!i915->gmch.pdev) {
  27                 drm_err(&i915->drm, "bridge device not found\n");
  28                 return -EIO;
  29         }
  30
  31         return drmm_add_action_or_reset(&i915->drm, intel_gmch_bridge_release,
  32                                         i915->gmch.pdev);
  33 }
  34
  35 /* Allocate space for the MCH regs if needed, return nonzero on error */
  36 static int
  37 intel_alloc_mchbar_resource(struct drm_i915_private *i915)
  38 {
  39         int reg = GRAPHICS_VER(i915) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
  40         u32 temp_lo, temp_hi = 0;
  41         u64 mchbar_addr;
  42         int ret;
  43
  44         if (GRAPHICS_VER(i915) >= 4)
  45                 pci_read_config_dword(i915->gmch.pdev, reg + 4, &temp_hi);
  46         pci_read_config_dword(i915->gmch.pdev, reg, &temp_lo);
  47         mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
  48
  49         /* If ACPI doesn't have it, assume we need to allocate it ourselves */
  50 #ifdef CONFIG_PNP
  51         if (mchbar_addr &&
  52             pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
  53                 return 0;
  54 #endif
  55
  56         /* Get some space for it */
  57         i915->gmch.mch_res.name = "i915 MCHBAR";
  58         i915->gmch.mch_res.flags = IORESOURCE_MEM;
  59         ret = pci_bus_alloc_resource(i915->gmch.pdev->bus,
  60                                      &i915->gmch.mch_res,
  61                                      MCHBAR_SIZE, MCHBAR_SIZE,
  62                                      PCIBIOS_MIN_MEM,
  63                                      0, pcibios_align_resource,
  64                                      i915->gmch.pdev);
  65         if (ret) {
  66                 drm_dbg(&i915->drm, "failed bus alloc: %d\n", ret);
  67                 i915->gmch.mch_res.start = 0;
  68                 return ret;
  69         }
  70
  71         if (GRAPHICS_VER(i915) >= 4)
  72                 pci_write_config_dword(i915->gmch.pdev, reg + 4,
  73                                        upper_32_bits(i915->gmch.mch_res.start));
  74
  75         pci_write_config_dword(i915->gmch.pdev, reg,
  76                                lower_32_bits(i915->gmch.mch_res.start));
  77         return 0;
  78 }
  79
  80 /* Setup MCHBAR if possible, return true if we should disable it again */
  81 void intel_gmch_bar_setup(struct drm_i915_private *i915)
  82 {
  83         int mchbar_reg = GRAPHICS_VER(i915) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
  84         u32 temp;
  85         bool enabled;
  86
  87         if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915))
  88                 return;
  89
  90         i915->gmch.mchbar_need_disable = false;
  91
  92         if (IS_I915G(i915) || IS_I915GM(i915)) {
  93                 pci_read_config_dword(i915->gmch.pdev, DEVEN, &temp);
  94                 enabled = !!(temp & DEVEN_MCHBAR_EN);
  95         } else {
  96                 pci_read_config_dword(i915->gmch.pdev, mchbar_reg, &temp);
  97                 enabled = temp & 1;
  98         }
  99
 100         /* If it's already enabled, don't have to do anything */
 101         if (enabled)
 102                 return;
 103
 104         if (intel_alloc_mchbar_resource(i915))
 105                 return;
 106
 107         i915->gmch.mchbar_need_disable = true;
 108
 109         /* Space is allocated or reserved, so enable it. */
 110         if (IS_I915G(i915) || IS_I915GM(i915)) {
 111                 pci_write_config_dword(i915->gmch.pdev, DEVEN,
 112                                        temp | DEVEN_MCHBAR_EN);
 113         } else {
 114                 pci_read_config_dword(i915->gmch.pdev, mchbar_reg, &temp);
 115                 pci_write_config_dword(i915->gmch.pdev, mchbar_reg, temp | 1);
 116         }
 117 }
 118
 119 void intel_gmch_bar_teardown(struct drm_i915_private *i915)
 120 {
 121         int mchbar_reg = GRAPHICS_VER(i915) >= 4 ? MCHBAR_I965 : MCHBAR_I915;
 122
 123         if (i915->gmch.mchbar_need_disable) {
 124                 if (IS_I915G(i915) || IS_I915GM(i915)) {
 125                         u32 deven_val;
 126
 127                         pci_read_config_dword(i915->gmch.pdev, DEVEN,
 128                                               &deven_val);
 129                         deven_val &= ~DEVEN_MCHBAR_EN;
 130                         pci_write_config_dword(i915->gmch.pdev, DEVEN,
 131                                                deven_val);
 132                 } else {
 133                         u32 mchbar_val;
 134
 135                         pci_read_config_dword(i915->gmch.pdev, mchbar_reg,
 136                                               &mchbar_val);
 137                         mchbar_val &= ~1;
 138                         pci_write_config_dword(i915->gmch.pdev, mchbar_reg,
 139                                                mchbar_val);
 140                 }
 141         }
 142
 143         if (i915->gmch.mch_res.start)
 144                 release_resource(&i915->gmch.mch_res);
 145 }
 146
 147 int intel_gmch_vga_set_state(struct drm_i915_private *i915, bool enable_decode)
 148 {
 149         unsigned int reg = DISPLAY_VER(i915) >= 6 ? SNB_GMCH_CTRL : INTEL_GMCH_CTRL;
 150         u16 gmch_ctrl;
 151
 152         if (pci_read_config_word(i915->gmch.pdev, reg, &gmch_ctrl)) {
 153                 drm_err(&i915->drm, "failed to read control word\n");
 154                 return -EIO;
 155         }
 156
 157         if (!!(gmch_ctrl & INTEL_GMCH_VGA_DISABLE) == !enable_decode)
 158                 return 0;
 159
 160         if (enable_decode)
 161                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
 162         else
 163                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
 164
 165         if (pci_write_config_word(i915->gmch.pdev, reg, gmch_ctrl)) {
 166                 drm_err(&i915->drm, "failed to write control word\n");
 167                 return -EIO;
 168         }
 169
 170         return 0;
 171 }