1 // SPDX-License-Identifier: MIT
3 * Copyright © 2020 Intel Corporation
6 #include <linux/string_helpers.h>
10 #include "intel_dram.h"
11 #include "intel_mchbar_regs.h"
12 #include "intel_pcode.h"
13 #include "vlv_sideband.h"
15 struct dram_dimm_info {
20 struct dram_channel_info {
21 struct dram_dimm_info dimm_l, dimm_s;
26 #define DRAM_TYPE_STR(type) [INTEL_DRAM_ ## type] = #type
28 static const char *intel_dram_type_str(enum intel_dram_type type)
30 static const char * const str[] = {
31 DRAM_TYPE_STR(UNKNOWN),
34 DRAM_TYPE_STR(LPDDR3),
35 DRAM_TYPE_STR(LPDDR4),
38 if (type >= ARRAY_SIZE(str))
39 type = INTEL_DRAM_UNKNOWN;
46 static void pnv_detect_mem_freq(struct drm_i915_private *dev_priv)
50 tmp = intel_uncore_read(&dev_priv->uncore, CLKCFG);
52 switch (tmp & CLKCFG_FSB_MASK) {
54 dev_priv->fsb_freq = 533; /* 133*4 */
57 dev_priv->fsb_freq = 800; /* 200*4 */
60 dev_priv->fsb_freq = 667; /* 167*4 */
63 dev_priv->fsb_freq = 400; /* 100*4 */
67 switch (tmp & CLKCFG_MEM_MASK) {
69 dev_priv->mem_freq = 533;
72 dev_priv->mem_freq = 667;
75 dev_priv->mem_freq = 800;
79 /* detect pineview DDR3 setting */
80 tmp = intel_uncore_read(&dev_priv->uncore, CSHRDDR3CTL);
81 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
84 static void ilk_detect_mem_freq(struct drm_i915_private *dev_priv)
88 ddrpll = intel_uncore_read16(&dev_priv->uncore, DDRMPLL1);
89 switch (ddrpll & 0xff) {
91 dev_priv->mem_freq = 800;
94 dev_priv->mem_freq = 1066;
97 dev_priv->mem_freq = 1333;
100 dev_priv->mem_freq = 1600;
103 drm_dbg(&dev_priv->drm, "unknown memory frequency 0x%02x\n",
105 dev_priv->mem_freq = 0;
109 csipll = intel_uncore_read16(&dev_priv->uncore, CSIPLL0);
110 switch (csipll & 0x3ff) {
112 dev_priv->fsb_freq = 3200;
115 dev_priv->fsb_freq = 3733;
118 dev_priv->fsb_freq = 4266;
121 dev_priv->fsb_freq = 4800;
124 dev_priv->fsb_freq = 5333;
127 dev_priv->fsb_freq = 5866;
130 dev_priv->fsb_freq = 6400;
133 drm_dbg(&dev_priv->drm, "unknown fsb frequency 0x%04x\n",
135 dev_priv->fsb_freq = 0;
140 static void chv_detect_mem_freq(struct drm_i915_private *i915)
144 vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_CCK));
145 val = vlv_cck_read(i915, CCK_FUSE_REG);
146 vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_CCK));
148 switch ((val >> 2) & 0x7) {
150 i915->mem_freq = 2000;
153 i915->mem_freq = 1600;
158 static void vlv_detect_mem_freq(struct drm_i915_private *i915)
162 vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_PUNIT));
163 val = vlv_punit_read(i915, PUNIT_REG_GPU_FREQ_STS);
164 vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_PUNIT));
166 switch ((val >> 6) & 3) {
169 i915->mem_freq = 800;
172 i915->mem_freq = 1066;
175 i915->mem_freq = 1333;
180 static void detect_mem_freq(struct drm_i915_private *i915)
182 if (IS_PINEVIEW(i915))
183 pnv_detect_mem_freq(i915);
184 else if (GRAPHICS_VER(i915) == 5)
185 ilk_detect_mem_freq(i915);
186 else if (IS_CHERRYVIEW(i915))
187 chv_detect_mem_freq(i915);
188 else if (IS_VALLEYVIEW(i915))
189 vlv_detect_mem_freq(i915);
192 drm_dbg(&i915->drm, "DDR speed: %d MHz\n", i915->mem_freq);
195 static int intel_dimm_num_devices(const struct dram_dimm_info *dimm)
197 return dimm->ranks * 64 / (dimm->width ?: 1);
200 /* Returns total Gb for the whole DIMM */
201 static int skl_get_dimm_size(u16 val)
203 return (val & SKL_DRAM_SIZE_MASK) * 8;
206 static int skl_get_dimm_width(u16 val)
208 if (skl_get_dimm_size(val) == 0)
211 switch (val & SKL_DRAM_WIDTH_MASK) {
212 case SKL_DRAM_WIDTH_X8:
213 case SKL_DRAM_WIDTH_X16:
214 case SKL_DRAM_WIDTH_X32:
215 val = (val & SKL_DRAM_WIDTH_MASK) >> SKL_DRAM_WIDTH_SHIFT;
223 static int skl_get_dimm_ranks(u16 val)
225 if (skl_get_dimm_size(val) == 0)
228 val = (val & SKL_DRAM_RANK_MASK) >> SKL_DRAM_RANK_SHIFT;
233 /* Returns total Gb for the whole DIMM */
234 static int icl_get_dimm_size(u16 val)
236 return (val & ICL_DRAM_SIZE_MASK) * 8 / 2;
239 static int icl_get_dimm_width(u16 val)
241 if (icl_get_dimm_size(val) == 0)
244 switch (val & ICL_DRAM_WIDTH_MASK) {
245 case ICL_DRAM_WIDTH_X8:
246 case ICL_DRAM_WIDTH_X16:
247 case ICL_DRAM_WIDTH_X32:
248 val = (val & ICL_DRAM_WIDTH_MASK) >> ICL_DRAM_WIDTH_SHIFT;
256 static int icl_get_dimm_ranks(u16 val)
258 if (icl_get_dimm_size(val) == 0)
261 val = (val & ICL_DRAM_RANK_MASK) >> ICL_DRAM_RANK_SHIFT;
267 skl_is_16gb_dimm(const struct dram_dimm_info *dimm)
269 /* Convert total Gb to Gb per DRAM device */
270 return dimm->size / (intel_dimm_num_devices(dimm) ?: 1) == 16;
274 skl_dram_get_dimm_info(struct drm_i915_private *i915,
275 struct dram_dimm_info *dimm,
276 int channel, char dimm_name, u16 val)
278 if (GRAPHICS_VER(i915) >= 11) {
279 dimm->size = icl_get_dimm_size(val);
280 dimm->width = icl_get_dimm_width(val);
281 dimm->ranks = icl_get_dimm_ranks(val);
283 dimm->size = skl_get_dimm_size(val);
284 dimm->width = skl_get_dimm_width(val);
285 dimm->ranks = skl_get_dimm_ranks(val);
288 drm_dbg_kms(&i915->drm,
289 "CH%u DIMM %c size: %u Gb, width: X%u, ranks: %u, 16Gb DIMMs: %s\n",
290 channel, dimm_name, dimm->size, dimm->width, dimm->ranks,
291 str_yes_no(skl_is_16gb_dimm(dimm)));
295 skl_dram_get_channel_info(struct drm_i915_private *i915,
296 struct dram_channel_info *ch,
297 int channel, u32 val)
299 skl_dram_get_dimm_info(i915, &ch->dimm_l,
300 channel, 'L', val & 0xffff);
301 skl_dram_get_dimm_info(i915, &ch->dimm_s,
302 channel, 'S', val >> 16);
304 if (ch->dimm_l.size == 0 && ch->dimm_s.size == 0) {
305 drm_dbg_kms(&i915->drm, "CH%u not populated\n", channel);
309 if (ch->dimm_l.ranks == 2 || ch->dimm_s.ranks == 2)
311 else if (ch->dimm_l.ranks == 1 && ch->dimm_s.ranks == 1)
316 ch->is_16gb_dimm = skl_is_16gb_dimm(&ch->dimm_l) ||
317 skl_is_16gb_dimm(&ch->dimm_s);
319 drm_dbg_kms(&i915->drm, "CH%u ranks: %u, 16Gb DIMMs: %s\n",
320 channel, ch->ranks, str_yes_no(ch->is_16gb_dimm));
326 intel_is_dram_symmetric(const struct dram_channel_info *ch0,
327 const struct dram_channel_info *ch1)
329 return !memcmp(ch0, ch1, sizeof(*ch0)) &&
330 (ch0->dimm_s.size == 0 ||
331 !memcmp(&ch0->dimm_l, &ch0->dimm_s, sizeof(ch0->dimm_l)));
335 skl_dram_get_channels_info(struct drm_i915_private *i915)
337 struct dram_info *dram_info = &i915->dram_info;
338 struct dram_channel_info ch0 = {}, ch1 = {};
342 val = intel_uncore_read(&i915->uncore,
343 SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN);
344 ret = skl_dram_get_channel_info(i915, &ch0, 0, val);
346 dram_info->num_channels++;
348 val = intel_uncore_read(&i915->uncore,
349 SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN);
350 ret = skl_dram_get_channel_info(i915, &ch1, 1, val);
352 dram_info->num_channels++;
354 if (dram_info->num_channels == 0) {
355 drm_info(&i915->drm, "Number of memory channels is zero\n");
359 if (ch0.ranks == 0 && ch1.ranks == 0) {
360 drm_info(&i915->drm, "couldn't get memory rank information\n");
364 dram_info->wm_lv_0_adjust_needed = ch0.is_16gb_dimm || ch1.is_16gb_dimm;
366 dram_info->symmetric_memory = intel_is_dram_symmetric(&ch0, &ch1);
368 drm_dbg_kms(&i915->drm, "Memory configuration is symmetric? %s\n",
369 str_yes_no(dram_info->symmetric_memory));
374 static enum intel_dram_type
375 skl_get_dram_type(struct drm_i915_private *i915)
379 val = intel_uncore_read(&i915->uncore,
380 SKL_MAD_INTER_CHANNEL_0_0_0_MCHBAR_MCMAIN);
382 switch (val & SKL_DRAM_DDR_TYPE_MASK) {
383 case SKL_DRAM_DDR_TYPE_DDR3:
384 return INTEL_DRAM_DDR3;
385 case SKL_DRAM_DDR_TYPE_DDR4:
386 return INTEL_DRAM_DDR4;
387 case SKL_DRAM_DDR_TYPE_LPDDR3:
388 return INTEL_DRAM_LPDDR3;
389 case SKL_DRAM_DDR_TYPE_LPDDR4:
390 return INTEL_DRAM_LPDDR4;
393 return INTEL_DRAM_UNKNOWN;
398 skl_get_dram_info(struct drm_i915_private *i915)
400 struct dram_info *dram_info = &i915->dram_info;
403 dram_info->type = skl_get_dram_type(i915);
404 drm_dbg_kms(&i915->drm, "DRAM type: %s\n",
405 intel_dram_type_str(dram_info->type));
407 ret = skl_dram_get_channels_info(i915);
414 /* Returns Gb per DRAM device */
415 static int bxt_get_dimm_size(u32 val)
417 switch (val & BXT_DRAM_SIZE_MASK) {
418 case BXT_DRAM_SIZE_4GBIT:
420 case BXT_DRAM_SIZE_6GBIT:
422 case BXT_DRAM_SIZE_8GBIT:
424 case BXT_DRAM_SIZE_12GBIT:
426 case BXT_DRAM_SIZE_16GBIT:
434 static int bxt_get_dimm_width(u32 val)
436 if (!bxt_get_dimm_size(val))
439 val = (val & BXT_DRAM_WIDTH_MASK) >> BXT_DRAM_WIDTH_SHIFT;
444 static int bxt_get_dimm_ranks(u32 val)
446 if (!bxt_get_dimm_size(val))
449 switch (val & BXT_DRAM_RANK_MASK) {
450 case BXT_DRAM_RANK_SINGLE:
452 case BXT_DRAM_RANK_DUAL:
460 static enum intel_dram_type bxt_get_dimm_type(u32 val)
462 if (!bxt_get_dimm_size(val))
463 return INTEL_DRAM_UNKNOWN;
465 switch (val & BXT_DRAM_TYPE_MASK) {
466 case BXT_DRAM_TYPE_DDR3:
467 return INTEL_DRAM_DDR3;
468 case BXT_DRAM_TYPE_LPDDR3:
469 return INTEL_DRAM_LPDDR3;
470 case BXT_DRAM_TYPE_DDR4:
471 return INTEL_DRAM_DDR4;
472 case BXT_DRAM_TYPE_LPDDR4:
473 return INTEL_DRAM_LPDDR4;
476 return INTEL_DRAM_UNKNOWN;
480 static void bxt_get_dimm_info(struct dram_dimm_info *dimm, u32 val)
482 dimm->width = bxt_get_dimm_width(val);
483 dimm->ranks = bxt_get_dimm_ranks(val);
486 * Size in register is Gb per DRAM device. Convert to total
487 * Gb to match the way we report this for non-LP platforms.
489 dimm->size = bxt_get_dimm_size(val) * intel_dimm_num_devices(dimm);
492 static int bxt_get_dram_info(struct drm_i915_private *i915)
494 struct dram_info *dram_info = &i915->dram_info;
500 * Now read each DUNIT8/9/10/11 to check the rank of each dimms.
502 for (i = BXT_D_CR_DRP0_DUNIT_START; i <= BXT_D_CR_DRP0_DUNIT_END; i++) {
503 struct dram_dimm_info dimm;
504 enum intel_dram_type type;
506 val = intel_uncore_read(&i915->uncore, BXT_D_CR_DRP0_DUNIT(i));
507 if (val == 0xFFFFFFFF)
510 dram_info->num_channels++;
512 bxt_get_dimm_info(&dimm, val);
513 type = bxt_get_dimm_type(val);
515 drm_WARN_ON(&i915->drm, type != INTEL_DRAM_UNKNOWN &&
516 dram_info->type != INTEL_DRAM_UNKNOWN &&
517 dram_info->type != type);
519 drm_dbg_kms(&i915->drm,
520 "CH%u DIMM size: %u Gb, width: X%u, ranks: %u, type: %s\n",
521 i - BXT_D_CR_DRP0_DUNIT_START,
522 dimm.size, dimm.width, dimm.ranks,
523 intel_dram_type_str(type));
525 if (valid_ranks == 0)
526 valid_ranks = dimm.ranks;
528 if (type != INTEL_DRAM_UNKNOWN)
529 dram_info->type = type;
532 if (dram_info->type == INTEL_DRAM_UNKNOWN || valid_ranks == 0) {
533 drm_info(&i915->drm, "couldn't get memory information\n");
540 static int icl_pcode_read_mem_global_info(struct drm_i915_private *dev_priv)
542 struct dram_info *dram_info = &dev_priv->dram_info;
546 ret = snb_pcode_read(&dev_priv->uncore, ICL_PCODE_MEM_SUBSYSYSTEM_INFO |
547 ICL_PCODE_MEM_SS_READ_GLOBAL_INFO, &val, NULL);
551 if (GRAPHICS_VER(dev_priv) == 12) {
554 dram_info->type = INTEL_DRAM_DDR4;
557 dram_info->type = INTEL_DRAM_DDR5;
560 dram_info->type = INTEL_DRAM_LPDDR5;
563 dram_info->type = INTEL_DRAM_LPDDR4;
566 dram_info->type = INTEL_DRAM_DDR3;
569 dram_info->type = INTEL_DRAM_LPDDR3;
572 MISSING_CASE(val & 0xf);
578 dram_info->type = INTEL_DRAM_DDR4;
581 dram_info->type = INTEL_DRAM_DDR3;
584 dram_info->type = INTEL_DRAM_LPDDR3;
587 dram_info->type = INTEL_DRAM_LPDDR4;
590 MISSING_CASE(val & 0xf);
595 dram_info->num_channels = (val & 0xf0) >> 4;
596 dram_info->num_qgv_points = (val & 0xf00) >> 8;
597 dram_info->num_psf_gv_points = (val & 0x3000) >> 12;
602 static int gen11_get_dram_info(struct drm_i915_private *i915)
604 int ret = skl_get_dram_info(i915);
609 return icl_pcode_read_mem_global_info(i915);
612 static int gen12_get_dram_info(struct drm_i915_private *i915)
614 i915->dram_info.wm_lv_0_adjust_needed = false;
616 return icl_pcode_read_mem_global_info(i915);
619 static int xelpdp_get_dram_info(struct drm_i915_private *i915)
621 u32 val = intel_uncore_read(&i915->uncore, MTL_MEM_SS_INFO_GLOBAL);
622 struct dram_info *dram_info = &i915->dram_info;
624 switch (REG_FIELD_GET(MTL_DDR_TYPE_MASK, val)) {
626 dram_info->type = INTEL_DRAM_DDR4;
629 dram_info->type = INTEL_DRAM_DDR5;
632 dram_info->type = INTEL_DRAM_LPDDR5;
635 dram_info->type = INTEL_DRAM_LPDDR4;
638 dram_info->type = INTEL_DRAM_DDR3;
641 dram_info->type = INTEL_DRAM_LPDDR3;
648 dram_info->num_channels = REG_FIELD_GET(MTL_N_OF_POPULATED_CH_MASK, val);
649 dram_info->num_qgv_points = REG_FIELD_GET(MTL_N_OF_ENABLED_QGV_POINTS_MASK, val);
650 /* PSF GV points not supported in D14+ */
655 void intel_dram_detect(struct drm_i915_private *i915)
657 struct dram_info *dram_info = &i915->dram_info;
660 detect_mem_freq(i915);
662 if (GRAPHICS_VER(i915) < 9 || IS_DG2(i915) || !HAS_DISPLAY(i915))
666 * Assume level 0 watermark latency adjustment is needed until proven
667 * otherwise, this w/a is not needed by bxt/glk.
669 dram_info->wm_lv_0_adjust_needed = !IS_GEN9_LP(i915);
671 if (DISPLAY_VER(i915) >= 14)
672 ret = xelpdp_get_dram_info(i915);
673 else if (GRAPHICS_VER(i915) >= 12)
674 ret = gen12_get_dram_info(i915);
675 else if (GRAPHICS_VER(i915) >= 11)
676 ret = gen11_get_dram_info(i915);
677 else if (IS_GEN9_LP(i915))
678 ret = bxt_get_dram_info(i915);
680 ret = skl_get_dram_info(i915);
684 drm_dbg_kms(&i915->drm, "DRAM channels: %u\n", dram_info->num_channels);
686 drm_dbg_kms(&i915->drm, "Watermark level 0 adjustment needed: %s\n",
687 str_yes_no(dram_info->wm_lv_0_adjust_needed));
690 static u32 gen9_edram_size_mb(struct drm_i915_private *i915, u32 cap)
692 static const u8 ways[8] = { 4, 8, 12, 16, 16, 16, 16, 16 };
693 static const u8 sets[4] = { 1, 1, 2, 2 };
695 return EDRAM_NUM_BANKS(cap) *
696 ways[EDRAM_WAYS_IDX(cap)] *
697 sets[EDRAM_SETS_IDX(cap)];
700 void intel_dram_edram_detect(struct drm_i915_private *i915)
704 if (!(IS_HASWELL(i915) || IS_BROADWELL(i915) || GRAPHICS_VER(i915) >= 9))
707 edram_cap = __raw_uncore_read32(&i915->uncore, HSW_EDRAM_CAP);
709 /* NB: We can't write IDICR yet because we don't have gt funcs set up */
711 if (!(edram_cap & EDRAM_ENABLED))
715 * The needed capability bits for size calculation are not there with
716 * pre gen9 so return 128MB always.
718 if (GRAPHICS_VER(i915) < 9)
719 i915->edram_size_mb = 128;
721 i915->edram_size_mb = gen9_edram_size_mb(i915, edram_cap);
723 drm_info(&i915->drm, "Found %uMB of eDRAM\n", i915->edram_size_mb);