drivers/gpu/drm/i915/intel_device_info.c

   1 /*
   2  * Copyright © 2016 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  */
  24
  25 #include <linux/string_helpers.h>
  26
  27 #include <drm/drm_print.h>
  28 #include <drm/i915_pciids.h>
  29
  30 #include "display/intel_cdclk.h"
  31 #include "display/intel_de.h"
  32 #include "display/intel_display.h"
  33 #include "gt/intel_gt_regs.h"
  34 #include "i915_drv.h"
  35 #include "i915_reg.h"
  36 #include "i915_utils.h"
  37 #include "intel_device_info.h"
  38
  39 #define PLATFORM_NAME(x) [INTEL_##x] = #x
  40 static const char * const platform_names[] = {
  41         PLATFORM_NAME(I830),
  42         PLATFORM_NAME(I845G),
  43         PLATFORM_NAME(I85X),
  44         PLATFORM_NAME(I865G),
  45         PLATFORM_NAME(I915G),
  46         PLATFORM_NAME(I915GM),
  47         PLATFORM_NAME(I945G),
  48         PLATFORM_NAME(I945GM),
  49         PLATFORM_NAME(G33),
  50         PLATFORM_NAME(PINEVIEW),
  51         PLATFORM_NAME(I965G),
  52         PLATFORM_NAME(I965GM),
  53         PLATFORM_NAME(G45),
  54         PLATFORM_NAME(GM45),
  55         PLATFORM_NAME(IRONLAKE),
  56         PLATFORM_NAME(SANDYBRIDGE),
  57         PLATFORM_NAME(IVYBRIDGE),
  58         PLATFORM_NAME(VALLEYVIEW),
  59         PLATFORM_NAME(HASWELL),
  60         PLATFORM_NAME(BROADWELL),
  61         PLATFORM_NAME(CHERRYVIEW),
  62         PLATFORM_NAME(SKYLAKE),
  63         PLATFORM_NAME(BROXTON),
  64         PLATFORM_NAME(KABYLAKE),
  65         PLATFORM_NAME(GEMINILAKE),
  66         PLATFORM_NAME(COFFEELAKE),
  67         PLATFORM_NAME(COMETLAKE),
  68         PLATFORM_NAME(ICELAKE),
  69         PLATFORM_NAME(ELKHARTLAKE),
  70         PLATFORM_NAME(JASPERLAKE),
  71         PLATFORM_NAME(TIGERLAKE),
  72         PLATFORM_NAME(ROCKETLAKE),
  73         PLATFORM_NAME(DG1),
  74         PLATFORM_NAME(ALDERLAKE_S),
  75         PLATFORM_NAME(ALDERLAKE_P),
  76         PLATFORM_NAME(XEHPSDV),
  77         PLATFORM_NAME(DG2),
  78         PLATFORM_NAME(PONTEVECCHIO),
  79         PLATFORM_NAME(METEORLAKE),
  80 };
  81 #undef PLATFORM_NAME
  82
  83 const char *intel_platform_name(enum intel_platform platform)
  84 {
  85         BUILD_BUG_ON(ARRAY_SIZE(platform_names) != INTEL_MAX_PLATFORMS);
  86
  87         if (WARN_ON_ONCE(platform >= ARRAY_SIZE(platform_names) ||
  88                          platform_names[platform] == NULL))
  89                 return "<unknown>";
  90
  91         return platform_names[platform];
  92 }
  93
  94 void intel_device_info_print(const struct intel_device_info *info,
  95                              const struct intel_runtime_info *runtime,
  96                              struct drm_printer *p)
  97 {
  98         const struct intel_display_runtime_info *display_runtime =
  99                 &info->display->__runtime_defaults;
 100
 101         if (runtime->graphics.ip.rel)
 102                 drm_printf(p, "graphics version: %u.%02u\n",
 103                            runtime->graphics.ip.ver,
 104                            runtime->graphics.ip.rel);
 105         else
 106                 drm_printf(p, "graphics version: %u\n",
 107                            runtime->graphics.ip.ver);
 108
 109         if (runtime->media.ip.rel)
 110                 drm_printf(p, "media version: %u.%02u\n",
 111                            runtime->media.ip.ver,
 112                            runtime->media.ip.rel);
 113         else
 114                 drm_printf(p, "media version: %u\n",
 115                            runtime->media.ip.ver);
 116
 117         if (display_runtime->ip.rel)
 118                 drm_printf(p, "display version: %u.%02u\n",
 119                            display_runtime->ip.ver,
 120                            display_runtime->ip.rel);
 121         else
 122                 drm_printf(p, "display version: %u\n",
 123                            display_runtime->ip.ver);
 124
 125         drm_printf(p, "graphics stepping: %s\n", intel_step_name(runtime->step.graphics_step));
 126         drm_printf(p, "media stepping: %s\n", intel_step_name(runtime->step.media_step));
 127         drm_printf(p, "display stepping: %s\n", intel_step_name(runtime->step.display_step));
 128         drm_printf(p, "base die stepping: %s\n", intel_step_name(runtime->step.basedie_step));
 129
 130         drm_printf(p, "gt: %d\n", info->gt);
 131         drm_printf(p, "memory-regions: 0x%x\n", runtime->memory_regions);
 132         drm_printf(p, "page-sizes: 0x%x\n", runtime->page_sizes);
 133         drm_printf(p, "platform: %s\n", intel_platform_name(info->platform));
 134         drm_printf(p, "ppgtt-size: %d\n", runtime->ppgtt_size);
 135         drm_printf(p, "ppgtt-type: %d\n", runtime->ppgtt_type);
 136         drm_printf(p, "dma_mask_size: %u\n", info->dma_mask_size);
 137
 138 #define PRINT_FLAG(name) drm_printf(p, "%s: %s\n", #name, str_yes_no(info->name))
 139         DEV_INFO_FOR_EACH_FLAG(PRINT_FLAG);
 140 #undef PRINT_FLAG
 141
 142         drm_printf(p, "has_pooled_eu: %s\n", str_yes_no(runtime->has_pooled_eu));
 143
 144 #define PRINT_FLAG(name) drm_printf(p, "%s: %s\n", #name, str_yes_no(info->display->name))
 145         DEV_INFO_DISPLAY_FOR_EACH_FLAG(PRINT_FLAG);
 146 #undef PRINT_FLAG
 147
 148         drm_printf(p, "has_hdcp: %s\n", str_yes_no(display_runtime->has_hdcp));
 149         drm_printf(p, "has_dmc: %s\n", str_yes_no(display_runtime->has_dmc));
 150         drm_printf(p, "has_dsc: %s\n", str_yes_no(display_runtime->has_dsc));
 151
 152         drm_printf(p, "rawclk rate: %u kHz\n", runtime->rawclk_freq);
 153 }
 154
 155 #undef INTEL_VGA_DEVICE
 156 #define INTEL_VGA_DEVICE(id, info) (id)
 157
 158 static const u16 subplatform_ult_ids[] = {
 159         INTEL_HSW_ULT_GT1_IDS(0),
 160         INTEL_HSW_ULT_GT2_IDS(0),
 161         INTEL_HSW_ULT_GT3_IDS(0),
 162         INTEL_BDW_ULT_GT1_IDS(0),
 163         INTEL_BDW_ULT_GT2_IDS(0),
 164         INTEL_BDW_ULT_GT3_IDS(0),
 165         INTEL_BDW_ULT_RSVD_IDS(0),
 166         INTEL_SKL_ULT_GT1_IDS(0),
 167         INTEL_SKL_ULT_GT2_IDS(0),
 168         INTEL_SKL_ULT_GT3_IDS(0),
 169         INTEL_KBL_ULT_GT1_IDS(0),
 170         INTEL_KBL_ULT_GT2_IDS(0),
 171         INTEL_KBL_ULT_GT3_IDS(0),
 172         INTEL_CFL_U_GT2_IDS(0),
 173         INTEL_CFL_U_GT3_IDS(0),
 174         INTEL_WHL_U_GT1_IDS(0),
 175         INTEL_WHL_U_GT2_IDS(0),
 176         INTEL_WHL_U_GT3_IDS(0),
 177         INTEL_CML_U_GT1_IDS(0),
 178         INTEL_CML_U_GT2_IDS(0),
 179 };
 180
 181 static const u16 subplatform_ulx_ids[] = {
 182         INTEL_HSW_ULX_GT1_IDS(0),
 183         INTEL_HSW_ULX_GT2_IDS(0),
 184         INTEL_BDW_ULX_GT1_IDS(0),
 185         INTEL_BDW_ULX_GT2_IDS(0),
 186         INTEL_BDW_ULX_GT3_IDS(0),
 187         INTEL_BDW_ULX_RSVD_IDS(0),
 188         INTEL_SKL_ULX_GT1_IDS(0),
 189         INTEL_SKL_ULX_GT2_IDS(0),
 190         INTEL_KBL_ULX_GT1_IDS(0),
 191         INTEL_KBL_ULX_GT2_IDS(0),
 192         INTEL_AML_KBL_GT2_IDS(0),
 193         INTEL_AML_CFL_GT2_IDS(0),
 194 };
 195
 196 static const u16 subplatform_portf_ids[] = {
 197         INTEL_ICL_PORT_F_IDS(0),
 198 };
 199
 200 static const u16 subplatform_uy_ids[] = {
 201         INTEL_TGL_12_GT2_IDS(0),
 202 };
 203
 204 static const u16 subplatform_n_ids[] = {
 205         INTEL_ADLN_IDS(0),
 206 };
 207
 208 static const u16 subplatform_rpl_ids[] = {
 209         INTEL_RPLS_IDS(0),
 210         INTEL_RPLP_IDS(0),
 211 };
 212
 213 static const u16 subplatform_rplu_ids[] = {
 214         INTEL_RPLU_IDS(0),
 215 };
 216
 217 static const u16 subplatform_g10_ids[] = {
 218         INTEL_DG2_G10_IDS(0),
 219         INTEL_ATS_M150_IDS(0),
 220 };
 221
 222 static const u16 subplatform_g11_ids[] = {
 223         INTEL_DG2_G11_IDS(0),
 224         INTEL_ATS_M75_IDS(0),
 225 };
 226
 227 static const u16 subplatform_g12_ids[] = {
 228         INTEL_DG2_G12_IDS(0),
 229 };
 230
 231 static const u16 subplatform_m_ids[] = {
 232         INTEL_MTL_M_IDS(0),
 233 };
 234
 235 static const u16 subplatform_p_ids[] = {
 236         INTEL_MTL_P_IDS(0),
 237 };
 238
 239 static bool find_devid(u16 id, const u16 *p, unsigned int num)
 240 {
 241         for (; num; num--, p++) {
 242                 if (*p == id)
 243                         return true;
 244         }
 245
 246         return false;
 247 }
 248
 249 static void intel_device_info_subplatform_init(struct drm_i915_private *i915)
 250 {
 251         const struct intel_device_info *info = INTEL_INFO(i915);
 252         const struct intel_runtime_info *rinfo = RUNTIME_INFO(i915);
 253         const unsigned int pi = __platform_mask_index(rinfo, info->platform);
 254         const unsigned int pb = __platform_mask_bit(rinfo, info->platform);
 255         u16 devid = INTEL_DEVID(i915);
 256         u32 mask = 0;
 257
 258         /* Make sure IS_<platform> checks are working. */
 259         RUNTIME_INFO(i915)->platform_mask[pi] = BIT(pb);
 260
 261         /* Find and mark subplatform bits based on the PCI device id. */
 262         if (find_devid(devid, subplatform_ult_ids,
 263                        ARRAY_SIZE(subplatform_ult_ids))) {
 264                 mask = BIT(INTEL_SUBPLATFORM_ULT);
 265         } else if (find_devid(devid, subplatform_ulx_ids,
 266                               ARRAY_SIZE(subplatform_ulx_ids))) {
 267                 mask = BIT(INTEL_SUBPLATFORM_ULX);
 268                 if (IS_HASWELL(i915) || IS_BROADWELL(i915)) {
 269                         /* ULX machines are also considered ULT. */
 270                         mask |= BIT(INTEL_SUBPLATFORM_ULT);
 271                 }
 272         } else if (find_devid(devid, subplatform_portf_ids,
 273                               ARRAY_SIZE(subplatform_portf_ids))) {
 274                 mask = BIT(INTEL_SUBPLATFORM_PORTF);
 275         } else if (find_devid(devid, subplatform_uy_ids,
 276                            ARRAY_SIZE(subplatform_uy_ids))) {
 277                 mask = BIT(INTEL_SUBPLATFORM_UY);
 278         } else if (find_devid(devid, subplatform_n_ids,
 279                                 ARRAY_SIZE(subplatform_n_ids))) {
 280                 mask = BIT(INTEL_SUBPLATFORM_N);
 281         } else if (find_devid(devid, subplatform_rpl_ids,
 282                               ARRAY_SIZE(subplatform_rpl_ids))) {
 283                 mask = BIT(INTEL_SUBPLATFORM_RPL);
 284                 if (find_devid(devid, subplatform_rplu_ids,
 285                                ARRAY_SIZE(subplatform_rplu_ids)))
 286                         mask |= BIT(INTEL_SUBPLATFORM_RPLU);
 287         } else if (find_devid(devid, subplatform_g10_ids,
 288                               ARRAY_SIZE(subplatform_g10_ids))) {
 289                 mask = BIT(INTEL_SUBPLATFORM_G10);
 290         } else if (find_devid(devid, subplatform_g11_ids,
 291                               ARRAY_SIZE(subplatform_g11_ids))) {
 292                 mask = BIT(INTEL_SUBPLATFORM_G11);
 293         } else if (find_devid(devid, subplatform_g12_ids,
 294                               ARRAY_SIZE(subplatform_g12_ids))) {
 295                 mask = BIT(INTEL_SUBPLATFORM_G12);
 296         } else if (find_devid(devid, subplatform_m_ids,
 297                               ARRAY_SIZE(subplatform_m_ids))) {
 298                 mask = BIT(INTEL_SUBPLATFORM_M);
 299         } else if (find_devid(devid, subplatform_p_ids,
 300                               ARRAY_SIZE(subplatform_p_ids))) {
 301                 mask = BIT(INTEL_SUBPLATFORM_P);
 302         }
 303
 304         GEM_BUG_ON(mask & ~INTEL_SUBPLATFORM_MASK);
 305
 306         RUNTIME_INFO(i915)->platform_mask[pi] |= mask;
 307 }
 308
 309 static void ip_ver_read(struct drm_i915_private *i915, u32 offset, struct intel_ip_version *ip)
 310 {
 311         struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
 312         void __iomem *addr;
 313         u32 val;
 314         u8 expected_ver = ip->ver;
 315         u8 expected_rel = ip->rel;
 316
 317         addr = pci_iomap_range(pdev, 0, offset, sizeof(u32));
 318         if (drm_WARN_ON(&i915->drm, !addr))
 319                 return;
 320
 321         val = ioread32(addr);
 322         pci_iounmap(pdev, addr);
 323
 324         ip->ver = REG_FIELD_GET(GMD_ID_ARCH_MASK, val);
 325         ip->rel = REG_FIELD_GET(GMD_ID_RELEASE_MASK, val);
 326         ip->step = REG_FIELD_GET(GMD_ID_STEP, val);
 327
 328         /* Sanity check against expected versions from device info */
 329         if (IP_VER(ip->ver, ip->rel) < IP_VER(expected_ver, expected_rel))
 330                 drm_dbg(&i915->drm,
 331                         "Hardware reports GMD IP version %u.%u (REG[0x%x] = 0x%08x) but minimum expected is %u.%u\n",
 332                         ip->ver, ip->rel, offset, val, expected_ver, expected_rel);
 333 }
 334
 335 /*
 336  * Setup the graphics version for the current device.  This must be done before
 337  * any code that performs checks on GRAPHICS_VER or DISPLAY_VER, so this
 338  * function should be called very early in the driver initialization sequence.
 339  *
 340  * Regular MMIO access is not yet setup at the point this function is called so
 341  * we peek at the appropriate MMIO offset directly.  The GMD_ID register is
 342  * part of an 'always on' power well by design, so we don't need to worry about
 343  * forcewake while reading it.
 344  */
 345 static void intel_ipver_early_init(struct drm_i915_private *i915)
 346 {
 347         struct intel_runtime_info *runtime = RUNTIME_INFO(i915);
 348
 349         if (!HAS_GMD_ID(i915)) {
 350                 drm_WARN_ON(&i915->drm, RUNTIME_INFO(i915)->graphics.ip.ver > 12);
 351                 /*
 352                  * On older platforms, graphics and media share the same ip
 353                  * version and release.
 354                  */
 355                 RUNTIME_INFO(i915)->media.ip =
 356                         RUNTIME_INFO(i915)->graphics.ip;
 357                 return;
 358         }
 359
 360         ip_ver_read(i915, i915_mmio_reg_offset(GMD_ID_GRAPHICS),
 361                     &runtime->graphics.ip);
 362         /* Wa_22012778468 */
 363         if (runtime->graphics.ip.ver == 0x0 &&
 364             INTEL_INFO(i915)->platform == INTEL_METEORLAKE) {
 365                 RUNTIME_INFO(i915)->graphics.ip.ver = 12;
 366                 RUNTIME_INFO(i915)->graphics.ip.rel = 70;
 367         }
 368         ip_ver_read(i915, i915_mmio_reg_offset(GMD_ID_MEDIA),
 369                     &runtime->media.ip);
 370 }
 371
 372 /**
 373  * intel_device_info_runtime_init_early - initialize early runtime info
 374  * @i915: the i915 device
 375  *
 376  * Determine early intel_device_info fields at runtime. This function needs
 377  * to be called before the MMIO has been setup.
 378  */
 379 void intel_device_info_runtime_init_early(struct drm_i915_private *i915)
 380 {
 381         intel_ipver_early_init(i915);
 382         intel_device_info_subplatform_init(i915);
 383 }
 384
 385 /* FIXME: Remove this, and make device info a const pointer to rodata. */
 386 static struct intel_device_info *
 387 mkwrite_device_info(struct drm_i915_private *i915)
 388 {
 389         return (struct intel_device_info *)INTEL_INFO(i915);
 390 }
 391
 392 static const struct intel_display_device_info no_display = {};
 393
 394 /**
 395  * intel_device_info_runtime_init - initialize runtime info
 396  * @dev_priv: the i915 device
 397  *
 398  * Determine various intel_device_info fields at runtime.
 399  *
 400  * Use it when either:
 401  *   - it's judged too laborious to fill n static structures with the limit
 402  *     when a simple if statement does the job,
 403  *   - run-time checks (eg read fuse/strap registers) are needed.
 404  *
 405  * This function needs to be called:
 406  *   - after the MMIO has been setup as we are reading registers,
 407  *   - after the PCH has been detected,
 408  *   - before the first usage of the fields it can tweak.
 409  */
 410 void intel_device_info_runtime_init(struct drm_i915_private *dev_priv)
 411 {
 412         struct intel_device_info *info = mkwrite_device_info(dev_priv);
 413         struct intel_runtime_info *runtime = RUNTIME_INFO(dev_priv);
 414         struct intel_display_runtime_info *display_runtime =
 415                 DISPLAY_RUNTIME_INFO(dev_priv);
 416         enum pipe pipe;
 417
 418         /* Wa_14011765242: adl-s A0,A1 */
 419         if (IS_ADLS_DISPLAY_STEP(dev_priv, STEP_A0, STEP_A2))
 420                 for_each_pipe(dev_priv, pipe)
 421                         display_runtime->num_scalers[pipe] = 0;
 422         else if (DISPLAY_VER(dev_priv) >= 11) {
 423                 for_each_pipe(dev_priv, pipe)
 424                         display_runtime->num_scalers[pipe] = 2;
 425         } else if (DISPLAY_VER(dev_priv) >= 9) {
 426                 display_runtime->num_scalers[PIPE_A] = 2;
 427                 display_runtime->num_scalers[PIPE_B] = 2;
 428                 display_runtime->num_scalers[PIPE_C] = 1;
 429         }
 430
 431         BUILD_BUG_ON(BITS_PER_TYPE(intel_engine_mask_t) < I915_NUM_ENGINES);
 432
 433         if (DISPLAY_VER(dev_priv) >= 13 || HAS_D12_PLANE_MINIMIZATION(dev_priv))
 434                 for_each_pipe(dev_priv, pipe)
 435                         display_runtime->num_sprites[pipe] = 4;
 436         else if (DISPLAY_VER(dev_priv) >= 11)
 437                 for_each_pipe(dev_priv, pipe)
 438                         display_runtime->num_sprites[pipe] = 6;
 439         else if (DISPLAY_VER(dev_priv) == 10)
 440                 for_each_pipe(dev_priv, pipe)
 441                         display_runtime->num_sprites[pipe] = 3;
 442         else if (IS_BROXTON(dev_priv)) {
 443                 /*
 444                  * Skylake and Broxton currently don't expose the topmost plane as its
 445                  * use is exclusive with the legacy cursor and we only want to expose
 446                  * one of those, not both. Until we can safely expose the topmost plane
 447                  * as a DRM_PLANE_TYPE_CURSOR with all the features exposed/supported,
 448                  * we don't expose the topmost plane at all to prevent ABI breakage
 449                  * down the line.
 450                  */
 451
 452                 display_runtime->num_sprites[PIPE_A] = 2;
 453                 display_runtime->num_sprites[PIPE_B] = 2;
 454                 display_runtime->num_sprites[PIPE_C] = 1;
 455         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
 456                 for_each_pipe(dev_priv, pipe)
 457                         display_runtime->num_sprites[pipe] = 2;
 458         } else if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv)) {
 459                 for_each_pipe(dev_priv, pipe)
 460                         display_runtime->num_sprites[pipe] = 1;
 461         }
 462
 463         if (HAS_DISPLAY(dev_priv) &&
 464             (IS_DGFX(dev_priv) || DISPLAY_VER(dev_priv) >= 14) &&
 465             !(intel_de_read(dev_priv, GU_CNTL_PROTECTED) & DEPRESENT)) {
 466                 drm_info(&dev_priv->drm, "Display not present, disabling\n");
 467
 468                 display_runtime->pipe_mask = 0;
 469         }
 470
 471         if (HAS_DISPLAY(dev_priv) && IS_GRAPHICS_VER(dev_priv, 7, 8) &&
 472             HAS_PCH_SPLIT(dev_priv)) {
 473                 u32 fuse_strap = intel_de_read(dev_priv, FUSE_STRAP);
 474                 u32 sfuse_strap = intel_de_read(dev_priv, SFUSE_STRAP);
 475
 476                 /*
 477                  * SFUSE_STRAP is supposed to have a bit signalling the display
 478                  * is fused off. Unfortunately it seems that, at least in
 479                  * certain cases, fused off display means that PCH display
 480                  * reads don't land anywhere. In that case, we read 0s.
 481                  *
 482                  * On CPT/PPT, we can detect this case as SFUSE_STRAP_FUSE_LOCK
 483                  * should be set when taking over after the firmware.
 484                  */
 485                 if (fuse_strap & ILK_INTERNAL_DISPLAY_DISABLE ||
 486                     sfuse_strap & SFUSE_STRAP_DISPLAY_DISABLED ||
 487                     (HAS_PCH_CPT(dev_priv) &&
 488                      !(sfuse_strap & SFUSE_STRAP_FUSE_LOCK))) {
 489                         drm_info(&dev_priv->drm,
 490                                  "Display fused off, disabling\n");
 491                         display_runtime->pipe_mask = 0;
 492                 } else if (fuse_strap & IVB_PIPE_C_DISABLE) {
 493                         drm_info(&dev_priv->drm, "PipeC fused off\n");
 494                         display_runtime->pipe_mask &= ~BIT(PIPE_C);
 495                         display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_C);
 496                 }
 497         } else if (HAS_DISPLAY(dev_priv) && DISPLAY_VER(dev_priv) >= 9) {
 498                 u32 dfsm = intel_de_read(dev_priv, SKL_DFSM);
 499
 500                 if (dfsm & SKL_DFSM_PIPE_A_DISABLE) {
 501                         display_runtime->pipe_mask &= ~BIT(PIPE_A);
 502                         display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_A);
 503                         display_runtime->fbc_mask &= ~BIT(INTEL_FBC_A);
 504                 }
 505                 if (dfsm & SKL_DFSM_PIPE_B_DISABLE) {
 506                         display_runtime->pipe_mask &= ~BIT(PIPE_B);
 507                         display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_B);
 508                 }
 509                 if (dfsm & SKL_DFSM_PIPE_C_DISABLE) {
 510                         display_runtime->pipe_mask &= ~BIT(PIPE_C);
 511                         display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_C);
 512                 }
 513
 514                 if (DISPLAY_VER(dev_priv) >= 12 &&
 515                     (dfsm & TGL_DFSM_PIPE_D_DISABLE)) {
 516                         display_runtime->pipe_mask &= ~BIT(PIPE_D);
 517                         display_runtime->cpu_transcoder_mask &= ~BIT(TRANSCODER_D);
 518                 }
 519
 520                 if (dfsm & SKL_DFSM_DISPLAY_HDCP_DISABLE)
 521                         display_runtime->has_hdcp = 0;
 522
 523                 if (dfsm & SKL_DFSM_DISPLAY_PM_DISABLE)
 524                         display_runtime->fbc_mask = 0;
 525
 526                 if (DISPLAY_VER(dev_priv) >= 11 && (dfsm & ICL_DFSM_DMC_DISABLE))
 527                         display_runtime->has_dmc = 0;
 528
 529                 if (IS_DISPLAY_VER(dev_priv, 10, 12) &&
 530                     (dfsm & GLK_DFSM_DISPLAY_DSC_DISABLE))
 531                         display_runtime->has_dsc = 0;
 532         }
 533
 534         if (GRAPHICS_VER(dev_priv) == 6 && i915_vtd_active(dev_priv)) {
 535                 drm_info(&dev_priv->drm,
 536                          "Disabling ppGTT for VT-d support\n");
 537                 runtime->ppgtt_type = INTEL_PPGTT_NONE;
 538         }
 539
 540         runtime->rawclk_freq = intel_read_rawclk(dev_priv);
 541         drm_dbg(&dev_priv->drm, "rawclk rate: %d kHz\n", runtime->rawclk_freq);
 542
 543         if (!HAS_DISPLAY(dev_priv)) {
 544                 dev_priv->drm.driver_features &= ~(DRIVER_MODESET |
 545                                                    DRIVER_ATOMIC);
 546                 info->display = &no_display;
 547
 548                 display_runtime->cpu_transcoder_mask = 0;
 549                 memset(display_runtime->num_sprites, 0, sizeof(display_runtime->num_sprites));
 550                 memset(display_runtime->num_scalers, 0, sizeof(display_runtime->num_scalers));
 551                 display_runtime->fbc_mask = 0;
 552                 display_runtime->has_hdcp = false;
 553                 display_runtime->has_dmc = false;
 554                 display_runtime->has_dsc = false;
 555         }
 556
 557         /* Disable nuclear pageflip by default on pre-g4x */
 558         if (!dev_priv->params.nuclear_pageflip &&
 559             DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv))
 560                 dev_priv->drm.driver_features &= ~DRIVER_ATOMIC;
 561 }
 562
 563 /*
 564  * Set up device info and initial runtime info at driver create.
 565  *
 566  * Note: i915 is only an allocated blob of memory at this point.
 567  */
 568 void intel_device_info_driver_create(struct drm_i915_private *i915,
 569                                      u16 device_id,
 570                                      const struct intel_device_info *match_info)
 571 {
 572         struct intel_device_info *info;
 573         struct intel_runtime_info *runtime;
 574         u16 ver, rel, step;
 575
 576         /* Setup the write-once "constant" device info */
 577         info = mkwrite_device_info(i915);
 578         memcpy(info, match_info, sizeof(*info));
 579
 580         /* Initialize initial runtime info from static const data and pdev. */
 581         runtime = RUNTIME_INFO(i915);
 582         memcpy(runtime, &INTEL_INFO(i915)->__runtime, sizeof(*runtime));
 583
 584         /* Probe display support */
 585         info->display = intel_display_device_probe(i915, info->has_gmd_id,
 586                                                    &ver, &rel, &step);
 587         memcpy(DISPLAY_RUNTIME_INFO(i915),
 588                &DISPLAY_INFO(i915)->__runtime_defaults,
 589                sizeof(*DISPLAY_RUNTIME_INFO(i915)));
 590
 591         if (info->has_gmd_id) {
 592                 DISPLAY_RUNTIME_INFO(i915)->ip.ver = ver;
 593                 DISPLAY_RUNTIME_INFO(i915)->ip.rel = rel;
 594                 DISPLAY_RUNTIME_INFO(i915)->ip.step = step;
 595         }
 596
 597         runtime->device_id = device_id;
 598 }
 599
 600 void intel_driver_caps_print(const struct intel_driver_caps *caps,
 601                              struct drm_printer *p)
 602 {
 603         drm_printf(p, "Has logical contexts? %s\n",
 604                    str_yes_no(caps->has_logical_contexts));
 605         drm_printf(p, "scheduler: 0x%x\n", caps->scheduler);
 606 }