2 * SPDX-License-Identifier: MIT
4 * Copyright © 2008-2018 Intel Corporation
7 #ifndef _I915_GPU_ERROR_H_
8 #define _I915_GPU_ERROR_H_
10 #include <linux/atomic.h>
11 #include <linux/kref.h>
12 #include <linux/ktime.h>
13 #include <linux/sched.h>
15 #include <drm/drm_mm.h>
17 #include "gt/intel_engine.h"
18 #include "gt/intel_gt_types.h"
19 #include "gt/uc/intel_uc_fw.h"
21 #include "intel_device_info.h"
24 #include "i915_gem_gtt.h"
25 #include "i915_params.h"
26 #include "i915_scheduler.h"
28 struct drm_i915_private;
29 struct i915_vma_compress;
30 struct intel_engine_capture_vma;
31 struct intel_overlay_error_state;
33 struct i915_vma_coredump {
34 struct i915_vma_coredump *next;
43 struct list_head page_list;
46 struct i915_request_coredump {
53 struct i915_sched_attr sched_attr;
56 struct __guc_capture_parsed_output;
58 struct intel_engine_coredump {
59 const struct intel_engine_cs *engine;
65 /* position of active request inside the ring */
66 u32 rq_head, rq_post, rq_tail;
86 u32 rc_psmi; /* sleep state */
94 struct intel_instdone instdone;
96 /* GuC matched capture-lists info */
97 struct intel_guc_state_capture *guc_capture;
98 struct __guc_capture_parsed_output *guc_capture_node;
100 struct i915_gem_context_coredump {
101 char comm[TASK_COMM_LEN];
109 struct i915_sched_attr sched_attr;
113 struct i915_vma_coredump *vma;
115 struct i915_request_coredump execlist[EXECLIST_MAX_PORTS];
116 unsigned int num_ports;
126 struct intel_engine_coredump *next;
129 struct intel_ctb_coredump {
138 struct intel_gt_coredump {
139 const struct intel_gt *_gt;
143 struct intel_gt_info info;
145 /* Generic register state */
149 u32 gtier[6], ngtier;
151 u32 error; /* gen6+ */
152 u32 err_int; /* gen7 */
153 u32 fault_data0; /* gen8, gen9 */
154 u32 fault_data1; /* gen8, gen9 */
161 u32 aux_err; /* gen12 */
162 u32 gam_done; /* gen12 */
166 /* Display related */
168 u32 sfc_done[I915_MAX_SFC]; /* gen12 */
171 u64 fence[I915_MAX_NUM_FENCES];
173 struct intel_engine_coredump *engine;
175 struct intel_uc_coredump {
176 struct intel_uc_fw guc_fw;
177 struct intel_uc_fw huc_fw;
179 struct intel_ctb_coredump ctb[2];
180 struct i915_vma_coredump *vma_ctb;
181 struct i915_vma_coredump *vma_log;
188 struct intel_gt_coredump *next;
191 struct i915_gpu_coredump {
196 unsigned long capture;
198 struct drm_i915_private *i915;
200 struct intel_gt_coredump *gt;
210 struct intel_device_info device_info;
211 struct intel_runtime_info runtime_info;
212 struct intel_driver_caps driver_caps;
213 struct i915_params params;
215 struct intel_overlay_error_state *overlay;
217 struct scatterlist *sgl, *fit;
220 struct i915_gpu_error {
221 /* For reset and error_state handling. */
223 /* Protected by the above dev->gpu_error.lock. */
224 struct i915_gpu_coredump *first_error;
226 atomic_t pending_fb_pin;
228 /** Number of times the device has been reset (global) */
229 atomic_t reset_count;
231 /** Number of times an engine has been reset */
232 atomic_t reset_engine_count[I915_NUM_ENGINES];
235 struct drm_i915_error_state_buf {
236 struct drm_i915_private *i915;
237 struct scatterlist *sgl, *cur, *end;
247 static inline u32 i915_reset_count(struct i915_gpu_error *error)
249 return atomic_read(&error->reset_count);
252 static inline u32 i915_reset_engine_count(struct i915_gpu_error *error,
253 const struct intel_engine_cs *engine)
255 return atomic_read(&error->reset_engine_count[engine->uabi_class]);
258 #define CORE_DUMP_FLAG_NONE 0x0
259 #define CORE_DUMP_FLAG_IS_GUC_CAPTURE BIT(0)
261 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) && IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)
262 void intel_klog_error_capture(struct intel_gt *gt,
263 intel_engine_mask_t engine_mask);
265 static inline void intel_klog_error_capture(struct intel_gt *gt,
266 intel_engine_mask_t engine_mask)
271 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
274 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...);
275 void intel_gpu_error_print_vma(struct drm_i915_error_state_buf *m,
276 const struct intel_engine_cs *engine,
277 const struct i915_vma_coredump *vma);
278 struct i915_vma_coredump *
279 intel_gpu_error_find_batch(const struct intel_engine_coredump *ee);
281 struct i915_gpu_coredump *i915_gpu_coredump(struct intel_gt *gt,
282 intel_engine_mask_t engine_mask, u32 dump_flags);
283 void i915_capture_error_state(struct intel_gt *gt,
284 intel_engine_mask_t engine_mask, u32 dump_flags);
286 struct i915_gpu_coredump *
287 i915_gpu_coredump_alloc(struct drm_i915_private *i915, gfp_t gfp);
289 struct intel_gt_coredump *
290 intel_gt_coredump_alloc(struct intel_gt *gt, gfp_t gfp, u32 dump_flags);
292 struct intel_engine_coredump *
293 intel_engine_coredump_alloc(struct intel_engine_cs *engine, gfp_t gfp, u32 dump_flags);
295 struct intel_engine_capture_vma *
296 intel_engine_coredump_add_request(struct intel_engine_coredump *ee,
297 struct i915_request *rq,
300 void intel_engine_coredump_add_vma(struct intel_engine_coredump *ee,
301 struct intel_engine_capture_vma *capture,
302 struct i915_vma_compress *compress);
304 struct i915_vma_compress *
305 i915_vma_capture_prepare(struct intel_gt_coredump *gt);
307 void i915_vma_capture_finish(struct intel_gt_coredump *gt,
308 struct i915_vma_compress *compress);
310 void i915_error_state_store(struct i915_gpu_coredump *error);
312 static inline struct i915_gpu_coredump *
313 i915_gpu_coredump_get(struct i915_gpu_coredump *gpu)
320 i915_gpu_coredump_copy_to_buffer(struct i915_gpu_coredump *error,
321 char *buf, loff_t offset, size_t count);
323 void __i915_gpu_coredump_free(struct kref *kref);
324 static inline void i915_gpu_coredump_put(struct i915_gpu_coredump *gpu)
327 kref_put(&gpu->ref, __i915_gpu_coredump_free);
330 struct i915_gpu_coredump *i915_first_error_state(struct drm_i915_private *i915);
331 void i915_reset_error_state(struct drm_i915_private *i915);
332 void i915_disable_error_state(struct drm_i915_private *i915, int err);
338 i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...)
343 i915_capture_error_state(struct intel_gt *gt, intel_engine_mask_t engine_mask, u32 dump_flags)
347 static inline struct i915_gpu_coredump *
348 i915_gpu_coredump_alloc(struct drm_i915_private *i915, gfp_t gfp)
353 static inline struct intel_gt_coredump *
354 intel_gt_coredump_alloc(struct intel_gt *gt, gfp_t gfp, u32 dump_flags)
359 static inline struct intel_engine_coredump *
360 intel_engine_coredump_alloc(struct intel_engine_cs *engine, gfp_t gfp, u32 dump_flags)
365 static inline struct intel_engine_capture_vma *
366 intel_engine_coredump_add_request(struct intel_engine_coredump *ee,
367 struct i915_request *rq,
374 intel_engine_coredump_add_vma(struct intel_engine_coredump *ee,
375 struct intel_engine_capture_vma *capture,
376 struct i915_vma_compress *compress)
380 static inline struct i915_vma_compress *
381 i915_vma_capture_prepare(struct intel_gt_coredump *gt)
387 i915_vma_capture_finish(struct intel_gt_coredump *gt,
388 struct i915_vma_compress *compress)
393 i915_error_state_store(struct i915_gpu_coredump *error)
397 static inline void i915_gpu_coredump_put(struct i915_gpu_coredump *gpu)
401 static inline struct i915_gpu_coredump *
402 i915_first_error_state(struct drm_i915_private *i915)
404 return ERR_PTR(-ENODEV);
407 static inline void i915_reset_error_state(struct drm_i915_private *i915)
411 static inline void i915_disable_error_state(struct drm_i915_private *i915,
416 #endif /* IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR) */
418 #endif /* _I915_GPU_ERROR_H_ */