drivers/gpu/drm/i915/i915_gpu_error.c

   1 /*
   2  * Copyright (c) 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <[email protected]>
  25  *    Keith Packard <[email protected]>
  26  *    Mika Kuoppala <[email protected]>
  27  *
  28  */
  29
  30 #include <linux/ascii85.h>
  31 #include <linux/highmem.h>
  32 #include <linux/nmi.h>
  33 #include <linux/pagevec.h>
  34 #include <linux/scatterlist.h>
  35 #include <linux/string_helpers.h>
  36 #include <linux/utsname.h>
  37 #include <linux/zlib.h>
  38
  39 #include <drm/drm_cache.h>
  40 #include <drm/drm_print.h>
  41
  42 #include "display/intel_dmc.h"
  43 #include "display/intel_overlay.h"
  44
  45 #include "gem/i915_gem_context.h"
  46 #include "gem/i915_gem_lmem.h"
  47 #include "gt/intel_engine_regs.h"
  48 #include "gt/intel_gt.h"
  49 #include "gt/intel_gt_mcr.h"
  50 #include "gt/intel_gt_pm.h"
  51 #include "gt/intel_gt_regs.h"
  52 #include "gt/uc/intel_guc_capture.h"
  53
  54 #include "i915_driver.h"
  55 #include "i915_drv.h"
  56 #include "i915_gpu_error.h"
  57 #include "i915_memcpy.h"
  58 #include "i915_reg.h"
  59 #include "i915_scatterlist.h"
  60 #include "i915_utils.h"
  61
  62 #define ALLOW_FAIL (__GFP_KSWAPD_RECLAIM | __GFP_RETRY_MAYFAIL | __GFP_NOWARN)
  63 #define ATOMIC_MAYFAIL (GFP_ATOMIC | __GFP_NOWARN)
  64
  65 static void __sg_set_buf(struct scatterlist *sg,
  66                          void *addr, unsigned int len, loff_t it)
  67 {
  68         sg->page_link = (unsigned long)virt_to_page(addr);
  69         sg->offset = offset_in_page(addr);
  70         sg->length = len;
  71         sg->dma_address = it;
  72 }
  73
  74 static bool __i915_error_grow(struct drm_i915_error_state_buf *e, size_t len)
  75 {
  76         if (!len)
  77                 return false;
  78
  79         if (e->bytes + len + 1 <= e->size)
  80                 return true;
  81
  82         if (e->bytes) {
  83                 __sg_set_buf(e->cur++, e->buf, e->bytes, e->iter);
  84                 e->iter += e->bytes;
  85                 e->buf = NULL;
  86                 e->bytes = 0;
  87         }
  88
  89         if (e->cur == e->end) {
  90                 struct scatterlist *sgl;
  91
  92                 sgl = (typeof(sgl))__get_free_page(ALLOW_FAIL);
  93                 if (!sgl) {
  94                         e->err = -ENOMEM;
  95                         return false;
  96                 }
  97
  98                 if (e->cur) {
  99                         e->cur->offset = 0;
 100                         e->cur->length = 0;
 101                         e->cur->page_link =
 102                                 (unsigned long)sgl | SG_CHAIN;
 103                 } else {
 104                         e->sgl = sgl;
 105                 }
 106
 107                 e->cur = sgl;
 108                 e->end = sgl + SG_MAX_SINGLE_ALLOC - 1;
 109         }
 110
 111         e->size = ALIGN(len + 1, SZ_64K);
 112         e->buf = kmalloc(e->size, ALLOW_FAIL);
 113         if (!e->buf) {
 114                 e->size = PAGE_ALIGN(len + 1);
 115                 e->buf = kmalloc(e->size, GFP_KERNEL);
 116         }
 117         if (!e->buf) {
 118                 e->err = -ENOMEM;
 119                 return false;
 120         }
 121
 122         return true;
 123 }
 124
 125 __printf(2, 0)
 126 static void i915_error_vprintf(struct drm_i915_error_state_buf *e,
 127                                const char *fmt, va_list args)
 128 {
 129         va_list ap;
 130         int len;
 131
 132         if (e->err)
 133                 return;
 134
 135         va_copy(ap, args);
 136         len = vsnprintf(NULL, 0, fmt, ap);
 137         va_end(ap);
 138         if (len <= 0) {
 139                 e->err = len;
 140                 return;
 141         }
 142
 143         if (!__i915_error_grow(e, len))
 144                 return;
 145
 146         GEM_BUG_ON(e->bytes >= e->size);
 147         len = vscnprintf(e->buf + e->bytes, e->size - e->bytes, fmt, args);
 148         if (len < 0) {
 149                 e->err = len;
 150                 return;
 151         }
 152         e->bytes += len;
 153 }
 154
 155 static void i915_error_puts(struct drm_i915_error_state_buf *e, const char *str)
 156 {
 157         unsigned len;
 158
 159         if (e->err || !str)
 160                 return;
 161
 162         len = strlen(str);
 163         if (!__i915_error_grow(e, len))
 164                 return;
 165
 166         GEM_BUG_ON(e->bytes + len > e->size);
 167         memcpy(e->buf + e->bytes, str, len);
 168         e->bytes += len;
 169 }
 170
 171 #define err_printf(e, ...) i915_error_printf(e, __VA_ARGS__)
 172 #define err_puts(e, s) i915_error_puts(e, s)
 173
 174 static void __i915_printfn_error(struct drm_printer *p, struct va_format *vaf)
 175 {
 176         i915_error_vprintf(p->arg, vaf->fmt, *vaf->va);
 177 }
 178
 179 static inline struct drm_printer
 180 i915_error_printer(struct drm_i915_error_state_buf *e)
 181 {
 182         struct drm_printer p = {
 183                 .printfn = __i915_printfn_error,
 184                 .arg = e,
 185         };
 186         return p;
 187 }
 188
 189 /* single threaded page allocator with a reserved stash for emergencies */
 190 static void pool_fini(struct pagevec *pv)
 191 {
 192         pagevec_release(pv);
 193 }
 194
 195 static int pool_refill(struct pagevec *pv, gfp_t gfp)
 196 {
 197         while (pagevec_space(pv)) {
 198                 struct page *p;
 199
 200                 p = alloc_page(gfp);
 201                 if (!p)
 202                         return -ENOMEM;
 203
 204                 pagevec_add(pv, p);
 205         }
 206
 207         return 0;
 208 }
 209
 210 static int pool_init(struct pagevec *pv, gfp_t gfp)
 211 {
 212         int err;
 213
 214         pagevec_init(pv);
 215
 216         err = pool_refill(pv, gfp);
 217         if (err)
 218                 pool_fini(pv);
 219
 220         return err;
 221 }
 222
 223 static void *pool_alloc(struct pagevec *pv, gfp_t gfp)
 224 {
 225         struct page *p;
 226
 227         p = alloc_page(gfp);
 228         if (!p && pagevec_count(pv))
 229                 p = pv->pages[--pv->nr];
 230
 231         return p ? page_address(p) : NULL;
 232 }
 233
 234 static void pool_free(struct pagevec *pv, void *addr)
 235 {
 236         struct page *p = virt_to_page(addr);
 237
 238         if (pagevec_space(pv))
 239                 pagevec_add(pv, p);
 240         else
 241                 __free_page(p);
 242 }
 243
 244 #ifdef CONFIG_DRM_I915_COMPRESS_ERROR
 245
 246 struct i915_vma_compress {
 247         struct pagevec pool;
 248         struct z_stream_s zstream;
 249         void *tmp;
 250 };
 251
 252 static bool compress_init(struct i915_vma_compress *c)
 253 {
 254         struct z_stream_s *zstream = &c->zstream;
 255
 256         if (pool_init(&c->pool, ALLOW_FAIL))
 257                 return false;
 258
 259         zstream->workspace =
 260                 kmalloc(zlib_deflate_workspacesize(MAX_WBITS, MAX_MEM_LEVEL),
 261                         ALLOW_FAIL);
 262         if (!zstream->workspace) {
 263                 pool_fini(&c->pool);
 264                 return false;
 265         }
 266
 267         c->tmp = NULL;
 268         if (i915_has_memcpy_from_wc())
 269                 c->tmp = pool_alloc(&c->pool, ALLOW_FAIL);
 270
 271         return true;
 272 }
 273
 274 static bool compress_start(struct i915_vma_compress *c)
 275 {
 276         struct z_stream_s *zstream = &c->zstream;
 277         void *workspace = zstream->workspace;
 278
 279         memset(zstream, 0, sizeof(*zstream));
 280         zstream->workspace = workspace;
 281
 282         return zlib_deflateInit(zstream, Z_DEFAULT_COMPRESSION) == Z_OK;
 283 }
 284
 285 static void *compress_next_page(struct i915_vma_compress *c,
 286                                 struct i915_vma_coredump *dst)
 287 {
 288         void *page_addr;
 289         struct page *page;
 290
 291         page_addr = pool_alloc(&c->pool, ALLOW_FAIL);
 292         if (!page_addr)
 293                 return ERR_PTR(-ENOMEM);
 294
 295         page = virt_to_page(page_addr);
 296         list_add_tail(&page->lru, &dst->page_list);
 297         return page_addr;
 298 }
 299
 300 static int compress_page(struct i915_vma_compress *c,
 301                          void *src,
 302                          struct i915_vma_coredump *dst,
 303                          bool wc)
 304 {
 305         struct z_stream_s *zstream = &c->zstream;
 306
 307         zstream->next_in = src;
 308         if (wc && c->tmp && i915_memcpy_from_wc(c->tmp, src, PAGE_SIZE))
 309                 zstream->next_in = c->tmp;
 310         zstream->avail_in = PAGE_SIZE;
 311
 312         do {
 313                 if (zstream->avail_out == 0) {
 314                         zstream->next_out = compress_next_page(c, dst);
 315                         if (IS_ERR(zstream->next_out))
 316                                 return PTR_ERR(zstream->next_out);
 317
 318                         zstream->avail_out = PAGE_SIZE;
 319                 }
 320
 321                 if (zlib_deflate(zstream, Z_NO_FLUSH) != Z_OK)
 322                         return -EIO;
 323
 324                 cond_resched();
 325         } while (zstream->avail_in);
 326
 327         /* Fallback to uncompressed if we increase size? */
 328         if (0 && zstream->total_out > zstream->total_in)
 329                 return -E2BIG;
 330
 331         return 0;
 332 }
 333
 334 static int compress_flush(struct i915_vma_compress *c,
 335                           struct i915_vma_coredump *dst)
 336 {
 337         struct z_stream_s *zstream = &c->zstream;
 338
 339         do {
 340                 switch (zlib_deflate(zstream, Z_FINISH)) {
 341                 case Z_OK: /* more space requested */
 342                         zstream->next_out = compress_next_page(c, dst);
 343                         if (IS_ERR(zstream->next_out))
 344                                 return PTR_ERR(zstream->next_out);
 345
 346                         zstream->avail_out = PAGE_SIZE;
 347                         break;
 348
 349                 case Z_STREAM_END:
 350                         goto end;
 351
 352                 default: /* any error */
 353                         return -EIO;
 354                 }
 355         } while (1);
 356
 357 end:
 358         memset(zstream->next_out, 0, zstream->avail_out);
 359         dst->unused = zstream->avail_out;
 360         return 0;
 361 }
 362
 363 static void compress_finish(struct i915_vma_compress *c)
 364 {
 365         zlib_deflateEnd(&c->zstream);
 366 }
 367
 368 static void compress_fini(struct i915_vma_compress *c)
 369 {
 370         kfree(c->zstream.workspace);
 371         if (c->tmp)
 372                 pool_free(&c->pool, c->tmp);
 373         pool_fini(&c->pool);
 374 }
 375
 376 static void err_compression_marker(struct drm_i915_error_state_buf *m)
 377 {
 378         err_puts(m, ":");
 379 }
 380
 381 #else
 382
 383 struct i915_vma_compress {
 384         struct pagevec pool;
 385 };
 386
 387 static bool compress_init(struct i915_vma_compress *c)
 388 {
 389         return pool_init(&c->pool, ALLOW_FAIL) == 0;
 390 }
 391
 392 static bool compress_start(struct i915_vma_compress *c)
 393 {
 394         return true;
 395 }
 396
 397 static int compress_page(struct i915_vma_compress *c,
 398                          void *src,
 399                          struct i915_vma_coredump *dst,
 400                          bool wc)
 401 {
 402         void *ptr;
 403
 404         ptr = pool_alloc(&c->pool, ALLOW_FAIL);
 405         if (!ptr)
 406                 return -ENOMEM;
 407
 408         if (!(wc && i915_memcpy_from_wc(ptr, src, PAGE_SIZE)))
 409                 memcpy(ptr, src, PAGE_SIZE);
 410         list_add_tail(&virt_to_page(ptr)->lru, &dst->page_list);
 411         cond_resched();
 412
 413         return 0;
 414 }
 415
 416 static int compress_flush(struct i915_vma_compress *c,
 417                           struct i915_vma_coredump *dst)
 418 {
 419         return 0;
 420 }
 421
 422 static void compress_finish(struct i915_vma_compress *c)
 423 {
 424 }
 425
 426 static void compress_fini(struct i915_vma_compress *c)
 427 {
 428         pool_fini(&c->pool);
 429 }
 430
 431 static void err_compression_marker(struct drm_i915_error_state_buf *m)
 432 {
 433         err_puts(m, "~");
 434 }
 435
 436 #endif
 437
 438 static void error_print_instdone(struct drm_i915_error_state_buf *m,
 439                                  const struct intel_engine_coredump *ee)
 440 {
 441         int slice;
 442         int subslice;
 443         int iter;
 444
 445         err_printf(m, "  INSTDONE: 0x%08x\n",
 446                    ee->instdone.instdone);
 447
 448         if (ee->engine->class != RENDER_CLASS || GRAPHICS_VER(m->i915) <= 3)
 449                 return;
 450
 451         err_printf(m, "  SC_INSTDONE: 0x%08x\n",
 452                    ee->instdone.slice_common);
 453
 454         if (GRAPHICS_VER(m->i915) <= 6)
 455                 return;
 456
 457         for_each_ss_steering(iter, ee->engine->gt, slice, subslice)
 458                 err_printf(m, "  SAMPLER_INSTDONE[%d][%d]: 0x%08x\n",
 459                            slice, subslice,
 460                            ee->instdone.sampler[slice][subslice]);
 461
 462         for_each_ss_steering(iter, ee->engine->gt, slice, subslice)
 463                 err_printf(m, "  ROW_INSTDONE[%d][%d]: 0x%08x\n",
 464                            slice, subslice,
 465                            ee->instdone.row[slice][subslice]);
 466
 467         if (GRAPHICS_VER(m->i915) < 12)
 468                 return;
 469
 470         if (GRAPHICS_VER_FULL(m->i915) >= IP_VER(12, 55)) {
 471                 for_each_ss_steering(iter, ee->engine->gt, slice, subslice)
 472                         err_printf(m, "  GEOM_SVGUNIT_INSTDONE[%d][%d]: 0x%08x\n",
 473                                    slice, subslice,
 474                                    ee->instdone.geom_svg[slice][subslice]);
 475         }
 476
 477         err_printf(m, "  SC_INSTDONE_EXTRA: 0x%08x\n",
 478                    ee->instdone.slice_common_extra[0]);
 479         err_printf(m, "  SC_INSTDONE_EXTRA2: 0x%08x\n",
 480                    ee->instdone.slice_common_extra[1]);
 481 }
 482
 483 static void error_print_request(struct drm_i915_error_state_buf *m,
 484                                 const char *prefix,
 485                                 const struct i915_request_coredump *erq)
 486 {
 487         if (!erq->seqno)
 488                 return;
 489
 490         err_printf(m, "%s pid %d, seqno %8x:%08x%s%s, prio %d, head %08x, tail %08x\n",
 491                    prefix, erq->pid, erq->context, erq->seqno,
 492                    test_bit(DMA_FENCE_FLAG_SIGNALED_BIT,
 493                             &erq->flags) ? "!" : "",
 494                    test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT,
 495                             &erq->flags) ? "+" : "",
 496                    erq->sched_attr.priority,
 497                    erq->head, erq->tail);
 498 }
 499
 500 static void error_print_context(struct drm_i915_error_state_buf *m,
 501                                 const char *header,
 502                                 const struct i915_gem_context_coredump *ctx)
 503 {
 504         err_printf(m, "%s%s[%d] prio %d, guilty %d active %d, runtime total %lluns, avg %lluns\n",
 505                    header, ctx->comm, ctx->pid, ctx->sched_attr.priority,
 506                    ctx->guilty, ctx->active,
 507                    ctx->total_runtime, ctx->avg_runtime);
 508         err_printf(m, "  context timeline seqno %u\n", ctx->hwsp_seqno);
 509 }
 510
 511 static struct i915_vma_coredump *
 512 __find_vma(struct i915_vma_coredump *vma, const char *name)
 513 {
 514         while (vma) {
 515                 if (strcmp(vma->name, name) == 0)
 516                         return vma;
 517                 vma = vma->next;
 518         }
 519
 520         return NULL;
 521 }
 522
 523 struct i915_vma_coredump *
 524 intel_gpu_error_find_batch(const struct intel_engine_coredump *ee)
 525 {
 526         return __find_vma(ee->vma, "batch");
 527 }
 528
 529 static void error_print_engine(struct drm_i915_error_state_buf *m,
 530                                const struct intel_engine_coredump *ee)
 531 {
 532         struct i915_vma_coredump *batch;
 533         int n;
 534
 535         err_printf(m, "%s command stream:\n", ee->engine->name);
 536         err_printf(m, "  CCID:  0x%08x\n", ee->ccid);
 537         err_printf(m, "  START: 0x%08x\n", ee->start);
 538         err_printf(m, "  HEAD:  0x%08x [0x%08x]\n", ee->head, ee->rq_head);
 539         err_printf(m, "  TAIL:  0x%08x [0x%08x, 0x%08x]\n",
 540                    ee->tail, ee->rq_post, ee->rq_tail);
 541         err_printf(m, "  CTL:   0x%08x\n", ee->ctl);
 542         err_printf(m, "  MODE:  0x%08x\n", ee->mode);
 543         err_printf(m, "  HWS:   0x%08x\n", ee->hws);
 544         err_printf(m, "  ACTHD: 0x%08x %08x\n",
 545                    (u32)(ee->acthd>>32), (u32)ee->acthd);
 546         err_printf(m, "  IPEIR: 0x%08x\n", ee->ipeir);
 547         err_printf(m, "  IPEHR: 0x%08x\n", ee->ipehr);
 548         err_printf(m, "  ESR:   0x%08x\n", ee->esr);
 549
 550         error_print_instdone(m, ee);
 551
 552         batch = intel_gpu_error_find_batch(ee);
 553         if (batch) {
 554                 u64 start = batch->gtt_offset;
 555                 u64 end = start + batch->gtt_size;
 556
 557                 err_printf(m, "  batch: [0x%08x_%08x, 0x%08x_%08x]\n",
 558                            upper_32_bits(start), lower_32_bits(start),
 559                            upper_32_bits(end), lower_32_bits(end));
 560         }
 561         if (GRAPHICS_VER(m->i915) >= 4) {
 562                 err_printf(m, "  BBADDR: 0x%08x_%08x\n",
 563                            (u32)(ee->bbaddr>>32), (u32)ee->bbaddr);
 564                 err_printf(m, "  BB_STATE: 0x%08x\n", ee->bbstate);
 565                 err_printf(m, "  INSTPS: 0x%08x\n", ee->instps);
 566         }
 567         err_printf(m, "  INSTPM: 0x%08x\n", ee->instpm);
 568         err_printf(m, "  FADDR: 0x%08x %08x\n", upper_32_bits(ee->faddr),
 569                    lower_32_bits(ee->faddr));
 570         if (GRAPHICS_VER(m->i915) >= 6) {
 571                 err_printf(m, "  RC PSMI: 0x%08x\n", ee->rc_psmi);
 572                 err_printf(m, "  FAULT_REG: 0x%08x\n", ee->fault_reg);
 573         }
 574         if (GRAPHICS_VER(m->i915) >= 11) {
 575                 err_printf(m, "  NOPID: 0x%08x\n", ee->nopid);
 576                 err_printf(m, "  EXCC: 0x%08x\n", ee->excc);
 577                 err_printf(m, "  CMD_CCTL: 0x%08x\n", ee->cmd_cctl);
 578                 err_printf(m, "  CSCMDOP: 0x%08x\n", ee->cscmdop);
 579                 err_printf(m, "  CTX_SR_CTL: 0x%08x\n", ee->ctx_sr_ctl);
 580                 err_printf(m, "  DMA_FADDR_HI: 0x%08x\n", ee->dma_faddr_hi);
 581                 err_printf(m, "  DMA_FADDR_LO: 0x%08x\n", ee->dma_faddr_lo);
 582         }
 583         if (HAS_PPGTT(m->i915)) {
 584                 err_printf(m, "  GFX_MODE: 0x%08x\n", ee->vm_info.gfx_mode);
 585
 586                 if (GRAPHICS_VER(m->i915) >= 8) {
 587                         int i;
 588                         for (i = 0; i < 4; i++)
 589                                 err_printf(m, "  PDP%d: 0x%016llx\n",
 590                                            i, ee->vm_info.pdp[i]);
 591                 } else {
 592                         err_printf(m, "  PP_DIR_BASE: 0x%08x\n",
 593                                    ee->vm_info.pp_dir_base);
 594                 }
 595         }
 596
 597         for (n = 0; n < ee->num_ports; n++) {
 598                 err_printf(m, "  ELSP[%d]:", n);
 599                 error_print_request(m, " ", &ee->execlist[n]);
 600         }
 601 }
 602
 603 void i915_error_printf(struct drm_i915_error_state_buf *e, const char *f, ...)
 604 {
 605         va_list args;
 606
 607         va_start(args, f);
 608         i915_error_vprintf(e, f, args);
 609         va_end(args);
 610 }
 611
 612 void intel_gpu_error_print_vma(struct drm_i915_error_state_buf *m,
 613                                const struct intel_engine_cs *engine,
 614                                const struct i915_vma_coredump *vma)
 615 {
 616         char out[ASCII85_BUFSZ];
 617         struct page *page;
 618
 619         if (!vma)
 620                 return;
 621
 622         err_printf(m, "%s --- %s = 0x%08x %08x\n",
 623                    engine ? engine->name : "global", vma->name,
 624                    upper_32_bits(vma->gtt_offset),
 625                    lower_32_bits(vma->gtt_offset));
 626
 627         if (vma->gtt_page_sizes > I915_GTT_PAGE_SIZE_4K)
 628                 err_printf(m, "gtt_page_sizes = 0x%08x\n", vma->gtt_page_sizes);
 629
 630         err_compression_marker(m);
 631         list_for_each_entry(page, &vma->page_list, lru) {
 632                 int i, len;
 633                 const u32 *addr = page_address(page);
 634
 635                 len = PAGE_SIZE;
 636                 if (page == list_last_entry(&vma->page_list, typeof(*page), lru))
 637                         len -= vma->unused;
 638                 len = ascii85_encode_len(len);
 639
 640                 for (i = 0; i < len; i++)
 641                         err_puts(m, ascii85_encode(addr[i], out));
 642         }
 643         err_puts(m, "\n");
 644 }
 645
 646 static void err_print_capabilities(struct drm_i915_error_state_buf *m,
 647                                    struct i915_gpu_coredump *error)
 648 {
 649         struct drm_printer p = i915_error_printer(m);
 650
 651         intel_device_info_print(&error->device_info, &error->runtime_info, &p);
 652         intel_driver_caps_print(&error->driver_caps, &p);
 653 }
 654
 655 static void err_print_params(struct drm_i915_error_state_buf *m,
 656                              const struct i915_params *params)
 657 {
 658         struct drm_printer p = i915_error_printer(m);
 659
 660         i915_params_dump(params, &p);
 661 }
 662
 663 static void err_print_pciid(struct drm_i915_error_state_buf *m,
 664                             struct drm_i915_private *i915)
 665 {
 666         struct pci_dev *pdev = to_pci_dev(i915->drm.dev);
 667
 668         err_printf(m, "PCI ID: 0x%04x\n", pdev->device);
 669         err_printf(m, "PCI Revision: 0x%02x\n", pdev->revision);
 670         err_printf(m, "PCI Subsystem: %04x:%04x\n",
 671                    pdev->subsystem_vendor,
 672                    pdev->subsystem_device);
 673 }
 674
 675 static void err_print_guc_ctb(struct drm_i915_error_state_buf *m,
 676                               const char *name,
 677                               const struct intel_ctb_coredump *ctb)
 678 {
 679         if (!ctb->size)
 680                 return;
 681
 682         err_printf(m, "GuC %s CTB: raw: 0x%08X, 0x%08X/%08X, cached: 0x%08X/%08X, desc = 0x%08X, buf = 0x%08X x 0x%08X\n",
 683                    name, ctb->raw_status, ctb->raw_head, ctb->raw_tail,
 684                    ctb->head, ctb->tail, ctb->desc_offset, ctb->cmds_offset, ctb->size);
 685 }
 686
 687 static void err_print_uc(struct drm_i915_error_state_buf *m,
 688                          const struct intel_uc_coredump *error_uc)
 689 {
 690         struct drm_printer p = i915_error_printer(m);
 691
 692         intel_uc_fw_dump(&error_uc->guc_fw, &p);
 693         intel_uc_fw_dump(&error_uc->huc_fw, &p);
 694         err_printf(m, "GuC timestamp: 0x%08x\n", error_uc->guc.timestamp);
 695         intel_gpu_error_print_vma(m, NULL, error_uc->guc.vma_log);
 696         err_printf(m, "GuC CTB fence: %d\n", error_uc->guc.last_fence);
 697         err_print_guc_ctb(m, "Send", error_uc->guc.ctb + 0);
 698         err_print_guc_ctb(m, "Recv", error_uc->guc.ctb + 1);
 699         intel_gpu_error_print_vma(m, NULL, error_uc->guc.vma_ctb);
 700 }
 701
 702 static void err_free_sgl(struct scatterlist *sgl)
 703 {
 704         while (sgl) {
 705                 struct scatterlist *sg;
 706
 707                 for (sg = sgl; !sg_is_chain(sg); sg++) {
 708                         kfree(sg_virt(sg));
 709                         if (sg_is_last(sg))
 710                                 break;
 711                 }
 712
 713                 sg = sg_is_last(sg) ? NULL : sg_chain_ptr(sg);
 714                 free_page((unsigned long)sgl);
 715                 sgl = sg;
 716         }
 717 }
 718
 719 static void err_print_gt_info(struct drm_i915_error_state_buf *m,
 720                               struct intel_gt_coredump *gt)
 721 {
 722         struct drm_printer p = i915_error_printer(m);
 723
 724         intel_gt_info_print(&gt->info, &p);
 725         intel_sseu_print_topology(gt->_gt->i915, &gt->info.sseu, &p);
 726 }
 727
 728 static void err_print_gt_display(struct drm_i915_error_state_buf *m,
 729                                  struct intel_gt_coredump *gt)
 730 {
 731         err_printf(m, "IER: 0x%08x\n", gt->ier);
 732         err_printf(m, "DERRMR: 0x%08x\n", gt->derrmr);
 733 }
 734
 735 static void err_print_gt_global_nonguc(struct drm_i915_error_state_buf *m,
 736                                        struct intel_gt_coredump *gt)
 737 {
 738         int i;
 739
 740         err_printf(m, "GT awake: %s\n", str_yes_no(gt->awake));
 741         err_printf(m, "CS timestamp frequency: %u Hz, %d ns\n",
 742                    gt->clock_frequency, gt->clock_period_ns);
 743         err_printf(m, "EIR: 0x%08x\n", gt->eir);
 744         err_printf(m, "PGTBL_ER: 0x%08x\n", gt->pgtbl_er);
 745
 746         for (i = 0; i < gt->ngtier; i++)
 747                 err_printf(m, "GTIER[%d]: 0x%08x\n", i, gt->gtier[i]);
 748 }
 749
 750 static void err_print_gt_global(struct drm_i915_error_state_buf *m,
 751                                 struct intel_gt_coredump *gt)
 752 {
 753         err_printf(m, "FORCEWAKE: 0x%08x\n", gt->forcewake);
 754
 755         if (IS_GRAPHICS_VER(m->i915, 6, 11)) {
 756                 err_printf(m, "ERROR: 0x%08x\n", gt->error);
 757                 err_printf(m, "DONE_REG: 0x%08x\n", gt->done_reg);
 758         }
 759
 760         if (GRAPHICS_VER(m->i915) >= 8)
 761                 err_printf(m, "FAULT_TLB_DATA: 0x%08x 0x%08x\n",
 762                            gt->fault_data1, gt->fault_data0);
 763
 764         if (GRAPHICS_VER(m->i915) == 7)
 765                 err_printf(m, "ERR_INT: 0x%08x\n", gt->err_int);
 766
 767         if (IS_GRAPHICS_VER(m->i915, 8, 11))
 768                 err_printf(m, "GTT_CACHE_EN: 0x%08x\n", gt->gtt_cache);
 769
 770         if (GRAPHICS_VER(m->i915) == 12)
 771                 err_printf(m, "AUX_ERR_DBG: 0x%08x\n", gt->aux_err);
 772
 773         if (GRAPHICS_VER(m->i915) >= 12) {
 774                 int i;
 775
 776                 for (i = 0; i < I915_MAX_SFC; i++) {
 777                         /*
 778                          * SFC_DONE resides in the VD forcewake domain, so it
 779                          * only exists if the corresponding VCS engine is
 780                          * present.
 781                          */
 782                         if ((gt->_gt->info.sfc_mask & BIT(i)) == 0 ||
 783                             !HAS_ENGINE(gt->_gt, _VCS(i * 2)))
 784                                 continue;
 785
 786                         err_printf(m, "  SFC_DONE[%d]: 0x%08x\n", i,
 787                                    gt->sfc_done[i]);
 788                 }
 789
 790                 err_printf(m, "  GAM_DONE: 0x%08x\n", gt->gam_done);
 791         }
 792 }
 793
 794 static void err_print_gt_fences(struct drm_i915_error_state_buf *m,
 795                                 struct intel_gt_coredump *gt)
 796 {
 797         int i;
 798
 799         for (i = 0; i < gt->nfence; i++)
 800                 err_printf(m, "  fence[%d] = %08llx\n", i, gt->fence[i]);
 801 }
 802
 803 static void err_print_gt_engines(struct drm_i915_error_state_buf *m,
 804                                  struct intel_gt_coredump *gt)
 805 {
 806         const struct intel_engine_coredump *ee;
 807
 808         for (ee = gt->engine; ee; ee = ee->next) {
 809                 const struct i915_vma_coredump *vma;
 810
 811                 if (gt->uc && gt->uc->guc.is_guc_capture) {
 812                         if (ee->guc_capture_node)
 813                                 intel_guc_capture_print_engine_node(m, ee);
 814                         else
 815                                 err_printf(m, "  Missing GuC capture node for %s\n",
 816                                            ee->engine->name);
 817                 } else {
 818                         error_print_engine(m, ee);
 819                 }
 820
 821                 err_printf(m, "  hung: %u\n", ee->hung);
 822                 err_printf(m, "  engine reset count: %u\n", ee->reset_count);
 823                 error_print_context(m, "  Active context: ", &ee->context);
 824
 825                 for (vma = ee->vma; vma; vma = vma->next)
 826                         intel_gpu_error_print_vma(m, ee->engine, vma);
 827         }
 828
 829 }
 830
 831 static void __err_print_to_sgl(struct drm_i915_error_state_buf *m,
 832                                struct i915_gpu_coredump *error)
 833 {
 834         const struct intel_engine_coredump *ee;
 835         struct timespec64 ts;
 836
 837         if (*error->error_msg)
 838                 err_printf(m, "%s\n", error->error_msg);
 839         err_printf(m, "Kernel: %s %s\n",
 840                    init_utsname()->release,
 841                    init_utsname()->machine);
 842         err_printf(m, "Driver: %s\n", DRIVER_DATE);
 843         ts = ktime_to_timespec64(error->time);
 844         err_printf(m, "Time: %lld s %ld us\n",
 845                    (s64)ts.tv_sec, ts.tv_nsec / NSEC_PER_USEC);
 846         ts = ktime_to_timespec64(error->boottime);
 847         err_printf(m, "Boottime: %lld s %ld us\n",
 848                    (s64)ts.tv_sec, ts.tv_nsec / NSEC_PER_USEC);
 849         ts = ktime_to_timespec64(error->uptime);
 850         err_printf(m, "Uptime: %lld s %ld us\n",
 851                    (s64)ts.tv_sec, ts.tv_nsec / NSEC_PER_USEC);
 852         err_printf(m, "Capture: %lu jiffies; %d ms ago\n",
 853                    error->capture, jiffies_to_msecs(jiffies - error->capture));
 854
 855         for (ee = error->gt ? error->gt->engine : NULL; ee; ee = ee->next)
 856                 err_printf(m, "Active process (on ring %s): %s [%d]\n",
 857                            ee->engine->name,
 858                            ee->context.comm,
 859                            ee->context.pid);
 860
 861         err_printf(m, "Reset count: %u\n", error->reset_count);
 862         err_printf(m, "Suspend count: %u\n", error->suspend_count);
 863         err_printf(m, "Platform: %s\n", intel_platform_name(error->device_info.platform));
 864         err_printf(m, "Subplatform: 0x%x\n",
 865                    intel_subplatform(&error->runtime_info,
 866                                      error->device_info.platform));
 867         err_print_pciid(m, m->i915);
 868
 869         err_printf(m, "IOMMU enabled?: %d\n", error->iommu);
 870
 871         intel_dmc_print_error_state(m, m->i915);
 872
 873         err_printf(m, "RPM wakelock: %s\n", str_yes_no(error->wakelock));
 874         err_printf(m, "PM suspended: %s\n", str_yes_no(error->suspended));
 875
 876         if (error->gt) {
 877                 bool print_guc_capture = false;
 878
 879                 if (error->gt->uc && error->gt->uc->guc.is_guc_capture)
 880                         print_guc_capture = true;
 881
 882                 err_print_gt_display(m, error->gt);
 883                 err_print_gt_global_nonguc(m, error->gt);
 884                 err_print_gt_fences(m, error->gt);
 885
 886                 /*
 887                  * GuC dumped global, eng-class and eng-instance registers together
 888                  * as part of engine state dump so we print in err_print_gt_engines
 889                  */
 890                 if (!print_guc_capture)
 891                         err_print_gt_global(m, error->gt);
 892
 893                 err_print_gt_engines(m, error->gt);
 894
 895                 if (error->gt->uc)
 896                         err_print_uc(m, error->gt->uc);
 897
 898                 err_print_gt_info(m, error->gt);
 899         }
 900
 901         if (error->overlay)
 902                 intel_overlay_print_error_state(m, error->overlay);
 903
 904         err_print_capabilities(m, error);
 905         err_print_params(m, &error->params);
 906 }
 907
 908 static int err_print_to_sgl(struct i915_gpu_coredump *error)
 909 {
 910         struct drm_i915_error_state_buf m;
 911
 912         if (IS_ERR(error))
 913                 return PTR_ERR(error);
 914
 915         if (READ_ONCE(error->sgl))
 916                 return 0;
 917
 918         memset(&m, 0, sizeof(m));
 919         m.i915 = error->i915;
 920
 921         __err_print_to_sgl(&m, error);
 922
 923         if (m.buf) {
 924                 __sg_set_buf(m.cur++, m.buf, m.bytes, m.iter);
 925                 m.bytes = 0;
 926                 m.buf = NULL;
 927         }
 928         if (m.cur) {
 929                 GEM_BUG_ON(m.end < m.cur);
 930                 sg_mark_end(m.cur - 1);
 931         }
 932         GEM_BUG_ON(m.sgl && !m.cur);
 933
 934         if (m.err) {
 935                 err_free_sgl(m.sgl);
 936                 return m.err;
 937         }
 938
 939         if (cmpxchg(&error->sgl, NULL, m.sgl))
 940                 err_free_sgl(m.sgl);
 941
 942         return 0;
 943 }
 944
 945 ssize_t i915_gpu_coredump_copy_to_buffer(struct i915_gpu_coredump *error,
 946                                          char *buf, loff_t off, size_t rem)
 947 {
 948         struct scatterlist *sg;
 949         size_t count;
 950         loff_t pos;
 951         int err;
 952
 953         if (!error || !rem)
 954                 return 0;
 955
 956         err = err_print_to_sgl(error);
 957         if (err)
 958                 return err;
 959
 960         sg = READ_ONCE(error->fit);
 961         if (!sg || off < sg->dma_address)
 962                 sg = error->sgl;
 963         if (!sg)
 964                 return 0;
 965
 966         pos = sg->dma_address;
 967         count = 0;
 968         do {
 969                 size_t len, start;
 970
 971                 if (sg_is_chain(sg)) {
 972                         sg = sg_chain_ptr(sg);
 973                         GEM_BUG_ON(sg_is_chain(sg));
 974                 }
 975
 976                 len = sg->length;
 977                 if (pos + len <= off) {
 978                         pos += len;
 979                         continue;
 980                 }
 981
 982                 start = sg->offset;
 983                 if (pos < off) {
 984                         GEM_BUG_ON(off - pos > len);
 985                         len -= off - pos;
 986                         start += off - pos;
 987                         pos = off;
 988                 }
 989
 990                 len = min(len, rem);
 991                 GEM_BUG_ON(!len || len > sg->length);
 992
 993                 memcpy(buf, page_address(sg_page(sg)) + start, len);
 994
 995                 count += len;
 996                 pos += len;
 997
 998                 buf += len;
 999                 rem -= len;
1000                 if (!rem) {
1001                         WRITE_ONCE(error->fit, sg);
1002                         break;
1003                 }
1004         } while (!sg_is_last(sg++));
1005
1006         return count;
1007 }
1008
1009 static void i915_vma_coredump_free(struct i915_vma_coredump *vma)
1010 {
1011         while (vma) {
1012                 struct i915_vma_coredump *next = vma->next;
1013                 struct page *page, *n;
1014
1015                 list_for_each_entry_safe(page, n, &vma->page_list, lru) {
1016                         list_del_init(&page->lru);
1017                         __free_page(page);
1018                 }
1019
1020                 kfree(vma);
1021                 vma = next;
1022         }
1023 }
1024
1025 static void cleanup_params(struct i915_gpu_coredump *error)
1026 {
1027         i915_params_free(&error->params);
1028 }
1029
1030 static void cleanup_uc(struct intel_uc_coredump *uc)
1031 {
1032         kfree(uc->guc_fw.file_selected.path);
1033         kfree(uc->huc_fw.file_selected.path);
1034         kfree(uc->guc_fw.file_wanted.path);
1035         kfree(uc->huc_fw.file_wanted.path);
1036         i915_vma_coredump_free(uc->guc.vma_log);
1037         i915_vma_coredump_free(uc->guc.vma_ctb);
1038
1039         kfree(uc);
1040 }
1041
1042 static void cleanup_gt(struct intel_gt_coredump *gt)
1043 {
1044         while (gt->engine) {
1045                 struct intel_engine_coredump *ee = gt->engine;
1046
1047                 gt->engine = ee->next;
1048
1049                 i915_vma_coredump_free(ee->vma);
1050                 intel_guc_capture_free_node(ee);
1051                 kfree(ee);
1052         }
1053
1054         if (gt->uc)
1055                 cleanup_uc(gt->uc);
1056
1057         kfree(gt);
1058 }
1059
1060 void __i915_gpu_coredump_free(struct kref *error_ref)
1061 {
1062         struct i915_gpu_coredump *error =
1063                 container_of(error_ref, typeof(*error), ref);
1064
1065         while (error->gt) {
1066                 struct intel_gt_coredump *gt = error->gt;
1067
1068                 error->gt = gt->next;
1069                 cleanup_gt(gt);
1070         }
1071
1072         kfree(error->overlay);
1073
1074         cleanup_params(error);
1075
1076         err_free_sgl(error->sgl);
1077         kfree(error);
1078 }
1079
1080 static struct i915_vma_coredump *
1081 i915_vma_coredump_create(const struct intel_gt *gt,
1082                          const struct i915_vma_resource *vma_res,
1083                          struct i915_vma_compress *compress,
1084                          const char *name)
1085
1086 {
1087         struct i915_ggtt *ggtt = gt->ggtt;
1088         const u64 slot = ggtt->error_capture.start;
1089         struct i915_vma_coredump *dst;
1090         struct sgt_iter iter;
1091         int ret;
1092
1093         might_sleep();
1094
1095         if (!vma_res || !vma_res->bi.pages || !compress)
1096                 return NULL;
1097
1098         dst = kmalloc(sizeof(*dst), ALLOW_FAIL);
1099         if (!dst)
1100                 return NULL;
1101
1102         if (!compress_start(compress)) {
1103                 kfree(dst);
1104                 return NULL;
1105         }
1106
1107         INIT_LIST_HEAD(&dst->page_list);
1108         strcpy(dst->name, name);
1109         dst->next = NULL;
1110
1111         dst->gtt_offset = vma_res->start;
1112         dst->gtt_size = vma_res->node_size;
1113         dst->gtt_page_sizes = vma_res->page_sizes_gtt;
1114         dst->unused = 0;
1115
1116         ret = -EINVAL;
1117         if (drm_mm_node_allocated(&ggtt->error_capture)) {
1118                 void __iomem *s;
1119                 dma_addr_t dma;
1120
1121                 for_each_sgt_daddr(dma, iter, vma_res->bi.pages) {
1122                         mutex_lock(&ggtt->error_mutex);
1123                         if (ggtt->vm.raw_insert_page)
1124                                 ggtt->vm.raw_insert_page(&ggtt->vm, dma, slot,
1125                                                          i915_gem_get_pat_index(gt->i915,
1126                                                                                 I915_CACHE_NONE),
1127                                                          0);
1128                         else
1129                                 ggtt->vm.insert_page(&ggtt->vm, dma, slot,
1130                                                      i915_gem_get_pat_index(gt->i915,
1131                                                                             I915_CACHE_NONE),
1132                                                      0);
1133                         mb();
1134
1135                         s = io_mapping_map_wc(&ggtt->iomap, slot, PAGE_SIZE);
1136                         ret = compress_page(compress,
1137                                             (void  __force *)s, dst,
1138                                             true);
1139                         io_mapping_unmap(s);
1140
1141                         mb();
1142                         ggtt->vm.clear_range(&ggtt->vm, slot, PAGE_SIZE);
1143                         mutex_unlock(&ggtt->error_mutex);
1144                         if (ret)
1145                                 break;
1146                 }
1147         } else if (vma_res->bi.lmem) {
1148                 struct intel_memory_region *mem = vma_res->mr;
1149                 dma_addr_t dma;
1150
1151                 for_each_sgt_daddr(dma, iter, vma_res->bi.pages) {
1152                         dma_addr_t offset = dma - mem->region.start;
1153                         void __iomem *s;
1154
1155                         if (offset + PAGE_SIZE > mem->io_size) {
1156                                 ret = -EINVAL;
1157                                 break;
1158                         }
1159
1160                         s = io_mapping_map_wc(&mem->iomap, offset, PAGE_SIZE);
1161                         ret = compress_page(compress,
1162                                             (void __force *)s, dst,
1163                                             true);
1164                         io_mapping_unmap(s);
1165                         if (ret)
1166                                 break;
1167                 }
1168         } else {
1169                 struct page *page;
1170
1171                 for_each_sgt_page(page, iter, vma_res->bi.pages) {
1172                         void *s;
1173
1174                         drm_clflush_pages(&page, 1);
1175
1176                         s = kmap(page);
1177                         ret = compress_page(compress, s, dst, false);
1178                         kunmap(page);
1179
1180                         drm_clflush_pages(&page, 1);
1181
1182                         if (ret)
1183                                 break;
1184                 }
1185         }
1186
1187         if (ret || compress_flush(compress, dst)) {
1188                 struct page *page, *n;
1189
1190                 list_for_each_entry_safe_reverse(page, n, &dst->page_list, lru) {
1191                         list_del_init(&page->lru);
1192                         pool_free(&compress->pool, page_address(page));
1193                 }
1194
1195                 kfree(dst);
1196                 dst = NULL;
1197         }
1198         compress_finish(compress);
1199
1200         return dst;
1201 }
1202
1203 static void gt_record_fences(struct intel_gt_coredump *gt)
1204 {
1205         struct i915_ggtt *ggtt = gt->_gt->ggtt;
1206         struct intel_uncore *uncore = gt->_gt->uncore;
1207         int i;
1208
1209         if (GRAPHICS_VER(uncore->i915) >= 6) {
1210                 for (i = 0; i < ggtt->num_fences; i++)
1211                         gt->fence[i] =
1212                                 intel_uncore_read64(uncore,
1213                                                     FENCE_REG_GEN6_LO(i));
1214         } else if (GRAPHICS_VER(uncore->i915) >= 4) {
1215                 for (i = 0; i < ggtt->num_fences; i++)
1216                         gt->fence[i] =
1217                                 intel_uncore_read64(uncore,
1218                                                     FENCE_REG_965_LO(i));
1219         } else {
1220                 for (i = 0; i < ggtt->num_fences; i++)
1221                         gt->fence[i] =
1222                                 intel_uncore_read(uncore, FENCE_REG(i));
1223         }
1224         gt->nfence = i;
1225 }
1226
1227 static void engine_record_registers(struct intel_engine_coredump *ee)
1228 {
1229         const struct intel_engine_cs *engine = ee->engine;
1230         struct drm_i915_private *i915 = engine->i915;
1231
1232         if (GRAPHICS_VER(i915) >= 6) {
1233                 ee->rc_psmi = ENGINE_READ(engine, RING_PSMI_CTL);
1234
1235                 if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50))
1236                         ee->fault_reg = intel_gt_mcr_read_any(engine->gt,
1237                                                               XEHP_RING_FAULT_REG);
1238                 else if (GRAPHICS_VER(i915) >= 12)
1239                         ee->fault_reg = intel_uncore_read(engine->uncore,
1240                                                           GEN12_RING_FAULT_REG);
1241                 else if (GRAPHICS_VER(i915) >= 8)
1242                         ee->fault_reg = intel_uncore_read(engine->uncore,
1243                                                           GEN8_RING_FAULT_REG);
1244                 else
1245                         ee->fault_reg = GEN6_RING_FAULT_REG_READ(engine);
1246         }
1247
1248         if (GRAPHICS_VER(i915) >= 4) {
1249                 ee->esr = ENGINE_READ(engine, RING_ESR);
1250                 ee->faddr = ENGINE_READ(engine, RING_DMA_FADD);
1251                 ee->ipeir = ENGINE_READ(engine, RING_IPEIR);
1252                 ee->ipehr = ENGINE_READ(engine, RING_IPEHR);
1253                 ee->instps = ENGINE_READ(engine, RING_INSTPS);
1254                 ee->bbaddr = ENGINE_READ(engine, RING_BBADDR);
1255                 ee->ccid = ENGINE_READ(engine, CCID);
1256                 if (GRAPHICS_VER(i915) >= 8) {
1257                         ee->faddr |= (u64)ENGINE_READ(engine, RING_DMA_FADD_UDW) << 32;
1258                         ee->bbaddr |= (u64)ENGINE_READ(engine, RING_BBADDR_UDW) << 32;
1259                 }
1260                 ee->bbstate = ENGINE_READ(engine, RING_BBSTATE);
1261         } else {
1262                 ee->faddr = ENGINE_READ(engine, DMA_FADD_I8XX);
1263                 ee->ipeir = ENGINE_READ(engine, IPEIR);
1264                 ee->ipehr = ENGINE_READ(engine, IPEHR);
1265         }
1266
1267         if (GRAPHICS_VER(i915) >= 11) {
1268                 ee->cmd_cctl = ENGINE_READ(engine, RING_CMD_CCTL);
1269                 ee->cscmdop = ENGINE_READ(engine, RING_CSCMDOP);
1270                 ee->ctx_sr_ctl = ENGINE_READ(engine, RING_CTX_SR_CTL);
1271                 ee->dma_faddr_hi = ENGINE_READ(engine, RING_DMA_FADD_UDW);
1272                 ee->dma_faddr_lo = ENGINE_READ(engine, RING_DMA_FADD);
1273                 ee->nopid = ENGINE_READ(engine, RING_NOPID);
1274                 ee->excc = ENGINE_READ(engine, RING_EXCC);
1275         }
1276
1277         intel_engine_get_instdone(engine, &ee->instdone);
1278
1279         ee->instpm = ENGINE_READ(engine, RING_INSTPM);
1280         ee->acthd = intel_engine_get_active_head(engine);
1281         ee->start = ENGINE_READ(engine, RING_START);
1282         ee->head = ENGINE_READ(engine, RING_HEAD);
1283         ee->tail = ENGINE_READ(engine, RING_TAIL);
1284         ee->ctl = ENGINE_READ(engine, RING_CTL);
1285         if (GRAPHICS_VER(i915) > 2)
1286                 ee->mode = ENGINE_READ(engine, RING_MI_MODE);
1287
1288         if (!HWS_NEEDS_PHYSICAL(i915)) {
1289                 i915_reg_t mmio;
1290
1291                 if (GRAPHICS_VER(i915) == 7) {
1292                         switch (engine->id) {
1293                         default:
1294                                 MISSING_CASE(engine->id);
1295                                 fallthrough;
1296                         case RCS0:
1297                                 mmio = RENDER_HWS_PGA_GEN7;
1298                                 break;
1299                         case BCS0:
1300                                 mmio = BLT_HWS_PGA_GEN7;
1301                                 break;
1302                         case VCS0:
1303                                 mmio = BSD_HWS_PGA_GEN7;
1304                                 break;
1305                         case VECS0:
1306                                 mmio = VEBOX_HWS_PGA_GEN7;
1307                                 break;
1308                         }
1309                 } else if (GRAPHICS_VER(engine->i915) == 6) {
1310                         mmio = RING_HWS_PGA_GEN6(engine->mmio_base);
1311                 } else {
1312                         /* XXX: gen8 returns to sanity */
1313                         mmio = RING_HWS_PGA(engine->mmio_base);
1314                 }
1315
1316                 ee->hws = intel_uncore_read(engine->uncore, mmio);
1317         }
1318
1319         ee->reset_count = i915_reset_engine_count(&i915->gpu_error, engine);
1320
1321         if (HAS_PPGTT(i915)) {
1322                 int i;
1323
1324                 ee->vm_info.gfx_mode = ENGINE_READ(engine, RING_MODE_GEN7);
1325
1326                 if (GRAPHICS_VER(i915) == 6) {
1327                         ee->vm_info.pp_dir_base =
1328                                 ENGINE_READ(engine, RING_PP_DIR_BASE_READ);
1329                 } else if (GRAPHICS_VER(i915) == 7) {
1330                         ee->vm_info.pp_dir_base =
1331                                 ENGINE_READ(engine, RING_PP_DIR_BASE);
1332                 } else if (GRAPHICS_VER(i915) >= 8) {
1333                         u32 base = engine->mmio_base;
1334
1335                         for (i = 0; i < 4; i++) {
1336                                 ee->vm_info.pdp[i] =
1337                                         intel_uncore_read(engine->uncore,
1338                                                           GEN8_RING_PDP_UDW(base, i));
1339                                 ee->vm_info.pdp[i] <<= 32;
1340                                 ee->vm_info.pdp[i] |=
1341                                         intel_uncore_read(engine->uncore,
1342                                                           GEN8_RING_PDP_LDW(base, i));
1343                         }
1344                 }
1345         }
1346 }
1347
1348 static void record_request(const struct i915_request *request,
1349                            struct i915_request_coredump *erq)
1350 {
1351         erq->flags = request->fence.flags;
1352         erq->context = request->fence.context;
1353         erq->seqno = request->fence.seqno;
1354         erq->sched_attr = request->sched.attr;
1355         erq->head = request->head;
1356         erq->tail = request->tail;
1357
1358         erq->pid = 0;
1359         rcu_read_lock();
1360         if (!intel_context_is_closed(request->context)) {
1361                 const struct i915_gem_context *ctx;
1362
1363                 ctx = rcu_dereference(request->context->gem_context);
1364                 if (ctx)
1365                         erq->pid = pid_nr(ctx->pid);
1366         }
1367         rcu_read_unlock();
1368 }
1369
1370 static void engine_record_execlists(struct intel_engine_coredump *ee)
1371 {
1372         const struct intel_engine_execlists * const el = &ee->engine->execlists;
1373         struct i915_request * const *port = el->active;
1374         unsigned int n = 0;
1375
1376         while (*port)
1377                 record_request(*port++, &ee->execlist[n++]);
1378
1379         ee->num_ports = n;
1380 }
1381
1382 static bool record_context(struct i915_gem_context_coredump *e,
1383                            struct intel_context *ce)
1384 {
1385         struct i915_gem_context *ctx;
1386         struct task_struct *task;
1387         bool simulated;
1388
1389         rcu_read_lock();
1390         ctx = rcu_dereference(ce->gem_context);
1391         if (ctx && !kref_get_unless_zero(&ctx->ref))
1392                 ctx = NULL;
1393         rcu_read_unlock();
1394         if (!ctx)
1395                 return true;
1396
1397         rcu_read_lock();
1398         task = pid_task(ctx->pid, PIDTYPE_PID);
1399         if (task) {
1400                 strcpy(e->comm, task->comm);
1401                 e->pid = task->pid;
1402         }
1403         rcu_read_unlock();
1404
1405         e->sched_attr = ctx->sched;
1406         e->guilty = atomic_read(&ctx->guilty_count);
1407         e->active = atomic_read(&ctx->active_count);
1408         e->hwsp_seqno = (ce->timeline && ce->timeline->hwsp_seqno) ?
1409                                 *ce->timeline->hwsp_seqno : ~0U;
1410
1411         e->total_runtime = intel_context_get_total_runtime_ns(ce);
1412         e->avg_runtime = intel_context_get_avg_runtime_ns(ce);
1413
1414         simulated = i915_gem_context_no_error_capture(ctx);
1415
1416         i915_gem_context_put(ctx);
1417         return simulated;
1418 }
1419
1420 struct intel_engine_capture_vma {
1421         struct intel_engine_capture_vma *next;
1422         struct i915_vma_resource *vma_res;
1423         char name[16];
1424         bool lockdep_cookie;
1425 };
1426
1427 static struct intel_engine_capture_vma *
1428 capture_vma_snapshot(struct intel_engine_capture_vma *next,
1429                      struct i915_vma_resource *vma_res,
1430                      gfp_t gfp, const char *name)
1431 {
1432         struct intel_engine_capture_vma *c;
1433
1434         if (!vma_res)
1435                 return next;
1436
1437         c = kmalloc(sizeof(*c), gfp);
1438         if (!c)
1439                 return next;
1440
1441         if (!i915_vma_resource_hold(vma_res, &c->lockdep_cookie)) {
1442                 kfree(c);
1443                 return next;
1444         }
1445
1446         strcpy(c->name, name);
1447         c->vma_res = i915_vma_resource_get(vma_res);
1448
1449         c->next = next;
1450         return c;
1451 }
1452
1453 static struct intel_engine_capture_vma *
1454 capture_vma(struct intel_engine_capture_vma *next,
1455             struct i915_vma *vma,
1456             const char *name,
1457             gfp_t gfp)
1458 {
1459         if (!vma)
1460                 return next;
1461
1462         /*
1463          * If the vma isn't pinned, then the vma should be snapshotted
1464          * to a struct i915_vma_snapshot at command submission time.
1465          * Not here.
1466          */
1467         if (GEM_WARN_ON(!i915_vma_is_pinned(vma)))
1468                 return next;
1469
1470         next = capture_vma_snapshot(next, vma->resource, gfp, name);
1471
1472         return next;
1473 }
1474
1475 static struct intel_engine_capture_vma *
1476 capture_user(struct intel_engine_capture_vma *capture,
1477              const struct i915_request *rq,
1478              gfp_t gfp)
1479 {
1480         struct i915_capture_list *c;
1481
1482         for (c = rq->capture_list; c; c = c->next)
1483                 capture = capture_vma_snapshot(capture, c->vma_res, gfp,
1484                                                "user");
1485
1486         return capture;
1487 }
1488
1489 static void add_vma(struct intel_engine_coredump *ee,
1490                     struct i915_vma_coredump *vma)
1491 {
1492         if (vma) {
1493                 vma->next = ee->vma;
1494                 ee->vma = vma;
1495         }
1496 }
1497
1498 static struct i915_vma_coredump *
1499 create_vma_coredump(const struct intel_gt *gt, struct i915_vma *vma,
1500                     const char *name, struct i915_vma_compress *compress)
1501 {
1502         struct i915_vma_coredump *ret = NULL;
1503         struct i915_vma_resource *vma_res;
1504         bool lockdep_cookie;
1505
1506         if (!vma)
1507                 return NULL;
1508
1509         vma_res = vma->resource;
1510
1511         if (i915_vma_resource_hold(vma_res, &lockdep_cookie)) {
1512                 ret = i915_vma_coredump_create(gt, vma_res, compress, name);
1513                 i915_vma_resource_unhold(vma_res, lockdep_cookie);
1514         }
1515
1516         return ret;
1517 }
1518
1519 static void add_vma_coredump(struct intel_engine_coredump *ee,
1520                              const struct intel_gt *gt,
1521                              struct i915_vma *vma,
1522                              const char *name,
1523                              struct i915_vma_compress *compress)
1524 {
1525         add_vma(ee, create_vma_coredump(gt, vma, name, compress));
1526 }
1527
1528 struct intel_engine_coredump *
1529 intel_engine_coredump_alloc(struct intel_engine_cs *engine, gfp_t gfp, u32 dump_flags)
1530 {
1531         struct intel_engine_coredump *ee;
1532
1533         ee = kzalloc(sizeof(*ee), gfp);
1534         if (!ee)
1535                 return NULL;
1536
1537         ee->engine = engine;
1538
1539         if (!(dump_flags & CORE_DUMP_FLAG_IS_GUC_CAPTURE)) {
1540                 engine_record_registers(ee);
1541                 engine_record_execlists(ee);
1542         }
1543
1544         return ee;
1545 }
1546
1547 static struct intel_engine_capture_vma *
1548 engine_coredump_add_context(struct intel_engine_coredump *ee,
1549                             struct intel_context *ce,
1550                             gfp_t gfp)
1551 {
1552         struct intel_engine_capture_vma *vma = NULL;
1553
1554         ee->simulated |= record_context(&ee->context, ce);
1555         if (ee->simulated)
1556                 return NULL;
1557
1558         /*
1559          * We need to copy these to an anonymous buffer
1560          * as the simplest method to avoid being overwritten
1561          * by userspace.
1562          */
1563         vma = capture_vma(vma, ce->ring->vma, "ring", gfp);
1564         vma = capture_vma(vma, ce->state, "HW context", gfp);
1565
1566         return vma;
1567 }
1568
1569 struct intel_engine_capture_vma *
1570 intel_engine_coredump_add_request(struct intel_engine_coredump *ee,
1571                                   struct i915_request *rq,
1572                                   gfp_t gfp)
1573 {
1574         struct intel_engine_capture_vma *vma;
1575
1576         vma = engine_coredump_add_context(ee, rq->context, gfp);
1577         if (!vma)
1578                 return NULL;
1579
1580         /*
1581          * We need to copy these to an anonymous buffer
1582          * as the simplest method to avoid being overwritten
1583          * by userspace.
1584          */
1585         vma = capture_vma_snapshot(vma, rq->batch_res, gfp, "batch");
1586         vma = capture_user(vma, rq, gfp);
1587
1588         ee->rq_head = rq->head;
1589         ee->rq_post = rq->postfix;
1590         ee->rq_tail = rq->tail;
1591
1592         return vma;
1593 }
1594
1595 void
1596 intel_engine_coredump_add_vma(struct intel_engine_coredump *ee,
1597                               struct intel_engine_capture_vma *capture,
1598                               struct i915_vma_compress *compress)
1599 {
1600         const struct intel_engine_cs *engine = ee->engine;
1601
1602         while (capture) {
1603                 struct intel_engine_capture_vma *this = capture;
1604                 struct i915_vma_resource *vma_res = this->vma_res;
1605
1606                 add_vma(ee,
1607                         i915_vma_coredump_create(engine->gt, vma_res,
1608                                                  compress, this->name));
1609
1610                 i915_vma_resource_unhold(vma_res, this->lockdep_cookie);
1611                 i915_vma_resource_put(vma_res);
1612
1613                 capture = this->next;
1614                 kfree(this);
1615         }
1616
1617         add_vma_coredump(ee, engine->gt, engine->status_page.vma,
1618                          "HW Status", compress);
1619
1620         add_vma_coredump(ee, engine->gt, engine->wa_ctx.vma,
1621                          "WA context", compress);
1622 }
1623
1624 static struct intel_engine_coredump *
1625 capture_engine(struct intel_engine_cs *engine,
1626                struct i915_vma_compress *compress,
1627                u32 dump_flags)
1628 {
1629         struct intel_engine_capture_vma *capture = NULL;
1630         struct intel_engine_coredump *ee;
1631         struct intel_context *ce = NULL;
1632         struct i915_request *rq = NULL;
1633
1634         ee = intel_engine_coredump_alloc(engine, ALLOW_FAIL, dump_flags);
1635         if (!ee)
1636                 return NULL;
1637
1638         intel_engine_get_hung_entity(engine, &ce, &rq);
1639         if (rq && !i915_request_started(rq))
1640                 drm_info(&engine->gt->i915->drm, "Got hung context on %s with active request %lld:%lld [0x%04X] not yet started\n",
1641                          engine->name, rq->fence.context, rq->fence.seqno, ce->guc_id.id);
1642
1643         if (rq) {
1644                 capture = intel_engine_coredump_add_request(ee, rq, ATOMIC_MAYFAIL);
1645                 i915_request_put(rq);
1646         } else if (ce) {
1647                 capture = engine_coredump_add_context(ee, ce, ATOMIC_MAYFAIL);
1648         }
1649
1650         if (capture) {
1651                 intel_engine_coredump_add_vma(ee, capture, compress);
1652
1653                 if (dump_flags & CORE_DUMP_FLAG_IS_GUC_CAPTURE)
1654                         intel_guc_capture_get_matching_node(engine->gt, ee, ce);
1655         } else {
1656                 kfree(ee);
1657                 ee = NULL;
1658         }
1659
1660         return ee;
1661 }
1662
1663 static void
1664 gt_record_engines(struct intel_gt_coredump *gt,
1665                   intel_engine_mask_t engine_mask,
1666                   struct i915_vma_compress *compress,
1667                   u32 dump_flags)
1668 {
1669         struct intel_engine_cs *engine;
1670         enum intel_engine_id id;
1671
1672         for_each_engine(engine, gt->_gt, id) {
1673                 struct intel_engine_coredump *ee;
1674
1675                 /* Refill our page pool before entering atomic section */
1676                 pool_refill(&compress->pool, ALLOW_FAIL);
1677
1678                 ee = capture_engine(engine, compress, dump_flags);
1679                 if (!ee)
1680                         continue;
1681
1682                 ee->hung = engine->mask & engine_mask;
1683
1684                 gt->simulated |= ee->simulated;
1685                 if (ee->simulated) {
1686                         if (dump_flags & CORE_DUMP_FLAG_IS_GUC_CAPTURE)
1687                                 intel_guc_capture_free_node(ee);
1688                         kfree(ee);
1689                         continue;
1690                 }
1691
1692                 ee->next = gt->engine;
1693                 gt->engine = ee;
1694         }
1695 }
1696
1697 static void gt_record_guc_ctb(struct intel_ctb_coredump *saved,
1698                               const struct intel_guc_ct_buffer *ctb,
1699                               const void *blob_ptr, struct intel_guc *guc)
1700 {
1701         if (!ctb || !ctb->desc)
1702                 return;
1703
1704         saved->raw_status = ctb->desc->status;
1705         saved->raw_head = ctb->desc->head;
1706         saved->raw_tail = ctb->desc->tail;
1707         saved->head = ctb->head;
1708         saved->tail = ctb->tail;
1709         saved->size = ctb->size;
1710         saved->desc_offset = ((void *)ctb->desc) - blob_ptr;
1711         saved->cmds_offset = ((void *)ctb->cmds) - blob_ptr;
1712 }
1713
1714 static struct intel_uc_coredump *
1715 gt_record_uc(struct intel_gt_coredump *gt,
1716              struct i915_vma_compress *compress)
1717 {
1718         const struct intel_uc *uc = &gt->_gt->uc;
1719         struct intel_uc_coredump *error_uc;
1720
1721         error_uc = kzalloc(sizeof(*error_uc), ALLOW_FAIL);
1722         if (!error_uc)
1723                 return NULL;
1724
1725         memcpy(&error_uc->guc_fw, &uc->guc.fw, sizeof(uc->guc.fw));
1726         memcpy(&error_uc->huc_fw, &uc->huc.fw, sizeof(uc->huc.fw));
1727
1728         error_uc->guc_fw.file_selected.path = kstrdup(uc->guc.fw.file_selected.path, ALLOW_FAIL);
1729         error_uc->huc_fw.file_selected.path = kstrdup(uc->huc.fw.file_selected.path, ALLOW_FAIL);
1730         error_uc->guc_fw.file_wanted.path = kstrdup(uc->guc.fw.file_wanted.path, ALLOW_FAIL);
1731         error_uc->huc_fw.file_wanted.path = kstrdup(uc->huc.fw.file_wanted.path, ALLOW_FAIL);
1732
1733         /*
1734          * Save the GuC log and include a timestamp reference for converting the
1735          * log times to system times (in conjunction with the error->boottime and
1736          * gt->clock_frequency fields saved elsewhere).
1737          */
1738         error_uc->guc.timestamp = intel_uncore_read(gt->_gt->uncore, GUCPMTIMESTAMP);
1739         error_uc->guc.vma_log = create_vma_coredump(gt->_gt, uc->guc.log.vma,
1740                                                     "GuC log buffer", compress);
1741         error_uc->guc.vma_ctb = create_vma_coredump(gt->_gt, uc->guc.ct.vma,
1742                                                     "GuC CT buffer", compress);
1743         error_uc->guc.last_fence = uc->guc.ct.requests.last_fence;
1744         gt_record_guc_ctb(error_uc->guc.ctb + 0, &uc->guc.ct.ctbs.send,
1745                           uc->guc.ct.ctbs.send.desc, (struct intel_guc *)&uc->guc);
1746         gt_record_guc_ctb(error_uc->guc.ctb + 1, &uc->guc.ct.ctbs.recv,
1747                           uc->guc.ct.ctbs.send.desc, (struct intel_guc *)&uc->guc);
1748
1749         return error_uc;
1750 }
1751
1752 /* Capture display registers. */
1753 static void gt_record_display_regs(struct intel_gt_coredump *gt)
1754 {
1755         struct intel_uncore *uncore = gt->_gt->uncore;
1756         struct drm_i915_private *i915 = uncore->i915;
1757
1758         if (GRAPHICS_VER(i915) >= 6)
1759                 gt->derrmr = intel_uncore_read(uncore, DERRMR);
1760
1761         if (GRAPHICS_VER(i915) >= 8)
1762                 gt->ier = intel_uncore_read(uncore, GEN8_DE_MISC_IER);
1763         else if (IS_VALLEYVIEW(i915))
1764                 gt->ier = intel_uncore_read(uncore, VLV_IER);
1765         else if (HAS_PCH_SPLIT(i915))
1766                 gt->ier = intel_uncore_read(uncore, DEIER);
1767         else if (GRAPHICS_VER(i915) == 2)
1768                 gt->ier = intel_uncore_read16(uncore, GEN2_IER);
1769         else
1770                 gt->ier = intel_uncore_read(uncore, GEN2_IER);
1771 }
1772
1773 /* Capture all other registers that GuC doesn't capture. */
1774 static void gt_record_global_nonguc_regs(struct intel_gt_coredump *gt)
1775 {
1776         struct intel_uncore *uncore = gt->_gt->uncore;
1777         struct drm_i915_private *i915 = uncore->i915;
1778         int i;
1779
1780         if (IS_VALLEYVIEW(i915)) {
1781                 gt->gtier[0] = intel_uncore_read(uncore, GTIER);
1782                 gt->ngtier = 1;
1783         } else if (GRAPHICS_VER(i915) >= 11) {
1784                 gt->gtier[0] =
1785                         intel_uncore_read(uncore,
1786                                           GEN11_RENDER_COPY_INTR_ENABLE);
1787                 gt->gtier[1] =
1788                         intel_uncore_read(uncore, GEN11_VCS_VECS_INTR_ENABLE);
1789                 gt->gtier[2] =
1790                         intel_uncore_read(uncore, GEN11_GUC_SG_INTR_ENABLE);
1791                 gt->gtier[3] =
1792                         intel_uncore_read(uncore,
1793                                           GEN11_GPM_WGBOXPERF_INTR_ENABLE);
1794                 gt->gtier[4] =
1795                         intel_uncore_read(uncore,
1796                                           GEN11_CRYPTO_RSVD_INTR_ENABLE);
1797                 gt->gtier[5] =
1798                         intel_uncore_read(uncore,
1799                                           GEN11_GUNIT_CSME_INTR_ENABLE);
1800                 gt->ngtier = 6;
1801         } else if (GRAPHICS_VER(i915) >= 8) {
1802                 for (i = 0; i < 4; i++)
1803                         gt->gtier[i] =
1804                                 intel_uncore_read(uncore, GEN8_GT_IER(i));
1805                 gt->ngtier = 4;
1806         } else if (HAS_PCH_SPLIT(i915)) {
1807                 gt->gtier[0] = intel_uncore_read(uncore, GTIER);
1808                 gt->ngtier = 1;
1809         }
1810
1811         gt->eir = intel_uncore_read(uncore, EIR);
1812         gt->pgtbl_er = intel_uncore_read(uncore, PGTBL_ER);
1813 }
1814
1815 /*
1816  * Capture all registers that relate to workload submission.
1817  * NOTE: In GuC submission, when GuC resets an engine, it can dump these for us
1818  */
1819 static void gt_record_global_regs(struct intel_gt_coredump *gt)
1820 {
1821         struct intel_uncore *uncore = gt->_gt->uncore;
1822         struct drm_i915_private *i915 = uncore->i915;
1823         int i;
1824
1825         /*
1826          * General organization
1827          * 1. Registers specific to a single generation
1828          * 2. Registers which belong to multiple generations
1829          * 3. Feature specific registers.
1830          * 4. Everything else
1831          * Please try to follow the order.
1832          */
1833
1834         /* 1: Registers specific to a single generation */
1835         if (IS_VALLEYVIEW(i915))
1836                 gt->forcewake = intel_uncore_read_fw(uncore, FORCEWAKE_VLV);
1837
1838         if (GRAPHICS_VER(i915) == 7)
1839                 gt->err_int = intel_uncore_read(uncore, GEN7_ERR_INT);
1840
1841         if (GRAPHICS_VER_FULL(i915) >= IP_VER(12, 50)) {
1842                 gt->fault_data0 = intel_gt_mcr_read_any((struct intel_gt *)gt->_gt,
1843                                                         XEHP_FAULT_TLB_DATA0);
1844                 gt->fault_data1 = intel_gt_mcr_read_any((struct intel_gt *)gt->_gt,
1845                                                         XEHP_FAULT_TLB_DATA1);
1846         } else if (GRAPHICS_VER(i915) >= 12) {
1847                 gt->fault_data0 = intel_uncore_read(uncore,
1848                                                     GEN12_FAULT_TLB_DATA0);
1849                 gt->fault_data1 = intel_uncore_read(uncore,
1850                                                     GEN12_FAULT_TLB_DATA1);
1851         } else if (GRAPHICS_VER(i915) >= 8) {
1852                 gt->fault_data0 = intel_uncore_read(uncore,
1853                                                     GEN8_FAULT_TLB_DATA0);
1854                 gt->fault_data1 = intel_uncore_read(uncore,
1855                                                     GEN8_FAULT_TLB_DATA1);
1856         }
1857
1858         if (GRAPHICS_VER(i915) == 6) {
1859                 gt->forcewake = intel_uncore_read_fw(uncore, FORCEWAKE);
1860                 gt->gab_ctl = intel_uncore_read(uncore, GAB_CTL);
1861                 gt->gfx_mode = intel_uncore_read(uncore, GFX_MODE);
1862         }
1863
1864         /* 2: Registers which belong to multiple generations */
1865         if (GRAPHICS_VER(i915) >= 7)
1866                 gt->forcewake = intel_uncore_read_fw(uncore, FORCEWAKE_MT);
1867
1868         if (GRAPHICS_VER(i915) >= 6) {
1869                 if (GRAPHICS_VER(i915) < 12) {
1870                         gt->error = intel_uncore_read(uncore, ERROR_GEN6);
1871                         gt->done_reg = intel_uncore_read(uncore, DONE_REG);
1872                 }
1873         }
1874
1875         /* 3: Feature specific registers */
1876         if (IS_GRAPHICS_VER(i915, 6, 7)) {
1877                 gt->gam_ecochk = intel_uncore_read(uncore, GAM_ECOCHK);
1878                 gt->gac_eco = intel_uncore_read(uncore, GAC_ECO_BITS);
1879         }
1880
1881         if (IS_GRAPHICS_VER(i915, 8, 11))
1882                 gt->gtt_cache = intel_uncore_read(uncore, HSW_GTT_CACHE_EN);
1883
1884         if (GRAPHICS_VER(i915) == 12)
1885                 gt->aux_err = intel_uncore_read(uncore, GEN12_AUX_ERR_DBG);
1886
1887         if (GRAPHICS_VER(i915) >= 12) {
1888                 for (i = 0; i < I915_MAX_SFC; i++) {
1889                         /*
1890                          * SFC_DONE resides in the VD forcewake domain, so it
1891                          * only exists if the corresponding VCS engine is
1892                          * present.
1893                          */
1894                         if ((gt->_gt->info.sfc_mask & BIT(i)) == 0 ||
1895                             !HAS_ENGINE(gt->_gt, _VCS(i * 2)))
1896                                 continue;
1897
1898                         gt->sfc_done[i] =
1899                                 intel_uncore_read(uncore, GEN12_SFC_DONE(i));
1900                 }
1901
1902                 gt->gam_done = intel_uncore_read(uncore, GEN12_GAM_DONE);
1903         }
1904 }
1905
1906 static void gt_record_info(struct intel_gt_coredump *gt)
1907 {
1908         memcpy(&gt->info, &gt->_gt->info, sizeof(struct intel_gt_info));
1909         gt->clock_frequency = gt->_gt->clock_frequency;
1910         gt->clock_period_ns = gt->_gt->clock_period_ns;
1911 }
1912
1913 /*
1914  * Generate a semi-unique error code. The code is not meant to have meaning, The
1915  * code's only purpose is to try to prevent false duplicated bug reports by
1916  * grossly estimating a GPU error state.
1917  *
1918  * TODO Ideally, hashing the batchbuffer would be a very nice way to determine
1919  * the hang if we could strip the GTT offset information from it.
1920  *
1921  * It's only a small step better than a random number in its current form.
1922  */
1923 static u32 generate_ecode(const struct intel_engine_coredump *ee)
1924 {
1925         /*
1926          * IPEHR would be an ideal way to detect errors, as it's the gross
1927          * measure of "the command that hung." However, has some very common
1928          * synchronization commands which almost always appear in the case
1929          * strictly a client bug. Use instdone to differentiate those some.
1930          */
1931         return ee ? ee->ipehr ^ ee->instdone.instdone : 0;
1932 }
1933
1934 static const char *error_msg(struct i915_gpu_coredump *error)
1935 {
1936         struct intel_engine_coredump *first = NULL;
1937         unsigned int hung_classes = 0;
1938         struct intel_gt_coredump *gt;
1939         int len;
1940
1941         for (gt = error->gt; gt; gt = gt->next) {
1942                 struct intel_engine_coredump *cs;
1943
1944                 for (cs = gt->engine; cs; cs = cs->next) {
1945                         if (cs->hung) {
1946                                 hung_classes |= BIT(cs->engine->uabi_class);
1947                                 if (!first)
1948                                         first = cs;
1949                         }
1950                 }
1951         }
1952
1953         len = scnprintf(error->error_msg, sizeof(error->error_msg),
1954                         "GPU HANG: ecode %d:%x:%08x",
1955                         GRAPHICS_VER(error->i915), hung_classes,
1956                         generate_ecode(first));
1957         if (first && first->context.pid) {
1958                 /* Just show the first executing process, more is confusing */
1959                 len += scnprintf(error->error_msg + len,
1960                                  sizeof(error->error_msg) - len,
1961                                  ", in %s [%d]",
1962                                  first->context.comm, first->context.pid);
1963         }
1964
1965         return error->error_msg;
1966 }
1967
1968 static void capture_gen(struct i915_gpu_coredump *error)
1969 {
1970         struct drm_i915_private *i915 = error->i915;
1971
1972         error->wakelock = atomic_read(&i915->runtime_pm.wakeref_count);
1973         error->suspended = i915->runtime_pm.suspended;
1974
1975         error->iommu = i915_vtd_active(i915);
1976         error->reset_count = i915_reset_count(&i915->gpu_error);
1977         error->suspend_count = i915->suspend_count;
1978
1979         i915_params_copy(&error->params, &i915->params);
1980         memcpy(&error->device_info,
1981                INTEL_INFO(i915),
1982                sizeof(error->device_info));
1983         memcpy(&error->runtime_info,
1984                RUNTIME_INFO(i915),
1985                sizeof(error->runtime_info));
1986         error->driver_caps = i915->caps;
1987 }
1988
1989 struct i915_gpu_coredump *
1990 i915_gpu_coredump_alloc(struct drm_i915_private *i915, gfp_t gfp)
1991 {
1992         struct i915_gpu_coredump *error;
1993
1994         if (!i915->params.error_capture)
1995                 return NULL;
1996
1997         error = kzalloc(sizeof(*error), gfp);
1998         if (!error)
1999                 return NULL;
2000
2001         kref_init(&error->ref);
2002         error->i915 = i915;
2003
2004         error->time = ktime_get_real();
2005         error->boottime = ktime_get_boottime();
2006         error->uptime = ktime_sub(ktime_get(), to_gt(i915)->last_init_time);
2007         error->capture = jiffies;
2008
2009         capture_gen(error);
2010
2011         return error;
2012 }
2013
2014 #define DAY_AS_SECONDS(x) (24 * 60 * 60 * (x))
2015
2016 struct intel_gt_coredump *
2017 intel_gt_coredump_alloc(struct intel_gt *gt, gfp_t gfp, u32 dump_flags)
2018 {
2019         struct intel_gt_coredump *gc;
2020
2021         gc = kzalloc(sizeof(*gc), gfp);
2022         if (!gc)
2023                 return NULL;
2024
2025         gc->_gt = gt;
2026         gc->awake = intel_gt_pm_is_awake(gt);
2027
2028         gt_record_display_regs(gc);
2029         gt_record_global_nonguc_regs(gc);
2030
2031         /*
2032          * GuC dumps global, eng-class and eng-instance registers
2033          * (that can change as part of engine state during execution)
2034          * before an engine is reset due to a hung context.
2035          * GuC captures and reports all three groups of registers
2036          * together as a single set before the engine is reset.
2037          * Thus, if GuC triggered the context reset we retrieve
2038          * the register values as part of gt_record_engines.
2039          */
2040         if (!(dump_flags & CORE_DUMP_FLAG_IS_GUC_CAPTURE))
2041                 gt_record_global_regs(gc);
2042
2043         gt_record_fences(gc);
2044
2045         return gc;
2046 }
2047
2048 struct i915_vma_compress *
2049 i915_vma_capture_prepare(struct intel_gt_coredump *gt)
2050 {
2051         struct i915_vma_compress *compress;
2052
2053         compress = kmalloc(sizeof(*compress), ALLOW_FAIL);
2054         if (!compress)
2055                 return NULL;
2056
2057         if (!compress_init(compress)) {
2058                 kfree(compress);
2059                 return NULL;
2060         }
2061
2062         return compress;
2063 }
2064
2065 void i915_vma_capture_finish(struct intel_gt_coredump *gt,
2066                              struct i915_vma_compress *compress)
2067 {
2068         if (!compress)
2069                 return;
2070
2071         compress_fini(compress);
2072         kfree(compress);
2073 }
2074
2075 static struct i915_gpu_coredump *
2076 __i915_gpu_coredump(struct intel_gt *gt, intel_engine_mask_t engine_mask, u32 dump_flags)
2077 {
2078         struct drm_i915_private *i915 = gt->i915;
2079         struct i915_gpu_coredump *error;
2080
2081         /* Check if GPU capture has been disabled */
2082         error = READ_ONCE(i915->gpu_error.first_error);
2083         if (IS_ERR(error))
2084                 return error;
2085
2086         error = i915_gpu_coredump_alloc(i915, ALLOW_FAIL);
2087         if (!error)
2088                 return ERR_PTR(-ENOMEM);
2089
2090         error->gt = intel_gt_coredump_alloc(gt, ALLOW_FAIL, dump_flags);
2091         if (error->gt) {
2092                 struct i915_vma_compress *compress;
2093
2094                 compress = i915_vma_capture_prepare(error->gt);
2095                 if (!compress) {
2096                         kfree(error->gt);
2097                         kfree(error);
2098                         return ERR_PTR(-ENOMEM);
2099                 }
2100
2101                 if (INTEL_INFO(i915)->has_gt_uc) {
2102                         error->gt->uc = gt_record_uc(error->gt, compress);
2103                         if (error->gt->uc) {
2104                                 if (dump_flags & CORE_DUMP_FLAG_IS_GUC_CAPTURE)
2105                                         error->gt->uc->guc.is_guc_capture = true;
2106                                 else
2107                                         GEM_BUG_ON(error->gt->uc->guc.is_guc_capture);
2108                         }
2109                 }
2110
2111                 gt_record_info(error->gt);
2112                 gt_record_engines(error->gt, engine_mask, compress, dump_flags);
2113
2114
2115                 i915_vma_capture_finish(error->gt, compress);
2116
2117                 error->simulated |= error->gt->simulated;
2118         }
2119
2120         error->overlay = intel_overlay_capture_error_state(i915);
2121
2122         return error;
2123 }
2124
2125 struct i915_gpu_coredump *
2126 i915_gpu_coredump(struct intel_gt *gt, intel_engine_mask_t engine_mask, u32 dump_flags)
2127 {
2128         static DEFINE_MUTEX(capture_mutex);
2129         int ret = mutex_lock_interruptible(&capture_mutex);
2130         struct i915_gpu_coredump *dump;
2131
2132         if (ret)
2133                 return ERR_PTR(ret);
2134
2135         dump = __i915_gpu_coredump(gt, engine_mask, dump_flags);
2136         mutex_unlock(&capture_mutex);
2137
2138         return dump;
2139 }
2140
2141 void i915_error_state_store(struct i915_gpu_coredump *error)
2142 {
2143         struct drm_i915_private *i915;
2144         static bool warned;
2145
2146         if (IS_ERR_OR_NULL(error))
2147                 return;
2148
2149         i915 = error->i915;
2150         drm_info(&i915->drm, "%s\n", error_msg(error));
2151
2152         if (error->simulated ||
2153             cmpxchg(&i915->gpu_error.first_error, NULL, error))
2154                 return;
2155
2156         i915_gpu_coredump_get(error);
2157
2158         if (!xchg(&warned, true) &&
2159             ktime_get_real_seconds() - DRIVER_TIMESTAMP < DAY_AS_SECONDS(180)) {
2160                 pr_info("GPU hangs can indicate a bug anywhere in the entire gfx stack, including userspace.\n");
2161                 pr_info("Please file a _new_ bug report at https://gitlab.freedesktop.org/drm/intel/issues/new.\n");
2162                 pr_info("Please see https://gitlab.freedesktop.org/drm/intel/-/wikis/How-to-file-i915-bugs for details.\n");
2163                 pr_info("drm/i915 developers can then reassign to the right component if it's not a kernel issue.\n");
2164                 pr_info("The GPU crash dump is required to analyze GPU hangs, so please always attach it.\n");
2165                 pr_info("GPU crash dump saved to /sys/class/drm/card%d/error\n",
2166                         i915->drm.primary->index);
2167         }
2168 }
2169
2170 /**
2171  * i915_capture_error_state - capture an error record for later analysis
2172  * @gt: intel_gt which originated the hang
2173  * @engine_mask: hung engines
2174  * @dump_flags: dump flags
2175  *
2176  * Should be called when an error is detected (either a hang or an error
2177  * interrupt) to capture error state from the time of the error.  Fills
2178  * out a structure which becomes available in debugfs for user level tools
2179  * to pick up.
2180  */
2181 void i915_capture_error_state(struct intel_gt *gt,
2182                               intel_engine_mask_t engine_mask, u32 dump_flags)
2183 {
2184         struct i915_gpu_coredump *error;
2185
2186         error = i915_gpu_coredump(gt, engine_mask, dump_flags);
2187         if (IS_ERR(error)) {
2188                 cmpxchg(&gt->i915->gpu_error.first_error, NULL, error);
2189                 return;
2190         }
2191
2192         i915_error_state_store(error);
2193         i915_gpu_coredump_put(error);
2194 }
2195
2196 struct i915_gpu_coredump *
2197 i915_first_error_state(struct drm_i915_private *i915)
2198 {
2199         struct i915_gpu_coredump *error;
2200
2201         spin_lock_irq(&i915->gpu_error.lock);
2202         error = i915->gpu_error.first_error;
2203         if (!IS_ERR_OR_NULL(error))
2204                 i915_gpu_coredump_get(error);
2205         spin_unlock_irq(&i915->gpu_error.lock);
2206
2207         return error;
2208 }
2209
2210 void i915_reset_error_state(struct drm_i915_private *i915)
2211 {
2212         struct i915_gpu_coredump *error;
2213
2214         spin_lock_irq(&i915->gpu_error.lock);
2215         error = i915->gpu_error.first_error;
2216         if (error != ERR_PTR(-ENODEV)) /* if disabled, always disabled */
2217                 i915->gpu_error.first_error = NULL;
2218         spin_unlock_irq(&i915->gpu_error.lock);
2219
2220         if (!IS_ERR_OR_NULL(error))
2221                 i915_gpu_coredump_put(error);
2222 }
2223
2224 void i915_disable_error_state(struct drm_i915_private *i915, int err)
2225 {
2226         spin_lock_irq(&i915->gpu_error.lock);
2227         if (!i915->gpu_error.first_error)
2228                 i915->gpu_error.first_error = ERR_PTR(err);
2229         spin_unlock_irq(&i915->gpu_error.lock);
2230 }
2231
2232 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM)
2233 void intel_klog_error_capture(struct intel_gt *gt,
2234                               intel_engine_mask_t engine_mask)
2235 {
2236         static int g_count;
2237         struct drm_i915_private *i915 = gt->i915;
2238         struct i915_gpu_coredump *error;
2239         intel_wakeref_t wakeref;
2240         size_t buf_size = PAGE_SIZE * 128;
2241         size_t pos_err;
2242         char *buf, *ptr, *next;
2243         int l_count = g_count++;
2244         int line = 0;
2245
2246         /* Can't allocate memory during a reset */
2247         if (test_bit(I915_RESET_BACKOFF, &gt->reset.flags)) {
2248                 drm_err(&gt->i915->drm, "[Capture/%d.%d] Inside GT reset, skipping error capture :(\n",
2249                         l_count, line++);
2250                 return;
2251         }
2252
2253         error = READ_ONCE(i915->gpu_error.first_error);
2254         if (error) {
2255                 drm_err(&i915->drm, "[Capture/%d.%d] Clearing existing error capture first...\n",
2256                         l_count, line++);
2257                 i915_reset_error_state(i915);
2258         }
2259
2260         with_intel_runtime_pm(&i915->runtime_pm, wakeref)
2261                 error = i915_gpu_coredump(gt, engine_mask, CORE_DUMP_FLAG_NONE);
2262
2263         if (IS_ERR(error)) {
2264                 drm_err(&i915->drm, "[Capture/%d.%d] Failed to capture error capture: %ld!\n",
2265                         l_count, line++, PTR_ERR(error));
2266                 return;
2267         }
2268
2269         buf = kvmalloc(buf_size, GFP_KERNEL);
2270         if (!buf) {
2271                 drm_err(&i915->drm, "[Capture/%d.%d] Failed to allocate buffer for error capture!\n",
2272                         l_count, line++);
2273                 i915_gpu_coredump_put(error);
2274                 return;
2275         }
2276
2277         drm_info(&i915->drm, "[Capture/%d.%d] Dumping i915 error capture for %ps...\n",
2278                  l_count, line++, __builtin_return_address(0));
2279
2280         /* Largest string length safe to print via dmesg */
2281 #       define MAX_CHUNK        800
2282
2283         pos_err = 0;
2284         while (1) {
2285                 ssize_t got = i915_gpu_coredump_copy_to_buffer(error, buf, pos_err, buf_size - 1);
2286
2287                 if (got <= 0)
2288                         break;
2289
2290                 buf[got] = 0;
2291                 pos_err += got;
2292
2293                 ptr = buf;
2294                 while (got > 0) {
2295                         size_t count;
2296                         char tag[2];
2297
2298                         next = strnchr(ptr, got, '\n');
2299                         if (next) {
2300                                 count = next - ptr;
2301                                 *next = 0;
2302                                 tag[0] = '>';
2303                                 tag[1] = '<';
2304                         } else {
2305                                 count = got;
2306                                 tag[0] = '}';
2307                                 tag[1] = '{';
2308                         }
2309
2310                         if (count > MAX_CHUNK) {
2311                                 size_t pos;
2312                                 char *ptr2 = ptr;
2313
2314                                 for (pos = MAX_CHUNK; pos < count; pos += MAX_CHUNK) {
2315                                         char chr = ptr[pos];
2316
2317                                         ptr[pos] = 0;
2318                                         drm_info(&i915->drm, "[Capture/%d.%d] }%s{\n",
2319                                                  l_count, line++, ptr2);
2320                                         ptr[pos] = chr;
2321                                         ptr2 = ptr + pos;
2322
2323                                         /*
2324                                          * If spewing large amounts of data via a serial console,
2325                                          * this can be a very slow process. So be friendly and try
2326                                          * not to cause 'softlockup on CPU' problems.
2327                                          */
2328                                         cond_resched();
2329                                 }
2330
2331                                 if (ptr2 < (ptr + count))
2332                                         drm_info(&i915->drm, "[Capture/%d.%d] %c%s%c\n",
2333                                                  l_count, line++, tag[0], ptr2, tag[1]);
2334                                 else if (tag[0] == '>')
2335                                         drm_info(&i915->drm, "[Capture/%d.%d] ><\n",
2336                                                  l_count, line++);
2337                         } else {
2338                                 drm_info(&i915->drm, "[Capture/%d.%d] %c%s%c\n",
2339                                          l_count, line++, tag[0], ptr, tag[1]);
2340                         }
2341
2342                         ptr = next;
2343                         got -= count;
2344                         if (next) {
2345                                 ptr++;
2346                                 got--;
2347                         }
2348
2349                         /* As above. */
2350                         cond_resched();
2351                 }
2352
2353                 if (got)
2354                         drm_info(&i915->drm, "[Capture/%d.%d] Got %zd bytes remaining!\n",
2355                                  l_count, line++, got);
2356         }
2357
2358         kvfree(buf);
2359
2360         drm_info(&i915->drm, "[Capture/%d.%d] Dumped %zd bytes\n", l_count, line++, pos_err);
2361 }
2362 #endif