drivers/gpu/drm/i915/i915_driver.c

   1 /* i915_drv.c -- i830,i845,i855,i865,i915 driver -*- linux-c -*-
   2  */
   3 /*
   4  *
   5  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   6  * All Rights Reserved.
   7  *
   8  * Permission is hereby granted, free of charge, to any person obtaining a
   9  * copy of this software and associated documentation files (the
  10  * "Software"), to deal in the Software without restriction, including
  11  * without limitation the rights to use, copy, modify, merge, publish,
  12  * distribute, sub license, and/or sell copies of the Software, and to
  13  * permit persons to whom the Software is furnished to do so, subject to
  14  * the following conditions:
  15  *
  16  * The above copyright notice and this permission notice (including the
  17  * next paragraph) shall be included in all copies or substantial portions
  18  * of the Software.
  19  *
  20  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  21  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  22  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  23  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  24  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  25  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  26  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  27  *
  28  */
  29
  30 #include <linux/acpi.h>
  31 #include <linux/device.h>
  32 #include <linux/module.h>
  33 #include <linux/oom.h>
  34 #include <linux/pci.h>
  35 #include <linux/pm.h>
  36 #include <linux/pm_runtime.h>
  37 #include <linux/slab.h>
  38 #include <linux/string_helpers.h>
  39 #include <linux/vga_switcheroo.h>
  40 #include <linux/vt.h>
  41
  42 #include <drm/drm_aperture.h>
  43 #include <drm/drm_atomic_helper.h>
  44 #include <drm/drm_ioctl.h>
  45 #include <drm/drm_managed.h>
  46 #include <drm/drm_probe_helper.h>
  47
  48 #include "display/intel_acpi.h"
  49 #include "display/intel_bw.h"
  50 #include "display/intel_cdclk.h"
  51 #include "display/intel_display_driver.h"
  52 #include "display/intel_display_types.h"
  53 #include "display/intel_dmc.h"
  54 #include "display/intel_dp.h"
  55 #include "display/intel_dpt.h"
  56 #include "display/intel_fbdev.h"
  57 #include "display/intel_hotplug.h"
  58 #include "display/intel_overlay.h"
  59 #include "display/intel_pch_refclk.h"
  60 #include "display/intel_pipe_crc.h"
  61 #include "display/intel_pps.h"
  62 #include "display/intel_sprite.h"
  63 #include "display/intel_vga.h"
  64 #include "display/skl_watermark.h"
  65
  66 #include "gem/i915_gem_context.h"
  67 #include "gem/i915_gem_create.h"
  68 #include "gem/i915_gem_dmabuf.h"
  69 #include "gem/i915_gem_ioctls.h"
  70 #include "gem/i915_gem_mman.h"
  71 #include "gem/i915_gem_pm.h"
  72 #include "gt/intel_gt.h"
  73 #include "gt/intel_gt_pm.h"
  74 #include "gt/intel_rc6.h"
  75
  76 #include "pxp/intel_pxp.h"
  77 #include "pxp/intel_pxp_debugfs.h"
  78 #include "pxp/intel_pxp_pm.h"
  79
  80 #include "soc/intel_dram.h"
  81 #include "soc/intel_gmch.h"
  82
  83 #include "i915_debugfs.h"
  84 #include "i915_driver.h"
  85 #include "i915_drm_client.h"
  86 #include "i915_drv.h"
  87 #include "i915_file_private.h"
  88 #include "i915_getparam.h"
  89 #include "i915_hwmon.h"
  90 #include "i915_ioc32.h"
  91 #include "i915_ioctl.h"
  92 #include "i915_irq.h"
  93 #include "i915_memcpy.h"
  94 #include "i915_perf.h"
  95 #include "i915_query.h"
  96 #include "i915_suspend.h"
  97 #include "i915_switcheroo.h"
  98 #include "i915_sysfs.h"
  99 #include "i915_utils.h"
 100 #include "i915_vgpu.h"
 101 #include "intel_clock_gating.h"
 102 #include "intel_gvt.h"
 103 #include "intel_memory_region.h"
 104 #include "intel_pci_config.h"
 105 #include "intel_pcode.h"
 106 #include "intel_region_ttm.h"
 107 #include "vlv_suspend.h"
 108
 109 static const struct drm_driver i915_drm_driver;
 110
 111 static int i915_workqueues_init(struct drm_i915_private *dev_priv)
 112 {
 113         /*
 114          * The i915 workqueue is primarily used for batched retirement of
 115          * requests (and thus managing bo) once the task has been completed
 116          * by the GPU. i915_retire_requests() is called directly when we
 117          * need high-priority retirement, such as waiting for an explicit
 118          * bo.
 119          *
 120          * It is also used for periodic low-priority events, such as
 121          * idle-timers and recording error state.
 122          *
 123          * All tasks on the workqueue are expected to acquire the dev mutex
 124          * so there is no point in running more than one instance of the
 125          * workqueue at any time.  Use an ordered one.
 126          */
 127         dev_priv->wq = alloc_ordered_workqueue("i915", 0);
 128         if (dev_priv->wq == NULL)
 129                 goto out_err;
 130
 131         dev_priv->display.hotplug.dp_wq = alloc_ordered_workqueue("i915-dp", 0);
 132         if (dev_priv->display.hotplug.dp_wq == NULL)
 133                 goto out_free_wq;
 134
 135         return 0;
 136
 137 out_free_wq:
 138         destroy_workqueue(dev_priv->wq);
 139 out_err:
 140         drm_err(&dev_priv->drm, "Failed to allocate workqueues.\n");
 141
 142         return -ENOMEM;
 143 }
 144
 145 static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv)
 146 {
 147         destroy_workqueue(dev_priv->display.hotplug.dp_wq);
 148         destroy_workqueue(dev_priv->wq);
 149 }
 150
 151 /*
 152  * We don't keep the workarounds for pre-production hardware, so we expect our
 153  * driver to fail on these machines in one way or another. A little warning on
 154  * dmesg may help both the user and the bug triagers.
 155  *
 156  * Our policy for removing pre-production workarounds is to keep the
 157  * current gen workarounds as a guide to the bring-up of the next gen
 158  * (workarounds have a habit of persisting!). Anything older than that
 159  * should be removed along with the complications they introduce.
 160  */
 161 static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv)
 162 {
 163         bool pre = false;
 164
 165         pre |= IS_HSW_EARLY_SDV(dev_priv);
 166         pre |= IS_SKYLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x6;
 167         pre |= IS_BROXTON(dev_priv) && INTEL_REVID(dev_priv) < 0xA;
 168         pre |= IS_KABYLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x1;
 169         pre |= IS_GEMINILAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x3;
 170         pre |= IS_ICELAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x7;
 171         pre |= IS_TIGERLAKE(dev_priv) && INTEL_REVID(dev_priv) < 0x1;
 172         pre |= IS_DG1(dev_priv) && INTEL_REVID(dev_priv) < 0x1;
 173
 174         if (pre) {
 175                 drm_err(&dev_priv->drm, "This is a pre-production stepping. "
 176                           "It may not be fully functional.\n");
 177                 add_taint(TAINT_MACHINE_CHECK, LOCKDEP_STILL_OK);
 178         }
 179 }
 180
 181 static void sanitize_gpu(struct drm_i915_private *i915)
 182 {
 183         if (!INTEL_INFO(i915)->gpu_reset_clobbers_display) {
 184                 struct intel_gt *gt;
 185                 unsigned int i;
 186
 187                 for_each_gt(gt, i915, i)
 188                         __intel_gt_reset(gt, ALL_ENGINES);
 189         }
 190 }
 191
 192 /**
 193  * i915_driver_early_probe - setup state not requiring device access
 194  * @dev_priv: device private
 195  *
 196  * Initialize everything that is a "SW-only" state, that is state not
 197  * requiring accessing the device or exposing the driver via kernel internal
 198  * or userspace interfaces. Example steps belonging here: lock initialization,
 199  * system memory allocation, setting up device specific attributes and
 200  * function hooks not requiring accessing the device.
 201  */
 202 static int i915_driver_early_probe(struct drm_i915_private *dev_priv)
 203 {
 204         int ret = 0;
 205
 206         if (i915_inject_probe_failure(dev_priv))
 207                 return -ENODEV;
 208
 209         intel_device_info_runtime_init_early(dev_priv);
 210
 211         intel_step_init(dev_priv);
 212
 213         intel_uncore_mmio_debug_init_early(dev_priv);
 214
 215         spin_lock_init(&dev_priv->irq_lock);
 216         spin_lock_init(&dev_priv->gpu_error.lock);
 217         mutex_init(&dev_priv->display.backlight.lock);
 218
 219         mutex_init(&dev_priv->sb_lock);
 220         cpu_latency_qos_add_request(&dev_priv->sb_qos, PM_QOS_DEFAULT_VALUE);
 221
 222         mutex_init(&dev_priv->display.audio.mutex);
 223         mutex_init(&dev_priv->display.wm.wm_mutex);
 224         mutex_init(&dev_priv->display.pps.mutex);
 225         mutex_init(&dev_priv->display.hdcp.hdcp_mutex);
 226
 227         i915_memcpy_init_early(dev_priv);
 228         intel_runtime_pm_init_early(&dev_priv->runtime_pm);
 229
 230         ret = i915_workqueues_init(dev_priv);
 231         if (ret < 0)
 232                 return ret;
 233
 234         ret = vlv_suspend_init(dev_priv);
 235         if (ret < 0)
 236                 goto err_workqueues;
 237
 238         ret = intel_region_ttm_device_init(dev_priv);
 239         if (ret)
 240                 goto err_ttm;
 241
 242         ret = intel_root_gt_init_early(dev_priv);
 243         if (ret < 0)
 244                 goto err_rootgt;
 245
 246         i915_gem_init_early(dev_priv);
 247
 248         /* This must be called before any calls to HAS_PCH_* */
 249         intel_detect_pch(dev_priv);
 250
 251         intel_irq_init(dev_priv);
 252         intel_display_driver_early_probe(dev_priv);
 253         intel_clock_gating_hooks_init(dev_priv);
 254
 255         intel_detect_preproduction_hw(dev_priv);
 256
 257         return 0;
 258
 259 err_rootgt:
 260         intel_region_ttm_device_fini(dev_priv);
 261 err_ttm:
 262         vlv_suspend_cleanup(dev_priv);
 263 err_workqueues:
 264         i915_workqueues_cleanup(dev_priv);
 265         return ret;
 266 }
 267
 268 /**
 269  * i915_driver_late_release - cleanup the setup done in
 270  *                             i915_driver_early_probe()
 271  * @dev_priv: device private
 272  */
 273 static void i915_driver_late_release(struct drm_i915_private *dev_priv)
 274 {
 275         intel_irq_fini(dev_priv);
 276         intel_power_domains_cleanup(dev_priv);
 277         i915_gem_cleanup_early(dev_priv);
 278         intel_gt_driver_late_release_all(dev_priv);
 279         intel_region_ttm_device_fini(dev_priv);
 280         vlv_suspend_cleanup(dev_priv);
 281         i915_workqueues_cleanup(dev_priv);
 282
 283         cpu_latency_qos_remove_request(&dev_priv->sb_qos);
 284         mutex_destroy(&dev_priv->sb_lock);
 285
 286         i915_params_free(&dev_priv->params);
 287 }
 288
 289 /**
 290  * i915_driver_mmio_probe - setup device MMIO
 291  * @dev_priv: device private
 292  *
 293  * Setup minimal device state necessary for MMIO accesses later in the
 294  * initialization sequence. The setup here should avoid any other device-wide
 295  * side effects or exposing the driver via kernel internal or user space
 296  * interfaces.
 297  */
 298 static int i915_driver_mmio_probe(struct drm_i915_private *dev_priv)
 299 {
 300         struct intel_gt *gt;
 301         int ret, i;
 302
 303         if (i915_inject_probe_failure(dev_priv))
 304                 return -ENODEV;
 305
 306         ret = intel_gmch_bridge_setup(dev_priv);
 307         if (ret < 0)
 308                 return ret;
 309
 310         for_each_gt(gt, dev_priv, i) {
 311                 ret = intel_uncore_init_mmio(gt->uncore);
 312                 if (ret)
 313                         return ret;
 314
 315                 ret = drmm_add_action_or_reset(&dev_priv->drm,
 316                                                intel_uncore_fini_mmio,
 317                                                gt->uncore);
 318                 if (ret)
 319                         return ret;
 320         }
 321
 322         /* Try to make sure MCHBAR is enabled before poking at it */
 323         intel_gmch_bar_setup(dev_priv);
 324         intel_device_info_runtime_init(dev_priv);
 325
 326         for_each_gt(gt, dev_priv, i) {
 327                 ret = intel_gt_init_mmio(gt);
 328                 if (ret)
 329                         goto err_uncore;
 330         }
 331
 332         /* As early as possible, scrub existing GPU state before clobbering */
 333         sanitize_gpu(dev_priv);
 334
 335         return 0;
 336
 337 err_uncore:
 338         intel_gmch_bar_teardown(dev_priv);
 339
 340         return ret;
 341 }
 342
 343 /**
 344  * i915_driver_mmio_release - cleanup the setup done in i915_driver_mmio_probe()
 345  * @dev_priv: device private
 346  */
 347 static void i915_driver_mmio_release(struct drm_i915_private *dev_priv)
 348 {
 349         intel_gmch_bar_teardown(dev_priv);
 350 }
 351
 352 /**
 353  * i915_set_dma_info - set all relevant PCI dma info as configured for the
 354  * platform
 355  * @i915: valid i915 instance
 356  *
 357  * Set the dma max segment size, device and coherent masks.  The dma mask set
 358  * needs to occur before i915_ggtt_probe_hw.
 359  *
 360  * A couple of platforms have special needs.  Address them as well.
 361  *
 362  */
 363 static int i915_set_dma_info(struct drm_i915_private *i915)
 364 {
 365         unsigned int mask_size = INTEL_INFO(i915)->dma_mask_size;
 366         int ret;
 367
 368         GEM_BUG_ON(!mask_size);
 369
 370         /*
 371          * We don't have a max segment size, so set it to the max so sg's
 372          * debugging layer doesn't complain
 373          */
 374         dma_set_max_seg_size(i915->drm.dev, UINT_MAX);
 375
 376         ret = dma_set_mask(i915->drm.dev, DMA_BIT_MASK(mask_size));
 377         if (ret)
 378                 goto mask_err;
 379
 380         /* overlay on gen2 is broken and can't address above 1G */
 381         if (GRAPHICS_VER(i915) == 2)
 382                 mask_size = 30;
 383
 384         /*
 385          * 965GM sometimes incorrectly writes to hardware status page (HWS)
 386          * using 32bit addressing, overwriting memory if HWS is located
 387          * above 4GB.
 388          *
 389          * The documentation also mentions an issue with undefined
 390          * behaviour if any general state is accessed within a page above 4GB,
 391          * which also needs to be handled carefully.
 392          */
 393         if (IS_I965G(i915) || IS_I965GM(i915))
 394                 mask_size = 32;
 395
 396         ret = dma_set_coherent_mask(i915->drm.dev, DMA_BIT_MASK(mask_size));
 397         if (ret)
 398                 goto mask_err;
 399
 400         return 0;
 401
 402 mask_err:
 403         drm_err(&i915->drm, "Can't set DMA mask/consistent mask (%d)\n", ret);
 404         return ret;
 405 }
 406
 407 static int i915_pcode_init(struct drm_i915_private *i915)
 408 {
 409         struct intel_gt *gt;
 410         int id, ret;
 411
 412         for_each_gt(gt, i915, id) {
 413                 ret = intel_pcode_init(gt->uncore);
 414                 if (ret) {
 415                         drm_err(&gt->i915->drm, "gt%d: intel_pcode_init failed %d\n", id, ret);
 416                         return ret;
 417                 }
 418         }
 419
 420         return 0;
 421 }
 422
 423 /**
 424  * i915_driver_hw_probe - setup state requiring device access
 425  * @dev_priv: device private
 426  *
 427  * Setup state that requires accessing the device, but doesn't require
 428  * exposing the driver via kernel internal or userspace interfaces.
 429  */
 430 static int i915_driver_hw_probe(struct drm_i915_private *dev_priv)
 431 {
 432         struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
 433         struct pci_dev *root_pdev;
 434         int ret;
 435
 436         if (i915_inject_probe_failure(dev_priv))
 437                 return -ENODEV;
 438
 439         if (HAS_PPGTT(dev_priv)) {
 440                 if (intel_vgpu_active(dev_priv) &&
 441                     !intel_vgpu_has_full_ppgtt(dev_priv)) {
 442                         i915_report_error(dev_priv,
 443                                           "incompatible vGPU found, support for isolated ppGTT required\n");
 444                         return -ENXIO;
 445                 }
 446         }
 447
 448         if (HAS_EXECLISTS(dev_priv)) {
 449                 /*
 450                  * Older GVT emulation depends upon intercepting CSB mmio,
 451                  * which we no longer use, preferring to use the HWSP cache
 452                  * instead.
 453                  */
 454                 if (intel_vgpu_active(dev_priv) &&
 455                     !intel_vgpu_has_hwsp_emulation(dev_priv)) {
 456                         i915_report_error(dev_priv,
 457                                           "old vGPU host found, support for HWSP emulation required\n");
 458                         return -ENXIO;
 459                 }
 460         }
 461
 462         /* needs to be done before ggtt probe */
 463         intel_dram_edram_detect(dev_priv);
 464
 465         ret = i915_set_dma_info(dev_priv);
 466         if (ret)
 467                 return ret;
 468
 469         ret = i915_perf_init(dev_priv);
 470         if (ret)
 471                 return ret;
 472
 473         ret = i915_ggtt_probe_hw(dev_priv);
 474         if (ret)
 475                 goto err_perf;
 476
 477         ret = drm_aperture_remove_conflicting_pci_framebuffers(pdev, dev_priv->drm.driver);
 478         if (ret)
 479                 goto err_ggtt;
 480
 481         ret = i915_ggtt_init_hw(dev_priv);
 482         if (ret)
 483                 goto err_ggtt;
 484
 485         /*
 486          * Make sure we probe lmem before we probe stolen-lmem. The BAR size
 487          * might be different due to bar resizing.
 488          */
 489         ret = intel_gt_tiles_init(dev_priv);
 490         if (ret)
 491                 goto err_ggtt;
 492
 493         ret = intel_memory_regions_hw_probe(dev_priv);
 494         if (ret)
 495                 goto err_ggtt;
 496
 497         ret = i915_ggtt_enable_hw(dev_priv);
 498         if (ret) {
 499                 drm_err(&dev_priv->drm, "failed to enable GGTT\n");
 500                 goto err_mem_regions;
 501         }
 502
 503         pci_set_master(pdev);
 504
 505         /* On the 945G/GM, the chipset reports the MSI capability on the
 506          * integrated graphics even though the support isn't actually there
 507          * according to the published specs.  It doesn't appear to function
 508          * correctly in testing on 945G.
 509          * This may be a side effect of MSI having been made available for PEG
 510          * and the registers being closely associated.
 511          *
 512          * According to chipset errata, on the 965GM, MSI interrupts may
 513          * be lost or delayed, and was defeatured. MSI interrupts seem to
 514          * get lost on g4x as well, and interrupt delivery seems to stay
 515          * properly dead afterwards. So we'll just disable them for all
 516          * pre-gen5 chipsets.
 517          *
 518          * dp aux and gmbus irq on gen4 seems to be able to generate legacy
 519          * interrupts even when in MSI mode. This results in spurious
 520          * interrupt warnings if the legacy irq no. is shared with another
 521          * device. The kernel then disables that interrupt source and so
 522          * prevents the other device from working properly.
 523          */
 524         if (GRAPHICS_VER(dev_priv) >= 5) {
 525                 if (pci_enable_msi(pdev) < 0)
 526                         drm_dbg(&dev_priv->drm, "can't enable MSI");
 527         }
 528
 529         ret = intel_gvt_init(dev_priv);
 530         if (ret)
 531                 goto err_msi;
 532
 533         intel_opregion_setup(dev_priv);
 534
 535         ret = i915_pcode_init(dev_priv);
 536         if (ret)
 537                 goto err_opregion;
 538
 539         /*
 540          * Fill the dram structure to get the system dram info. This will be
 541          * used for memory latency calculation.
 542          */
 543         intel_dram_detect(dev_priv);
 544
 545         intel_bw_init_hw(dev_priv);
 546
 547         /*
 548          * FIXME: Temporary hammer to avoid freezing the machine on our DGFX
 549          * This should be totally removed when we handle the pci states properly
 550          * on runtime PM and on s2idle cases.
 551          */
 552         root_pdev = pcie_find_root_port(pdev);
 553         if (root_pdev)
 554                 pci_d3cold_disable(root_pdev);
 555
 556         return 0;
 557
 558 err_opregion:
 559         intel_opregion_cleanup(dev_priv);
 560 err_msi:
 561         if (pdev->msi_enabled)
 562                 pci_disable_msi(pdev);
 563 err_mem_regions:
 564         intel_memory_regions_driver_release(dev_priv);
 565 err_ggtt:
 566         i915_ggtt_driver_release(dev_priv);
 567         i915_gem_drain_freed_objects(dev_priv);
 568         i915_ggtt_driver_late_release(dev_priv);
 569 err_perf:
 570         i915_perf_fini(dev_priv);
 571         return ret;
 572 }
 573
 574 /**
 575  * i915_driver_hw_remove - cleanup the setup done in i915_driver_hw_probe()
 576  * @dev_priv: device private
 577  */
 578 static void i915_driver_hw_remove(struct drm_i915_private *dev_priv)
 579 {
 580         struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
 581         struct pci_dev *root_pdev;
 582
 583         i915_perf_fini(dev_priv);
 584
 585         intel_opregion_cleanup(dev_priv);
 586
 587         if (pdev->msi_enabled)
 588                 pci_disable_msi(pdev);
 589
 590         root_pdev = pcie_find_root_port(pdev);
 591         if (root_pdev)
 592                 pci_d3cold_enable(root_pdev);
 593 }
 594
 595 /**
 596  * i915_driver_register - register the driver with the rest of the system
 597  * @dev_priv: device private
 598  *
 599  * Perform any steps necessary to make the driver available via kernel
 600  * internal or userspace interfaces.
 601  */
 602 static void i915_driver_register(struct drm_i915_private *dev_priv)
 603 {
 604         struct intel_gt *gt;
 605         unsigned int i;
 606
 607         i915_gem_driver_register(dev_priv);
 608         i915_pmu_register(dev_priv);
 609
 610         intel_vgpu_register(dev_priv);
 611
 612         /* Reveal our presence to userspace */
 613         if (drm_dev_register(&dev_priv->drm, 0)) {
 614                 drm_err(&dev_priv->drm,
 615                         "Failed to register driver for userspace access!\n");
 616                 return;
 617         }
 618
 619         i915_debugfs_register(dev_priv);
 620         i915_setup_sysfs(dev_priv);
 621
 622         /* Depends on sysfs having been initialized */
 623         i915_perf_register(dev_priv);
 624
 625         for_each_gt(gt, dev_priv, i)
 626                 intel_gt_driver_register(gt);
 627
 628         intel_pxp_debugfs_register(dev_priv->pxp);
 629
 630         i915_hwmon_register(dev_priv);
 631
 632         intel_display_driver_register(dev_priv);
 633
 634         intel_power_domains_enable(dev_priv);
 635         intel_runtime_pm_enable(&dev_priv->runtime_pm);
 636
 637         intel_register_dsm_handler();
 638
 639         if (i915_switcheroo_register(dev_priv))
 640                 drm_err(&dev_priv->drm, "Failed to register vga switcheroo!\n");
 641 }
 642
 643 /**
 644  * i915_driver_unregister - cleanup the registration done in i915_driver_regiser()
 645  * @dev_priv: device private
 646  */
 647 static void i915_driver_unregister(struct drm_i915_private *dev_priv)
 648 {
 649         struct intel_gt *gt;
 650         unsigned int i;
 651
 652         i915_switcheroo_unregister(dev_priv);
 653
 654         intel_unregister_dsm_handler();
 655
 656         intel_runtime_pm_disable(&dev_priv->runtime_pm);
 657         intel_power_domains_disable(dev_priv);
 658
 659         intel_display_driver_unregister(dev_priv);
 660
 661         intel_pxp_fini(dev_priv);
 662
 663         for_each_gt(gt, dev_priv, i)
 664                 intel_gt_driver_unregister(gt);
 665
 666         i915_hwmon_unregister(dev_priv);
 667
 668         i915_perf_unregister(dev_priv);
 669         i915_pmu_unregister(dev_priv);
 670
 671         i915_teardown_sysfs(dev_priv);
 672         drm_dev_unplug(&dev_priv->drm);
 673
 674         i915_gem_driver_unregister(dev_priv);
 675 }
 676
 677 void
 678 i915_print_iommu_status(struct drm_i915_private *i915, struct drm_printer *p)
 679 {
 680         drm_printf(p, "iommu: %s\n",
 681                    str_enabled_disabled(i915_vtd_active(i915)));
 682 }
 683
 684 static void i915_welcome_messages(struct drm_i915_private *dev_priv)
 685 {
 686         if (drm_debug_enabled(DRM_UT_DRIVER)) {
 687                 struct drm_printer p = drm_debug_printer("i915 device info:");
 688                 struct intel_gt *gt;
 689                 unsigned int i;
 690
 691                 drm_printf(&p, "pciid=0x%04x rev=0x%02x platform=%s (subplatform=0x%x) gen=%i\n",
 692                            INTEL_DEVID(dev_priv),
 693                            INTEL_REVID(dev_priv),
 694                            intel_platform_name(INTEL_INFO(dev_priv)->platform),
 695                            intel_subplatform(RUNTIME_INFO(dev_priv),
 696                                              INTEL_INFO(dev_priv)->platform),
 697                            GRAPHICS_VER(dev_priv));
 698
 699                 intel_device_info_print(INTEL_INFO(dev_priv),
 700                                         RUNTIME_INFO(dev_priv), &p);
 701                 i915_print_iommu_status(dev_priv, &p);
 702                 for_each_gt(gt, dev_priv, i)
 703                         intel_gt_info_print(&gt->info, &p);
 704         }
 705
 706         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG))
 707                 drm_info(&dev_priv->drm, "DRM_I915_DEBUG enabled\n");
 708         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
 709                 drm_info(&dev_priv->drm, "DRM_I915_DEBUG_GEM enabled\n");
 710         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM))
 711                 drm_info(&dev_priv->drm,
 712                          "DRM_I915_DEBUG_RUNTIME_PM enabled\n");
 713 }
 714
 715 static struct drm_i915_private *
 716 i915_driver_create(struct pci_dev *pdev, const struct pci_device_id *ent)
 717 {
 718         const struct intel_device_info *match_info =
 719                 (struct intel_device_info *)ent->driver_data;
 720         struct drm_i915_private *i915;
 721
 722         i915 = devm_drm_dev_alloc(&pdev->dev, &i915_drm_driver,
 723                                   struct drm_i915_private, drm);
 724         if (IS_ERR(i915))
 725                 return i915;
 726
 727         pci_set_drvdata(pdev, i915);
 728
 729         /* Device parameters start as a copy of module parameters. */
 730         i915_params_copy(&i915->params, &i915_modparams);
 731
 732         /* Set up device info and initial runtime info. */
 733         intel_device_info_driver_create(i915, pdev->device, match_info);
 734
 735         return i915;
 736 }
 737
 738 /**
 739  * i915_driver_probe - setup chip and create an initial config
 740  * @pdev: PCI device
 741  * @ent: matching PCI ID entry
 742  *
 743  * The driver probe routine has to do several things:
 744  *   - drive output discovery via intel_display_driver_probe()
 745  *   - initialize the memory manager
 746  *   - allocate initial config memory
 747  *   - setup the DRM framebuffer with the allocated memory
 748  */
 749 int i915_driver_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 750 {
 751         struct drm_i915_private *i915;
 752         int ret;
 753
 754         ret = pci_enable_device(pdev);
 755         if (ret) {
 756                 pr_err("Failed to enable graphics device: %pe\n", ERR_PTR(ret));
 757                 return ret;
 758         }
 759
 760         i915 = i915_driver_create(pdev, ent);
 761         if (IS_ERR(i915)) {
 762                 ret = PTR_ERR(i915);
 763                 goto out_pci_disable;
 764         }
 765
 766         ret = i915_driver_early_probe(i915);
 767         if (ret < 0)
 768                 goto out_pci_disable;
 769
 770         disable_rpm_wakeref_asserts(&i915->runtime_pm);
 771
 772         intel_vgpu_detect(i915);
 773
 774         ret = intel_gt_probe_all(i915);
 775         if (ret < 0)
 776                 goto out_runtime_pm_put;
 777
 778         ret = i915_driver_mmio_probe(i915);
 779         if (ret < 0)
 780                 goto out_tiles_cleanup;
 781
 782         ret = i915_driver_hw_probe(i915);
 783         if (ret < 0)
 784                 goto out_cleanup_mmio;
 785
 786         ret = intel_display_driver_probe_noirq(i915);
 787         if (ret < 0)
 788                 goto out_cleanup_hw;
 789
 790         ret = intel_irq_install(i915);
 791         if (ret)
 792                 goto out_cleanup_modeset;
 793
 794         ret = intel_display_driver_probe_nogem(i915);
 795         if (ret)
 796                 goto out_cleanup_irq;
 797
 798         ret = i915_gem_init(i915);
 799         if (ret)
 800                 goto out_cleanup_modeset2;
 801
 802         intel_pxp_init(i915);
 803
 804         ret = intel_display_driver_probe(i915);
 805         if (ret)
 806                 goto out_cleanup_gem;
 807
 808         i915_driver_register(i915);
 809
 810         enable_rpm_wakeref_asserts(&i915->runtime_pm);
 811
 812         i915_welcome_messages(i915);
 813
 814         i915->do_release = true;
 815
 816         return 0;
 817
 818 out_cleanup_gem:
 819         i915_gem_suspend(i915);
 820         i915_gem_driver_remove(i915);
 821         i915_gem_driver_release(i915);
 822 out_cleanup_modeset2:
 823         /* FIXME clean up the error path */
 824         intel_display_driver_remove(i915);
 825         intel_irq_uninstall(i915);
 826         intel_display_driver_remove_noirq(i915);
 827         goto out_cleanup_modeset;
 828 out_cleanup_irq:
 829         intel_irq_uninstall(i915);
 830 out_cleanup_modeset:
 831         intel_display_driver_remove_nogem(i915);
 832 out_cleanup_hw:
 833         i915_driver_hw_remove(i915);
 834         intel_memory_regions_driver_release(i915);
 835         i915_ggtt_driver_release(i915);
 836         i915_gem_drain_freed_objects(i915);
 837         i915_ggtt_driver_late_release(i915);
 838 out_cleanup_mmio:
 839         i915_driver_mmio_release(i915);
 840 out_tiles_cleanup:
 841         intel_gt_release_all(i915);
 842 out_runtime_pm_put:
 843         enable_rpm_wakeref_asserts(&i915->runtime_pm);
 844         i915_driver_late_release(i915);
 845 out_pci_disable:
 846         pci_disable_device(pdev);
 847         i915_probe_error(i915, "Device initialization failed (%d)\n", ret);
 848         return ret;
 849 }
 850
 851 void i915_driver_remove(struct drm_i915_private *i915)
 852 {
 853         intel_wakeref_t wakeref;
 854
 855         wakeref = intel_runtime_pm_get(&i915->runtime_pm);
 856
 857         i915_driver_unregister(i915);
 858
 859         /* Flush any external code that still may be under the RCU lock */
 860         synchronize_rcu();
 861
 862         i915_gem_suspend(i915);
 863
 864         intel_gvt_driver_remove(i915);
 865
 866         intel_display_driver_remove(i915);
 867
 868         intel_irq_uninstall(i915);
 869
 870         intel_display_driver_remove_noirq(i915);
 871
 872         i915_reset_error_state(i915);
 873         i915_gem_driver_remove(i915);
 874
 875         intel_display_driver_remove_nogem(i915);
 876
 877         i915_driver_hw_remove(i915);
 878
 879         intel_runtime_pm_put(&i915->runtime_pm, wakeref);
 880 }
 881
 882 static void i915_driver_release(struct drm_device *dev)
 883 {
 884         struct drm_i915_private *dev_priv = to_i915(dev);
 885         struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
 886         intel_wakeref_t wakeref;
 887
 888         if (!dev_priv->do_release)
 889                 return;
 890
 891         wakeref = intel_runtime_pm_get(rpm);
 892
 893         i915_gem_driver_release(dev_priv);
 894
 895         intel_memory_regions_driver_release(dev_priv);
 896         i915_ggtt_driver_release(dev_priv);
 897         i915_gem_drain_freed_objects(dev_priv);
 898         i915_ggtt_driver_late_release(dev_priv);
 899
 900         i915_driver_mmio_release(dev_priv);
 901
 902         intel_runtime_pm_put(rpm, wakeref);
 903
 904         intel_runtime_pm_driver_release(rpm);
 905
 906         i915_driver_late_release(dev_priv);
 907 }
 908
 909 static int i915_driver_open(struct drm_device *dev, struct drm_file *file)
 910 {
 911         struct drm_i915_private *i915 = to_i915(dev);
 912         int ret;
 913
 914         ret = i915_gem_open(i915, file);
 915         if (ret)
 916                 return ret;
 917
 918         return 0;
 919 }
 920
 921 /**
 922  * i915_driver_lastclose - clean up after all DRM clients have exited
 923  * @dev: DRM device
 924  *
 925  * Take care of cleaning up after all DRM clients have exited.  In the
 926  * mode setting case, we want to restore the kernel's initial mode (just
 927  * in case the last client left us in a bad state).
 928  *
 929  * Additionally, in the non-mode setting case, we'll tear down the GTT
 930  * and DMA structures, since the kernel won't be using them, and clea
 931  * up any GEM state.
 932  */
 933 static void i915_driver_lastclose(struct drm_device *dev)
 934 {
 935         struct drm_i915_private *i915 = to_i915(dev);
 936
 937         intel_fbdev_restore_mode(i915);
 938
 939         vga_switcheroo_process_delayed_switch();
 940 }
 941
 942 static void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
 943 {
 944         struct drm_i915_file_private *file_priv = file->driver_priv;
 945
 946         i915_gem_context_close(file);
 947         i915_drm_client_put(file_priv->client);
 948
 949         kfree_rcu(file_priv, rcu);
 950
 951         /* Catch up with all the deferred frees from "this" client */
 952         i915_gem_flush_free_objects(to_i915(dev));
 953 }
 954
 955 static void intel_suspend_encoders(struct drm_i915_private *dev_priv)
 956 {
 957         struct intel_encoder *encoder;
 958
 959         if (!HAS_DISPLAY(dev_priv))
 960                 return;
 961
 962         /*
 963          * TODO: check and remove holding the modeset locks if none of
 964          * the encoders depends on this.
 965          */
 966         drm_modeset_lock_all(&dev_priv->drm);
 967         for_each_intel_encoder(&dev_priv->drm, encoder)
 968                 if (encoder->suspend)
 969                         encoder->suspend(encoder);
 970         drm_modeset_unlock_all(&dev_priv->drm);
 971
 972         for_each_intel_encoder(&dev_priv->drm, encoder)
 973                 if (encoder->suspend_complete)
 974                         encoder->suspend_complete(encoder);
 975 }
 976
 977 static void intel_shutdown_encoders(struct drm_i915_private *dev_priv)
 978 {
 979         struct intel_encoder *encoder;
 980
 981         if (!HAS_DISPLAY(dev_priv))
 982                 return;
 983
 984         /*
 985          * TODO: check and remove holding the modeset locks if none of
 986          * the encoders depends on this.
 987          */
 988         drm_modeset_lock_all(&dev_priv->drm);
 989         for_each_intel_encoder(&dev_priv->drm, encoder)
 990                 if (encoder->shutdown)
 991                         encoder->shutdown(encoder);
 992         drm_modeset_unlock_all(&dev_priv->drm);
 993
 994         for_each_intel_encoder(&dev_priv->drm, encoder)
 995                 if (encoder->shutdown_complete)
 996                         encoder->shutdown_complete(encoder);
 997 }
 998
 999 void i915_driver_shutdown(struct drm_i915_private *i915)
1000 {
1001         disable_rpm_wakeref_asserts(&i915->runtime_pm);
1002         intel_runtime_pm_disable(&i915->runtime_pm);
1003         intel_power_domains_disable(i915);
1004
1005         if (HAS_DISPLAY(i915)) {
1006                 drm_kms_helper_poll_disable(&i915->drm);
1007
1008                 drm_atomic_helper_shutdown(&i915->drm);
1009         }
1010
1011         intel_dp_mst_suspend(i915);
1012
1013         intel_runtime_pm_disable_interrupts(i915);
1014         intel_hpd_cancel_work(i915);
1015
1016         intel_suspend_encoders(i915);
1017         intel_shutdown_encoders(i915);
1018
1019         intel_dmc_suspend(i915);
1020
1021         i915_gem_suspend(i915);
1022
1023         /*
1024          * The only requirement is to reboot with display DC states disabled,
1025          * for now leaving all display power wells in the INIT power domain
1026          * enabled.
1027          *
1028          * TODO:
1029          * - unify the pci_driver::shutdown sequence here with the
1030          *   pci_driver.driver.pm.poweroff,poweroff_late sequence.
1031          * - unify the driver remove and system/runtime suspend sequences with
1032          *   the above unified shutdown/poweroff sequence.
1033          */
1034         intel_power_domains_driver_remove(i915);
1035         enable_rpm_wakeref_asserts(&i915->runtime_pm);
1036
1037         intel_runtime_pm_driver_release(&i915->runtime_pm);
1038 }
1039
1040 static bool suspend_to_idle(struct drm_i915_private *dev_priv)
1041 {
1042 #if IS_ENABLED(CONFIG_ACPI_SLEEP)
1043         if (acpi_target_system_state() < ACPI_STATE_S3)
1044                 return true;
1045 #endif
1046         return false;
1047 }
1048
1049 static void i915_drm_complete(struct drm_device *dev)
1050 {
1051         struct drm_i915_private *i915 = to_i915(dev);
1052
1053         intel_pxp_resume_complete(i915->pxp);
1054 }
1055
1056 static int i915_drm_prepare(struct drm_device *dev)
1057 {
1058         struct drm_i915_private *i915 = to_i915(dev);
1059
1060         intel_pxp_suspend_prepare(i915->pxp);
1061
1062         /*
1063          * NB intel_display_driver_suspend() may issue new requests after we've
1064          * ostensibly marked the GPU as ready-to-sleep here. We need to
1065          * split out that work and pull it forward so that after point,
1066          * the GPU is not woken again.
1067          */
1068         return i915_gem_backup_suspend(i915);
1069 }
1070
1071 static int i915_drm_suspend(struct drm_device *dev)
1072 {
1073         struct drm_i915_private *dev_priv = to_i915(dev);
1074         struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
1075         pci_power_t opregion_target_state;
1076
1077         disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1078
1079         /* We do a lot of poking in a lot of registers, make sure they work
1080          * properly. */
1081         intel_power_domains_disable(dev_priv);
1082         if (HAS_DISPLAY(dev_priv))
1083                 drm_kms_helper_poll_disable(dev);
1084
1085         pci_save_state(pdev);
1086
1087         intel_display_driver_suspend(dev_priv);
1088
1089         intel_dp_mst_suspend(dev_priv);
1090
1091         intel_runtime_pm_disable_interrupts(dev_priv);
1092         intel_hpd_cancel_work(dev_priv);
1093
1094         intel_suspend_encoders(dev_priv);
1095
1096         /* Must be called before GGTT is suspended. */
1097         intel_dpt_suspend(dev_priv);
1098         i915_ggtt_suspend(to_gt(dev_priv)->ggtt);
1099
1100         i915_save_display(dev_priv);
1101
1102         opregion_target_state = suspend_to_idle(dev_priv) ? PCI_D1 : PCI_D3cold;
1103         intel_opregion_suspend(dev_priv, opregion_target_state);
1104
1105         intel_fbdev_set_suspend(dev, FBINFO_STATE_SUSPENDED, true);
1106
1107         dev_priv->suspend_count++;
1108
1109         intel_dmc_suspend(dev_priv);
1110
1111         enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1112
1113         i915_gem_drain_freed_objects(dev_priv);
1114
1115         return 0;
1116 }
1117
1118 static int i915_drm_suspend_late(struct drm_device *dev, bool hibernation)
1119 {
1120         struct drm_i915_private *dev_priv = to_i915(dev);
1121         struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
1122         struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
1123         struct intel_gt *gt;
1124         int ret, i;
1125         bool s2idle = !hibernation && suspend_to_idle(dev_priv);
1126
1127         disable_rpm_wakeref_asserts(rpm);
1128
1129         intel_pxp_suspend(dev_priv->pxp);
1130
1131         i915_gem_suspend_late(dev_priv);
1132
1133         for_each_gt(gt, dev_priv, i)
1134                 intel_uncore_suspend(gt->uncore);
1135
1136         intel_power_domains_suspend(dev_priv, s2idle);
1137
1138         intel_display_power_suspend_late(dev_priv);
1139
1140         ret = vlv_suspend_complete(dev_priv);
1141         if (ret) {
1142                 drm_err(&dev_priv->drm, "Suspend complete failed: %d\n", ret);
1143                 intel_power_domains_resume(dev_priv);
1144
1145                 goto out;
1146         }
1147
1148         pci_disable_device(pdev);
1149         /*
1150          * During hibernation on some platforms the BIOS may try to access
1151          * the device even though it's already in D3 and hang the machine. So
1152          * leave the device in D0 on those platforms and hope the BIOS will
1153          * power down the device properly. The issue was seen on multiple old
1154          * GENs with different BIOS vendors, so having an explicit blacklist
1155          * is inpractical; apply the workaround on everything pre GEN6. The
1156          * platforms where the issue was seen:
1157          * Lenovo Thinkpad X301, X61s, X60, T60, X41
1158          * Fujitsu FSC S7110
1159          * Acer Aspire 1830T
1160          */
1161         if (!(hibernation && GRAPHICS_VER(dev_priv) < 6))
1162                 pci_set_power_state(pdev, PCI_D3hot);
1163
1164 out:
1165         enable_rpm_wakeref_asserts(rpm);
1166         if (!dev_priv->uncore.user_forcewake_count)
1167                 intel_runtime_pm_driver_release(rpm);
1168
1169         return ret;
1170 }
1171
1172 int i915_driver_suspend_switcheroo(struct drm_i915_private *i915,
1173                                    pm_message_t state)
1174 {
1175         int error;
1176
1177         if (drm_WARN_ON_ONCE(&i915->drm, state.event != PM_EVENT_SUSPEND &&
1178                              state.event != PM_EVENT_FREEZE))
1179                 return -EINVAL;
1180
1181         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1182                 return 0;
1183
1184         error = i915_drm_suspend(&i915->drm);
1185         if (error)
1186                 return error;
1187
1188         return i915_drm_suspend_late(&i915->drm, false);
1189 }
1190
1191 static int i915_drm_resume(struct drm_device *dev)
1192 {
1193         struct drm_i915_private *dev_priv = to_i915(dev);
1194         struct intel_gt *gt;
1195         int ret, i;
1196
1197         disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1198
1199         ret = i915_pcode_init(dev_priv);
1200         if (ret)
1201                 return ret;
1202
1203         sanitize_gpu(dev_priv);
1204
1205         ret = i915_ggtt_enable_hw(dev_priv);
1206         if (ret)
1207                 drm_err(&dev_priv->drm, "failed to re-enable GGTT\n");
1208
1209         i915_ggtt_resume(to_gt(dev_priv)->ggtt);
1210
1211         for_each_gt(gt, dev_priv, i)
1212                 if (GRAPHICS_VER(gt->i915) >= 8)
1213                         setup_private_pat(gt);
1214
1215         /* Must be called after GGTT is resumed. */
1216         intel_dpt_resume(dev_priv);
1217
1218         intel_dmc_resume(dev_priv);
1219
1220         i915_restore_display(dev_priv);
1221         intel_pps_unlock_regs_wa(dev_priv);
1222
1223         intel_init_pch_refclk(dev_priv);
1224
1225         /*
1226          * Interrupts have to be enabled before any batches are run. If not the
1227          * GPU will hang. i915_gem_init_hw() will initiate batches to
1228          * update/restore the context.
1229          *
1230          * drm_mode_config_reset() needs AUX interrupts.
1231          *
1232          * Modeset enabling in intel_display_driver_init_hw() also needs working
1233          * interrupts.
1234          */
1235         intel_runtime_pm_enable_interrupts(dev_priv);
1236
1237         if (HAS_DISPLAY(dev_priv))
1238                 drm_mode_config_reset(dev);
1239
1240         i915_gem_resume(dev_priv);
1241
1242         intel_display_driver_init_hw(dev_priv);
1243
1244         intel_clock_gating_init(dev_priv);
1245         intel_hpd_init(dev_priv);
1246
1247         /* MST sideband requires HPD interrupts enabled */
1248         intel_dp_mst_resume(dev_priv);
1249         intel_display_driver_resume(dev_priv);
1250
1251         intel_hpd_poll_disable(dev_priv);
1252         if (HAS_DISPLAY(dev_priv))
1253                 drm_kms_helper_poll_enable(dev);
1254
1255         intel_opregion_resume(dev_priv);
1256
1257         intel_fbdev_set_suspend(dev, FBINFO_STATE_RUNNING, false);
1258
1259         intel_power_domains_enable(dev_priv);
1260
1261         intel_gvt_resume(dev_priv);
1262
1263         enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1264
1265         return 0;
1266 }
1267
1268 static int i915_drm_resume_early(struct drm_device *dev)
1269 {
1270         struct drm_i915_private *dev_priv = to_i915(dev);
1271         struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
1272         struct intel_gt *gt;
1273         int ret, i;
1274
1275         /*
1276          * We have a resume ordering issue with the snd-hda driver also
1277          * requiring our device to be power up. Due to the lack of a
1278          * parent/child relationship we currently solve this with an early
1279          * resume hook.
1280          *
1281          * FIXME: This should be solved with a special hdmi sink device or
1282          * similar so that power domains can be employed.
1283          */
1284
1285         /*
1286          * Note that we need to set the power state explicitly, since we
1287          * powered off the device during freeze and the PCI core won't power
1288          * it back up for us during thaw. Powering off the device during
1289          * freeze is not a hard requirement though, and during the
1290          * suspend/resume phases the PCI core makes sure we get here with the
1291          * device powered on. So in case we change our freeze logic and keep
1292          * the device powered we can also remove the following set power state
1293          * call.
1294          */
1295         ret = pci_set_power_state(pdev, PCI_D0);
1296         if (ret) {
1297                 drm_err(&dev_priv->drm,
1298                         "failed to set PCI D0 power state (%d)\n", ret);
1299                 return ret;
1300         }
1301
1302         /*
1303          * Note that pci_enable_device() first enables any parent bridge
1304          * device and only then sets the power state for this device. The
1305          * bridge enabling is a nop though, since bridge devices are resumed
1306          * first. The order of enabling power and enabling the device is
1307          * imposed by the PCI core as described above, so here we preserve the
1308          * same order for the freeze/thaw phases.
1309          *
1310          * TODO: eventually we should remove pci_disable_device() /
1311          * pci_enable_enable_device() from suspend/resume. Due to how they
1312          * depend on the device enable refcount we can't anyway depend on them
1313          * disabling/enabling the device.
1314          */
1315         if (pci_enable_device(pdev))
1316                 return -EIO;
1317
1318         pci_set_master(pdev);
1319
1320         disable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1321
1322         ret = vlv_resume_prepare(dev_priv, false);
1323         if (ret)
1324                 drm_err(&dev_priv->drm,
1325                         "Resume prepare failed: %d, continuing anyway\n", ret);
1326
1327         for_each_gt(gt, dev_priv, i) {
1328                 intel_uncore_resume_early(gt->uncore);
1329                 intel_gt_check_and_clear_faults(gt);
1330         }
1331
1332         intel_display_power_resume_early(dev_priv);
1333
1334         intel_power_domains_resume(dev_priv);
1335
1336         enable_rpm_wakeref_asserts(&dev_priv->runtime_pm);
1337
1338         return ret;
1339 }
1340
1341 int i915_driver_resume_switcheroo(struct drm_i915_private *i915)
1342 {
1343         int ret;
1344
1345         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1346                 return 0;
1347
1348         ret = i915_drm_resume_early(&i915->drm);
1349         if (ret)
1350                 return ret;
1351
1352         return i915_drm_resume(&i915->drm);
1353 }
1354
1355 static int i915_pm_prepare(struct device *kdev)
1356 {
1357         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1358
1359         if (!i915) {
1360                 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
1361                 return -ENODEV;
1362         }
1363
1364         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1365                 return 0;
1366
1367         return i915_drm_prepare(&i915->drm);
1368 }
1369
1370 static int i915_pm_suspend(struct device *kdev)
1371 {
1372         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1373
1374         if (!i915) {
1375                 dev_err(kdev, "DRM not initialized, aborting suspend.\n");
1376                 return -ENODEV;
1377         }
1378
1379         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1380                 return 0;
1381
1382         return i915_drm_suspend(&i915->drm);
1383 }
1384
1385 static int i915_pm_suspend_late(struct device *kdev)
1386 {
1387         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1388
1389         /*
1390          * We have a suspend ordering issue with the snd-hda driver also
1391          * requiring our device to be power up. Due to the lack of a
1392          * parent/child relationship we currently solve this with an late
1393          * suspend hook.
1394          *
1395          * FIXME: This should be solved with a special hdmi sink device or
1396          * similar so that power domains can be employed.
1397          */
1398         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1399                 return 0;
1400
1401         return i915_drm_suspend_late(&i915->drm, false);
1402 }
1403
1404 static int i915_pm_poweroff_late(struct device *kdev)
1405 {
1406         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1407
1408         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1409                 return 0;
1410
1411         return i915_drm_suspend_late(&i915->drm, true);
1412 }
1413
1414 static int i915_pm_resume_early(struct device *kdev)
1415 {
1416         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1417
1418         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1419                 return 0;
1420
1421         return i915_drm_resume_early(&i915->drm);
1422 }
1423
1424 static int i915_pm_resume(struct device *kdev)
1425 {
1426         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1427
1428         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1429                 return 0;
1430
1431         return i915_drm_resume(&i915->drm);
1432 }
1433
1434 static void i915_pm_complete(struct device *kdev)
1435 {
1436         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1437
1438         if (i915->drm.switch_power_state == DRM_SWITCH_POWER_OFF)
1439                 return;
1440
1441         i915_drm_complete(&i915->drm);
1442 }
1443
1444 /* freeze: before creating the hibernation_image */
1445 static int i915_pm_freeze(struct device *kdev)
1446 {
1447         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1448         int ret;
1449
1450         if (i915->drm.switch_power_state != DRM_SWITCH_POWER_OFF) {
1451                 ret = i915_drm_suspend(&i915->drm);
1452                 if (ret)
1453                         return ret;
1454         }
1455
1456         ret = i915_gem_freeze(i915);
1457         if (ret)
1458                 return ret;
1459
1460         return 0;
1461 }
1462
1463 static int i915_pm_freeze_late(struct device *kdev)
1464 {
1465         struct drm_i915_private *i915 = kdev_to_i915(kdev);
1466         int ret;
1467
1468         if (i915->drm.switch_power_state != DRM_SWITCH_POWER_OFF) {
1469                 ret = i915_drm_suspend_late(&i915->drm, true);
1470                 if (ret)
1471                         return ret;
1472         }
1473
1474         ret = i915_gem_freeze_late(i915);
1475         if (ret)
1476                 return ret;
1477
1478         return 0;
1479 }
1480
1481 /* thaw: called after creating the hibernation image, but before turning off. */
1482 static int i915_pm_thaw_early(struct device *kdev)
1483 {
1484         return i915_pm_resume_early(kdev);
1485 }
1486
1487 static int i915_pm_thaw(struct device *kdev)
1488 {
1489         return i915_pm_resume(kdev);
1490 }
1491
1492 /* restore: called after loading the hibernation image. */
1493 static int i915_pm_restore_early(struct device *kdev)
1494 {
1495         return i915_pm_resume_early(kdev);
1496 }
1497
1498 static int i915_pm_restore(struct device *kdev)
1499 {
1500         return i915_pm_resume(kdev);
1501 }
1502
1503 static int intel_runtime_suspend(struct device *kdev)
1504 {
1505         struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
1506         struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
1507         struct intel_gt *gt;
1508         int ret, i;
1509
1510         if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_RUNTIME_PM(dev_priv)))
1511                 return -ENODEV;
1512
1513         drm_dbg(&dev_priv->drm, "Suspending device\n");
1514
1515         disable_rpm_wakeref_asserts(rpm);
1516
1517         /*
1518          * We are safe here against re-faults, since the fault handler takes
1519          * an RPM reference.
1520          */
1521         i915_gem_runtime_suspend(dev_priv);
1522
1523         intel_pxp_runtime_suspend(dev_priv->pxp);
1524
1525         for_each_gt(gt, dev_priv, i)
1526                 intel_gt_runtime_suspend(gt);
1527
1528         intel_runtime_pm_disable_interrupts(dev_priv);
1529
1530         for_each_gt(gt, dev_priv, i)
1531                 intel_uncore_suspend(gt->uncore);
1532
1533         intel_display_power_suspend(dev_priv);
1534
1535         ret = vlv_suspend_complete(dev_priv);
1536         if (ret) {
1537                 drm_err(&dev_priv->drm,
1538                         "Runtime suspend failed, disabling it (%d)\n", ret);
1539                 intel_uncore_runtime_resume(&dev_priv->uncore);
1540
1541                 intel_runtime_pm_enable_interrupts(dev_priv);
1542
1543                 for_each_gt(gt, dev_priv, i)
1544                         intel_gt_runtime_resume(gt);
1545
1546                 enable_rpm_wakeref_asserts(rpm);
1547
1548                 return ret;
1549         }
1550
1551         enable_rpm_wakeref_asserts(rpm);
1552         intel_runtime_pm_driver_release(rpm);
1553
1554         if (intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore))
1555                 drm_err(&dev_priv->drm,
1556                         "Unclaimed access detected prior to suspending\n");
1557
1558         rpm->suspended = true;
1559
1560         /*
1561          * FIXME: We really should find a document that references the arguments
1562          * used below!
1563          */
1564         if (IS_BROADWELL(dev_priv)) {
1565                 /*
1566                  * On Broadwell, if we use PCI_D1 the PCH DDI ports will stop
1567                  * being detected, and the call we do at intel_runtime_resume()
1568                  * won't be able to restore them. Since PCI_D3hot matches the
1569                  * actual specification and appears to be working, use it.
1570                  */
1571                 intel_opregion_notify_adapter(dev_priv, PCI_D3hot);
1572         } else {
1573                 /*
1574                  * current versions of firmware which depend on this opregion
1575                  * notification have repurposed the D1 definition to mean
1576                  * "runtime suspended" vs. what you would normally expect (D3)
1577                  * to distinguish it from notifications that might be sent via
1578                  * the suspend path.
1579                  */
1580                 intel_opregion_notify_adapter(dev_priv, PCI_D1);
1581         }
1582
1583         assert_forcewakes_inactive(&dev_priv->uncore);
1584
1585         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
1586                 intel_hpd_poll_enable(dev_priv);
1587
1588         drm_dbg(&dev_priv->drm, "Device suspended\n");
1589         return 0;
1590 }
1591
1592 static int intel_runtime_resume(struct device *kdev)
1593 {
1594         struct drm_i915_private *dev_priv = kdev_to_i915(kdev);
1595         struct intel_runtime_pm *rpm = &dev_priv->runtime_pm;
1596         struct intel_gt *gt;
1597         int ret, i;
1598
1599         if (drm_WARN_ON_ONCE(&dev_priv->drm, !HAS_RUNTIME_PM(dev_priv)))
1600                 return -ENODEV;
1601
1602         drm_dbg(&dev_priv->drm, "Resuming device\n");
1603
1604         drm_WARN_ON_ONCE(&dev_priv->drm, atomic_read(&rpm->wakeref_count));
1605         disable_rpm_wakeref_asserts(rpm);
1606
1607         intel_opregion_notify_adapter(dev_priv, PCI_D0);
1608         rpm->suspended = false;
1609         if (intel_uncore_unclaimed_mmio(&dev_priv->uncore))
1610                 drm_dbg(&dev_priv->drm,
1611                         "Unclaimed access during suspend, bios?\n");
1612
1613         intel_display_power_resume(dev_priv);
1614
1615         ret = vlv_resume_prepare(dev_priv, true);
1616
1617         for_each_gt(gt, dev_priv, i)
1618                 intel_uncore_runtime_resume(gt->uncore);
1619
1620         intel_runtime_pm_enable_interrupts(dev_priv);
1621
1622         /*
1623          * No point of rolling back things in case of an error, as the best
1624          * we can do is to hope that things will still work (and disable RPM).
1625          */
1626         for_each_gt(gt, dev_priv, i)
1627                 intel_gt_runtime_resume(gt);
1628
1629         intel_pxp_runtime_resume(dev_priv->pxp);
1630
1631         /*
1632          * On VLV/CHV display interrupts are part of the display
1633          * power well, so hpd is reinitialized from there. For
1634          * everyone else do it here.
1635          */
1636         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
1637                 intel_hpd_init(dev_priv);
1638                 intel_hpd_poll_disable(dev_priv);
1639         }
1640
1641         skl_watermark_ipc_update(dev_priv);
1642
1643         enable_rpm_wakeref_asserts(rpm);
1644
1645         if (ret)
1646                 drm_err(&dev_priv->drm,
1647                         "Runtime resume failed, disabling it (%d)\n", ret);
1648         else
1649                 drm_dbg(&dev_priv->drm, "Device resumed\n");
1650
1651         return ret;
1652 }
1653
1654 const struct dev_pm_ops i915_pm_ops = {
1655         /*
1656          * S0ix (via system suspend) and S3 event handlers [PMSG_SUSPEND,
1657          * PMSG_RESUME]
1658          */
1659         .prepare = i915_pm_prepare,
1660         .suspend = i915_pm_suspend,
1661         .suspend_late = i915_pm_suspend_late,
1662         .resume_early = i915_pm_resume_early,
1663         .resume = i915_pm_resume,
1664         .complete = i915_pm_complete,
1665
1666         /*
1667          * S4 event handlers
1668          * @freeze, @freeze_late    : called (1) before creating the
1669          *                            hibernation image [PMSG_FREEZE] and
1670          *                            (2) after rebooting, before restoring
1671          *                            the image [PMSG_QUIESCE]
1672          * @thaw, @thaw_early       : called (1) after creating the hibernation
1673          *                            image, before writing it [PMSG_THAW]
1674          *                            and (2) after failing to create or
1675          *                            restore the image [PMSG_RECOVER]
1676          * @poweroff, @poweroff_late: called after writing the hibernation
1677          *                            image, before rebooting [PMSG_HIBERNATE]
1678          * @restore, @restore_early : called after rebooting and restoring the
1679          *                            hibernation image [PMSG_RESTORE]
1680          */
1681         .freeze = i915_pm_freeze,
1682         .freeze_late = i915_pm_freeze_late,
1683         .thaw_early = i915_pm_thaw_early,
1684         .thaw = i915_pm_thaw,
1685         .poweroff = i915_pm_suspend,
1686         .poweroff_late = i915_pm_poweroff_late,
1687         .restore_early = i915_pm_restore_early,
1688         .restore = i915_pm_restore,
1689
1690         /* S0ix (via runtime suspend) event handlers */
1691         .runtime_suspend = intel_runtime_suspend,
1692         .runtime_resume = intel_runtime_resume,
1693 };
1694
1695 static const struct file_operations i915_driver_fops = {
1696         .owner = THIS_MODULE,
1697         .open = drm_open,
1698         .release = drm_release_noglobal,
1699         .unlocked_ioctl = drm_ioctl,
1700         .mmap = i915_gem_mmap,
1701         .poll = drm_poll,
1702         .read = drm_read,
1703         .compat_ioctl = i915_ioc32_compat_ioctl,
1704         .llseek = noop_llseek,
1705 #ifdef CONFIG_PROC_FS
1706         .show_fdinfo = drm_show_fdinfo,
1707 #endif
1708 };
1709
1710 static int
1711 i915_gem_reject_pin_ioctl(struct drm_device *dev, void *data,
1712                           struct drm_file *file)
1713 {
1714         return -ENODEV;
1715 }
1716
1717 static const struct drm_ioctl_desc i915_ioctls[] = {
1718         DRM_IOCTL_DEF_DRV(I915_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1719         DRM_IOCTL_DEF_DRV(I915_FLUSH, drm_noop, DRM_AUTH),
1720         DRM_IOCTL_DEF_DRV(I915_FLIP, drm_noop, DRM_AUTH),
1721         DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, drm_noop, DRM_AUTH),
1722         DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, drm_noop, DRM_AUTH),
1723         DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, drm_noop, DRM_AUTH),
1724         DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam_ioctl, DRM_RENDER_ALLOW),
1725         DRM_IOCTL_DEF_DRV(I915_SETPARAM, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1726         DRM_IOCTL_DEF_DRV(I915_ALLOC, drm_noop, DRM_AUTH),
1727         DRM_IOCTL_DEF_DRV(I915_FREE, drm_noop, DRM_AUTH),
1728         DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1729         DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, drm_noop, DRM_AUTH),
1730         DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1731         DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE,  drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1732         DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE,  drm_noop, DRM_AUTH),
1733         DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, drm_noop, DRM_AUTH),
1734         DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1735         DRM_IOCTL_DEF_DRV(I915_GEM_INIT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1736         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, drm_invalid_op, DRM_AUTH),
1737         DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2_WR, i915_gem_execbuffer2_ioctl, DRM_RENDER_ALLOW),
1738         DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
1739         DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_reject_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
1740         DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_RENDER_ALLOW),
1741         DRM_IOCTL_DEF_DRV(I915_GEM_SET_CACHING, i915_gem_set_caching_ioctl, DRM_RENDER_ALLOW),
1742         DRM_IOCTL_DEF_DRV(I915_GEM_GET_CACHING, i915_gem_get_caching_ioctl, DRM_RENDER_ALLOW),
1743         DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_RENDER_ALLOW),
1744         DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1745         DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, drm_noop, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1746         DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_RENDER_ALLOW),
1747         DRM_IOCTL_DEF_DRV(I915_GEM_CREATE_EXT, i915_gem_create_ext_ioctl, DRM_RENDER_ALLOW),
1748         DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_RENDER_ALLOW),
1749         DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_RENDER_ALLOW),
1750         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_RENDER_ALLOW),
1751         DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_OFFSET, i915_gem_mmap_offset_ioctl, DRM_RENDER_ALLOW),
1752         DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_RENDER_ALLOW),
1753         DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_RENDER_ALLOW),
1754         DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling_ioctl, DRM_RENDER_ALLOW),
1755         DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling_ioctl, DRM_RENDER_ALLOW),
1756         DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_RENDER_ALLOW),
1757         DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id_ioctl, 0),
1758         DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_RENDER_ALLOW),
1759         DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image_ioctl, DRM_MASTER),
1760         DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs_ioctl, DRM_MASTER),
1761         DRM_IOCTL_DEF_DRV(I915_SET_SPRITE_COLORKEY, intel_sprite_set_colorkey_ioctl, DRM_MASTER),
1762         DRM_IOCTL_DEF_DRV(I915_GET_SPRITE_COLORKEY, drm_noop, DRM_MASTER),
1763         DRM_IOCTL_DEF_DRV(I915_GEM_WAIT, i915_gem_wait_ioctl, DRM_RENDER_ALLOW),
1764         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_CREATE_EXT, i915_gem_context_create_ioctl, DRM_RENDER_ALLOW),
1765         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_DESTROY, i915_gem_context_destroy_ioctl, DRM_RENDER_ALLOW),
1766         DRM_IOCTL_DEF_DRV(I915_REG_READ, i915_reg_read_ioctl, DRM_RENDER_ALLOW),
1767         DRM_IOCTL_DEF_DRV(I915_GET_RESET_STATS, i915_gem_context_reset_stats_ioctl, DRM_RENDER_ALLOW),
1768         DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW),
1769         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW),
1770         DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW),
1771         DRM_IOCTL_DEF_DRV(I915_PERF_OPEN, i915_perf_open_ioctl, DRM_RENDER_ALLOW),
1772         DRM_IOCTL_DEF_DRV(I915_PERF_ADD_CONFIG, i915_perf_add_config_ioctl, DRM_RENDER_ALLOW),
1773         DRM_IOCTL_DEF_DRV(I915_PERF_REMOVE_CONFIG, i915_perf_remove_config_ioctl, DRM_RENDER_ALLOW),
1774         DRM_IOCTL_DEF_DRV(I915_QUERY, i915_query_ioctl, DRM_RENDER_ALLOW),
1775         DRM_IOCTL_DEF_DRV(I915_GEM_VM_CREATE, i915_gem_vm_create_ioctl, DRM_RENDER_ALLOW),
1776         DRM_IOCTL_DEF_DRV(I915_GEM_VM_DESTROY, i915_gem_vm_destroy_ioctl, DRM_RENDER_ALLOW),
1777 };
1778
1779 /*
1780  * Interface history:
1781  *
1782  * 1.1: Original.
1783  * 1.2: Add Power Management
1784  * 1.3: Add vblank support
1785  * 1.4: Fix cmdbuffer path, add heap destroy
1786  * 1.5: Add vblank pipe configuration
1787  * 1.6: - New ioctl for scheduling buffer swaps on vertical blank
1788  *      - Support vertical blank on secondary display pipe
1789  */
1790 #define DRIVER_MAJOR            1
1791 #define DRIVER_MINOR            6
1792 #define DRIVER_PATCHLEVEL       0
1793
1794 static const struct drm_driver i915_drm_driver = {
1795         /* Don't use MTRRs here; the Xserver or userspace app should
1796          * deal with them for Intel hardware.
1797          */
1798         .driver_features =
1799             DRIVER_GEM |
1800             DRIVER_RENDER | DRIVER_MODESET | DRIVER_ATOMIC | DRIVER_SYNCOBJ |
1801             DRIVER_SYNCOBJ_TIMELINE,
1802         .release = i915_driver_release,
1803         .open = i915_driver_open,
1804         .lastclose = i915_driver_lastclose,
1805         .postclose = i915_driver_postclose,
1806         .show_fdinfo = i915_drm_client_fdinfo,
1807
1808         .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
1809         .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
1810         .gem_prime_import = i915_gem_prime_import,
1811
1812         .dumb_create = i915_gem_dumb_create,
1813         .dumb_map_offset = i915_gem_dumb_mmap_offset,
1814
1815         .ioctls = i915_ioctls,
1816         .num_ioctls = ARRAY_SIZE(i915_ioctls),
1817         .fops = &i915_driver_fops,
1818         .name = DRIVER_NAME,
1819         .desc = DRIVER_DESC,
1820         .date = DRIVER_DATE,
1821         .major = DRIVER_MAJOR,
1822         .minor = DRIVER_MINOR,
1823         .patchlevel = DRIVER_PATCHLEVEL,
1824 };