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[linux.git] / drivers / gpu / drm / i915 / i915_debugfs.c
1 /*
2  * Copyright © 2008 Intel Corporation
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21  * IN THE SOFTWARE.
22  *
23  * Authors:
24  *    Eric Anholt <[email protected]>
25  *    Keith Packard <[email protected]>
26  *
27  */
28
29 #include <linux/sched/mm.h>
30 #include <linux/sort.h>
31 #include <linux/string_helpers.h>
32
33 #include <drm/drm_debugfs.h>
34
35 #include "gem/i915_gem_context.h"
36 #include "gt/intel_gt.h"
37 #include "gt/intel_gt_buffer_pool.h"
38 #include "gt/intel_gt_clock_utils.h"
39 #include "gt/intel_gt_debugfs.h"
40 #include "gt/intel_gt_pm.h"
41 #include "gt/intel_gt_pm_debugfs.h"
42 #include "gt/intel_gt_regs.h"
43 #include "gt/intel_gt_requests.h"
44 #include "gt/intel_rc6.h"
45 #include "gt/intel_reset.h"
46 #include "gt/intel_rps.h"
47 #include "gt/intel_sseu_debugfs.h"
48
49 #include "i915_debugfs.h"
50 #include "i915_debugfs_params.h"
51 #include "i915_driver.h"
52 #include "i915_irq.h"
53 #include "i915_reg.h"
54 #include "i915_scheduler.h"
55 #include "intel_mchbar_regs.h"
56
57 static inline struct drm_i915_private *node_to_i915(struct drm_info_node *node)
58 {
59         return to_i915(node->minor->dev);
60 }
61
62 static int i915_capabilities(struct seq_file *m, void *data)
63 {
64         struct drm_i915_private *i915 = node_to_i915(m->private);
65         struct drm_printer p = drm_seq_file_printer(m);
66
67         seq_printf(m, "pch: %d\n", INTEL_PCH_TYPE(i915));
68
69         intel_device_info_print(INTEL_INFO(i915), RUNTIME_INFO(i915), &p);
70         i915_print_iommu_status(i915, &p);
71         intel_gt_info_print(&to_gt(i915)->info, &p);
72         intel_driver_caps_print(&i915->caps, &p);
73
74         kernel_param_lock(THIS_MODULE);
75         i915_params_dump(&i915->params, &p);
76         kernel_param_unlock(THIS_MODULE);
77
78         return 0;
79 }
80
81 static char get_tiling_flag(struct drm_i915_gem_object *obj)
82 {
83         switch (i915_gem_object_get_tiling(obj)) {
84         default:
85         case I915_TILING_NONE: return ' ';
86         case I915_TILING_X: return 'X';
87         case I915_TILING_Y: return 'Y';
88         }
89 }
90
91 static char get_global_flag(struct drm_i915_gem_object *obj)
92 {
93         return READ_ONCE(obj->userfault_count) ? 'g' : ' ';
94 }
95
96 static char get_pin_mapped_flag(struct drm_i915_gem_object *obj)
97 {
98         return obj->mm.mapping ? 'M' : ' ';
99 }
100
101 static const char *
102 stringify_page_sizes(unsigned int page_sizes, char *buf, size_t len)
103 {
104         size_t x = 0;
105
106         switch (page_sizes) {
107         case 0:
108                 return "";
109         case I915_GTT_PAGE_SIZE_4K:
110                 return "4K";
111         case I915_GTT_PAGE_SIZE_64K:
112                 return "64K";
113         case I915_GTT_PAGE_SIZE_2M:
114                 return "2M";
115         default:
116                 if (!buf)
117                         return "M";
118
119                 if (page_sizes & I915_GTT_PAGE_SIZE_2M)
120                         x += snprintf(buf + x, len - x, "2M, ");
121                 if (page_sizes & I915_GTT_PAGE_SIZE_64K)
122                         x += snprintf(buf + x, len - x, "64K, ");
123                 if (page_sizes & I915_GTT_PAGE_SIZE_4K)
124                         x += snprintf(buf + x, len - x, "4K, ");
125                 buf[x-2] = '\0';
126
127                 return buf;
128         }
129 }
130
131 static const char *stringify_vma_type(const struct i915_vma *vma)
132 {
133         if (i915_vma_is_ggtt(vma))
134                 return "ggtt";
135
136         if (i915_vma_is_dpt(vma))
137                 return "dpt";
138
139         return "ppgtt";
140 }
141
142 static const char *i915_cache_level_str(struct drm_i915_gem_object *obj)
143 {
144         struct drm_i915_private *i915 = obj_to_i915(obj);
145
146         if (IS_METEORLAKE(i915)) {
147                 switch (obj->pat_index) {
148                 case 0: return " WB";
149                 case 1: return " WT";
150                 case 2: return " UC";
151                 case 3: return " WB (1-Way Coh)";
152                 case 4: return " WB (2-Way Coh)";
153                 default: return " not defined";
154                 }
155         } else if (IS_PONTEVECCHIO(i915)) {
156                 switch (obj->pat_index) {
157                 case 0: return " UC";
158                 case 1: return " WC";
159                 case 2: return " WT";
160                 case 3: return " WB";
161                 case 4: return " WT (CLOS1)";
162                 case 5: return " WB (CLOS1)";
163                 case 6: return " WT (CLOS2)";
164                 case 7: return " WT (CLOS2)";
165                 default: return " not defined";
166                 }
167         } else if (GRAPHICS_VER(i915) >= 12) {
168                 switch (obj->pat_index) {
169                 case 0: return " WB";
170                 case 1: return " WC";
171                 case 2: return " WT";
172                 case 3: return " UC";
173                 default: return " not defined";
174                 }
175         } else {
176                 switch (obj->pat_index) {
177                 case 0: return " UC";
178                 case 1: return HAS_LLC(i915) ?
179                                " LLC" : " snooped";
180                 case 2: return " L3+LLC";
181                 case 3: return " WT";
182                 default: return " not defined";
183                 }
184         }
185 }
186
187 void
188 i915_debugfs_describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
189 {
190         struct i915_vma *vma;
191         int pin_count = 0;
192
193         seq_printf(m, "%pK: %c%c%c %8zdKiB %02x %02x %s%s%s",
194                    &obj->base,
195                    get_tiling_flag(obj),
196                    get_global_flag(obj),
197                    get_pin_mapped_flag(obj),
198                    obj->base.size / 1024,
199                    obj->read_domains,
200                    obj->write_domain,
201                    i915_cache_level_str(obj),
202                    obj->mm.dirty ? " dirty" : "",
203                    obj->mm.madv == I915_MADV_DONTNEED ? " purgeable" : "");
204         if (obj->base.name)
205                 seq_printf(m, " (name: %d)", obj->base.name);
206
207         spin_lock(&obj->vma.lock);
208         list_for_each_entry(vma, &obj->vma.list, obj_link) {
209                 if (!drm_mm_node_allocated(&vma->node))
210                         continue;
211
212                 spin_unlock(&obj->vma.lock);
213
214                 if (i915_vma_is_pinned(vma))
215                         pin_count++;
216
217                 seq_printf(m, " (%s offset: %08llx, size: %08llx, pages: %s",
218                            stringify_vma_type(vma),
219                            i915_vma_offset(vma), i915_vma_size(vma),
220                            stringify_page_sizes(vma->resource->page_sizes_gtt,
221                                                 NULL, 0));
222                 if (i915_vma_is_ggtt(vma) || i915_vma_is_dpt(vma)) {
223                         switch (vma->gtt_view.type) {
224                         case I915_GTT_VIEW_NORMAL:
225                                 seq_puts(m, ", normal");
226                                 break;
227
228                         case I915_GTT_VIEW_PARTIAL:
229                                 seq_printf(m, ", partial [%08llx+%x]",
230                                            vma->gtt_view.partial.offset << PAGE_SHIFT,
231                                            vma->gtt_view.partial.size << PAGE_SHIFT);
232                                 break;
233
234                         case I915_GTT_VIEW_ROTATED:
235                                 seq_printf(m, ", rotated [(%ux%u, src_stride=%u, dst_stride=%u, offset=%u), (%ux%u, src_stride=%u, dst_stride=%u, offset=%u)]",
236                                            vma->gtt_view.rotated.plane[0].width,
237                                            vma->gtt_view.rotated.plane[0].height,
238                                            vma->gtt_view.rotated.plane[0].src_stride,
239                                            vma->gtt_view.rotated.plane[0].dst_stride,
240                                            vma->gtt_view.rotated.plane[0].offset,
241                                            vma->gtt_view.rotated.plane[1].width,
242                                            vma->gtt_view.rotated.plane[1].height,
243                                            vma->gtt_view.rotated.plane[1].src_stride,
244                                            vma->gtt_view.rotated.plane[1].dst_stride,
245                                            vma->gtt_view.rotated.plane[1].offset);
246                                 break;
247
248                         case I915_GTT_VIEW_REMAPPED:
249                                 seq_printf(m, ", remapped [(%ux%u, src_stride=%u, dst_stride=%u, offset=%u), (%ux%u, src_stride=%u, dst_stride=%u, offset=%u)]",
250                                            vma->gtt_view.remapped.plane[0].width,
251                                            vma->gtt_view.remapped.plane[0].height,
252                                            vma->gtt_view.remapped.plane[0].src_stride,
253                                            vma->gtt_view.remapped.plane[0].dst_stride,
254                                            vma->gtt_view.remapped.plane[0].offset,
255                                            vma->gtt_view.remapped.plane[1].width,
256                                            vma->gtt_view.remapped.plane[1].height,
257                                            vma->gtt_view.remapped.plane[1].src_stride,
258                                            vma->gtt_view.remapped.plane[1].dst_stride,
259                                            vma->gtt_view.remapped.plane[1].offset);
260                                 break;
261
262                         default:
263                                 MISSING_CASE(vma->gtt_view.type);
264                                 break;
265                         }
266                 }
267                 if (vma->fence)
268                         seq_printf(m, " , fence: %d", vma->fence->id);
269                 seq_puts(m, ")");
270
271                 spin_lock(&obj->vma.lock);
272         }
273         spin_unlock(&obj->vma.lock);
274
275         seq_printf(m, " (pinned x %d)", pin_count);
276         if (i915_gem_object_is_stolen(obj))
277                 seq_printf(m, " (stolen: %08llx)", obj->stolen->start);
278         if (i915_gem_object_is_framebuffer(obj))
279                 seq_printf(m, " (fb)");
280 }
281
282 static int i915_gem_object_info(struct seq_file *m, void *data)
283 {
284         struct drm_i915_private *i915 = node_to_i915(m->private);
285         struct drm_printer p = drm_seq_file_printer(m);
286         struct intel_memory_region *mr;
287         enum intel_region_id id;
288
289         seq_printf(m, "%u shrinkable [%u free] objects, %llu bytes\n",
290                    i915->mm.shrink_count,
291                    atomic_read(&i915->mm.free_count),
292                    i915->mm.shrink_memory);
293         for_each_memory_region(mr, i915, id)
294                 intel_memory_region_debug(mr, &p);
295
296         return 0;
297 }
298
299 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
300 static ssize_t gpu_state_read(struct file *file, char __user *ubuf,
301                               size_t count, loff_t *pos)
302 {
303         struct i915_gpu_coredump *error;
304         ssize_t ret;
305         void *buf;
306
307         error = file->private_data;
308         if (!error)
309                 return 0;
310
311         /* Bounce buffer required because of kernfs __user API convenience. */
312         buf = kmalloc(count, GFP_KERNEL);
313         if (!buf)
314                 return -ENOMEM;
315
316         ret = i915_gpu_coredump_copy_to_buffer(error, buf, *pos, count);
317         if (ret <= 0)
318                 goto out;
319
320         if (!copy_to_user(ubuf, buf, ret))
321                 *pos += ret;
322         else
323                 ret = -EFAULT;
324
325 out:
326         kfree(buf);
327         return ret;
328 }
329
330 static int gpu_state_release(struct inode *inode, struct file *file)
331 {
332         i915_gpu_coredump_put(file->private_data);
333         return 0;
334 }
335
336 static int i915_gpu_info_open(struct inode *inode, struct file *file)
337 {
338         struct drm_i915_private *i915 = inode->i_private;
339         struct i915_gpu_coredump *gpu;
340         intel_wakeref_t wakeref;
341
342         gpu = NULL;
343         with_intel_runtime_pm(&i915->runtime_pm, wakeref)
344                 gpu = i915_gpu_coredump(to_gt(i915), ALL_ENGINES, CORE_DUMP_FLAG_NONE);
345
346         if (IS_ERR(gpu))
347                 return PTR_ERR(gpu);
348
349         file->private_data = gpu;
350         return 0;
351 }
352
353 static const struct file_operations i915_gpu_info_fops = {
354         .owner = THIS_MODULE,
355         .open = i915_gpu_info_open,
356         .read = gpu_state_read,
357         .llseek = default_llseek,
358         .release = gpu_state_release,
359 };
360
361 static ssize_t
362 i915_error_state_write(struct file *filp,
363                        const char __user *ubuf,
364                        size_t cnt,
365                        loff_t *ppos)
366 {
367         struct i915_gpu_coredump *error = filp->private_data;
368
369         if (!error)
370                 return 0;
371
372         drm_dbg(&error->i915->drm, "Resetting error state\n");
373         i915_reset_error_state(error->i915);
374
375         return cnt;
376 }
377
378 static int i915_error_state_open(struct inode *inode, struct file *file)
379 {
380         struct i915_gpu_coredump *error;
381
382         error = i915_first_error_state(inode->i_private);
383         if (IS_ERR(error))
384                 return PTR_ERR(error);
385
386         file->private_data  = error;
387         return 0;
388 }
389
390 static const struct file_operations i915_error_state_fops = {
391         .owner = THIS_MODULE,
392         .open = i915_error_state_open,
393         .read = gpu_state_read,
394         .write = i915_error_state_write,
395         .llseek = default_llseek,
396         .release = gpu_state_release,
397 };
398 #endif
399
400 static int i915_frequency_info(struct seq_file *m, void *unused)
401 {
402         struct drm_i915_private *i915 = node_to_i915(m->private);
403         struct intel_gt *gt = to_gt(i915);
404         struct drm_printer p = drm_seq_file_printer(m);
405
406         intel_gt_pm_frequency_dump(gt, &p);
407
408         return 0;
409 }
410
411 static const char *swizzle_string(unsigned swizzle)
412 {
413         switch (swizzle) {
414         case I915_BIT_6_SWIZZLE_NONE:
415                 return "none";
416         case I915_BIT_6_SWIZZLE_9:
417                 return "bit9";
418         case I915_BIT_6_SWIZZLE_9_10:
419                 return "bit9/bit10";
420         case I915_BIT_6_SWIZZLE_9_11:
421                 return "bit9/bit11";
422         case I915_BIT_6_SWIZZLE_9_10_11:
423                 return "bit9/bit10/bit11";
424         case I915_BIT_6_SWIZZLE_9_17:
425                 return "bit9/bit17";
426         case I915_BIT_6_SWIZZLE_9_10_17:
427                 return "bit9/bit10/bit17";
428         case I915_BIT_6_SWIZZLE_UNKNOWN:
429                 return "unknown";
430         }
431
432         return "bug";
433 }
434
435 static int i915_swizzle_info(struct seq_file *m, void *data)
436 {
437         struct drm_i915_private *dev_priv = node_to_i915(m->private);
438         struct intel_uncore *uncore = &dev_priv->uncore;
439         intel_wakeref_t wakeref;
440
441         seq_printf(m, "bit6 swizzle for X-tiling = %s\n",
442                    swizzle_string(to_gt(dev_priv)->ggtt->bit_6_swizzle_x));
443         seq_printf(m, "bit6 swizzle for Y-tiling = %s\n",
444                    swizzle_string(to_gt(dev_priv)->ggtt->bit_6_swizzle_y));
445
446         if (dev_priv->gem_quirks & GEM_QUIRK_PIN_SWIZZLED_PAGES)
447                 seq_puts(m, "L-shaped memory detected\n");
448
449         /* On BDW+, swizzling is not used. See detect_bit_6_swizzle() */
450         if (GRAPHICS_VER(dev_priv) >= 8 || IS_VALLEYVIEW(dev_priv))
451                 return 0;
452
453         wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
454
455         if (IS_GRAPHICS_VER(dev_priv, 3, 4)) {
456                 seq_printf(m, "DDC = 0x%08x\n",
457                            intel_uncore_read(uncore, DCC));
458                 seq_printf(m, "DDC2 = 0x%08x\n",
459                            intel_uncore_read(uncore, DCC2));
460                 seq_printf(m, "C0DRB3 = 0x%04x\n",
461                            intel_uncore_read16(uncore, C0DRB3_BW));
462                 seq_printf(m, "C1DRB3 = 0x%04x\n",
463                            intel_uncore_read16(uncore, C1DRB3_BW));
464         } else if (GRAPHICS_VER(dev_priv) >= 6) {
465                 seq_printf(m, "MAD_DIMM_C0 = 0x%08x\n",
466                            intel_uncore_read(uncore, MAD_DIMM_C0));
467                 seq_printf(m, "MAD_DIMM_C1 = 0x%08x\n",
468                            intel_uncore_read(uncore, MAD_DIMM_C1));
469                 seq_printf(m, "MAD_DIMM_C2 = 0x%08x\n",
470                            intel_uncore_read(uncore, MAD_DIMM_C2));
471                 seq_printf(m, "TILECTL = 0x%08x\n",
472                            intel_uncore_read(uncore, TILECTL));
473                 if (GRAPHICS_VER(dev_priv) >= 8)
474                         seq_printf(m, "GAMTARBMODE = 0x%08x\n",
475                                    intel_uncore_read(uncore, GAMTARBMODE));
476                 else
477                         seq_printf(m, "ARB_MODE = 0x%08x\n",
478                                    intel_uncore_read(uncore, ARB_MODE));
479                 seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
480                            intel_uncore_read(uncore, DISP_ARB_CTL));
481         }
482
483         intel_runtime_pm_put(&dev_priv->runtime_pm, wakeref);
484
485         return 0;
486 }
487
488 static int i915_rps_boost_info(struct seq_file *m, void *data)
489 {
490         struct drm_i915_private *dev_priv = node_to_i915(m->private);
491         struct intel_rps *rps = &to_gt(dev_priv)->rps;
492
493         seq_printf(m, "RPS enabled? %s\n",
494                    str_yes_no(intel_rps_is_enabled(rps)));
495         seq_printf(m, "RPS active? %s\n",
496                    str_yes_no(intel_rps_is_active(rps)));
497         seq_printf(m, "GPU busy? %s\n", str_yes_no(to_gt(dev_priv)->awake));
498         seq_printf(m, "Boosts outstanding? %d\n",
499                    atomic_read(&rps->num_waiters));
500         seq_printf(m, "Interactive? %d\n", READ_ONCE(rps->power.interactive));
501         seq_printf(m, "Frequency requested %d, actual %d\n",
502                    intel_gpu_freq(rps, rps->cur_freq),
503                    intel_rps_read_actual_frequency(rps));
504         seq_printf(m, "  min hard:%d, soft:%d; max soft:%d, hard:%d\n",
505                    intel_gpu_freq(rps, rps->min_freq),
506                    intel_gpu_freq(rps, rps->min_freq_softlimit),
507                    intel_gpu_freq(rps, rps->max_freq_softlimit),
508                    intel_gpu_freq(rps, rps->max_freq));
509         seq_printf(m, "  idle:%d, efficient:%d, boost:%d\n",
510                    intel_gpu_freq(rps, rps->idle_freq),
511                    intel_gpu_freq(rps, rps->efficient_freq),
512                    intel_gpu_freq(rps, rps->boost_freq));
513
514         seq_printf(m, "Wait boosts: %d\n", READ_ONCE(rps->boosts));
515
516         return 0;
517 }
518
519 static int i915_runtime_pm_status(struct seq_file *m, void *unused)
520 {
521         struct drm_i915_private *dev_priv = node_to_i915(m->private);
522         struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
523
524         if (!HAS_RUNTIME_PM(dev_priv))
525                 seq_puts(m, "Runtime power management not supported\n");
526
527         seq_printf(m, "Runtime power status: %s\n",
528                    str_enabled_disabled(!dev_priv->display.power.domains.init_wakeref));
529
530         seq_printf(m, "GPU idle: %s\n", str_yes_no(!to_gt(dev_priv)->awake));
531         seq_printf(m, "IRQs disabled: %s\n",
532                    str_yes_no(!intel_irqs_enabled(dev_priv)));
533 #ifdef CONFIG_PM
534         seq_printf(m, "Usage count: %d\n",
535                    atomic_read(&dev_priv->drm.dev->power.usage_count));
536 #else
537         seq_printf(m, "Device Power Management (CONFIG_PM) disabled\n");
538 #endif
539         seq_printf(m, "PCI device power state: %s [%d]\n",
540                    pci_power_name(pdev->current_state),
541                    pdev->current_state);
542
543         if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)) {
544                 struct drm_printer p = drm_seq_file_printer(m);
545
546                 print_intel_runtime_pm_wakeref(&dev_priv->runtime_pm, &p);
547         }
548
549         return 0;
550 }
551
552 static int i915_engine_info(struct seq_file *m, void *unused)
553 {
554         struct drm_i915_private *i915 = node_to_i915(m->private);
555         struct intel_engine_cs *engine;
556         intel_wakeref_t wakeref;
557         struct drm_printer p;
558
559         wakeref = intel_runtime_pm_get(&i915->runtime_pm);
560
561         seq_printf(m, "GT awake? %s [%d], %llums\n",
562                    str_yes_no(to_gt(i915)->awake),
563                    atomic_read(&to_gt(i915)->wakeref.count),
564                    ktime_to_ms(intel_gt_get_awake_time(to_gt(i915))));
565         seq_printf(m, "CS timestamp frequency: %u Hz, %d ns\n",
566                    to_gt(i915)->clock_frequency,
567                    to_gt(i915)->clock_period_ns);
568
569         p = drm_seq_file_printer(m);
570         for_each_uabi_engine(engine, i915)
571                 intel_engine_dump(engine, &p, "%s\n", engine->name);
572
573         intel_gt_show_timelines(to_gt(i915), &p, i915_request_show_with_schedule);
574
575         intel_runtime_pm_put(&i915->runtime_pm, wakeref);
576
577         return 0;
578 }
579
580 static int i915_wa_registers(struct seq_file *m, void *unused)
581 {
582         struct drm_i915_private *i915 = node_to_i915(m->private);
583         struct intel_engine_cs *engine;
584
585         for_each_uabi_engine(engine, i915) {
586                 const struct i915_wa_list *wal = &engine->ctx_wa_list;
587                 const struct i915_wa *wa;
588                 unsigned int count;
589
590                 count = wal->count;
591                 if (!count)
592                         continue;
593
594                 seq_printf(m, "%s: Workarounds applied: %u\n",
595                            engine->name, count);
596
597                 for (wa = wal->list; count--; wa++)
598                         seq_printf(m, "0x%X: 0x%08X, mask: 0x%08X\n",
599                                    i915_mmio_reg_offset(wa->reg),
600                                    wa->set, wa->clr);
601
602                 seq_printf(m, "\n");
603         }
604
605         return 0;
606 }
607
608 static int i915_wedged_get(void *data, u64 *val)
609 {
610         struct drm_i915_private *i915 = data;
611         struct intel_gt *gt;
612         unsigned int i;
613
614         *val = 0;
615
616         for_each_gt(gt, i915, i) {
617                 int ret;
618
619                 ret = intel_gt_debugfs_reset_show(gt, val);
620                 if (ret)
621                         return ret;
622
623                 /* at least one tile should be wedged */
624                 if (*val)
625                         break;
626         }
627
628         return 0;
629 }
630
631 static int i915_wedged_set(void *data, u64 val)
632 {
633         struct drm_i915_private *i915 = data;
634         struct intel_gt *gt;
635         unsigned int i;
636
637         for_each_gt(gt, i915, i)
638                 intel_gt_debugfs_reset_store(gt, val);
639
640         return 0;
641 }
642
643 DEFINE_SIMPLE_ATTRIBUTE(i915_wedged_fops,
644                         i915_wedged_get, i915_wedged_set,
645                         "%llu\n");
646
647 static int
648 i915_perf_noa_delay_set(void *data, u64 val)
649 {
650         struct drm_i915_private *i915 = data;
651
652         /*
653          * This would lead to infinite waits as we're doing timestamp
654          * difference on the CS with only 32bits.
655          */
656         if (intel_gt_ns_to_clock_interval(to_gt(i915), val) > U32_MAX)
657                 return -EINVAL;
658
659         atomic64_set(&i915->perf.noa_programming_delay, val);
660         return 0;
661 }
662
663 static int
664 i915_perf_noa_delay_get(void *data, u64 *val)
665 {
666         struct drm_i915_private *i915 = data;
667
668         *val = atomic64_read(&i915->perf.noa_programming_delay);
669         return 0;
670 }
671
672 DEFINE_SIMPLE_ATTRIBUTE(i915_perf_noa_delay_fops,
673                         i915_perf_noa_delay_get,
674                         i915_perf_noa_delay_set,
675                         "%llu\n");
676
677 #define DROP_UNBOUND    BIT(0)
678 #define DROP_BOUND      BIT(1)
679 #define DROP_RETIRE     BIT(2)
680 #define DROP_ACTIVE     BIT(3)
681 #define DROP_FREED      BIT(4)
682 #define DROP_SHRINK_ALL BIT(5)
683 #define DROP_IDLE       BIT(6)
684 #define DROP_RESET_ACTIVE       BIT(7)
685 #define DROP_RESET_SEQNO        BIT(8)
686 #define DROP_RCU        BIT(9)
687 #define DROP_ALL (DROP_UNBOUND  | \
688                   DROP_BOUND    | \
689                   DROP_RETIRE   | \
690                   DROP_ACTIVE   | \
691                   DROP_FREED    | \
692                   DROP_SHRINK_ALL |\
693                   DROP_IDLE     | \
694                   DROP_RESET_ACTIVE | \
695                   DROP_RESET_SEQNO | \
696                   DROP_RCU)
697 static int
698 i915_drop_caches_get(void *data, u64 *val)
699 {
700         *val = DROP_ALL;
701
702         return 0;
703 }
704
705 static int
706 gt_drop_caches(struct intel_gt *gt, u64 val)
707 {
708         int ret;
709
710         if (val & DROP_RESET_ACTIVE &&
711             wait_for(intel_engines_are_idle(gt), 200))
712                 intel_gt_set_wedged(gt);
713
714         if (val & DROP_RETIRE)
715                 intel_gt_retire_requests(gt);
716
717         if (val & (DROP_IDLE | DROP_ACTIVE)) {
718                 ret = intel_gt_wait_for_idle(gt, MAX_SCHEDULE_TIMEOUT);
719                 if (ret)
720                         return ret;
721         }
722
723         if (val & DROP_IDLE) {
724                 ret = intel_gt_pm_wait_for_idle(gt);
725                 if (ret)
726                         return ret;
727         }
728
729         if (val & DROP_RESET_ACTIVE && intel_gt_terminally_wedged(gt))
730                 intel_gt_handle_error(gt, ALL_ENGINES, 0, NULL);
731
732         if (val & DROP_FREED)
733                 intel_gt_flush_buffer_pool(gt);
734
735         return 0;
736 }
737
738 static int
739 i915_drop_caches_set(void *data, u64 val)
740 {
741         struct drm_i915_private *i915 = data;
742         unsigned int flags;
743         int ret;
744
745         drm_dbg(&i915->drm, "Dropping caches: 0x%08llx [0x%08llx]\n",
746                 val, val & DROP_ALL);
747
748         ret = gt_drop_caches(to_gt(i915), val);
749         if (ret)
750                 return ret;
751
752         fs_reclaim_acquire(GFP_KERNEL);
753         flags = memalloc_noreclaim_save();
754         if (val & DROP_BOUND)
755                 i915_gem_shrink(NULL, i915, LONG_MAX, NULL, I915_SHRINK_BOUND);
756
757         if (val & DROP_UNBOUND)
758                 i915_gem_shrink(NULL, i915, LONG_MAX, NULL, I915_SHRINK_UNBOUND);
759
760         if (val & DROP_SHRINK_ALL)
761                 i915_gem_shrink_all(i915);
762         memalloc_noreclaim_restore(flags);
763         fs_reclaim_release(GFP_KERNEL);
764
765         if (val & DROP_RCU)
766                 rcu_barrier();
767
768         if (val & DROP_FREED)
769                 i915_gem_drain_freed_objects(i915);
770
771         return 0;
772 }
773
774 DEFINE_SIMPLE_ATTRIBUTE(i915_drop_caches_fops,
775                         i915_drop_caches_get, i915_drop_caches_set,
776                         "0x%08llx\n");
777
778 static int i915_sseu_status(struct seq_file *m, void *unused)
779 {
780         struct drm_i915_private *i915 = node_to_i915(m->private);
781         struct intel_gt *gt = to_gt(i915);
782
783         return intel_sseu_status(m, gt);
784 }
785
786 static int i915_forcewake_open(struct inode *inode, struct file *file)
787 {
788         struct drm_i915_private *i915 = inode->i_private;
789         struct intel_gt *gt;
790         unsigned int i;
791
792         for_each_gt(gt, i915, i)
793                 intel_gt_pm_debugfs_forcewake_user_open(gt);
794
795         return 0;
796 }
797
798 static int i915_forcewake_release(struct inode *inode, struct file *file)
799 {
800         struct drm_i915_private *i915 = inode->i_private;
801         struct intel_gt *gt;
802         unsigned int i;
803
804         for_each_gt(gt, i915, i)
805                 intel_gt_pm_debugfs_forcewake_user_release(gt);
806
807         return 0;
808 }
809
810 static const struct file_operations i915_forcewake_fops = {
811         .owner = THIS_MODULE,
812         .open = i915_forcewake_open,
813         .release = i915_forcewake_release,
814 };
815
816 static const struct drm_info_list i915_debugfs_list[] = {
817         {"i915_capabilities", i915_capabilities, 0},
818         {"i915_gem_objects", i915_gem_object_info, 0},
819         {"i915_frequency_info", i915_frequency_info, 0},
820         {"i915_swizzle_info", i915_swizzle_info, 0},
821         {"i915_runtime_pm_status", i915_runtime_pm_status, 0},
822         {"i915_engine_info", i915_engine_info, 0},
823         {"i915_wa_registers", i915_wa_registers, 0},
824         {"i915_sseu_status", i915_sseu_status, 0},
825         {"i915_rps_boost_info", i915_rps_boost_info, 0},
826 };
827
828 static const struct i915_debugfs_files {
829         const char *name;
830         const struct file_operations *fops;
831 } i915_debugfs_files[] = {
832         {"i915_perf_noa_delay", &i915_perf_noa_delay_fops},
833         {"i915_wedged", &i915_wedged_fops},
834         {"i915_gem_drop_caches", &i915_drop_caches_fops},
835 #if IS_ENABLED(CONFIG_DRM_I915_CAPTURE_ERROR)
836         {"i915_error_state", &i915_error_state_fops},
837         {"i915_gpu_info", &i915_gpu_info_fops},
838 #endif
839 };
840
841 void i915_debugfs_register(struct drm_i915_private *dev_priv)
842 {
843         struct drm_minor *minor = dev_priv->drm.primary;
844         int i;
845
846         i915_debugfs_params(dev_priv);
847
848         debugfs_create_file("i915_forcewake_user", S_IRUSR, minor->debugfs_root,
849                             to_i915(minor->dev), &i915_forcewake_fops);
850         for (i = 0; i < ARRAY_SIZE(i915_debugfs_files); i++) {
851                 debugfs_create_file(i915_debugfs_files[i].name,
852                                     S_IRUGO | S_IWUSR,
853                                     minor->debugfs_root,
854                                     to_i915(minor->dev),
855                                     i915_debugfs_files[i].fops);
856         }
857
858         drm_debugfs_create_files(i915_debugfs_list,
859                                  ARRAY_SIZE(i915_debugfs_list),
860                                  minor->debugfs_root, minor);
861 }
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