drivers/gpu/drm/i915/gt/intel_reset.c

   1 // SPDX-License-Identifier: MIT
   2 /*
   3  * Copyright © 2008-2018 Intel Corporation
   4  */
   5
   6 #include <linux/sched/mm.h>
   7 #include <linux/stop_machine.h>
   8 #include <linux/string_helpers.h>
   9
  10 #include "display/intel_display_reset.h"
  11 #include "display/intel_overlay.h"
  12
  13 #include "gem/i915_gem_context.h"
  14
  15 #include "gt/intel_gt_regs.h"
  16
  17 #include "gt/uc/intel_gsc_fw.h"
  18
  19 #include "i915_drv.h"
  20 #include "i915_file_private.h"
  21 #include "i915_gpu_error.h"
  22 #include "i915_irq.h"
  23 #include "i915_reg.h"
  24 #include "intel_breadcrumbs.h"
  25 #include "intel_engine_pm.h"
  26 #include "intel_engine_regs.h"
  27 #include "intel_gt.h"
  28 #include "intel_gt_pm.h"
  29 #include "intel_gt_requests.h"
  30 #include "intel_mchbar_regs.h"
  31 #include "intel_pci_config.h"
  32 #include "intel_reset.h"
  33
  34 #include "uc/intel_guc.h"
  35
  36 #define RESET_MAX_RETRIES 3
  37
  38 /* XXX How to handle concurrent GGTT updates using tiling registers? */
  39 #define RESET_UNDER_STOP_MACHINE 0
  40
  41 static void client_mark_guilty(struct i915_gem_context *ctx, bool banned)
  42 {
  43         struct drm_i915_file_private *file_priv = ctx->file_priv;
  44         unsigned long prev_hang;
  45         unsigned int score;
  46
  47         if (IS_ERR_OR_NULL(file_priv))
  48                 return;
  49
  50         score = 0;
  51         if (banned)
  52                 score = I915_CLIENT_SCORE_CONTEXT_BAN;
  53
  54         prev_hang = xchg(&file_priv->hang_timestamp, jiffies);
  55         if (time_before(jiffies, prev_hang + I915_CLIENT_FAST_HANG_JIFFIES))
  56                 score += I915_CLIENT_SCORE_HANG_FAST;
  57
  58         if (score) {
  59                 atomic_add(score, &file_priv->ban_score);
  60
  61                 drm_dbg(&ctx->i915->drm,
  62                         "client %s: gained %u ban score, now %u\n",
  63                         ctx->name, score,
  64                         atomic_read(&file_priv->ban_score));
  65         }
  66 }
  67
  68 static bool mark_guilty(struct i915_request *rq)
  69 {
  70         struct i915_gem_context *ctx;
  71         unsigned long prev_hang;
  72         bool banned;
  73         int i;
  74
  75         if (intel_context_is_closed(rq->context))
  76                 return true;
  77
  78         rcu_read_lock();
  79         ctx = rcu_dereference(rq->context->gem_context);
  80         if (ctx && !kref_get_unless_zero(&ctx->ref))
  81                 ctx = NULL;
  82         rcu_read_unlock();
  83         if (!ctx)
  84                 return intel_context_is_banned(rq->context);
  85
  86         atomic_inc(&ctx->guilty_count);
  87
  88         /* Cool contexts are too cool to be banned! (Used for reset testing.) */
  89         if (!i915_gem_context_is_bannable(ctx)) {
  90                 banned = false;
  91                 goto out;
  92         }
  93
  94         drm_notice(&ctx->i915->drm,
  95                    "%s context reset due to GPU hang\n",
  96                    ctx->name);
  97
  98         /* Record the timestamp for the last N hangs */
  99         prev_hang = ctx->hang_timestamp[0];
 100         for (i = 0; i < ARRAY_SIZE(ctx->hang_timestamp) - 1; i++)
 101                 ctx->hang_timestamp[i] = ctx->hang_timestamp[i + 1];
 102         ctx->hang_timestamp[i] = jiffies;
 103
 104         /* If we have hung N+1 times in rapid succession, we ban the context! */
 105         banned = !i915_gem_context_is_recoverable(ctx);
 106         if (time_before(jiffies, prev_hang + CONTEXT_FAST_HANG_JIFFIES))
 107                 banned = true;
 108         if (banned)
 109                 drm_dbg(&ctx->i915->drm, "context %s: guilty %d, banned\n",
 110                         ctx->name, atomic_read(&ctx->guilty_count));
 111
 112         client_mark_guilty(ctx, banned);
 113
 114 out:
 115         i915_gem_context_put(ctx);
 116         return banned;
 117 }
 118
 119 static void mark_innocent(struct i915_request *rq)
 120 {
 121         struct i915_gem_context *ctx;
 122
 123         rcu_read_lock();
 124         ctx = rcu_dereference(rq->context->gem_context);
 125         if (ctx)
 126                 atomic_inc(&ctx->active_count);
 127         rcu_read_unlock();
 128 }
 129
 130 void __i915_request_reset(struct i915_request *rq, bool guilty)
 131 {
 132         bool banned = false;
 133
 134         RQ_TRACE(rq, "guilty? %s\n", str_yes_no(guilty));
 135         GEM_BUG_ON(__i915_request_is_complete(rq));
 136
 137         rcu_read_lock(); /* protect the GEM context */
 138         if (guilty) {
 139                 i915_request_set_error_once(rq, -EIO);
 140                 __i915_request_skip(rq);
 141                 banned = mark_guilty(rq);
 142         } else {
 143                 i915_request_set_error_once(rq, -EAGAIN);
 144                 mark_innocent(rq);
 145         }
 146         rcu_read_unlock();
 147
 148         if (banned)
 149                 intel_context_ban(rq->context, rq);
 150 }
 151
 152 static bool i915_in_reset(struct pci_dev *pdev)
 153 {
 154         u8 gdrst;
 155
 156         pci_read_config_byte(pdev, I915_GDRST, &gdrst);
 157         return gdrst & GRDOM_RESET_STATUS;
 158 }
 159
 160 static int i915_do_reset(struct intel_gt *gt,
 161                          intel_engine_mask_t engine_mask,
 162                          unsigned int retry)
 163 {
 164         struct pci_dev *pdev = to_pci_dev(gt->i915->drm.dev);
 165         int err;
 166
 167         /* Assert reset for at least 20 usec, and wait for acknowledgement. */
 168         pci_write_config_byte(pdev, I915_GDRST, GRDOM_RESET_ENABLE);
 169         udelay(50);
 170         err = wait_for_atomic(i915_in_reset(pdev), 50);
 171
 172         /* Clear the reset request. */
 173         pci_write_config_byte(pdev, I915_GDRST, 0);
 174         udelay(50);
 175         if (!err)
 176                 err = wait_for_atomic(!i915_in_reset(pdev), 50);
 177
 178         return err;
 179 }
 180
 181 static bool g4x_reset_complete(struct pci_dev *pdev)
 182 {
 183         u8 gdrst;
 184
 185         pci_read_config_byte(pdev, I915_GDRST, &gdrst);
 186         return (gdrst & GRDOM_RESET_ENABLE) == 0;
 187 }
 188
 189 static int g33_do_reset(struct intel_gt *gt,
 190                         intel_engine_mask_t engine_mask,
 191                         unsigned int retry)
 192 {
 193         struct pci_dev *pdev = to_pci_dev(gt->i915->drm.dev);
 194
 195         pci_write_config_byte(pdev, I915_GDRST, GRDOM_RESET_ENABLE);
 196         return wait_for_atomic(g4x_reset_complete(pdev), 50);
 197 }
 198
 199 static int g4x_do_reset(struct intel_gt *gt,
 200                         intel_engine_mask_t engine_mask,
 201                         unsigned int retry)
 202 {
 203         struct pci_dev *pdev = to_pci_dev(gt->i915->drm.dev);
 204         struct intel_uncore *uncore = gt->uncore;
 205         int ret;
 206
 207         /* WaVcpClkGateDisableForMediaReset:ctg,elk */
 208         intel_uncore_rmw_fw(uncore, VDECCLK_GATE_D, 0, VCP_UNIT_CLOCK_GATE_DISABLE);
 209         intel_uncore_posting_read_fw(uncore, VDECCLK_GATE_D);
 210
 211         pci_write_config_byte(pdev, I915_GDRST,
 212                               GRDOM_MEDIA | GRDOM_RESET_ENABLE);
 213         ret =  wait_for_atomic(g4x_reset_complete(pdev), 50);
 214         if (ret) {
 215                 GT_TRACE(gt, "Wait for media reset failed\n");
 216                 goto out;
 217         }
 218
 219         pci_write_config_byte(pdev, I915_GDRST,
 220                               GRDOM_RENDER | GRDOM_RESET_ENABLE);
 221         ret =  wait_for_atomic(g4x_reset_complete(pdev), 50);
 222         if (ret) {
 223                 GT_TRACE(gt, "Wait for render reset failed\n");
 224                 goto out;
 225         }
 226
 227 out:
 228         pci_write_config_byte(pdev, I915_GDRST, 0);
 229
 230         intel_uncore_rmw_fw(uncore, VDECCLK_GATE_D, VCP_UNIT_CLOCK_GATE_DISABLE, 0);
 231         intel_uncore_posting_read_fw(uncore, VDECCLK_GATE_D);
 232
 233         return ret;
 234 }
 235
 236 static int ilk_do_reset(struct intel_gt *gt, intel_engine_mask_t engine_mask,
 237                         unsigned int retry)
 238 {
 239         struct intel_uncore *uncore = gt->uncore;
 240         int ret;
 241
 242         intel_uncore_write_fw(uncore, ILK_GDSR,
 243                               ILK_GRDOM_RENDER | ILK_GRDOM_RESET_ENABLE);
 244         ret = __intel_wait_for_register_fw(uncore, ILK_GDSR,
 245                                            ILK_GRDOM_RESET_ENABLE, 0,
 246                                            5000, 0,
 247                                            NULL);
 248         if (ret) {
 249                 GT_TRACE(gt, "Wait for render reset failed\n");
 250                 goto out;
 251         }
 252
 253         intel_uncore_write_fw(uncore, ILK_GDSR,
 254                               ILK_GRDOM_MEDIA | ILK_GRDOM_RESET_ENABLE);
 255         ret = __intel_wait_for_register_fw(uncore, ILK_GDSR,
 256                                            ILK_GRDOM_RESET_ENABLE, 0,
 257                                            5000, 0,
 258                                            NULL);
 259         if (ret) {
 260                 GT_TRACE(gt, "Wait for media reset failed\n");
 261                 goto out;
 262         }
 263
 264 out:
 265         intel_uncore_write_fw(uncore, ILK_GDSR, 0);
 266         intel_uncore_posting_read_fw(uncore, ILK_GDSR);
 267         return ret;
 268 }
 269
 270 /* Reset the hardware domains (GENX_GRDOM_*) specified by mask */
 271 static int gen6_hw_domain_reset(struct intel_gt *gt, u32 hw_domain_mask)
 272 {
 273         struct intel_uncore *uncore = gt->uncore;
 274         int loops;
 275         int err;
 276
 277         /*
 278          * On some platforms, e.g. Jasperlake, we see that the engine register
 279          * state is not cleared until shortly after GDRST reports completion,
 280          * causing a failure as we try to immediately resume while the internal
 281          * state is still in flux. If we immediately repeat the reset, the
 282          * second reset appears to serialise with the first, and since it is a
 283          * no-op, the registers should retain their reset value. However, there
 284          * is still a concern that upon leaving the second reset, the internal
 285          * engine state is still in flux and not ready for resuming.
 286          *
 287          * Starting on MTL, there are some prep steps that we need to do when
 288          * resetting some engines that need to be applied every time we write to
 289          * GEN6_GDRST. As those are time consuming (tens of ms), we don't want
 290          * to perform that twice, so, since the Jasperlake issue hasn't been
 291          * observed on MTL, we avoid repeating the reset on newer platforms.
 292          */
 293         loops = GRAPHICS_VER_FULL(gt->i915) < IP_VER(12, 70) ? 2 : 1;
 294
 295         /*
 296          * GEN6_GDRST is not in the gt power well, no need to check
 297          * for fifo space for the write or forcewake the chip for
 298          * the read
 299          */
 300         do {
 301                 intel_uncore_write_fw(uncore, GEN6_GDRST, hw_domain_mask);
 302
 303                 /* Wait for the device to ack the reset requests. */
 304                 err = __intel_wait_for_register_fw(uncore, GEN6_GDRST,
 305                                                    hw_domain_mask, 0,
 306                                                    2000, 0,
 307                                                    NULL);
 308         } while (err == 0 && --loops);
 309         if (err)
 310                 GT_TRACE(gt,
 311                          "Wait for 0x%08x engines reset failed\n",
 312                          hw_domain_mask);
 313
 314         /*
 315          * As we have observed that the engine state is still volatile
 316          * after GDRST is acked, impose a small delay to let everything settle.
 317          */
 318         udelay(50);
 319
 320         return err;
 321 }
 322
 323 static int __gen6_reset_engines(struct intel_gt *gt,
 324                                 intel_engine_mask_t engine_mask,
 325                                 unsigned int retry)
 326 {
 327         struct intel_engine_cs *engine;
 328         u32 hw_mask;
 329
 330         if (engine_mask == ALL_ENGINES) {
 331                 hw_mask = GEN6_GRDOM_FULL;
 332         } else {
 333                 intel_engine_mask_t tmp;
 334
 335                 hw_mask = 0;
 336                 for_each_engine_masked(engine, gt, engine_mask, tmp) {
 337                         hw_mask |= engine->reset_domain;
 338                 }
 339         }
 340
 341         return gen6_hw_domain_reset(gt, hw_mask);
 342 }
 343
 344 static int gen6_reset_engines(struct intel_gt *gt,
 345                               intel_engine_mask_t engine_mask,
 346                               unsigned int retry)
 347 {
 348         unsigned long flags;
 349         int ret;
 350
 351         spin_lock_irqsave(&gt->uncore->lock, flags);
 352         ret = __gen6_reset_engines(gt, engine_mask, retry);
 353         spin_unlock_irqrestore(&gt->uncore->lock, flags);
 354
 355         return ret;
 356 }
 357
 358 static struct intel_engine_cs *find_sfc_paired_vecs_engine(struct intel_engine_cs *engine)
 359 {
 360         int vecs_id;
 361
 362         GEM_BUG_ON(engine->class != VIDEO_DECODE_CLASS);
 363
 364         vecs_id = _VECS((engine->instance) / 2);
 365
 366         return engine->gt->engine[vecs_id];
 367 }
 368
 369 struct sfc_lock_data {
 370         i915_reg_t lock_reg;
 371         i915_reg_t ack_reg;
 372         i915_reg_t usage_reg;
 373         u32 lock_bit;
 374         u32 ack_bit;
 375         u32 usage_bit;
 376         u32 reset_bit;
 377 };
 378
 379 static void get_sfc_forced_lock_data(struct intel_engine_cs *engine,
 380                                      struct sfc_lock_data *sfc_lock)
 381 {
 382         switch (engine->class) {
 383         default:
 384                 MISSING_CASE(engine->class);
 385                 fallthrough;
 386         case VIDEO_DECODE_CLASS:
 387                 sfc_lock->lock_reg = GEN11_VCS_SFC_FORCED_LOCK(engine->mmio_base);
 388                 sfc_lock->lock_bit = GEN11_VCS_SFC_FORCED_LOCK_BIT;
 389
 390                 sfc_lock->ack_reg = GEN11_VCS_SFC_LOCK_STATUS(engine->mmio_base);
 391                 sfc_lock->ack_bit  = GEN11_VCS_SFC_LOCK_ACK_BIT;
 392
 393                 sfc_lock->usage_reg = GEN11_VCS_SFC_LOCK_STATUS(engine->mmio_base);
 394                 sfc_lock->usage_bit = GEN11_VCS_SFC_USAGE_BIT;
 395                 sfc_lock->reset_bit = GEN11_VCS_SFC_RESET_BIT(engine->instance);
 396
 397                 break;
 398         case VIDEO_ENHANCEMENT_CLASS:
 399                 sfc_lock->lock_reg = GEN11_VECS_SFC_FORCED_LOCK(engine->mmio_base);
 400                 sfc_lock->lock_bit = GEN11_VECS_SFC_FORCED_LOCK_BIT;
 401
 402                 sfc_lock->ack_reg = GEN11_VECS_SFC_LOCK_ACK(engine->mmio_base);
 403                 sfc_lock->ack_bit  = GEN11_VECS_SFC_LOCK_ACK_BIT;
 404
 405                 sfc_lock->usage_reg = GEN11_VECS_SFC_USAGE(engine->mmio_base);
 406                 sfc_lock->usage_bit = GEN11_VECS_SFC_USAGE_BIT;
 407                 sfc_lock->reset_bit = GEN11_VECS_SFC_RESET_BIT(engine->instance);
 408
 409                 break;
 410         }
 411 }
 412
 413 static int gen11_lock_sfc(struct intel_engine_cs *engine,
 414                           u32 *reset_mask,
 415                           u32 *unlock_mask)
 416 {
 417         struct intel_uncore *uncore = engine->uncore;
 418         u8 vdbox_sfc_access = engine->gt->info.vdbox_sfc_access;
 419         struct sfc_lock_data sfc_lock;
 420         bool lock_obtained, lock_to_other = false;
 421         int ret;
 422
 423         switch (engine->class) {
 424         case VIDEO_DECODE_CLASS:
 425                 if ((BIT(engine->instance) & vdbox_sfc_access) == 0)
 426                         return 0;
 427
 428                 fallthrough;
 429         case VIDEO_ENHANCEMENT_CLASS:
 430                 get_sfc_forced_lock_data(engine, &sfc_lock);
 431
 432                 break;
 433         default:
 434                 return 0;
 435         }
 436
 437         if (!(intel_uncore_read_fw(uncore, sfc_lock.usage_reg) & sfc_lock.usage_bit)) {
 438                 struct intel_engine_cs *paired_vecs;
 439
 440                 if (engine->class != VIDEO_DECODE_CLASS ||
 441                     GRAPHICS_VER(engine->i915) != 12)
 442                         return 0;
 443
 444                 /*
 445                  * Wa_14010733141
 446                  *
 447                  * If the VCS-MFX isn't using the SFC, we also need to check
 448                  * whether VCS-HCP is using it.  If so, we need to issue a *VE*
 449                  * forced lock on the VE engine that shares the same SFC.
 450                  */
 451                 if (!(intel_uncore_read_fw(uncore,
 452                                            GEN12_HCP_SFC_LOCK_STATUS(engine->mmio_base)) &
 453                       GEN12_HCP_SFC_USAGE_BIT))
 454                         return 0;
 455
 456                 paired_vecs = find_sfc_paired_vecs_engine(engine);
 457                 get_sfc_forced_lock_data(paired_vecs, &sfc_lock);
 458                 lock_to_other = true;
 459                 *unlock_mask |= paired_vecs->mask;
 460         } else {
 461                 *unlock_mask |= engine->mask;
 462         }
 463
 464         /*
 465          * If the engine is using an SFC, tell the engine that a software reset
 466          * is going to happen. The engine will then try to force lock the SFC.
 467          * If SFC ends up being locked to the engine we want to reset, we have
 468          * to reset it as well (we will unlock it once the reset sequence is
 469          * completed).
 470          */
 471         intel_uncore_rmw_fw(uncore, sfc_lock.lock_reg, 0, sfc_lock.lock_bit);
 472
 473         ret = __intel_wait_for_register_fw(uncore,
 474                                            sfc_lock.ack_reg,
 475                                            sfc_lock.ack_bit,
 476                                            sfc_lock.ack_bit,
 477                                            1000, 0, NULL);
 478
 479         /*
 480          * Was the SFC released while we were trying to lock it?
 481          *
 482          * We should reset both the engine and the SFC if:
 483          *  - We were locking the SFC to this engine and the lock succeeded
 484          *       OR
 485          *  - We were locking the SFC to a different engine (Wa_14010733141)
 486          *    but the SFC was released before the lock was obtained.
 487          *
 488          * Otherwise we need only reset the engine by itself and we can
 489          * leave the SFC alone.
 490          */
 491         lock_obtained = (intel_uncore_read_fw(uncore, sfc_lock.usage_reg) &
 492                         sfc_lock.usage_bit) != 0;
 493         if (lock_obtained == lock_to_other)
 494                 return 0;
 495
 496         if (ret) {
 497                 ENGINE_TRACE(engine, "Wait for SFC forced lock ack failed\n");
 498                 return ret;
 499         }
 500
 501         *reset_mask |= sfc_lock.reset_bit;
 502         return 0;
 503 }
 504
 505 static void gen11_unlock_sfc(struct intel_engine_cs *engine)
 506 {
 507         struct intel_uncore *uncore = engine->uncore;
 508         u8 vdbox_sfc_access = engine->gt->info.vdbox_sfc_access;
 509         struct sfc_lock_data sfc_lock = {};
 510
 511         if (engine->class != VIDEO_DECODE_CLASS &&
 512             engine->class != VIDEO_ENHANCEMENT_CLASS)
 513                 return;
 514
 515         if (engine->class == VIDEO_DECODE_CLASS &&
 516             (BIT(engine->instance) & vdbox_sfc_access) == 0)
 517                 return;
 518
 519         get_sfc_forced_lock_data(engine, &sfc_lock);
 520
 521         intel_uncore_rmw_fw(uncore, sfc_lock.lock_reg, sfc_lock.lock_bit, 0);
 522 }
 523
 524 static int __gen11_reset_engines(struct intel_gt *gt,
 525                                  intel_engine_mask_t engine_mask,
 526                                  unsigned int retry)
 527 {
 528         struct intel_engine_cs *engine;
 529         intel_engine_mask_t tmp;
 530         u32 reset_mask, unlock_mask = 0;
 531         int ret;
 532
 533         if (engine_mask == ALL_ENGINES) {
 534                 reset_mask = GEN11_GRDOM_FULL;
 535         } else {
 536                 reset_mask = 0;
 537                 for_each_engine_masked(engine, gt, engine_mask, tmp) {
 538                         reset_mask |= engine->reset_domain;
 539                         ret = gen11_lock_sfc(engine, &reset_mask, &unlock_mask);
 540                         if (ret)
 541                                 goto sfc_unlock;
 542                 }
 543         }
 544
 545         ret = gen6_hw_domain_reset(gt, reset_mask);
 546
 547 sfc_unlock:
 548         /*
 549          * We unlock the SFC based on the lock status and not the result of
 550          * gen11_lock_sfc to make sure that we clean properly if something
 551          * wrong happened during the lock (e.g. lock acquired after timeout
 552          * expiration).
 553          *
 554          * Due to Wa_14010733141, we may have locked an SFC to an engine that
 555          * wasn't being reset.  So instead of calling gen11_unlock_sfc()
 556          * on engine_mask, we instead call it on the mask of engines that our
 557          * gen11_lock_sfc() calls told us actually had locks attempted.
 558          */
 559         for_each_engine_masked(engine, gt, unlock_mask, tmp)
 560                 gen11_unlock_sfc(engine);
 561
 562         return ret;
 563 }
 564
 565 static int gen8_engine_reset_prepare(struct intel_engine_cs *engine)
 566 {
 567         struct intel_uncore *uncore = engine->uncore;
 568         const i915_reg_t reg = RING_RESET_CTL(engine->mmio_base);
 569         u32 request, mask, ack;
 570         int ret;
 571
 572         if (I915_SELFTEST_ONLY(should_fail(&engine->reset_timeout, 1)))
 573                 return -ETIMEDOUT;
 574
 575         ack = intel_uncore_read_fw(uncore, reg);
 576         if (ack & RESET_CTL_CAT_ERROR) {
 577                 /*
 578                  * For catastrophic errors, ready-for-reset sequence
 579                  * needs to be bypassed: HAS#396813
 580                  */
 581                 request = RESET_CTL_CAT_ERROR;
 582                 mask = RESET_CTL_CAT_ERROR;
 583
 584                 /* Catastrophic errors need to be cleared by HW */
 585                 ack = 0;
 586         } else if (!(ack & RESET_CTL_READY_TO_RESET)) {
 587                 request = RESET_CTL_REQUEST_RESET;
 588                 mask = RESET_CTL_READY_TO_RESET;
 589                 ack = RESET_CTL_READY_TO_RESET;
 590         } else {
 591                 return 0;
 592         }
 593
 594         intel_uncore_write_fw(uncore, reg, _MASKED_BIT_ENABLE(request));
 595         ret = __intel_wait_for_register_fw(uncore, reg, mask, ack,
 596                                            700, 0, NULL);
 597         if (ret)
 598                 drm_err(&engine->i915->drm,
 599                         "%s reset request timed out: {request: %08x, RESET_CTL: %08x}\n",
 600                         engine->name, request,
 601                         intel_uncore_read_fw(uncore, reg));
 602
 603         return ret;
 604 }
 605
 606 static void gen8_engine_reset_cancel(struct intel_engine_cs *engine)
 607 {
 608         intel_uncore_write_fw(engine->uncore,
 609                               RING_RESET_CTL(engine->mmio_base),
 610                               _MASKED_BIT_DISABLE(RESET_CTL_REQUEST_RESET));
 611 }
 612
 613 static int gen8_reset_engines(struct intel_gt *gt,
 614                               intel_engine_mask_t engine_mask,
 615                               unsigned int retry)
 616 {
 617         struct intel_engine_cs *engine;
 618         const bool reset_non_ready = retry >= 1;
 619         intel_engine_mask_t tmp;
 620         unsigned long flags;
 621         int ret;
 622
 623         spin_lock_irqsave(&gt->uncore->lock, flags);
 624
 625         for_each_engine_masked(engine, gt, engine_mask, tmp) {
 626                 ret = gen8_engine_reset_prepare(engine);
 627                 if (ret && !reset_non_ready)
 628                         goto skip_reset;
 629
 630                 /*
 631                  * If this is not the first failed attempt to prepare,
 632                  * we decide to proceed anyway.
 633                  *
 634                  * By doing so we risk context corruption and with
 635                  * some gens (kbl), possible system hang if reset
 636                  * happens during active bb execution.
 637                  *
 638                  * We rather take context corruption instead of
 639                  * failed reset with a wedged driver/gpu. And
 640                  * active bb execution case should be covered by
 641                  * stop_engines() we have before the reset.
 642                  */
 643         }
 644
 645         /*
 646          * Wa_22011100796:dg2, whenever Full soft reset is required,
 647          * reset all individual engines firstly, and then do a full soft reset.
 648          *
 649          * This is best effort, so ignore any error from the initial reset.
 650          */
 651         if (IS_DG2(gt->i915) && engine_mask == ALL_ENGINES)
 652                 __gen11_reset_engines(gt, gt->info.engine_mask, 0);
 653
 654         if (GRAPHICS_VER(gt->i915) >= 11)
 655                 ret = __gen11_reset_engines(gt, engine_mask, retry);
 656         else
 657                 ret = __gen6_reset_engines(gt, engine_mask, retry);
 658
 659 skip_reset:
 660         for_each_engine_masked(engine, gt, engine_mask, tmp)
 661                 gen8_engine_reset_cancel(engine);
 662
 663         spin_unlock_irqrestore(&gt->uncore->lock, flags);
 664
 665         return ret;
 666 }
 667
 668 static int mock_reset(struct intel_gt *gt,
 669                       intel_engine_mask_t mask,
 670                       unsigned int retry)
 671 {
 672         return 0;
 673 }
 674
 675 typedef int (*reset_func)(struct intel_gt *,
 676                           intel_engine_mask_t engine_mask,
 677                           unsigned int retry);
 678
 679 static reset_func intel_get_gpu_reset(const struct intel_gt *gt)
 680 {
 681         struct drm_i915_private *i915 = gt->i915;
 682
 683         if (is_mock_gt(gt))
 684                 return mock_reset;
 685         else if (GRAPHICS_VER(i915) >= 8)
 686                 return gen8_reset_engines;
 687         else if (GRAPHICS_VER(i915) >= 6)
 688                 return gen6_reset_engines;
 689         else if (GRAPHICS_VER(i915) >= 5)
 690                 return ilk_do_reset;
 691         else if (IS_G4X(i915))
 692                 return g4x_do_reset;
 693         else if (IS_G33(i915) || IS_PINEVIEW(i915))
 694                 return g33_do_reset;
 695         else if (GRAPHICS_VER(i915) >= 3)
 696                 return i915_do_reset;
 697         else
 698                 return NULL;
 699 }
 700
 701 static int __reset_guc(struct intel_gt *gt)
 702 {
 703         u32 guc_domain =
 704                 GRAPHICS_VER(gt->i915) >= 11 ? GEN11_GRDOM_GUC : GEN9_GRDOM_GUC;
 705
 706         return gen6_hw_domain_reset(gt, guc_domain);
 707 }
 708
 709 static bool needs_wa_14015076503(struct intel_gt *gt, intel_engine_mask_t engine_mask)
 710 {
 711         if (!IS_METEORLAKE(gt->i915) || !HAS_ENGINE(gt, GSC0))
 712                 return false;
 713
 714         if (!__HAS_ENGINE(engine_mask, GSC0))
 715                 return false;
 716
 717         return intel_gsc_uc_fw_init_done(&gt->uc.gsc);
 718 }
 719
 720 static intel_engine_mask_t
 721 wa_14015076503_start(struct intel_gt *gt, intel_engine_mask_t engine_mask, bool first)
 722 {
 723         if (!needs_wa_14015076503(gt, engine_mask))
 724                 return engine_mask;
 725
 726         /*
 727          * wa_14015076503: if the GSC FW is loaded, we need to alert it that
 728          * we're going to do a GSC engine reset and then wait for 200ms for the
 729          * FW to get ready for it. However, if this is the first ALL_ENGINES
 730          * reset attempt and the GSC is not busy, we can try to instead reset
 731          * the GuC and all the other engines individually to avoid the 200ms
 732          * wait.
 733          * Skipping the GSC engine is safe because, differently from other
 734          * engines, the GSCCS only role is to forward the commands to the GSC
 735          * FW, so it doesn't have any HW outside of the CS itself and therefore
 736          * it has no state that we don't explicitly re-init on resume or on
 737          * context switch LRC or power context). The HW for the GSC uC is
 738          * managed by the GSC FW so we don't need to care about that.
 739          */
 740         if (engine_mask == ALL_ENGINES && first && intel_engine_is_idle(gt->engine[GSC0])) {
 741                 __reset_guc(gt);
 742                 engine_mask = gt->info.engine_mask & ~BIT(GSC0);
 743         } else {
 744                 intel_uncore_rmw(gt->uncore,
 745                                  HECI_H_GS1(MTL_GSC_HECI2_BASE),
 746                                  0, HECI_H_GS1_ER_PREP);
 747
 748                 /* make sure the reset bit is clear when writing the CSR reg */
 749                 intel_uncore_rmw(gt->uncore,
 750                                  HECI_H_CSR(MTL_GSC_HECI2_BASE),
 751                                  HECI_H_CSR_RST, HECI_H_CSR_IG);
 752                 msleep(200);
 753         }
 754
 755         return engine_mask;
 756 }
 757
 758 static void
 759 wa_14015076503_end(struct intel_gt *gt, intel_engine_mask_t engine_mask)
 760 {
 761         if (!needs_wa_14015076503(gt, engine_mask))
 762                 return;
 763
 764         intel_uncore_rmw(gt->uncore,
 765                          HECI_H_GS1(MTL_GSC_HECI2_BASE),
 766                          HECI_H_GS1_ER_PREP, 0);
 767 }
 768
 769 int __intel_gt_reset(struct intel_gt *gt, intel_engine_mask_t engine_mask)
 770 {
 771         const int retries = engine_mask == ALL_ENGINES ? RESET_MAX_RETRIES : 1;
 772         reset_func reset;
 773         int ret = -ETIMEDOUT;
 774         int retry;
 775
 776         reset = intel_get_gpu_reset(gt);
 777         if (!reset)
 778                 return -ENODEV;
 779
 780         /*
 781          * If the power well sleeps during the reset, the reset
 782          * request may be dropped and never completes (causing -EIO).
 783          */
 784         intel_uncore_forcewake_get(gt->uncore, FORCEWAKE_ALL);
 785         for (retry = 0; ret == -ETIMEDOUT && retry < retries; retry++) {
 786                 intel_engine_mask_t reset_mask;
 787
 788                 reset_mask = wa_14015076503_start(gt, engine_mask, !retry);
 789
 790                 GT_TRACE(gt, "engine_mask=%x\n", reset_mask);
 791                 preempt_disable();
 792                 ret = reset(gt, reset_mask, retry);
 793                 preempt_enable();
 794
 795                 wa_14015076503_end(gt, reset_mask);
 796         }
 797         intel_uncore_forcewake_put(gt->uncore, FORCEWAKE_ALL);
 798
 799         return ret;
 800 }
 801
 802 bool intel_has_gpu_reset(const struct intel_gt *gt)
 803 {
 804         if (!gt->i915->params.reset)
 805                 return NULL;
 806
 807         return intel_get_gpu_reset(gt);
 808 }
 809
 810 bool intel_has_reset_engine(const struct intel_gt *gt)
 811 {
 812         if (gt->i915->params.reset < 2)
 813                 return false;
 814
 815         return INTEL_INFO(gt->i915)->has_reset_engine;
 816 }
 817
 818 int intel_reset_guc(struct intel_gt *gt)
 819 {
 820         int ret;
 821
 822         GEM_BUG_ON(!HAS_GT_UC(gt->i915));
 823
 824         intel_uncore_forcewake_get(gt->uncore, FORCEWAKE_ALL);
 825         ret = __reset_guc(gt);
 826         intel_uncore_forcewake_put(gt->uncore, FORCEWAKE_ALL);
 827
 828         return ret;
 829 }
 830
 831 /*
 832  * Ensure irq handler finishes, and not run again.
 833  * Also return the active request so that we only search for it once.
 834  */
 835 static void reset_prepare_engine(struct intel_engine_cs *engine)
 836 {
 837         /*
 838          * During the reset sequence, we must prevent the engine from
 839          * entering RC6. As the context state is undefined until we restart
 840          * the engine, if it does enter RC6 during the reset, the state
 841          * written to the powercontext is undefined and so we may lose
 842          * GPU state upon resume, i.e. fail to restart after a reset.
 843          */
 844         intel_uncore_forcewake_get(engine->uncore, FORCEWAKE_ALL);
 845         if (engine->reset.prepare)
 846                 engine->reset.prepare(engine);
 847 }
 848
 849 static void revoke_mmaps(struct intel_gt *gt)
 850 {
 851         int i;
 852
 853         for (i = 0; i < gt->ggtt->num_fences; i++) {
 854                 struct drm_vma_offset_node *node;
 855                 struct i915_vma *vma;
 856                 u64 vma_offset;
 857
 858                 vma = READ_ONCE(gt->ggtt->fence_regs[i].vma);
 859                 if (!vma)
 860                         continue;
 861
 862                 if (!i915_vma_has_userfault(vma))
 863                         continue;
 864
 865                 GEM_BUG_ON(vma->fence != &gt->ggtt->fence_regs[i]);
 866
 867                 if (!vma->mmo)
 868                         continue;
 869
 870                 node = &vma->mmo->vma_node;
 871                 vma_offset = vma->gtt_view.partial.offset << PAGE_SHIFT;
 872
 873                 unmap_mapping_range(gt->i915->drm.anon_inode->i_mapping,
 874                                     drm_vma_node_offset_addr(node) + vma_offset,
 875                                     vma->size,
 876                                     1);
 877         }
 878 }
 879
 880 static intel_engine_mask_t reset_prepare(struct intel_gt *gt)
 881 {
 882         struct intel_engine_cs *engine;
 883         intel_engine_mask_t awake = 0;
 884         enum intel_engine_id id;
 885
 886         /* For GuC mode, ensure submission is disabled before stopping ring */
 887         intel_uc_reset_prepare(&gt->uc);
 888
 889         for_each_engine(engine, gt, id) {
 890                 if (intel_engine_pm_get_if_awake(engine))
 891                         awake |= engine->mask;
 892                 reset_prepare_engine(engine);
 893         }
 894
 895         return awake;
 896 }
 897
 898 static void gt_revoke(struct intel_gt *gt)
 899 {
 900         revoke_mmaps(gt);
 901 }
 902
 903 static int gt_reset(struct intel_gt *gt, intel_engine_mask_t stalled_mask)
 904 {
 905         struct intel_engine_cs *engine;
 906         enum intel_engine_id id;
 907         int err;
 908
 909         /*
 910          * Everything depends on having the GTT running, so we need to start
 911          * there.
 912          */
 913         err = i915_ggtt_enable_hw(gt->i915);
 914         if (err)
 915                 return err;
 916
 917         local_bh_disable();
 918         for_each_engine(engine, gt, id)
 919                 __intel_engine_reset(engine, stalled_mask & engine->mask);
 920         local_bh_enable();
 921
 922         intel_uc_reset(&gt->uc, ALL_ENGINES);
 923
 924         intel_ggtt_restore_fences(gt->ggtt);
 925
 926         return err;
 927 }
 928
 929 static void reset_finish_engine(struct intel_engine_cs *engine)
 930 {
 931         if (engine->reset.finish)
 932                 engine->reset.finish(engine);
 933         intel_uncore_forcewake_put(engine->uncore, FORCEWAKE_ALL);
 934
 935         intel_engine_signal_breadcrumbs(engine);
 936 }
 937
 938 static void reset_finish(struct intel_gt *gt, intel_engine_mask_t awake)
 939 {
 940         struct intel_engine_cs *engine;
 941         enum intel_engine_id id;
 942
 943         for_each_engine(engine, gt, id) {
 944                 reset_finish_engine(engine);
 945                 if (awake & engine->mask)
 946                         intel_engine_pm_put(engine);
 947         }
 948
 949         intel_uc_reset_finish(&gt->uc);
 950 }
 951
 952 static void nop_submit_request(struct i915_request *request)
 953 {
 954         RQ_TRACE(request, "-EIO\n");
 955
 956         request = i915_request_mark_eio(request);
 957         if (request) {
 958                 i915_request_submit(request);
 959                 intel_engine_signal_breadcrumbs(request->engine);
 960
 961                 i915_request_put(request);
 962         }
 963 }
 964
 965 static void __intel_gt_set_wedged(struct intel_gt *gt)
 966 {
 967         struct intel_engine_cs *engine;
 968         intel_engine_mask_t awake;
 969         enum intel_engine_id id;
 970
 971         if (test_bit(I915_WEDGED, &gt->reset.flags))
 972                 return;
 973
 974         GT_TRACE(gt, "start\n");
 975
 976         /*
 977          * First, stop submission to hw, but do not yet complete requests by
 978          * rolling the global seqno forward (since this would complete requests
 979          * for which we haven't set the fence error to EIO yet).
 980          */
 981         awake = reset_prepare(gt);
 982
 983         /* Even if the GPU reset fails, it should still stop the engines */
 984         if (!INTEL_INFO(gt->i915)->gpu_reset_clobbers_display)
 985                 __intel_gt_reset(gt, ALL_ENGINES);
 986
 987         for_each_engine(engine, gt, id)
 988                 engine->submit_request = nop_submit_request;
 989
 990         /*
 991          * Make sure no request can slip through without getting completed by
 992          * either this call here to intel_engine_write_global_seqno, or the one
 993          * in nop_submit_request.
 994          */
 995         synchronize_rcu_expedited();
 996         set_bit(I915_WEDGED, &gt->reset.flags);
 997
 998         /* Mark all executing requests as skipped */
 999         local_bh_disable();
1000         for_each_engine(engine, gt, id)
1001                 if (engine->reset.cancel)
1002                         engine->reset.cancel(engine);
1003         intel_uc_cancel_requests(&gt->uc);
1004         local_bh_enable();
1005
1006         reset_finish(gt, awake);
1007
1008         GT_TRACE(gt, "end\n");
1009 }
1010
1011 void intel_gt_set_wedged(struct intel_gt *gt)
1012 {
1013         intel_wakeref_t wakeref;
1014
1015         if (test_bit(I915_WEDGED, &gt->reset.flags))
1016                 return;
1017
1018         wakeref = intel_runtime_pm_get(gt->uncore->rpm);
1019         mutex_lock(&gt->reset.mutex);
1020
1021         if (GEM_SHOW_DEBUG()) {
1022                 struct drm_printer p = drm_debug_printer(__func__);
1023                 struct intel_engine_cs *engine;
1024                 enum intel_engine_id id;
1025
1026                 drm_printf(&p, "called from %pS\n", (void *)_RET_IP_);
1027                 for_each_engine(engine, gt, id) {
1028                         if (intel_engine_is_idle(engine))
1029                                 continue;
1030
1031                         intel_engine_dump(engine, &p, "%s\n", engine->name);
1032                 }
1033         }
1034
1035         __intel_gt_set_wedged(gt);
1036
1037         mutex_unlock(&gt->reset.mutex);
1038         intel_runtime_pm_put(gt->uncore->rpm, wakeref);
1039 }
1040
1041 static bool __intel_gt_unset_wedged(struct intel_gt *gt)
1042 {
1043         struct intel_gt_timelines *timelines = &gt->timelines;
1044         struct intel_timeline *tl;
1045         bool ok;
1046
1047         if (!test_bit(I915_WEDGED, &gt->reset.flags))
1048                 return true;
1049
1050         /* Never fully initialised, recovery impossible */
1051         if (intel_gt_has_unrecoverable_error(gt))
1052                 return false;
1053
1054         GT_TRACE(gt, "start\n");
1055
1056         /*
1057          * Before unwedging, make sure that all pending operations
1058          * are flushed and errored out - we may have requests waiting upon
1059          * third party fences. We marked all inflight requests as EIO, and
1060          * every execbuf since returned EIO, for consistency we want all
1061          * the currently pending requests to also be marked as EIO, which
1062          * is done inside our nop_submit_request - and so we must wait.
1063          *
1064          * No more can be submitted until we reset the wedged bit.
1065          */
1066         spin_lock(&timelines->lock);
1067         list_for_each_entry(tl, &timelines->active_list, link) {
1068                 struct dma_fence *fence;
1069
1070                 fence = i915_active_fence_get(&tl->last_request);
1071                 if (!fence)
1072                         continue;
1073
1074                 spin_unlock(&timelines->lock);
1075
1076                 /*
1077                  * All internal dependencies (i915_requests) will have
1078                  * been flushed by the set-wedge, but we may be stuck waiting
1079                  * for external fences. These should all be capped to 10s
1080                  * (I915_FENCE_TIMEOUT) so this wait should not be unbounded
1081                  * in the worst case.
1082                  */
1083                 dma_fence_default_wait(fence, false, MAX_SCHEDULE_TIMEOUT);
1084                 dma_fence_put(fence);
1085
1086                 /* Restart iteration after droping lock */
1087                 spin_lock(&timelines->lock);
1088                 tl = list_entry(&timelines->active_list, typeof(*tl), link);
1089         }
1090         spin_unlock(&timelines->lock);
1091
1092         /* We must reset pending GPU events before restoring our submission */
1093         ok = !HAS_EXECLISTS(gt->i915); /* XXX better agnosticism desired */
1094         if (!INTEL_INFO(gt->i915)->gpu_reset_clobbers_display)
1095                 ok = __intel_gt_reset(gt, ALL_ENGINES) == 0;
1096         if (!ok) {
1097                 /*
1098                  * Warn CI about the unrecoverable wedged condition.
1099                  * Time for a reboot.
1100                  */
1101                 add_taint_for_CI(gt->i915, TAINT_WARN);
1102                 return false;
1103         }
1104
1105         /*
1106          * Undo nop_submit_request. We prevent all new i915 requests from
1107          * being queued (by disallowing execbuf whilst wedged) so having
1108          * waited for all active requests above, we know the system is idle
1109          * and do not have to worry about a thread being inside
1110          * engine->submit_request() as we swap over. So unlike installing
1111          * the nop_submit_request on reset, we can do this from normal
1112          * context and do not require stop_machine().
1113          */
1114         intel_engines_reset_default_submission(gt);
1115
1116         GT_TRACE(gt, "end\n");
1117
1118         smp_mb__before_atomic(); /* complete takeover before enabling execbuf */
1119         clear_bit(I915_WEDGED, &gt->reset.flags);
1120
1121         return true;
1122 }
1123
1124 bool intel_gt_unset_wedged(struct intel_gt *gt)
1125 {
1126         bool result;
1127
1128         mutex_lock(&gt->reset.mutex);
1129         result = __intel_gt_unset_wedged(gt);
1130         mutex_unlock(&gt->reset.mutex);
1131
1132         return result;
1133 }
1134
1135 static int do_reset(struct intel_gt *gt, intel_engine_mask_t stalled_mask)
1136 {
1137         int err, i;
1138
1139         err = __intel_gt_reset(gt, ALL_ENGINES);
1140         for (i = 0; err && i < RESET_MAX_RETRIES; i++) {
1141                 msleep(10 * (i + 1));
1142                 err = __intel_gt_reset(gt, ALL_ENGINES);
1143         }
1144         if (err)
1145                 return err;
1146
1147         return gt_reset(gt, stalled_mask);
1148 }
1149
1150 static int resume(struct intel_gt *gt)
1151 {
1152         struct intel_engine_cs *engine;
1153         enum intel_engine_id id;
1154         int ret;
1155
1156         for_each_engine(engine, gt, id) {
1157                 ret = intel_engine_resume(engine);
1158                 if (ret)
1159                         return ret;
1160         }
1161
1162         return 0;
1163 }
1164
1165 /**
1166  * intel_gt_reset - reset chip after a hang
1167  * @gt: #intel_gt to reset
1168  * @stalled_mask: mask of the stalled engines with the guilty requests
1169  * @reason: user error message for why we are resetting
1170  *
1171  * Reset the chip.  Useful if a hang is detected. Marks the device as wedged
1172  * on failure.
1173  *
1174  * Procedure is fairly simple:
1175  *   - reset the chip using the reset reg
1176  *   - re-init context state
1177  *   - re-init hardware status page
1178  *   - re-init ring buffer
1179  *   - re-init interrupt state
1180  *   - re-init display
1181  */
1182 void intel_gt_reset(struct intel_gt *gt,
1183                     intel_engine_mask_t stalled_mask,
1184                     const char *reason)
1185 {
1186         intel_engine_mask_t awake;
1187         int ret;
1188
1189         GT_TRACE(gt, "flags=%lx\n", gt->reset.flags);
1190
1191         might_sleep();
1192         GEM_BUG_ON(!test_bit(I915_RESET_BACKOFF, &gt->reset.flags));
1193
1194         /*
1195          * FIXME: Revoking cpu mmap ptes cannot be done from a dma_fence
1196          * critical section like gpu reset.
1197          */
1198         gt_revoke(gt);
1199
1200         mutex_lock(&gt->reset.mutex);
1201
1202         /* Clear any previous failed attempts at recovery. Time to try again. */
1203         if (!__intel_gt_unset_wedged(gt))
1204                 goto unlock;
1205
1206         if (reason)
1207                 drm_notice(&gt->i915->drm,
1208                            "Resetting chip for %s\n", reason);
1209         atomic_inc(&gt->i915->gpu_error.reset_count);
1210
1211         awake = reset_prepare(gt);
1212
1213         if (!intel_has_gpu_reset(gt)) {
1214                 if (gt->i915->params.reset)
1215                         drm_err(&gt->i915->drm, "GPU reset not supported\n");
1216                 else
1217                         drm_dbg(&gt->i915->drm, "GPU reset disabled\n");
1218                 goto error;
1219         }
1220
1221         if (INTEL_INFO(gt->i915)->gpu_reset_clobbers_display)
1222                 intel_runtime_pm_disable_interrupts(gt->i915);
1223
1224         if (do_reset(gt, stalled_mask)) {
1225                 drm_err(&gt->i915->drm, "Failed to reset chip\n");
1226                 goto taint;
1227         }
1228
1229         if (INTEL_INFO(gt->i915)->gpu_reset_clobbers_display)
1230                 intel_runtime_pm_enable_interrupts(gt->i915);
1231
1232         intel_overlay_reset(gt->i915);
1233
1234         /*
1235          * Next we need to restore the context, but we don't use those
1236          * yet either...
1237          *
1238          * Ring buffer needs to be re-initialized in the KMS case, or if X
1239          * was running at the time of the reset (i.e. we weren't VT
1240          * switched away).
1241          */
1242         ret = intel_gt_init_hw(gt);
1243         if (ret) {
1244                 drm_err(&gt->i915->drm,
1245                         "Failed to initialise HW following reset (%d)\n",
1246                         ret);
1247                 goto taint;
1248         }
1249
1250         ret = resume(gt);
1251         if (ret)
1252                 goto taint;
1253
1254 finish:
1255         reset_finish(gt, awake);
1256 unlock:
1257         mutex_unlock(&gt->reset.mutex);
1258         return;
1259
1260 taint:
1261         /*
1262          * History tells us that if we cannot reset the GPU now, we
1263          * never will. This then impacts everything that is run
1264          * subsequently. On failing the reset, we mark the driver
1265          * as wedged, preventing further execution on the GPU.
1266          * We also want to go one step further and add a taint to the
1267          * kernel so that any subsequent faults can be traced back to
1268          * this failure. This is important for CI, where if the
1269          * GPU/driver fails we would like to reboot and restart testing
1270          * rather than continue on into oblivion. For everyone else,
1271          * the system should still plod along, but they have been warned!
1272          */
1273         add_taint_for_CI(gt->i915, TAINT_WARN);
1274 error:
1275         __intel_gt_set_wedged(gt);
1276         goto finish;
1277 }
1278
1279 static int intel_gt_reset_engine(struct intel_engine_cs *engine)
1280 {
1281         return __intel_gt_reset(engine->gt, engine->mask);
1282 }
1283
1284 int __intel_engine_reset_bh(struct intel_engine_cs *engine, const char *msg)
1285 {
1286         struct intel_gt *gt = engine->gt;
1287         int ret;
1288
1289         ENGINE_TRACE(engine, "flags=%lx\n", gt->reset.flags);
1290         GEM_BUG_ON(!test_bit(I915_RESET_ENGINE + engine->id, &gt->reset.flags));
1291
1292         if (intel_engine_uses_guc(engine))
1293                 return -ENODEV;
1294
1295         if (!intel_engine_pm_get_if_awake(engine))
1296                 return 0;
1297
1298         reset_prepare_engine(engine);
1299
1300         if (msg)
1301                 drm_notice(&engine->i915->drm,
1302                            "Resetting %s for %s\n", engine->name, msg);
1303         atomic_inc(&engine->i915->gpu_error.reset_engine_count[engine->uabi_class]);
1304
1305         ret = intel_gt_reset_engine(engine);
1306         if (ret) {
1307                 /* If we fail here, we expect to fallback to a global reset */
1308                 ENGINE_TRACE(engine, "Failed to reset %s, err: %d\n", engine->name, ret);
1309                 goto out;
1310         }
1311
1312         /*
1313          * The request that caused the hang is stuck on elsp, we know the
1314          * active request and can drop it, adjust head to skip the offending
1315          * request to resume executing remaining requests in the queue.
1316          */
1317         __intel_engine_reset(engine, true);
1318
1319         /*
1320          * The engine and its registers (and workarounds in case of render)
1321          * have been reset to their default values. Follow the init_ring
1322          * process to program RING_MODE, HWSP and re-enable submission.
1323          */
1324         ret = intel_engine_resume(engine);
1325
1326 out:
1327         intel_engine_cancel_stop_cs(engine);
1328         reset_finish_engine(engine);
1329         intel_engine_pm_put_async(engine);
1330         return ret;
1331 }
1332
1333 /**
1334  * intel_engine_reset - reset GPU engine to recover from a hang
1335  * @engine: engine to reset
1336  * @msg: reason for GPU reset; or NULL for no drm_notice()
1337  *
1338  * Reset a specific GPU engine. Useful if a hang is detected.
1339  * Returns zero on successful reset or otherwise an error code.
1340  *
1341  * Procedure is:
1342  *  - identifies the request that caused the hang and it is dropped
1343  *  - reset engine (which will force the engine to idle)
1344  *  - re-init/configure engine
1345  */
1346 int intel_engine_reset(struct intel_engine_cs *engine, const char *msg)
1347 {
1348         int err;
1349
1350         local_bh_disable();
1351         err = __intel_engine_reset_bh(engine, msg);
1352         local_bh_enable();
1353
1354         return err;
1355 }
1356
1357 static void intel_gt_reset_global(struct intel_gt *gt,
1358                                   u32 engine_mask,
1359                                   const char *reason)
1360 {
1361         struct kobject *kobj = &gt->i915->drm.primary->kdev->kobj;
1362         char *error_event[] = { I915_ERROR_UEVENT "=1", NULL };
1363         char *reset_event[] = { I915_RESET_UEVENT "=1", NULL };
1364         char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL };
1365         struct intel_wedge_me w;
1366
1367         kobject_uevent_env(kobj, KOBJ_CHANGE, error_event);
1368
1369         GT_TRACE(gt, "resetting chip, engines=%x\n", engine_mask);
1370         kobject_uevent_env(kobj, KOBJ_CHANGE, reset_event);
1371
1372         /* Use a watchdog to ensure that our reset completes */
1373         intel_wedge_on_timeout(&w, gt, 60 * HZ) {
1374                 intel_display_reset_prepare(gt->i915);
1375
1376                 intel_gt_reset(gt, engine_mask, reason);
1377
1378                 intel_display_reset_finish(gt->i915);
1379         }
1380
1381         if (!test_bit(I915_WEDGED, &gt->reset.flags))
1382                 kobject_uevent_env(kobj, KOBJ_CHANGE, reset_done_event);
1383 }
1384
1385 /**
1386  * intel_gt_handle_error - handle a gpu error
1387  * @gt: the intel_gt
1388  * @engine_mask: mask representing engines that are hung
1389  * @flags: control flags
1390  * @fmt: Error message format string
1391  *
1392  * Do some basic checking of register state at error time and
1393  * dump it to the syslog.  Also call i915_capture_error_state() to make
1394  * sure we get a record and make it available in debugfs.  Fire a uevent
1395  * so userspace knows something bad happened (should trigger collection
1396  * of a ring dump etc.).
1397  */
1398 void intel_gt_handle_error(struct intel_gt *gt,
1399                            intel_engine_mask_t engine_mask,
1400                            unsigned long flags,
1401                            const char *fmt, ...)
1402 {
1403         struct intel_engine_cs *engine;
1404         intel_wakeref_t wakeref;
1405         intel_engine_mask_t tmp;
1406         char error_msg[80];
1407         char *msg = NULL;
1408
1409         if (fmt) {
1410                 va_list args;
1411
1412                 va_start(args, fmt);
1413                 vscnprintf(error_msg, sizeof(error_msg), fmt, args);
1414                 va_end(args);
1415
1416                 msg = error_msg;
1417         }
1418
1419         /*
1420          * In most cases it's guaranteed that we get here with an RPM
1421          * reference held, for example because there is a pending GPU
1422          * request that won't finish until the reset is done. This
1423          * isn't the case at least when we get here by doing a
1424          * simulated reset via debugfs, so get an RPM reference.
1425          */
1426         wakeref = intel_runtime_pm_get(gt->uncore->rpm);
1427
1428         engine_mask &= gt->info.engine_mask;
1429
1430         if (flags & I915_ERROR_CAPTURE) {
1431                 i915_capture_error_state(gt, engine_mask, CORE_DUMP_FLAG_NONE);
1432                 intel_gt_clear_error_registers(gt, engine_mask);
1433         }
1434
1435         /*
1436          * Try engine reset when available. We fall back to full reset if
1437          * single reset fails.
1438          */
1439         if (!intel_uc_uses_guc_submission(&gt->uc) &&
1440             intel_has_reset_engine(gt) && !intel_gt_is_wedged(gt)) {
1441                 local_bh_disable();
1442                 for_each_engine_masked(engine, gt, engine_mask, tmp) {
1443                         BUILD_BUG_ON(I915_RESET_MODESET >= I915_RESET_ENGINE);
1444                         if (test_and_set_bit(I915_RESET_ENGINE + engine->id,
1445                                              &gt->reset.flags))
1446                                 continue;
1447
1448                         if (__intel_engine_reset_bh(engine, msg) == 0)
1449                                 engine_mask &= ~engine->mask;
1450
1451                         clear_and_wake_up_bit(I915_RESET_ENGINE + engine->id,
1452                                               &gt->reset.flags);
1453                 }
1454                 local_bh_enable();
1455         }
1456
1457         if (!engine_mask)
1458                 goto out;
1459
1460         /* Full reset needs the mutex, stop any other user trying to do so. */
1461         if (test_and_set_bit(I915_RESET_BACKOFF, &gt->reset.flags)) {
1462                 wait_event(gt->reset.queue,
1463                            !test_bit(I915_RESET_BACKOFF, &gt->reset.flags));
1464                 goto out; /* piggy-back on the other reset */
1465         }
1466
1467         /* Make sure i915_reset_trylock() sees the I915_RESET_BACKOFF */
1468         synchronize_rcu_expedited();
1469
1470         /*
1471          * Prevent any other reset-engine attempt. We don't do this for GuC
1472          * submission the GuC owns the per-engine reset, not the i915.
1473          */
1474         if (!intel_uc_uses_guc_submission(&gt->uc)) {
1475                 for_each_engine(engine, gt, tmp) {
1476                         while (test_and_set_bit(I915_RESET_ENGINE + engine->id,
1477                                                 &gt->reset.flags))
1478                                 wait_on_bit(&gt->reset.flags,
1479                                             I915_RESET_ENGINE + engine->id,
1480                                             TASK_UNINTERRUPTIBLE);
1481                 }
1482         }
1483
1484         /* Flush everyone using a resource about to be clobbered */
1485         synchronize_srcu_expedited(&gt->reset.backoff_srcu);
1486
1487         intel_gt_reset_global(gt, engine_mask, msg);
1488
1489         if (!intel_uc_uses_guc_submission(&gt->uc)) {
1490                 for_each_engine(engine, gt, tmp)
1491                         clear_bit_unlock(I915_RESET_ENGINE + engine->id,
1492                                          &gt->reset.flags);
1493         }
1494         clear_bit_unlock(I915_RESET_BACKOFF, &gt->reset.flags);
1495         smp_mb__after_atomic();
1496         wake_up_all(&gt->reset.queue);
1497
1498 out:
1499         intel_runtime_pm_put(gt->uncore->rpm, wakeref);
1500 }
1501
1502 static int _intel_gt_reset_lock(struct intel_gt *gt, int *srcu, bool retry)
1503 {
1504         might_lock(&gt->reset.backoff_srcu);
1505         if (retry)
1506                 might_sleep();
1507
1508         rcu_read_lock();
1509         while (test_bit(I915_RESET_BACKOFF, &gt->reset.flags)) {
1510                 rcu_read_unlock();
1511
1512                 if (!retry)
1513                         return -EBUSY;
1514
1515                 if (wait_event_interruptible(gt->reset.queue,
1516                                              !test_bit(I915_RESET_BACKOFF,
1517                                                        &gt->reset.flags)))
1518                         return -EINTR;
1519
1520                 rcu_read_lock();
1521         }
1522         *srcu = srcu_read_lock(&gt->reset.backoff_srcu);
1523         rcu_read_unlock();
1524
1525         return 0;
1526 }
1527
1528 int intel_gt_reset_trylock(struct intel_gt *gt, int *srcu)
1529 {
1530         return _intel_gt_reset_lock(gt, srcu, false);
1531 }
1532
1533 int intel_gt_reset_lock_interruptible(struct intel_gt *gt, int *srcu)
1534 {
1535         return _intel_gt_reset_lock(gt, srcu, true);
1536 }
1537
1538 void intel_gt_reset_unlock(struct intel_gt *gt, int tag)
1539 __releases(&gt->reset.backoff_srcu)
1540 {
1541         srcu_read_unlock(&gt->reset.backoff_srcu, tag);
1542 }
1543
1544 int intel_gt_terminally_wedged(struct intel_gt *gt)
1545 {
1546         might_sleep();
1547
1548         if (!intel_gt_is_wedged(gt))
1549                 return 0;
1550
1551         if (intel_gt_has_unrecoverable_error(gt))
1552                 return -EIO;
1553
1554         /* Reset still in progress? Maybe we will recover? */
1555         if (wait_event_interruptible(gt->reset.queue,
1556                                      !test_bit(I915_RESET_BACKOFF,
1557                                                &gt->reset.flags)))
1558                 return -EINTR;
1559
1560         return intel_gt_is_wedged(gt) ? -EIO : 0;
1561 }
1562
1563 void intel_gt_set_wedged_on_init(struct intel_gt *gt)
1564 {
1565         BUILD_BUG_ON(I915_RESET_ENGINE + I915_NUM_ENGINES >
1566                      I915_WEDGED_ON_INIT);
1567         intel_gt_set_wedged(gt);
1568         i915_disable_error_state(gt->i915, -ENODEV);
1569         set_bit(I915_WEDGED_ON_INIT, &gt->reset.flags);
1570
1571         /* Wedged on init is non-recoverable */
1572         add_taint_for_CI(gt->i915, TAINT_WARN);
1573 }
1574
1575 void intel_gt_set_wedged_on_fini(struct intel_gt *gt)
1576 {
1577         intel_gt_set_wedged(gt);
1578         i915_disable_error_state(gt->i915, -ENODEV);
1579         set_bit(I915_WEDGED_ON_FINI, &gt->reset.flags);
1580         intel_gt_retire_requests(gt); /* cleanup any wedged requests */
1581 }
1582
1583 void intel_gt_init_reset(struct intel_gt *gt)
1584 {
1585         init_waitqueue_head(&gt->reset.queue);
1586         mutex_init(&gt->reset.mutex);
1587         init_srcu_struct(&gt->reset.backoff_srcu);
1588
1589         /*
1590          * While undesirable to wait inside the shrinker, complain anyway.
1591          *
1592          * If we have to wait during shrinking, we guarantee forward progress
1593          * by forcing the reset. Therefore during the reset we must not
1594          * re-enter the shrinker. By declaring that we take the reset mutex
1595          * within the shrinker, we forbid ourselves from performing any
1596          * fs-reclaim or taking related locks during reset.
1597          */
1598         i915_gem_shrinker_taints_mutex(gt->i915, &gt->reset.mutex);
1599
1600         /* no GPU until we are ready! */
1601         __set_bit(I915_WEDGED, &gt->reset.flags);
1602 }
1603
1604 void intel_gt_fini_reset(struct intel_gt *gt)
1605 {
1606         cleanup_srcu_struct(&gt->reset.backoff_srcu);
1607 }
1608
1609 static void intel_wedge_me(struct work_struct *work)
1610 {
1611         struct intel_wedge_me *w = container_of(work, typeof(*w), work.work);
1612
1613         drm_err(&w->gt->i915->drm,
1614                 "%s timed out, cancelling all in-flight rendering.\n",
1615                 w->name);
1616         intel_gt_set_wedged(w->gt);
1617 }
1618
1619 void __intel_init_wedge(struct intel_wedge_me *w,
1620                         struct intel_gt *gt,
1621                         long timeout,
1622                         const char *name)
1623 {
1624         w->gt = gt;
1625         w->name = name;
1626
1627         INIT_DELAYED_WORK_ONSTACK(&w->work, intel_wedge_me);
1628         schedule_delayed_work(&w->work, timeout);
1629 }
1630
1631 void __intel_fini_wedge(struct intel_wedge_me *w)
1632 {
1633         cancel_delayed_work_sync(&w->work);
1634         destroy_delayed_work_on_stack(&w->work);
1635         w->gt = NULL;
1636 }
1637
1638 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
1639 #include "selftest_reset.c"
1640 #include "selftest_hangcheck.c"
1641 #endif