drivers/gpu/drm/i915/gt/intel_rc6.c

   1 // SPDX-License-Identifier: MIT
   2 /*
   3  * Copyright © 2019 Intel Corporation
   4  */
   5
   6 #include <linux/pm_runtime.h>
   7 #include <linux/string_helpers.h>
   8
   9 #include "gem/i915_gem_region.h"
  10 #include "i915_drv.h"
  11 #include "i915_reg.h"
  12 #include "i915_vgpu.h"
  13 #include "intel_engine_regs.h"
  14 #include "intel_gt.h"
  15 #include "intel_gt_pm.h"
  16 #include "intel_gt_regs.h"
  17 #include "intel_pcode.h"
  18 #include "intel_rc6.h"
  19
  20 /**
  21  * DOC: RC6
  22  *
  23  * RC6 is a special power stage which allows the GPU to enter an very
  24  * low-voltage mode when idle, using down to 0V while at this stage.  This
  25  * stage is entered automatically when the GPU is idle when RC6 support is
  26  * enabled, and as soon as new workload arises GPU wakes up automatically as
  27  * well.
  28  *
  29  * There are different RC6 modes available in Intel GPU, which differentiate
  30  * among each other with the latency required to enter and leave RC6 and
  31  * voltage consumed by the GPU in different states.
  32  *
  33  * The combination of the following flags define which states GPU is allowed
  34  * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
  35  * RC6pp is deepest RC6. Their support by hardware varies according to the
  36  * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
  37  * which brings the most power savings; deeper states save more power, but
  38  * require higher latency to switch to and wake up.
  39  */
  40
  41 static struct intel_gt *rc6_to_gt(struct intel_rc6 *rc6)
  42 {
  43         return container_of(rc6, struct intel_gt, rc6);
  44 }
  45
  46 static struct intel_uncore *rc6_to_uncore(struct intel_rc6 *rc)
  47 {
  48         return rc6_to_gt(rc)->uncore;
  49 }
  50
  51 static struct drm_i915_private *rc6_to_i915(struct intel_rc6 *rc)
  52 {
  53         return rc6_to_gt(rc)->i915;
  54 }
  55
  56 static void gen11_rc6_enable(struct intel_rc6 *rc6)
  57 {
  58         struct intel_gt *gt = rc6_to_gt(rc6);
  59         struct intel_uncore *uncore = gt->uncore;
  60         struct intel_engine_cs *engine;
  61         enum intel_engine_id id;
  62         u32 pg_enable;
  63         int i;
  64
  65         /*
  66          * With GuCRC, these parameters are set by GuC
  67          */
  68         if (!intel_uc_uses_guc_rc(&gt->uc)) {
  69                 /* 2b: Program RC6 thresholds.*/
  70                 intel_uncore_write_fw(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16 | 85);
  71                 intel_uncore_write_fw(uncore, GEN10_MEDIA_WAKE_RATE_LIMIT, 150);
  72
  73                 intel_uncore_write_fw(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
  74                 intel_uncore_write_fw(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
  75                 for_each_engine(engine, rc6_to_gt(rc6), id)
  76                         intel_uncore_write_fw(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
  77
  78                 intel_uncore_write_fw(uncore, GUC_MAX_IDLE_COUNT, 0xA);
  79
  80                 intel_uncore_write_fw(uncore, GEN6_RC_SLEEP, 0);
  81
  82                 intel_uncore_write_fw(uncore, GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
  83         }
  84
  85         /*
  86          * 2c: Program Coarse Power Gating Policies.
  87          *
  88          * Bspec's guidance is to use 25us (really 25 * 1280ns) here. What we
  89          * use instead is a more conservative estimate for the maximum time
  90          * it takes us to service a CS interrupt and submit a new ELSP - that
  91          * is the time which the GPU is idle waiting for the CPU to select the
  92          * next request to execute. If the idle hysteresis is less than that
  93          * interrupt service latency, the hardware will automatically gate
  94          * the power well and we will then incur the wake up cost on top of
  95          * the service latency. A similar guide from plane_state is that we
  96          * do not want the enable hysteresis to less than the wakeup latency.
  97          *
  98          * igt/gem_exec_nop/sequential provides a rough estimate for the
  99          * service latency, and puts it under 10us for Icelake, similar to
 100          * Broadwell+, To be conservative, we want to factor in a context
 101          * switch on top (due to ksoftirqd).
 102          */
 103         intel_uncore_write_fw(uncore, GEN9_MEDIA_PG_IDLE_HYSTERESIS, 60);
 104         intel_uncore_write_fw(uncore, GEN9_RENDER_PG_IDLE_HYSTERESIS, 60);
 105
 106         /* 3a: Enable RC6
 107          *
 108          * With GuCRC, we do not enable bit 31 of RC_CTL,
 109          * thus allowing GuC to control RC6 entry/exit fully instead.
 110          * We will not set the HW ENABLE and EI bits
 111          */
 112         if (!intel_guc_rc_enable(&gt->uc.guc))
 113                 rc6->ctl_enable = GEN6_RC_CTL_RC6_ENABLE;
 114         else
 115                 rc6->ctl_enable =
 116                         GEN6_RC_CTL_HW_ENABLE |
 117                         GEN6_RC_CTL_RC6_ENABLE |
 118                         GEN6_RC_CTL_EI_MODE(1);
 119
 120         /*
 121          * Wa_16011777198 and BSpec 52698 - Render powergating must be off.
 122          * FIXME BSpec is outdated, disabling powergating for MTL is just
 123          * temporary wa and should be removed after fixing real cause
 124          * of forcewake timeouts.
 125          */
 126         if (IS_METEORLAKE(gt->i915) ||
 127             IS_DG2_GRAPHICS_STEP(gt->i915, G10, STEP_A0, STEP_C0) ||
 128             IS_DG2_GRAPHICS_STEP(gt->i915, G11, STEP_A0, STEP_B0))
 129                 pg_enable =
 130                         GEN9_MEDIA_PG_ENABLE |
 131                         GEN11_MEDIA_SAMPLER_PG_ENABLE;
 132         else
 133                 pg_enable =
 134                         GEN9_RENDER_PG_ENABLE |
 135                         GEN9_MEDIA_PG_ENABLE |
 136                         GEN11_MEDIA_SAMPLER_PG_ENABLE;
 137
 138         if (GRAPHICS_VER(gt->i915) >= 12) {
 139                 for (i = 0; i < I915_MAX_VCS; i++)
 140                         if (HAS_ENGINE(gt, _VCS(i)))
 141                                 pg_enable |= (VDN_HCP_POWERGATE_ENABLE(i) |
 142                                               VDN_MFX_POWERGATE_ENABLE(i));
 143         }
 144
 145         intel_uncore_write_fw(uncore, GEN9_PG_ENABLE, pg_enable);
 146 }
 147
 148 static void gen9_rc6_enable(struct intel_rc6 *rc6)
 149 {
 150         struct intel_uncore *uncore = rc6_to_uncore(rc6);
 151         struct intel_engine_cs *engine;
 152         enum intel_engine_id id;
 153
 154         /* 2b: Program RC6 thresholds.*/
 155         if (GRAPHICS_VER(rc6_to_i915(rc6)) >= 11) {
 156                 intel_uncore_write_fw(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16 | 85);
 157                 intel_uncore_write_fw(uncore, GEN10_MEDIA_WAKE_RATE_LIMIT, 150);
 158         } else if (IS_SKYLAKE(rc6_to_i915(rc6))) {
 159                 /*
 160                  * WaRsDoubleRc6WrlWithCoarsePowerGating:skl Doubling WRL only
 161                  * when CPG is enabled
 162                  */
 163                 intel_uncore_write_fw(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16);
 164         } else {
 165                 intel_uncore_write_fw(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
 166         }
 167
 168         intel_uncore_write_fw(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
 169         intel_uncore_write_fw(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
 170         for_each_engine(engine, rc6_to_gt(rc6), id)
 171                 intel_uncore_write_fw(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
 172
 173         intel_uncore_write_fw(uncore, GUC_MAX_IDLE_COUNT, 0xA);
 174
 175         intel_uncore_write_fw(uncore, GEN6_RC_SLEEP, 0);
 176
 177         /*
 178          * 2c: Program Coarse Power Gating Policies.
 179          *
 180          * Bspec's guidance is to use 25us (really 25 * 1280ns) here. What we
 181          * use instead is a more conservative estimate for the maximum time
 182          * it takes us to service a CS interrupt and submit a new ELSP - that
 183          * is the time which the GPU is idle waiting for the CPU to select the
 184          * next request to execute. If the idle hysteresis is less than that
 185          * interrupt service latency, the hardware will automatically gate
 186          * the power well and we will then incur the wake up cost on top of
 187          * the service latency. A similar guide from plane_state is that we
 188          * do not want the enable hysteresis to less than the wakeup latency.
 189          *
 190          * igt/gem_exec_nop/sequential provides a rough estimate for the
 191          * service latency, and puts it around 10us for Broadwell (and other
 192          * big core) and around 40us for Broxton (and other low power cores).
 193          * [Note that for legacy ringbuffer submission, this is less than 1us!]
 194          * However, the wakeup latency on Broxton is closer to 100us. To be
 195          * conservative, we have to factor in a context switch on top (due
 196          * to ksoftirqd).
 197          */
 198         intel_uncore_write_fw(uncore, GEN9_MEDIA_PG_IDLE_HYSTERESIS, 250);
 199         intel_uncore_write_fw(uncore, GEN9_RENDER_PG_IDLE_HYSTERESIS, 250);
 200
 201         /* 3a: Enable RC6 */
 202         intel_uncore_write_fw(uncore, GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
 203
 204         rc6->ctl_enable =
 205                 GEN6_RC_CTL_HW_ENABLE |
 206                 GEN6_RC_CTL_RC6_ENABLE |
 207                 GEN6_RC_CTL_EI_MODE(1);
 208
 209         /*
 210          * WaRsDisableCoarsePowerGating:skl,cnl
 211          *   - Render/Media PG need to be disabled with RC6.
 212          */
 213         if (!NEEDS_WaRsDisableCoarsePowerGating(rc6_to_i915(rc6)))
 214                 intel_uncore_write_fw(uncore, GEN9_PG_ENABLE,
 215                                       GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE);
 216 }
 217
 218 static void gen8_rc6_enable(struct intel_rc6 *rc6)
 219 {
 220         struct intel_uncore *uncore = rc6_to_uncore(rc6);
 221         struct intel_engine_cs *engine;
 222         enum intel_engine_id id;
 223
 224         /* 2b: Program RC6 thresholds.*/
 225         intel_uncore_write_fw(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
 226         intel_uncore_write_fw(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
 227         intel_uncore_write_fw(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
 228         for_each_engine(engine, rc6_to_gt(rc6), id)
 229                 intel_uncore_write_fw(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
 230         intel_uncore_write_fw(uncore, GEN6_RC_SLEEP, 0);
 231         intel_uncore_write_fw(uncore, GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
 232
 233         /* 3: Enable RC6 */
 234         rc6->ctl_enable =
 235             GEN6_RC_CTL_HW_ENABLE |
 236             GEN7_RC_CTL_TO_MODE |
 237             GEN6_RC_CTL_RC6_ENABLE;
 238 }
 239
 240 static void gen6_rc6_enable(struct intel_rc6 *rc6)
 241 {
 242         struct intel_uncore *uncore = rc6_to_uncore(rc6);
 243         struct drm_i915_private *i915 = rc6_to_i915(rc6);
 244         struct intel_engine_cs *engine;
 245         enum intel_engine_id id;
 246         u32 rc6vids, rc6_mask;
 247         int ret;
 248
 249         intel_uncore_write_fw(uncore, GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
 250         intel_uncore_write_fw(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
 251         intel_uncore_write_fw(uncore, GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
 252         intel_uncore_write_fw(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000);
 253         intel_uncore_write_fw(uncore, GEN6_RC_IDLE_HYSTERSIS, 25);
 254
 255         for_each_engine(engine, rc6_to_gt(rc6), id)
 256                 intel_uncore_write_fw(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
 257
 258         intel_uncore_write_fw(uncore, GEN6_RC_SLEEP, 0);
 259         intel_uncore_write_fw(uncore, GEN6_RC1e_THRESHOLD, 1000);
 260         intel_uncore_write_fw(uncore, GEN6_RC6_THRESHOLD, 50000);
 261         intel_uncore_write_fw(uncore, GEN6_RC6p_THRESHOLD, 150000);
 262         intel_uncore_write_fw(uncore, GEN6_RC6pp_THRESHOLD, 64000); /* unused */
 263
 264         /* We don't use those on Haswell */
 265         rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
 266         if (HAS_RC6p(i915))
 267                 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
 268         if (HAS_RC6pp(i915))
 269                 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
 270         rc6->ctl_enable =
 271             rc6_mask |
 272             GEN6_RC_CTL_EI_MODE(1) |
 273             GEN6_RC_CTL_HW_ENABLE;
 274
 275         rc6vids = 0;
 276         ret = snb_pcode_read(rc6_to_gt(rc6)->uncore, GEN6_PCODE_READ_RC6VIDS, &rc6vids, NULL);
 277         if (GRAPHICS_VER(i915) == 6 && ret) {
 278                 drm_dbg(&i915->drm, "Couldn't check for BIOS workaround\n");
 279         } else if (GRAPHICS_VER(i915) == 6 &&
 280                    (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
 281                 drm_dbg(&i915->drm,
 282                         "You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
 283                         GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
 284                 rc6vids &= 0xffff00;
 285                 rc6vids |= GEN6_ENCODE_RC6_VID(450);
 286                 ret = snb_pcode_write(rc6_to_gt(rc6)->uncore, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
 287                 if (ret)
 288                         drm_err(&i915->drm,
 289                                 "Couldn't fix incorrect rc6 voltage\n");
 290         }
 291 }
 292
 293 /* Check that the pcbr address is not empty. */
 294 static int chv_rc6_init(struct intel_rc6 *rc6)
 295 {
 296         struct intel_uncore *uncore = rc6_to_uncore(rc6);
 297         struct drm_i915_private *i915 = rc6_to_i915(rc6);
 298         resource_size_t pctx_paddr, paddr;
 299         resource_size_t pctx_size = 32 * SZ_1K;
 300         u32 pcbr;
 301
 302         pcbr = intel_uncore_read(uncore, VLV_PCBR);
 303         if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
 304                 drm_dbg(&i915->drm, "BIOS didn't set up PCBR, fixing up\n");
 305                 paddr = i915->dsm.stolen.end + 1 - pctx_size;
 306                 GEM_BUG_ON(paddr > U32_MAX);
 307
 308                 pctx_paddr = (paddr & ~4095);
 309                 intel_uncore_write(uncore, VLV_PCBR, pctx_paddr);
 310         }
 311
 312         return 0;
 313 }
 314
 315 static int vlv_rc6_init(struct intel_rc6 *rc6)
 316 {
 317         struct drm_i915_private *i915 = rc6_to_i915(rc6);
 318         struct intel_uncore *uncore = rc6_to_uncore(rc6);
 319         struct drm_i915_gem_object *pctx;
 320         resource_size_t pctx_paddr;
 321         resource_size_t pctx_size = 24 * SZ_1K;
 322         u32 pcbr;
 323
 324         pcbr = intel_uncore_read(uncore, VLV_PCBR);
 325         if (pcbr) {
 326                 /* BIOS set it up already, grab the pre-alloc'd space */
 327                 resource_size_t pcbr_offset;
 328
 329                 pcbr_offset = (pcbr & ~4095) - i915->dsm.stolen.start;
 330                 pctx = i915_gem_object_create_region_at(i915->mm.stolen_region,
 331                                                         pcbr_offset,
 332                                                         pctx_size,
 333                                                         0);
 334                 if (IS_ERR(pctx))
 335                         return PTR_ERR(pctx);
 336
 337                 goto out;
 338         }
 339
 340         drm_dbg(&i915->drm, "BIOS didn't set up PCBR, fixing up\n");
 341
 342         /*
 343          * From the Gunit register HAS:
 344          * The Gfx driver is expected to program this register and ensure
 345          * proper allocation within Gfx stolen memory.  For example, this
 346          * register should be programmed such than the PCBR range does not
 347          * overlap with other ranges, such as the frame buffer, protected
 348          * memory, or any other relevant ranges.
 349          */
 350         pctx = i915_gem_object_create_stolen(i915, pctx_size);
 351         if (IS_ERR(pctx)) {
 352                 drm_dbg(&i915->drm,
 353                         "not enough stolen space for PCTX, disabling\n");
 354                 return PTR_ERR(pctx);
 355         }
 356
 357         GEM_BUG_ON(range_overflows_end_t(u64,
 358                                          i915->dsm.stolen.start,
 359                                          pctx->stolen->start,
 360                                          U32_MAX));
 361         pctx_paddr = i915->dsm.stolen.start + pctx->stolen->start;
 362         intel_uncore_write(uncore, VLV_PCBR, pctx_paddr);
 363
 364 out:
 365         rc6->pctx = pctx;
 366         return 0;
 367 }
 368
 369 static void chv_rc6_enable(struct intel_rc6 *rc6)
 370 {
 371         struct intel_uncore *uncore = rc6_to_uncore(rc6);
 372         struct intel_engine_cs *engine;
 373         enum intel_engine_id id;
 374
 375         /* 2a: Program RC6 thresholds.*/
 376         intel_uncore_write_fw(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
 377         intel_uncore_write_fw(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
 378         intel_uncore_write_fw(uncore, GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
 379
 380         for_each_engine(engine, rc6_to_gt(rc6), id)
 381                 intel_uncore_write_fw(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
 382         intel_uncore_write_fw(uncore, GEN6_RC_SLEEP, 0);
 383
 384         /* TO threshold set to 500 us (0x186 * 1.28 us) */
 385         intel_uncore_write_fw(uncore, GEN6_RC6_THRESHOLD, 0x186);
 386
 387         /* Allows RC6 residency counter to work */
 388         intel_uncore_write_fw(uncore, VLV_COUNTER_CONTROL,
 389                               _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
 390                                                  VLV_MEDIA_RC6_COUNT_EN |
 391                                                  VLV_RENDER_RC6_COUNT_EN));
 392
 393         /* 3: Enable RC6 */
 394         rc6->ctl_enable = GEN7_RC_CTL_TO_MODE;
 395 }
 396
 397 static void vlv_rc6_enable(struct intel_rc6 *rc6)
 398 {
 399         struct intel_uncore *uncore = rc6_to_uncore(rc6);
 400         struct intel_engine_cs *engine;
 401         enum intel_engine_id id;
 402
 403         intel_uncore_write_fw(uncore, GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
 404         intel_uncore_write_fw(uncore, GEN6_RC_EVALUATION_INTERVAL, 125000);
 405         intel_uncore_write_fw(uncore, GEN6_RC_IDLE_HYSTERSIS, 25);
 406
 407         for_each_engine(engine, rc6_to_gt(rc6), id)
 408                 intel_uncore_write_fw(uncore, RING_MAX_IDLE(engine->mmio_base), 10);
 409
 410         intel_uncore_write_fw(uncore, GEN6_RC6_THRESHOLD, 0x557);
 411
 412         /* Allows RC6 residency counter to work */
 413         intel_uncore_write_fw(uncore, VLV_COUNTER_CONTROL,
 414                               _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
 415                                                  VLV_MEDIA_RC0_COUNT_EN |
 416                                                  VLV_RENDER_RC0_COUNT_EN |
 417                                                  VLV_MEDIA_RC6_COUNT_EN |
 418                                                  VLV_RENDER_RC6_COUNT_EN));
 419
 420         rc6->ctl_enable =
 421             GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
 422 }
 423
 424 bool intel_check_bios_c6_setup(struct intel_rc6 *rc6)
 425 {
 426         if (!rc6->bios_state_captured) {
 427                 struct intel_uncore *uncore = rc6_to_uncore(rc6);
 428                 intel_wakeref_t wakeref;
 429
 430                 with_intel_runtime_pm(uncore->rpm, wakeref)
 431                         rc6->bios_rc_state = intel_uncore_read(uncore, GEN6_RC_STATE);
 432
 433                 rc6->bios_state_captured = true;
 434         }
 435
 436         return rc6->bios_rc_state & RC_SW_TARGET_STATE_MASK;
 437 }
 438
 439 static bool bxt_check_bios_rc6_setup(struct intel_rc6 *rc6)
 440 {
 441         struct intel_uncore *uncore = rc6_to_uncore(rc6);
 442         struct drm_i915_private *i915 = rc6_to_i915(rc6);
 443         u32 rc6_ctx_base, rc_ctl, rc_sw_target;
 444         bool enable_rc6 = true;
 445
 446         rc_ctl = intel_uncore_read(uncore, GEN6_RC_CONTROL);
 447         rc_sw_target = intel_uncore_read(uncore, GEN6_RC_STATE);
 448         rc_sw_target &= RC_SW_TARGET_STATE_MASK;
 449         rc_sw_target >>= RC_SW_TARGET_STATE_SHIFT;
 450         drm_dbg(&i915->drm, "BIOS enabled RC states: "
 451                          "HW_CTRL %s HW_RC6 %s SW_TARGET_STATE %x\n",
 452                          str_on_off(rc_ctl & GEN6_RC_CTL_HW_ENABLE),
 453                          str_on_off(rc_ctl & GEN6_RC_CTL_RC6_ENABLE),
 454                          rc_sw_target);
 455
 456         if (!(intel_uncore_read(uncore, RC6_LOCATION) & RC6_CTX_IN_DRAM)) {
 457                 drm_dbg(&i915->drm, "RC6 Base location not set properly.\n");
 458                 enable_rc6 = false;
 459         }
 460
 461         /*
 462          * The exact context size is not known for BXT, so assume a page size
 463          * for this check.
 464          */
 465         rc6_ctx_base =
 466                 intel_uncore_read(uncore, RC6_CTX_BASE) & RC6_CTX_BASE_MASK;
 467         if (!(rc6_ctx_base >= i915->dsm.reserved.start &&
 468               rc6_ctx_base + PAGE_SIZE < i915->dsm.reserved.end)) {
 469                 drm_dbg(&i915->drm, "RC6 Base address not as expected.\n");
 470                 enable_rc6 = false;
 471         }
 472
 473         if (!((intel_uncore_read(uncore, PWRCTX_MAXCNT(RENDER_RING_BASE)) & IDLE_TIME_MASK) > 1 &&
 474               (intel_uncore_read(uncore, PWRCTX_MAXCNT(GEN6_BSD_RING_BASE)) & IDLE_TIME_MASK) > 1 &&
 475               (intel_uncore_read(uncore, PWRCTX_MAXCNT(BLT_RING_BASE)) & IDLE_TIME_MASK) > 1 &&
 476               (intel_uncore_read(uncore, PWRCTX_MAXCNT(VEBOX_RING_BASE)) & IDLE_TIME_MASK) > 1)) {
 477                 drm_dbg(&i915->drm,
 478                         "Engine Idle wait time not set properly.\n");
 479                 enable_rc6 = false;
 480         }
 481
 482         if (!intel_uncore_read(uncore, GEN8_PUSHBUS_CONTROL) ||
 483             !intel_uncore_read(uncore, GEN8_PUSHBUS_ENABLE) ||
 484             !intel_uncore_read(uncore, GEN8_PUSHBUS_SHIFT)) {
 485                 drm_dbg(&i915->drm, "Pushbus not setup properly.\n");
 486                 enable_rc6 = false;
 487         }
 488
 489         if (!intel_uncore_read(uncore, GEN6_GFXPAUSE)) {
 490                 drm_dbg(&i915->drm, "GFX pause not setup properly.\n");
 491                 enable_rc6 = false;
 492         }
 493
 494         if (!intel_uncore_read(uncore, GEN8_MISC_CTRL0)) {
 495                 drm_dbg(&i915->drm, "GPM control not setup properly.\n");
 496                 enable_rc6 = false;
 497         }
 498
 499         return enable_rc6;
 500 }
 501
 502 static bool rc6_supported(struct intel_rc6 *rc6)
 503 {
 504         struct drm_i915_private *i915 = rc6_to_i915(rc6);
 505         struct intel_gt *gt = rc6_to_gt(rc6);
 506
 507         if (!HAS_RC6(i915))
 508                 return false;
 509
 510         if (intel_vgpu_active(i915))
 511                 return false;
 512
 513         if (is_mock_gt(rc6_to_gt(rc6)))
 514                 return false;
 515
 516         if (IS_GEN9_LP(i915) && !bxt_check_bios_rc6_setup(rc6)) {
 517                 drm_notice(&i915->drm,
 518                            "RC6 and powersaving disabled by BIOS\n");
 519                 return false;
 520         }
 521
 522         if (IS_METEORLAKE(gt->i915) &&
 523             !intel_check_bios_c6_setup(rc6)) {
 524                 drm_notice(&i915->drm,
 525                            "C6 disabled by BIOS\n");
 526                 return false;
 527         }
 528
 529         if (IS_MTL_MEDIA_STEP(gt->i915, STEP_A0, STEP_B0) &&
 530             gt->type == GT_MEDIA) {
 531                 drm_notice(&i915->drm,
 532                            "Media RC6 disabled on A step\n");
 533                 return false;
 534         }
 535
 536         return true;
 537 }
 538
 539 static void rpm_get(struct intel_rc6 *rc6)
 540 {
 541         GEM_BUG_ON(rc6->wakeref);
 542         pm_runtime_get_sync(rc6_to_i915(rc6)->drm.dev);
 543         rc6->wakeref = true;
 544 }
 545
 546 static void rpm_put(struct intel_rc6 *rc6)
 547 {
 548         GEM_BUG_ON(!rc6->wakeref);
 549         pm_runtime_put(rc6_to_i915(rc6)->drm.dev);
 550         rc6->wakeref = false;
 551 }
 552
 553 static bool pctx_corrupted(struct intel_rc6 *rc6)
 554 {
 555         struct drm_i915_private *i915 = rc6_to_i915(rc6);
 556
 557         if (!NEEDS_RC6_CTX_CORRUPTION_WA(i915))
 558                 return false;
 559
 560         if (intel_uncore_read(rc6_to_uncore(rc6), GEN8_RC6_CTX_INFO))
 561                 return false;
 562
 563         drm_notice(&i915->drm,
 564                    "RC6 context corruption, disabling runtime power management\n");
 565         return true;
 566 }
 567
 568 static void __intel_rc6_disable(struct intel_rc6 *rc6)
 569 {
 570         struct drm_i915_private *i915 = rc6_to_i915(rc6);
 571         struct intel_uncore *uncore = rc6_to_uncore(rc6);
 572         struct intel_gt *gt = rc6_to_gt(rc6);
 573
 574         /* Take control of RC6 back from GuC */
 575         intel_guc_rc_disable(&gt->uc.guc);
 576
 577         intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
 578         if (GRAPHICS_VER(i915) >= 9)
 579                 intel_uncore_write_fw(uncore, GEN9_PG_ENABLE, 0);
 580         intel_uncore_write_fw(uncore, GEN6_RC_CONTROL, 0);
 581         intel_uncore_write_fw(uncore, GEN6_RC_STATE, 0);
 582         intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
 583 }
 584
 585 static void rc6_res_reg_init(struct intel_rc6 *rc6)
 586 {
 587         memset(rc6->res_reg, INVALID_MMIO_REG.reg, sizeof(rc6->res_reg));
 588
 589         switch (rc6_to_gt(rc6)->type) {
 590         case GT_MEDIA:
 591                 rc6->res_reg[INTEL_RC6_RES_RC6] = MTL_MEDIA_MC6;
 592                 break;
 593         default:
 594                 rc6->res_reg[INTEL_RC6_RES_RC6_LOCKED] = GEN6_GT_GFX_RC6_LOCKED;
 595                 rc6->res_reg[INTEL_RC6_RES_RC6] = GEN6_GT_GFX_RC6;
 596                 rc6->res_reg[INTEL_RC6_RES_RC6p] = GEN6_GT_GFX_RC6p;
 597                 rc6->res_reg[INTEL_RC6_RES_RC6pp] = GEN6_GT_GFX_RC6pp;
 598                 break;
 599         }
 600 }
 601
 602 void intel_rc6_init(struct intel_rc6 *rc6)
 603 {
 604         struct drm_i915_private *i915 = rc6_to_i915(rc6);
 605         int err;
 606
 607         /* Disable runtime-pm until we can save the GPU state with rc6 pctx */
 608         rpm_get(rc6);
 609
 610         if (!rc6_supported(rc6))
 611                 return;
 612
 613         rc6_res_reg_init(rc6);
 614
 615         if (IS_CHERRYVIEW(i915))
 616                 err = chv_rc6_init(rc6);
 617         else if (IS_VALLEYVIEW(i915))
 618                 err = vlv_rc6_init(rc6);
 619         else
 620                 err = 0;
 621
 622         /* Sanitize rc6, ensure it is disabled before we are ready. */
 623         __intel_rc6_disable(rc6);
 624
 625         rc6->supported = err == 0;
 626 }
 627
 628 void intel_rc6_sanitize(struct intel_rc6 *rc6)
 629 {
 630         memset(rc6->prev_hw_residency, 0, sizeof(rc6->prev_hw_residency));
 631
 632         if (rc6->enabled) { /* unbalanced suspend/resume */
 633                 rpm_get(rc6);
 634                 rc6->enabled = false;
 635         }
 636
 637         if (rc6->supported)
 638                 __intel_rc6_disable(rc6);
 639 }
 640
 641 void intel_rc6_enable(struct intel_rc6 *rc6)
 642 {
 643         struct drm_i915_private *i915 = rc6_to_i915(rc6);
 644         struct intel_uncore *uncore = rc6_to_uncore(rc6);
 645
 646         if (!rc6->supported)
 647                 return;
 648
 649         GEM_BUG_ON(rc6->enabled);
 650
 651         intel_uncore_forcewake_get(uncore, FORCEWAKE_ALL);
 652
 653         if (IS_CHERRYVIEW(i915))
 654                 chv_rc6_enable(rc6);
 655         else if (IS_VALLEYVIEW(i915))
 656                 vlv_rc6_enable(rc6);
 657         else if (GRAPHICS_VER(i915) >= 11)
 658                 gen11_rc6_enable(rc6);
 659         else if (GRAPHICS_VER(i915) >= 9)
 660                 gen9_rc6_enable(rc6);
 661         else if (IS_BROADWELL(i915))
 662                 gen8_rc6_enable(rc6);
 663         else if (GRAPHICS_VER(i915) >= 6)
 664                 gen6_rc6_enable(rc6);
 665
 666         rc6->manual = rc6->ctl_enable & GEN6_RC_CTL_RC6_ENABLE;
 667         if (NEEDS_RC6_CTX_CORRUPTION_WA(i915))
 668                 rc6->ctl_enable = 0;
 669
 670         intel_uncore_forcewake_put(uncore, FORCEWAKE_ALL);
 671
 672         if (unlikely(pctx_corrupted(rc6)))
 673                 return;
 674
 675         /* rc6 is ready, runtime-pm is go! */
 676         rpm_put(rc6);
 677         rc6->enabled = true;
 678 }
 679
 680 void intel_rc6_unpark(struct intel_rc6 *rc6)
 681 {
 682         struct intel_uncore *uncore = rc6_to_uncore(rc6);
 683
 684         if (!rc6->enabled)
 685                 return;
 686
 687         /* Restore HW timers for automatic RC6 entry while busy */
 688         intel_uncore_write_fw(uncore, GEN6_RC_CONTROL, rc6->ctl_enable);
 689 }
 690
 691 void intel_rc6_park(struct intel_rc6 *rc6)
 692 {
 693         struct intel_uncore *uncore = rc6_to_uncore(rc6);
 694         unsigned int target;
 695
 696         if (!rc6->enabled)
 697                 return;
 698
 699         if (unlikely(pctx_corrupted(rc6))) {
 700                 intel_rc6_disable(rc6);
 701                 return;
 702         }
 703
 704         if (!rc6->manual)
 705                 return;
 706
 707         /* Turn off the HW timers and go directly to rc6 */
 708         intel_uncore_write_fw(uncore, GEN6_RC_CONTROL, GEN6_RC_CTL_RC6_ENABLE);
 709
 710         if (HAS_RC6pp(rc6_to_i915(rc6)))
 711                 target = 0x6; /* deepest rc6 */
 712         else if (HAS_RC6p(rc6_to_i915(rc6)))
 713                 target = 0x5; /* deep rc6 */
 714         else
 715                 target = 0x4; /* normal rc6 */
 716         intel_uncore_write_fw(uncore, GEN6_RC_STATE, target << RC_SW_TARGET_STATE_SHIFT);
 717 }
 718
 719 void intel_rc6_disable(struct intel_rc6 *rc6)
 720 {
 721         if (!rc6->enabled)
 722                 return;
 723
 724         rpm_get(rc6);
 725         rc6->enabled = false;
 726
 727         __intel_rc6_disable(rc6);
 728 }
 729
 730 void intel_rc6_fini(struct intel_rc6 *rc6)
 731 {
 732         struct drm_i915_gem_object *pctx;
 733         struct intel_uncore *uncore = rc6_to_uncore(rc6);
 734
 735         intel_rc6_disable(rc6);
 736
 737         /* We want the BIOS C6 state preserved across loads for MTL */
 738         if (IS_METEORLAKE(rc6_to_i915(rc6)) && rc6->bios_state_captured)
 739                 intel_uncore_write_fw(uncore, GEN6_RC_STATE, rc6->bios_rc_state);
 740
 741         pctx = fetch_and_zero(&rc6->pctx);
 742         if (pctx)
 743                 i915_gem_object_put(pctx);
 744
 745         if (rc6->wakeref)
 746                 rpm_put(rc6);
 747 }
 748
 749 static u64 vlv_residency_raw(struct intel_uncore *uncore, const i915_reg_t reg)
 750 {
 751         u32 lower, upper, tmp;
 752         int loop = 2;
 753
 754         /*
 755          * The register accessed do not need forcewake. We borrow
 756          * uncore lock to prevent concurrent access to range reg.
 757          */
 758         lockdep_assert_held(&uncore->lock);
 759
 760         /*
 761          * vlv and chv residency counters are 40 bits in width.
 762          * With a control bit, we can choose between upper or lower
 763          * 32bit window into this counter.
 764          *
 765          * Although we always use the counter in high-range mode elsewhere,
 766          * userspace may attempt to read the value before rc6 is initialised,
 767          * before we have set the default VLV_COUNTER_CONTROL value. So always
 768          * set the high bit to be safe.
 769          */
 770         intel_uncore_write_fw(uncore, VLV_COUNTER_CONTROL,
 771                               _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH));
 772         upper = intel_uncore_read_fw(uncore, reg);
 773         do {
 774                 tmp = upper;
 775
 776                 intel_uncore_write_fw(uncore, VLV_COUNTER_CONTROL,
 777                                       _MASKED_BIT_DISABLE(VLV_COUNT_RANGE_HIGH));
 778                 lower = intel_uncore_read_fw(uncore, reg);
 779
 780                 intel_uncore_write_fw(uncore, VLV_COUNTER_CONTROL,
 781                                       _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH));
 782                 upper = intel_uncore_read_fw(uncore, reg);
 783         } while (upper != tmp && --loop);
 784
 785         /*
 786          * Everywhere else we always use VLV_COUNTER_CONTROL with the
 787          * VLV_COUNT_RANGE_HIGH bit set - so it is safe to leave it set
 788          * now.
 789          */
 790
 791         return lower | (u64)upper << 8;
 792 }
 793
 794 u64 intel_rc6_residency_ns(struct intel_rc6 *rc6, enum intel_rc6_res_type id)
 795 {
 796         struct drm_i915_private *i915 = rc6_to_i915(rc6);
 797         struct intel_uncore *uncore = rc6_to_uncore(rc6);
 798         u64 time_hw, prev_hw, overflow_hw;
 799         i915_reg_t reg = rc6->res_reg[id];
 800         unsigned int fw_domains;
 801         unsigned long flags;
 802         u32 mul, div;
 803
 804         if (!rc6->supported)
 805                 return 0;
 806
 807         fw_domains = intel_uncore_forcewake_for_reg(uncore, reg, FW_REG_READ);
 808
 809         spin_lock_irqsave(&uncore->lock, flags);
 810         intel_uncore_forcewake_get__locked(uncore, fw_domains);
 811
 812         /* On VLV and CHV, residency time is in CZ units rather than 1.28us */
 813         if (IS_VALLEYVIEW(i915) || IS_CHERRYVIEW(i915)) {
 814                 mul = 1000000;
 815                 div = i915->czclk_freq;
 816                 overflow_hw = BIT_ULL(40);
 817                 time_hw = vlv_residency_raw(uncore, reg);
 818         } else {
 819                 /* 833.33ns units on Gen9LP, 1.28us elsewhere. */
 820                 if (IS_GEN9_LP(i915)) {
 821                         mul = 10000;
 822                         div = 12;
 823                 } else {
 824                         mul = 1280;
 825                         div = 1;
 826                 }
 827
 828                 overflow_hw = BIT_ULL(32);
 829                 time_hw = intel_uncore_read_fw(uncore, reg);
 830         }
 831
 832         /*
 833          * Counter wrap handling.
 834          *
 835          * Store previous hw counter values for counter wrap-around handling. But
 836          * relying on a sufficient frequency of queries otherwise counters can still wrap.
 837          */
 838         prev_hw = rc6->prev_hw_residency[id];
 839         rc6->prev_hw_residency[id] = time_hw;
 840
 841         /* RC6 delta from last sample. */
 842         if (time_hw >= prev_hw)
 843                 time_hw -= prev_hw;
 844         else
 845                 time_hw += overflow_hw - prev_hw;
 846
 847         /* Add delta to RC6 extended raw driver copy. */
 848         time_hw += rc6->cur_residency[id];
 849         rc6->cur_residency[id] = time_hw;
 850
 851         intel_uncore_forcewake_put__locked(uncore, fw_domains);
 852         spin_unlock_irqrestore(&uncore->lock, flags);
 853
 854         return mul_u64_u32_div(time_hw, mul, div);
 855 }
 856
 857 u64 intel_rc6_residency_us(struct intel_rc6 *rc6, enum intel_rc6_res_type id)
 858 {
 859         return DIV_ROUND_UP_ULL(intel_rc6_residency_ns(rc6, id), 1000);
 860 }
 861
 862 void intel_rc6_print_residency(struct seq_file *m, const char *title,
 863                                enum intel_rc6_res_type id)
 864 {
 865         struct intel_gt *gt = m->private;
 866         i915_reg_t reg = gt->rc6.res_reg[id];
 867         intel_wakeref_t wakeref;
 868
 869         with_intel_runtime_pm(gt->uncore->rpm, wakeref)
 870                 seq_printf(m, "%s %u (%llu us)\n", title,
 871                            intel_uncore_read(gt->uncore, reg),
 872                            intel_rc6_residency_us(&gt->rc6, id));
 873 }
 874
 875 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
 876 #include "selftest_rc6.c"
 877 #endif