drivers/gpu/drm/i915/display/intel_modeset_setup.c

   1 // SPDX-License-Identifier: MIT
   2 /*
   3  * Copyright © 2022 Intel Corporation
   4  *
   5  * Read out the current hardware modeset state, and sanitize it to the current
   6  * state.
   7  */
   8
   9 #include <drm/drm_atomic_uapi.h>
  10 #include <drm/drm_atomic_state_helper.h>
  11
  12 #include "i915_drv.h"
  13 #include "i915_reg.h"
  14 #include "i9xx_wm.h"
  15 #include "intel_atomic.h"
  16 #include "intel_bw.h"
  17 #include "intel_color.h"
  18 #include "intel_crtc.h"
  19 #include "intel_crtc_state_dump.h"
  20 #include "intel_ddi.h"
  21 #include "intel_de.h"
  22 #include "intel_display.h"
  23 #include "intel_display_power.h"
  24 #include "intel_display_types.h"
  25 #include "intel_dmc.h"
  26 #include "intel_fifo_underrun.h"
  27 #include "intel_modeset_setup.h"
  28 #include "intel_pch_display.h"
  29 #include "intel_tc.h"
  30 #include "intel_vblank.h"
  31 #include "intel_wm.h"
  32 #include "skl_watermark.h"
  33
  34 static void intel_crtc_disable_noatomic_begin(struct intel_crtc *crtc,
  35                                               struct drm_modeset_acquire_ctx *ctx)
  36 {
  37         struct drm_i915_private *i915 = to_i915(crtc->base.dev);
  38         struct intel_crtc_state *crtc_state =
  39                 to_intel_crtc_state(crtc->base.state);
  40         struct intel_plane *plane;
  41         struct drm_atomic_state *state;
  42         struct intel_crtc *temp_crtc;
  43         enum pipe pipe = crtc->pipe;
  44
  45         if (!crtc_state->hw.active)
  46                 return;
  47
  48         for_each_intel_plane_on_crtc(&i915->drm, crtc, plane) {
  49                 const struct intel_plane_state *plane_state =
  50                         to_intel_plane_state(plane->base.state);
  51
  52                 if (plane_state->uapi.visible)
  53                         intel_plane_disable_noatomic(crtc, plane);
  54         }
  55
  56         state = drm_atomic_state_alloc(&i915->drm);
  57         if (!state) {
  58                 drm_dbg_kms(&i915->drm,
  59                             "failed to disable [CRTC:%d:%s], out of memory",
  60                             crtc->base.base.id, crtc->base.name);
  61                 return;
  62         }
  63
  64         state->acquire_ctx = ctx;
  65         to_intel_atomic_state(state)->internal = true;
  66
  67         /* Everything's already locked, -EDEADLK can't happen. */
  68         for_each_intel_crtc_in_pipe_mask(&i915->drm, temp_crtc,
  69                                          BIT(pipe) |
  70                                          intel_crtc_bigjoiner_slave_pipes(crtc_state)) {
  71                 struct intel_crtc_state *temp_crtc_state =
  72                         intel_atomic_get_crtc_state(state, temp_crtc);
  73                 int ret;
  74
  75                 ret = drm_atomic_add_affected_connectors(state, &temp_crtc->base);
  76
  77                 drm_WARN_ON(&i915->drm, IS_ERR(temp_crtc_state) || ret);
  78         }
  79
  80         i915->display.funcs.display->crtc_disable(to_intel_atomic_state(state), crtc);
  81
  82         drm_atomic_state_put(state);
  83
  84         drm_dbg_kms(&i915->drm,
  85                     "[CRTC:%d:%s] hw state adjusted, was enabled, now disabled\n",
  86                     crtc->base.base.id, crtc->base.name);
  87
  88         crtc->active = false;
  89         crtc->base.enabled = false;
  90
  91         if (crtc_state->shared_dpll)
  92                 intel_unreference_shared_dpll_crtc(crtc,
  93                                                    crtc_state->shared_dpll,
  94                                                    &crtc_state->shared_dpll->state);
  95 }
  96
  97 static void set_encoder_for_connector(struct intel_connector *connector,
  98                                       struct intel_encoder *encoder)
  99 {
 100         struct drm_connector_state *conn_state = connector->base.state;
 101
 102         if (conn_state->crtc)
 103                 drm_connector_put(&connector->base);
 104
 105         if (encoder) {
 106                 conn_state->best_encoder = &encoder->base;
 107                 conn_state->crtc = encoder->base.crtc;
 108                 drm_connector_get(&connector->base);
 109         } else {
 110                 conn_state->best_encoder = NULL;
 111                 conn_state->crtc = NULL;
 112         }
 113 }
 114
 115 static void reset_encoder_connector_state(struct intel_encoder *encoder)
 116 {
 117         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
 118         struct intel_connector *connector;
 119         struct drm_connector_list_iter conn_iter;
 120
 121         drm_connector_list_iter_begin(&i915->drm, &conn_iter);
 122         for_each_intel_connector_iter(connector, &conn_iter) {
 123                 if (connector->base.encoder != &encoder->base)
 124                         continue;
 125
 126                 set_encoder_for_connector(connector, NULL);
 127
 128                 connector->base.dpms = DRM_MODE_DPMS_OFF;
 129                 connector->base.encoder = NULL;
 130         }
 131         drm_connector_list_iter_end(&conn_iter);
 132 }
 133
 134 static void reset_crtc_encoder_state(struct intel_crtc *crtc)
 135 {
 136         struct drm_i915_private *i915 = to_i915(crtc->base.dev);
 137         struct intel_encoder *encoder;
 138
 139         for_each_encoder_on_crtc(&i915->drm, &crtc->base, encoder) {
 140                 reset_encoder_connector_state(encoder);
 141                 encoder->base.crtc = NULL;
 142         }
 143 }
 144
 145 static void intel_crtc_disable_noatomic_complete(struct intel_crtc *crtc)
 146 {
 147         struct drm_i915_private *i915 = to_i915(crtc->base.dev);
 148         struct intel_bw_state *bw_state =
 149                 to_intel_bw_state(i915->display.bw.obj.state);
 150         struct intel_cdclk_state *cdclk_state =
 151                 to_intel_cdclk_state(i915->display.cdclk.obj.state);
 152         struct intel_dbuf_state *dbuf_state =
 153                 to_intel_dbuf_state(i915->display.dbuf.obj.state);
 154         struct intel_crtc_state *crtc_state =
 155                 to_intel_crtc_state(crtc->base.state);
 156         enum pipe pipe = crtc->pipe;
 157
 158         __drm_atomic_helper_crtc_destroy_state(&crtc_state->uapi);
 159         intel_crtc_free_hw_state(crtc_state);
 160         intel_crtc_state_reset(crtc_state, crtc);
 161
 162         reset_crtc_encoder_state(crtc);
 163
 164         intel_fbc_disable(crtc);
 165         intel_update_watermarks(i915);
 166
 167         intel_display_power_put_all_in_set(i915, &crtc->enabled_power_domains);
 168
 169         cdclk_state->min_cdclk[pipe] = 0;
 170         cdclk_state->min_voltage_level[pipe] = 0;
 171         cdclk_state->active_pipes &= ~BIT(pipe);
 172
 173         dbuf_state->active_pipes &= ~BIT(pipe);
 174
 175         bw_state->data_rate[pipe] = 0;
 176         bw_state->num_active_planes[pipe] = 0;
 177 }
 178
 179 /*
 180  * Return all the pipes using a transcoder in @transcoder_mask.
 181  * For bigjoiner configs return only the bigjoiner master.
 182  */
 183 static u8 get_transcoder_pipes(struct drm_i915_private *i915,
 184                                u8 transcoder_mask)
 185 {
 186         struct intel_crtc *temp_crtc;
 187         u8 pipes = 0;
 188
 189         for_each_intel_crtc(&i915->drm, temp_crtc) {
 190                 struct intel_crtc_state *temp_crtc_state =
 191                         to_intel_crtc_state(temp_crtc->base.state);
 192
 193                 if (temp_crtc_state->cpu_transcoder == INVALID_TRANSCODER)
 194                         continue;
 195
 196                 if (intel_crtc_is_bigjoiner_slave(temp_crtc_state))
 197                         continue;
 198
 199                 if (transcoder_mask & BIT(temp_crtc_state->cpu_transcoder))
 200                         pipes |= BIT(temp_crtc->pipe);
 201         }
 202
 203         return pipes;
 204 }
 205
 206 /*
 207  * Return the port sync master and slave pipes linked to @crtc.
 208  * For bigjoiner configs return only the bigjoiner master pipes.
 209  */
 210 static void get_portsync_pipes(struct intel_crtc *crtc,
 211                                u8 *master_pipe_mask, u8 *slave_pipes_mask)
 212 {
 213         struct drm_i915_private *i915 = to_i915(crtc->base.dev);
 214         struct intel_crtc_state *crtc_state =
 215                 to_intel_crtc_state(crtc->base.state);
 216         struct intel_crtc *master_crtc;
 217         struct intel_crtc_state *master_crtc_state;
 218         enum transcoder master_transcoder;
 219
 220         if (!is_trans_port_sync_mode(crtc_state)) {
 221                 *master_pipe_mask = BIT(crtc->pipe);
 222                 *slave_pipes_mask = 0;
 223
 224                 return;
 225         }
 226
 227         if (is_trans_port_sync_master(crtc_state))
 228                 master_transcoder = crtc_state->cpu_transcoder;
 229         else
 230                 master_transcoder = crtc_state->master_transcoder;
 231
 232         *master_pipe_mask = get_transcoder_pipes(i915, BIT(master_transcoder));
 233         drm_WARN_ON(&i915->drm, !is_power_of_2(*master_pipe_mask));
 234
 235         master_crtc = intel_crtc_for_pipe(i915, ffs(*master_pipe_mask) - 1);
 236         master_crtc_state = to_intel_crtc_state(master_crtc->base.state);
 237         *slave_pipes_mask = get_transcoder_pipes(i915, master_crtc_state->sync_mode_slaves_mask);
 238 }
 239
 240 static u8 get_bigjoiner_slave_pipes(struct drm_i915_private *i915, u8 master_pipes_mask)
 241 {
 242         struct intel_crtc *master_crtc;
 243         u8 pipes = 0;
 244
 245         for_each_intel_crtc_in_pipe_mask(&i915->drm, master_crtc, master_pipes_mask) {
 246                 struct intel_crtc_state *master_crtc_state =
 247                         to_intel_crtc_state(master_crtc->base.state);
 248
 249                 pipes |= intel_crtc_bigjoiner_slave_pipes(master_crtc_state);
 250         }
 251
 252         return pipes;
 253 }
 254
 255 static void intel_crtc_disable_noatomic(struct intel_crtc *crtc,
 256                                         struct drm_modeset_acquire_ctx *ctx)
 257 {
 258         struct drm_i915_private *i915 = to_i915(crtc->base.dev);
 259         u8 portsync_master_mask;
 260         u8 portsync_slaves_mask;
 261         u8 bigjoiner_slaves_mask;
 262         struct intel_crtc *temp_crtc;
 263
 264         /* TODO: Add support for MST */
 265         get_portsync_pipes(crtc, &portsync_master_mask, &portsync_slaves_mask);
 266         bigjoiner_slaves_mask = get_bigjoiner_slave_pipes(i915,
 267                                                           portsync_master_mask |
 268                                                           portsync_slaves_mask);
 269
 270         drm_WARN_ON(&i915->drm,
 271                     portsync_master_mask & portsync_slaves_mask ||
 272                     portsync_master_mask & bigjoiner_slaves_mask ||
 273                     portsync_slaves_mask & bigjoiner_slaves_mask);
 274
 275         for_each_intel_crtc_in_pipe_mask(&i915->drm, temp_crtc, bigjoiner_slaves_mask)
 276                 intel_crtc_disable_noatomic_begin(temp_crtc, ctx);
 277
 278         for_each_intel_crtc_in_pipe_mask(&i915->drm, temp_crtc, portsync_slaves_mask)
 279                 intel_crtc_disable_noatomic_begin(temp_crtc, ctx);
 280
 281         for_each_intel_crtc_in_pipe_mask(&i915->drm, temp_crtc, portsync_master_mask)
 282                 intel_crtc_disable_noatomic_begin(temp_crtc, ctx);
 283
 284         for_each_intel_crtc_in_pipe_mask(&i915->drm, temp_crtc,
 285                                          bigjoiner_slaves_mask |
 286                                          portsync_slaves_mask |
 287                                          portsync_master_mask)
 288                 intel_crtc_disable_noatomic_complete(temp_crtc);
 289 }
 290
 291 static void intel_modeset_update_connector_atomic_state(struct drm_i915_private *i915)
 292 {
 293         struct intel_connector *connector;
 294         struct drm_connector_list_iter conn_iter;
 295
 296         drm_connector_list_iter_begin(&i915->drm, &conn_iter);
 297         for_each_intel_connector_iter(connector, &conn_iter) {
 298                 struct drm_connector_state *conn_state = connector->base.state;
 299                 struct intel_encoder *encoder =
 300                         to_intel_encoder(connector->base.encoder);
 301
 302                 set_encoder_for_connector(connector, encoder);
 303
 304                 if (encoder) {
 305                         struct intel_crtc *crtc =
 306                                 to_intel_crtc(encoder->base.crtc);
 307                         const struct intel_crtc_state *crtc_state =
 308                                 to_intel_crtc_state(crtc->base.state);
 309
 310                         conn_state->max_bpc = (crtc_state->pipe_bpp ?: 24) / 3;
 311                 }
 312         }
 313         drm_connector_list_iter_end(&conn_iter);
 314 }
 315
 316 static void intel_crtc_copy_hw_to_uapi_state(struct intel_crtc_state *crtc_state)
 317 {
 318         if (intel_crtc_is_bigjoiner_slave(crtc_state))
 319                 return;
 320
 321         crtc_state->uapi.enable = crtc_state->hw.enable;
 322         crtc_state->uapi.active = crtc_state->hw.active;
 323         drm_WARN_ON(crtc_state->uapi.crtc->dev,
 324                     drm_atomic_set_mode_for_crtc(&crtc_state->uapi, &crtc_state->hw.mode) < 0);
 325
 326         crtc_state->uapi.adjusted_mode = crtc_state->hw.adjusted_mode;
 327         crtc_state->uapi.scaling_filter = crtc_state->hw.scaling_filter;
 328
 329         /* assume 1:1 mapping */
 330         drm_property_replace_blob(&crtc_state->hw.degamma_lut,
 331                                   crtc_state->pre_csc_lut);
 332         drm_property_replace_blob(&crtc_state->hw.gamma_lut,
 333                                   crtc_state->post_csc_lut);
 334
 335         drm_property_replace_blob(&crtc_state->uapi.degamma_lut,
 336                                   crtc_state->hw.degamma_lut);
 337         drm_property_replace_blob(&crtc_state->uapi.gamma_lut,
 338                                   crtc_state->hw.gamma_lut);
 339         drm_property_replace_blob(&crtc_state->uapi.ctm,
 340                                   crtc_state->hw.ctm);
 341 }
 342
 343 static void
 344 intel_sanitize_plane_mapping(struct drm_i915_private *i915)
 345 {
 346         struct intel_crtc *crtc;
 347
 348         if (DISPLAY_VER(i915) >= 4)
 349                 return;
 350
 351         for_each_intel_crtc(&i915->drm, crtc) {
 352                 struct intel_plane *plane =
 353                         to_intel_plane(crtc->base.primary);
 354                 struct intel_crtc *plane_crtc;
 355                 enum pipe pipe;
 356
 357                 if (!plane->get_hw_state(plane, &pipe))
 358                         continue;
 359
 360                 if (pipe == crtc->pipe)
 361                         continue;
 362
 363                 drm_dbg_kms(&i915->drm,
 364                             "[PLANE:%d:%s] attached to the wrong pipe, disabling plane\n",
 365                             plane->base.base.id, plane->base.name);
 366
 367                 plane_crtc = intel_crtc_for_pipe(i915, pipe);
 368                 intel_plane_disable_noatomic(plane_crtc, plane);
 369         }
 370 }
 371
 372 static bool intel_crtc_has_encoders(struct intel_crtc *crtc)
 373 {
 374         struct drm_device *dev = crtc->base.dev;
 375         struct intel_encoder *encoder;
 376
 377         for_each_encoder_on_crtc(dev, &crtc->base, encoder)
 378                 return true;
 379
 380         return false;
 381 }
 382
 383 static bool intel_crtc_needs_link_reset(struct intel_crtc *crtc)
 384 {
 385         struct drm_device *dev = crtc->base.dev;
 386         struct intel_encoder *encoder;
 387
 388         for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
 389                 struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
 390
 391                 if (dig_port && intel_tc_port_link_needs_reset(dig_port))
 392                         return true;
 393         }
 394
 395         return false;
 396 }
 397
 398 static struct intel_connector *intel_encoder_find_connector(struct intel_encoder *encoder)
 399 {
 400         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
 401         struct drm_connector_list_iter conn_iter;
 402         struct intel_connector *connector;
 403         struct intel_connector *found_connector = NULL;
 404
 405         drm_connector_list_iter_begin(&i915->drm, &conn_iter);
 406         for_each_intel_connector_iter(connector, &conn_iter) {
 407                 if (&encoder->base == connector->base.encoder) {
 408                         found_connector = connector;
 409                         break;
 410                 }
 411         }
 412         drm_connector_list_iter_end(&conn_iter);
 413
 414         return found_connector;
 415 }
 416
 417 static void intel_sanitize_fifo_underrun_reporting(const struct intel_crtc_state *crtc_state)
 418 {
 419         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 420         struct drm_i915_private *i915 = to_i915(crtc->base.dev);
 421
 422         /*
 423          * We start out with underrun reporting disabled on active
 424          * pipes to avoid races.
 425          *
 426          * Also on gmch platforms we dont have any hardware bits to
 427          * disable the underrun reporting. Which means we need to start
 428          * out with underrun reporting disabled also on inactive pipes,
 429          * since otherwise we'll complain about the garbage we read when
 430          * e.g. coming up after runtime pm.
 431          *
 432          * No protection against concurrent access is required - at
 433          * worst a fifo underrun happens which also sets this to false.
 434          */
 435         intel_init_fifo_underrun_reporting(i915, crtc,
 436                                            !crtc_state->hw.active &&
 437                                            !HAS_GMCH(i915));
 438 }
 439
 440 static bool intel_sanitize_crtc(struct intel_crtc *crtc,
 441                                 struct drm_modeset_acquire_ctx *ctx)
 442 {
 443         struct drm_i915_private *i915 = to_i915(crtc->base.dev);
 444         struct intel_crtc_state *crtc_state = to_intel_crtc_state(crtc->base.state);
 445         bool needs_link_reset;
 446
 447         if (crtc_state->hw.active) {
 448                 struct intel_plane *plane;
 449
 450                 /* Disable everything but the primary plane */
 451                 for_each_intel_plane_on_crtc(&i915->drm, crtc, plane) {
 452                         const struct intel_plane_state *plane_state =
 453                                 to_intel_plane_state(plane->base.state);
 454
 455                         if (plane_state->uapi.visible &&
 456                             plane->base.type != DRM_PLANE_TYPE_PRIMARY)
 457                                 intel_plane_disable_noatomic(crtc, plane);
 458                 }
 459
 460                 /* Disable any background color/etc. set by the BIOS */
 461                 intel_color_commit_noarm(crtc_state);
 462                 intel_color_commit_arm(crtc_state);
 463         }
 464
 465         if (!crtc_state->hw.active ||
 466             intel_crtc_is_bigjoiner_slave(crtc_state))
 467                 return false;
 468
 469         needs_link_reset = intel_crtc_needs_link_reset(crtc);
 470
 471         /*
 472          * Adjust the state of the output pipe according to whether we have
 473          * active connectors/encoders.
 474          */
 475         if (!needs_link_reset && intel_crtc_has_encoders(crtc))
 476                 return false;
 477
 478         intel_crtc_disable_noatomic(crtc, ctx);
 479
 480         /*
 481          * The HPD state on other active/disconnected TC ports may be stuck in
 482          * the connected state until this port is disabled and a ~10ms delay has
 483          * passed, wait here for that so that sanitizing other CRTCs will see the
 484          * up-to-date HPD state.
 485          */
 486         if (needs_link_reset)
 487                 msleep(20);
 488
 489         return true;
 490 }
 491
 492 static void intel_sanitize_all_crtcs(struct drm_i915_private *i915,
 493                                      struct drm_modeset_acquire_ctx *ctx)
 494 {
 495         struct intel_crtc *crtc;
 496         u32 crtcs_forced_off = 0;
 497
 498         /*
 499          * An active and disconnected TypeC port prevents the HPD live state
 500          * to get updated on other active/disconnected TypeC ports, so after
 501          * a port gets disabled the CRTCs using other TypeC ports must be
 502          * rechecked wrt. their link status.
 503          */
 504         for (;;) {
 505                 u32 old_mask = crtcs_forced_off;
 506
 507                 for_each_intel_crtc(&i915->drm, crtc) {
 508                         u32 crtc_mask = drm_crtc_mask(&crtc->base);
 509
 510                         if (crtcs_forced_off & crtc_mask)
 511                                 continue;
 512
 513                         if (intel_sanitize_crtc(crtc, ctx))
 514                                 crtcs_forced_off |= crtc_mask;
 515                 }
 516                 if (crtcs_forced_off == old_mask)
 517                         break;
 518         }
 519
 520         for_each_intel_crtc(&i915->drm, crtc) {
 521                 struct intel_crtc_state *crtc_state =
 522                         to_intel_crtc_state(crtc->base.state);
 523
 524                 intel_crtc_state_dump(crtc_state, NULL, "setup_hw_state");
 525         }
 526 }
 527
 528 static bool has_bogus_dpll_config(const struct intel_crtc_state *crtc_state)
 529 {
 530         struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
 531
 532         /*
 533          * Some SNB BIOSen (eg. ASUS K53SV) are known to misprogram
 534          * the hardware when a high res displays plugged in. DPLL P
 535          * divider is zero, and the pipe timings are bonkers. We'll
 536          * try to disable everything in that case.
 537          *
 538          * FIXME would be nice to be able to sanitize this state
 539          * without several WARNs, but for now let's take the easy
 540          * road.
 541          */
 542         return IS_SANDYBRIDGE(i915) &&
 543                 crtc_state->hw.active &&
 544                 crtc_state->shared_dpll &&
 545                 crtc_state->port_clock == 0;
 546 }
 547
 548 static void intel_sanitize_encoder(struct intel_encoder *encoder)
 549 {
 550         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
 551         struct intel_connector *connector;
 552         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
 553         struct intel_crtc_state *crtc_state = crtc ?
 554                 to_intel_crtc_state(crtc->base.state) : NULL;
 555
 556         /*
 557          * We need to check both for a crtc link (meaning that the encoder is
 558          * active and trying to read from a pipe) and the pipe itself being
 559          * active.
 560          */
 561         bool has_active_crtc = crtc_state &&
 562                 crtc_state->hw.active;
 563
 564         if (crtc_state && has_bogus_dpll_config(crtc_state)) {
 565                 drm_dbg_kms(&i915->drm,
 566                             "BIOS has misprogrammed the hardware. Disabling pipe %c\n",
 567                             pipe_name(crtc->pipe));
 568                 has_active_crtc = false;
 569         }
 570
 571         connector = intel_encoder_find_connector(encoder);
 572         if (connector && !has_active_crtc) {
 573                 drm_dbg_kms(&i915->drm,
 574                             "[ENCODER:%d:%s] has active connectors but no active pipe!\n",
 575                             encoder->base.base.id,
 576                             encoder->base.name);
 577
 578                 /*
 579                  * Connector is active, but has no active pipe. This is fallout
 580                  * from our resume register restoring. Disable the encoder
 581                  * manually again.
 582                  */
 583                 if (crtc_state) {
 584                         struct drm_encoder *best_encoder;
 585
 586                         drm_dbg_kms(&i915->drm,
 587                                     "[ENCODER:%d:%s] manually disabled\n",
 588                                     encoder->base.base.id,
 589                                     encoder->base.name);
 590
 591                         /* avoid oopsing in case the hooks consult best_encoder */
 592                         best_encoder = connector->base.state->best_encoder;
 593                         connector->base.state->best_encoder = &encoder->base;
 594
 595                         /* FIXME NULL atomic state passed! */
 596                         if (encoder->disable)
 597                                 encoder->disable(NULL, encoder, crtc_state,
 598                                                  connector->base.state);
 599                         if (encoder->post_disable)
 600                                 encoder->post_disable(NULL, encoder, crtc_state,
 601                                                       connector->base.state);
 602
 603                         connector->base.state->best_encoder = best_encoder;
 604                 }
 605                 encoder->base.crtc = NULL;
 606
 607                 /*
 608                  * Inconsistent output/port/pipe state happens presumably due to
 609                  * a bug in one of the get_hw_state functions. Or someplace else
 610                  * in our code, like the register restore mess on resume. Clamp
 611                  * things to off as a safer default.
 612                  */
 613                 connector->base.dpms = DRM_MODE_DPMS_OFF;
 614                 connector->base.encoder = NULL;
 615         }
 616
 617         /* notify opregion of the sanitized encoder state */
 618         intel_opregion_notify_encoder(encoder, connector && has_active_crtc);
 619
 620         if (HAS_DDI(i915))
 621                 intel_ddi_sanitize_encoder_pll_mapping(encoder);
 622 }
 623
 624 /* FIXME read out full plane state for all planes */
 625 static void readout_plane_state(struct drm_i915_private *i915)
 626 {
 627         struct intel_plane *plane;
 628         struct intel_crtc *crtc;
 629
 630         for_each_intel_plane(&i915->drm, plane) {
 631                 struct intel_plane_state *plane_state =
 632                         to_intel_plane_state(plane->base.state);
 633                 struct intel_crtc_state *crtc_state;
 634                 enum pipe pipe = PIPE_A;
 635                 bool visible;
 636
 637                 visible = plane->get_hw_state(plane, &pipe);
 638
 639                 crtc = intel_crtc_for_pipe(i915, pipe);
 640                 crtc_state = to_intel_crtc_state(crtc->base.state);
 641
 642                 intel_set_plane_visible(crtc_state, plane_state, visible);
 643
 644                 drm_dbg_kms(&i915->drm,
 645                             "[PLANE:%d:%s] hw state readout: %s, pipe %c\n",
 646                             plane->base.base.id, plane->base.name,
 647                             str_enabled_disabled(visible), pipe_name(pipe));
 648         }
 649
 650         for_each_intel_crtc(&i915->drm, crtc) {
 651                 struct intel_crtc_state *crtc_state =
 652                         to_intel_crtc_state(crtc->base.state);
 653
 654                 intel_plane_fixup_bitmasks(crtc_state);
 655         }
 656 }
 657
 658 static void intel_modeset_readout_hw_state(struct drm_i915_private *i915)
 659 {
 660         struct intel_cdclk_state *cdclk_state =
 661                 to_intel_cdclk_state(i915->display.cdclk.obj.state);
 662         struct intel_dbuf_state *dbuf_state =
 663                 to_intel_dbuf_state(i915->display.dbuf.obj.state);
 664         enum pipe pipe;
 665         struct intel_crtc *crtc;
 666         struct intel_encoder *encoder;
 667         struct intel_connector *connector;
 668         struct drm_connector_list_iter conn_iter;
 669         u8 active_pipes = 0;
 670
 671         for_each_intel_crtc(&i915->drm, crtc) {
 672                 struct intel_crtc_state *crtc_state =
 673                         to_intel_crtc_state(crtc->base.state);
 674
 675                 __drm_atomic_helper_crtc_destroy_state(&crtc_state->uapi);
 676                 intel_crtc_free_hw_state(crtc_state);
 677                 intel_crtc_state_reset(crtc_state, crtc);
 678
 679                 intel_crtc_get_pipe_config(crtc_state);
 680
 681                 crtc_state->hw.enable = crtc_state->hw.active;
 682
 683                 crtc->base.enabled = crtc_state->hw.enable;
 684                 crtc->active = crtc_state->hw.active;
 685
 686                 if (crtc_state->hw.active)
 687                         active_pipes |= BIT(crtc->pipe);
 688
 689                 drm_dbg_kms(&i915->drm,
 690                             "[CRTC:%d:%s] hw state readout: %s\n",
 691                             crtc->base.base.id, crtc->base.name,
 692                             str_enabled_disabled(crtc_state->hw.active));
 693         }
 694
 695         cdclk_state->active_pipes = active_pipes;
 696         dbuf_state->active_pipes = active_pipes;
 697
 698         readout_plane_state(i915);
 699
 700         for_each_intel_encoder(&i915->drm, encoder) {
 701                 struct intel_crtc_state *crtc_state = NULL;
 702
 703                 pipe = 0;
 704
 705                 if (encoder->get_hw_state(encoder, &pipe)) {
 706                         crtc = intel_crtc_for_pipe(i915, pipe);
 707                         crtc_state = to_intel_crtc_state(crtc->base.state);
 708
 709                         encoder->base.crtc = &crtc->base;
 710                         intel_encoder_get_config(encoder, crtc_state);
 711
 712                         /* read out to slave crtc as well for bigjoiner */
 713                         if (crtc_state->bigjoiner_pipes) {
 714                                 struct intel_crtc *slave_crtc;
 715
 716                                 /* encoder should read be linked to bigjoiner master */
 717                                 WARN_ON(intel_crtc_is_bigjoiner_slave(crtc_state));
 718
 719                                 for_each_intel_crtc_in_pipe_mask(&i915->drm, slave_crtc,
 720                                                                  intel_crtc_bigjoiner_slave_pipes(crtc_state)) {
 721                                         struct intel_crtc_state *slave_crtc_state;
 722
 723                                         slave_crtc_state = to_intel_crtc_state(slave_crtc->base.state);
 724                                         intel_encoder_get_config(encoder, slave_crtc_state);
 725                                 }
 726                         }
 727                 } else {
 728                         encoder->base.crtc = NULL;
 729                 }
 730
 731                 if (encoder->sync_state)
 732                         encoder->sync_state(encoder, crtc_state);
 733
 734                 drm_dbg_kms(&i915->drm,
 735                             "[ENCODER:%d:%s] hw state readout: %s, pipe %c\n",
 736                             encoder->base.base.id, encoder->base.name,
 737                             str_enabled_disabled(encoder->base.crtc),
 738                             pipe_name(pipe));
 739         }
 740
 741         intel_dpll_readout_hw_state(i915);
 742
 743         drm_connector_list_iter_begin(&i915->drm, &conn_iter);
 744         for_each_intel_connector_iter(connector, &conn_iter) {
 745                 if (connector->get_hw_state(connector)) {
 746                         struct intel_crtc_state *crtc_state;
 747                         struct intel_crtc *crtc;
 748
 749                         connector->base.dpms = DRM_MODE_DPMS_ON;
 750
 751                         encoder = intel_attached_encoder(connector);
 752                         connector->base.encoder = &encoder->base;
 753
 754                         crtc = to_intel_crtc(encoder->base.crtc);
 755                         crtc_state = crtc ? to_intel_crtc_state(crtc->base.state) : NULL;
 756
 757                         if (crtc_state && crtc_state->hw.active) {
 758                                 /*
 759                                  * This has to be done during hardware readout
 760                                  * because anything calling .crtc_disable may
 761                                  * rely on the connector_mask being accurate.
 762                                  */
 763                                 crtc_state->uapi.connector_mask |=
 764                                         drm_connector_mask(&connector->base);
 765                                 crtc_state->uapi.encoder_mask |=
 766                                         drm_encoder_mask(&encoder->base);
 767                         }
 768                 } else {
 769                         connector->base.dpms = DRM_MODE_DPMS_OFF;
 770                         connector->base.encoder = NULL;
 771                 }
 772                 drm_dbg_kms(&i915->drm,
 773                             "[CONNECTOR:%d:%s] hw state readout: %s\n",
 774                             connector->base.base.id, connector->base.name,
 775                             str_enabled_disabled(connector->base.encoder));
 776         }
 777         drm_connector_list_iter_end(&conn_iter);
 778
 779         for_each_intel_crtc(&i915->drm, crtc) {
 780                 struct intel_bw_state *bw_state =
 781                         to_intel_bw_state(i915->display.bw.obj.state);
 782                 struct intel_crtc_state *crtc_state =
 783                         to_intel_crtc_state(crtc->base.state);
 784                 struct intel_plane *plane;
 785                 int min_cdclk = 0;
 786
 787                 if (crtc_state->hw.active) {
 788                         /*
 789                          * The initial mode needs to be set in order to keep
 790                          * the atomic core happy. It wants a valid mode if the
 791                          * crtc's enabled, so we do the above call.
 792                          *
 793                          * But we don't set all the derived state fully, hence
 794                          * set a flag to indicate that a full recalculation is
 795                          * needed on the next commit.
 796                          */
 797                         crtc_state->inherited = true;
 798
 799                         intel_crtc_update_active_timings(crtc_state,
 800                                                          crtc_state->vrr.enable);
 801
 802                         intel_crtc_copy_hw_to_uapi_state(crtc_state);
 803                 }
 804
 805                 for_each_intel_plane_on_crtc(&i915->drm, crtc, plane) {
 806                         const struct intel_plane_state *plane_state =
 807                                 to_intel_plane_state(plane->base.state);
 808
 809                         /*
 810                          * FIXME don't have the fb yet, so can't
 811                          * use intel_plane_data_rate() :(
 812                          */
 813                         if (plane_state->uapi.visible)
 814                                 crtc_state->data_rate[plane->id] =
 815                                         4 * crtc_state->pixel_rate;
 816                         /*
 817                          * FIXME don't have the fb yet, so can't
 818                          * use plane->min_cdclk() :(
 819                          */
 820                         if (plane_state->uapi.visible && plane->min_cdclk) {
 821                                 if (crtc_state->double_wide || DISPLAY_VER(i915) >= 10)
 822                                         crtc_state->min_cdclk[plane->id] =
 823                                                 DIV_ROUND_UP(crtc_state->pixel_rate, 2);
 824                                 else
 825                                         crtc_state->min_cdclk[plane->id] =
 826                                                 crtc_state->pixel_rate;
 827                         }
 828                         drm_dbg_kms(&i915->drm,
 829                                     "[PLANE:%d:%s] min_cdclk %d kHz\n",
 830                                     plane->base.base.id, plane->base.name,
 831                                     crtc_state->min_cdclk[plane->id]);
 832                 }
 833
 834                 if (crtc_state->hw.active) {
 835                         min_cdclk = intel_crtc_compute_min_cdclk(crtc_state);
 836                         if (drm_WARN_ON(&i915->drm, min_cdclk < 0))
 837                                 min_cdclk = 0;
 838                 }
 839
 840                 cdclk_state->min_cdclk[crtc->pipe] = min_cdclk;
 841                 cdclk_state->min_voltage_level[crtc->pipe] =
 842                         crtc_state->min_voltage_level;
 843
 844                 intel_bw_crtc_update(bw_state, crtc_state);
 845         }
 846 }
 847
 848 static void
 849 get_encoder_power_domains(struct drm_i915_private *i915)
 850 {
 851         struct intel_encoder *encoder;
 852
 853         for_each_intel_encoder(&i915->drm, encoder) {
 854                 struct intel_crtc_state *crtc_state;
 855
 856                 if (!encoder->get_power_domains)
 857                         continue;
 858
 859                 /*
 860                  * MST-primary and inactive encoders don't have a crtc state
 861                  * and neither of these require any power domain references.
 862                  */
 863                 if (!encoder->base.crtc)
 864                         continue;
 865
 866                 crtc_state = to_intel_crtc_state(encoder->base.crtc->state);
 867                 encoder->get_power_domains(encoder, crtc_state);
 868         }
 869 }
 870
 871 static void intel_early_display_was(struct drm_i915_private *i915)
 872 {
 873         /*
 874          * Display WA #1185 WaDisableDARBFClkGating:glk,icl,ehl,tgl
 875          * Also known as Wa_14010480278.
 876          */
 877         if (IS_DISPLAY_VER(i915, 10, 12))
 878                 intel_de_rmw(i915, GEN9_CLKGATE_DIS_0, 0, DARBF_GATING_DIS);
 879
 880         /*
 881          * WaRsPkgCStateDisplayPMReq:hsw
 882          * System hang if this isn't done before disabling all planes!
 883          */
 884         if (IS_HASWELL(i915))
 885                 intel_de_rmw(i915, CHICKEN_PAR1_1, 0, FORCE_ARB_IDLE_PLANES);
 886
 887         if (IS_KABYLAKE(i915) || IS_COFFEELAKE(i915) || IS_COMETLAKE(i915)) {
 888                 /* Display WA #1142:kbl,cfl,cml */
 889                 intel_de_rmw(i915, CHICKEN_PAR1_1,
 890                              KBL_ARB_FILL_SPARE_22, KBL_ARB_FILL_SPARE_22);
 891                 intel_de_rmw(i915, CHICKEN_MISC_2,
 892                              KBL_ARB_FILL_SPARE_13 | KBL_ARB_FILL_SPARE_14,
 893                              KBL_ARB_FILL_SPARE_14);
 894         }
 895 }
 896
 897 void intel_modeset_setup_hw_state(struct drm_i915_private *i915,
 898                                   struct drm_modeset_acquire_ctx *ctx)
 899 {
 900         struct intel_encoder *encoder;
 901         struct intel_crtc *crtc;
 902         intel_wakeref_t wakeref;
 903
 904         wakeref = intel_display_power_get(i915, POWER_DOMAIN_INIT);
 905
 906         intel_early_display_was(i915);
 907         intel_modeset_readout_hw_state(i915);
 908
 909         /* HW state is read out, now we need to sanitize this mess. */
 910         get_encoder_power_domains(i915);
 911
 912         intel_pch_sanitize(i915);
 913
 914         /*
 915          * intel_sanitize_plane_mapping() may need to do vblank
 916          * waits, so we need vblank interrupts restored beforehand.
 917          */
 918         for_each_intel_crtc(&i915->drm, crtc) {
 919                 struct intel_crtc_state *crtc_state =
 920                         to_intel_crtc_state(crtc->base.state);
 921
 922                 intel_sanitize_fifo_underrun_reporting(crtc_state);
 923
 924                 drm_crtc_vblank_reset(&crtc->base);
 925
 926                 if (crtc_state->hw.active) {
 927                         intel_dmc_enable_pipe(i915, crtc->pipe);
 928                         intel_crtc_vblank_on(crtc_state);
 929                 }
 930         }
 931
 932         intel_fbc_sanitize(i915);
 933
 934         intel_sanitize_plane_mapping(i915);
 935
 936         for_each_intel_encoder(&i915->drm, encoder)
 937                 intel_sanitize_encoder(encoder);
 938
 939         /*
 940          * Sanitizing CRTCs needs their connector atomic state to be
 941          * up-to-date, so ensure that already here.
 942          */
 943         intel_modeset_update_connector_atomic_state(i915);
 944
 945         intel_sanitize_all_crtcs(i915, ctx);
 946
 947         intel_dpll_sanitize_state(i915);
 948
 949         intel_wm_get_hw_state(i915);
 950
 951         for_each_intel_crtc(&i915->drm, crtc) {
 952                 struct intel_crtc_state *crtc_state =
 953                         to_intel_crtc_state(crtc->base.state);
 954                 struct intel_power_domain_mask put_domains;
 955
 956                 intel_modeset_get_crtc_power_domains(crtc_state, &put_domains);
 957                 if (drm_WARN_ON(&i915->drm, !bitmap_empty(put_domains.bits, POWER_DOMAIN_NUM)))
 958                         intel_modeset_put_crtc_power_domains(crtc, &put_domains);
 959         }
 960
 961         intel_display_power_put(i915, POWER_DOMAIN_INIT, wakeref);
 962
 963         intel_power_domains_sanitize_state(i915);
 964 }