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25 #ifndef _INTEL_DPLL_MGR_H_
26 #define _INTEL_DPLL_MGR_H_
28 #include <linux/types.h>
30 #include "intel_wakeref.h"
32 /*FIXME: Move this to a more appropriate place. */
33 #define abs_diff(a, b) ({ \
34 typeof(a) __a = (a); \
35 typeof(b) __b = (b); \
36 (void) (&__a == &__b); \
37 __a > __b ? (__a - __b) : (__b - __a); })
40 struct drm_i915_private;
41 struct intel_atomic_state;
43 struct intel_crtc_state;
45 struct intel_shared_dpll;
46 struct intel_shared_dpll_funcs;
49 * enum intel_dpll_id - possible DPLL ids
51 * Enumeration of possible IDs for a DPLL. Real shared dpll ids must be >= 0.
55 * @DPLL_ID_PRIVATE: non-shared dpll in use
60 * @DPLL_ID_PCH_PLL_A: DPLL A in ILK, SNB and IVB
62 DPLL_ID_PCH_PLL_A = 0,
64 * @DPLL_ID_PCH_PLL_B: DPLL B in ILK, SNB and IVB
66 DPLL_ID_PCH_PLL_B = 1,
70 * @DPLL_ID_WRPLL1: HSW and BDW WRPLL1
74 * @DPLL_ID_WRPLL2: HSW and BDW WRPLL2
78 * @DPLL_ID_SPLL: HSW and BDW SPLL
82 * @DPLL_ID_LCPLL_810: HSW and BDW 0.81 GHz LCPLL
84 DPLL_ID_LCPLL_810 = 3,
86 * @DPLL_ID_LCPLL_1350: HSW and BDW 1.35 GHz LCPLL
88 DPLL_ID_LCPLL_1350 = 4,
90 * @DPLL_ID_LCPLL_2700: HSW and BDW 2.7 GHz LCPLL
92 DPLL_ID_LCPLL_2700 = 5,
96 * @DPLL_ID_SKL_DPLL0: SKL and later DPLL0
98 DPLL_ID_SKL_DPLL0 = 0,
100 * @DPLL_ID_SKL_DPLL1: SKL and later DPLL1
102 DPLL_ID_SKL_DPLL1 = 1,
104 * @DPLL_ID_SKL_DPLL2: SKL and later DPLL2
106 DPLL_ID_SKL_DPLL2 = 2,
108 * @DPLL_ID_SKL_DPLL3: SKL and later DPLL3
110 DPLL_ID_SKL_DPLL3 = 3,
114 * @DPLL_ID_ICL_DPLL0: ICL/TGL combo PHY DPLL0
116 DPLL_ID_ICL_DPLL0 = 0,
118 * @DPLL_ID_ICL_DPLL1: ICL/TGL combo PHY DPLL1
120 DPLL_ID_ICL_DPLL1 = 1,
122 * @DPLL_ID_EHL_DPLL4: EHL combo PHY DPLL4
124 DPLL_ID_EHL_DPLL4 = 2,
126 * @DPLL_ID_ICL_TBTPLL: ICL/TGL TBT PLL
128 DPLL_ID_ICL_TBTPLL = 2,
130 * @DPLL_ID_ICL_MGPLL1: ICL MG PLL 1 port 1 (C),
131 * TGL TC PLL 1 port 1 (TC1)
133 DPLL_ID_ICL_MGPLL1 = 3,
135 * @DPLL_ID_ICL_MGPLL2: ICL MG PLL 1 port 2 (D)
136 * TGL TC PLL 1 port 2 (TC2)
138 DPLL_ID_ICL_MGPLL2 = 4,
140 * @DPLL_ID_ICL_MGPLL3: ICL MG PLL 1 port 3 (E)
141 * TGL TC PLL 1 port 3 (TC3)
143 DPLL_ID_ICL_MGPLL3 = 5,
145 * @DPLL_ID_ICL_MGPLL4: ICL MG PLL 1 port 4 (F)
146 * TGL TC PLL 1 port 4 (TC4)
148 DPLL_ID_ICL_MGPLL4 = 6,
150 * @DPLL_ID_TGL_MGPLL5: TGL TC PLL port 5 (TC5)
152 DPLL_ID_TGL_MGPLL5 = 7,
154 * @DPLL_ID_TGL_MGPLL6: TGL TC PLL port 6 (TC6)
156 DPLL_ID_TGL_MGPLL6 = 8,
159 * @DPLL_ID_DG1_DPLL0: DG1 combo PHY DPLL0
161 DPLL_ID_DG1_DPLL0 = 0,
163 * @DPLL_ID_DG1_DPLL1: DG1 combo PHY DPLL1
165 DPLL_ID_DG1_DPLL1 = 1,
167 * @DPLL_ID_DG1_DPLL2: DG1 combo PHY DPLL2
169 DPLL_ID_DG1_DPLL2 = 2,
171 * @DPLL_ID_DG1_DPLL3: DG1 combo PHY DPLL3
173 DPLL_ID_DG1_DPLL3 = 3,
176 #define I915_NUM_PLLS 9
178 enum icl_port_dpll_id {
179 ICL_PORT_DPLL_DEFAULT,
180 ICL_PORT_DPLL_MG_PHY,
185 struct intel_dpll_hw_state {
198 * DPLL_CTRL1 has 6 bits for each each this DPLL. We store those in
199 * lower part of ctrl1 and they get shifted into position when writing
200 * the register. This allows us to easily compare the state to share
204 /* HDMI only, 0 when used for DP */
214 u32 ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10, pcsdw12;
217 * ICL uses the following, already defined:
218 * u32 cfgcr0, cfgcr1;
221 u32 mg_clktop2_coreclkctl1;
222 u32 mg_clktop2_hsclkctl;
226 u32 mg_pll_frac_lock;
229 u32 mg_pll_tdc_coldst_bias;
230 u32 mg_pll_bias_mask;
231 u32 mg_pll_tdc_coldst_bias_mask;
235 * struct intel_shared_dpll_state - hold the DPLL atomic state
237 * This structure holds an atomic state for the DPLL, that can represent
238 * either its current state (in struct &intel_shared_dpll) or a desired
239 * future state which would be applied by an atomic mode set (stored in
240 * a struct &intel_atomic_state).
242 * See also intel_reserve_shared_dplls() and intel_release_shared_dplls().
244 struct intel_shared_dpll_state {
246 * @pipe_mask: mask of pipes using this DPLL, active or not
251 * @hw_state: hardware configuration for the DPLL stored in
252 * struct &intel_dpll_hw_state.
254 struct intel_dpll_hw_state hw_state;
258 * struct dpll_info - display PLL platform specific info
262 * @name: DPLL name; used for logging
267 * @funcs: platform specific hooks
269 const struct intel_shared_dpll_funcs *funcs;
272 * @id: unique indentifier for this DPLL; should match the index in the
273 * dev_priv->shared_dplls array
275 enum intel_dpll_id id;
277 #define INTEL_DPLL_ALWAYS_ON (1 << 0)
281 * INTEL_DPLL_ALWAYS_ON
282 * Inform the state checker that the DPLL is kept enabled even if
283 * not in use by any CRTC.
289 * struct intel_shared_dpll - display PLL with tracked state and users
291 struct intel_shared_dpll {
295 * Store the state for the pll, including its hw state
296 * and CRTCs using it.
298 struct intel_shared_dpll_state state;
301 * @active_mask: mask of active pipes (i.e. DPMS on) using this DPLL
306 * @on: is the PLL actually active? Disabled during modeset
311 * @info: platform specific info
313 const struct dpll_info *info;
316 * @wakeref: In some platforms a device-level runtime pm reference may
317 * need to be grabbed to disable DC states while this DPLL is enabled
319 intel_wakeref_t wakeref;
327 /* shared dpll functions */
328 struct intel_shared_dpll *
329 intel_get_shared_dpll_by_id(struct drm_i915_private *dev_priv,
330 enum intel_dpll_id id);
331 void assert_shared_dpll(struct drm_i915_private *dev_priv,
332 struct intel_shared_dpll *pll,
334 #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true)
335 #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false)
336 int intel_compute_shared_dplls(struct intel_atomic_state *state,
337 struct intel_crtc *crtc,
338 struct intel_encoder *encoder);
339 int intel_reserve_shared_dplls(struct intel_atomic_state *state,
340 struct intel_crtc *crtc,
341 struct intel_encoder *encoder);
342 void intel_release_shared_dplls(struct intel_atomic_state *state,
343 struct intel_crtc *crtc);
344 void intel_unreference_shared_dpll_crtc(const struct intel_crtc *crtc,
345 const struct intel_shared_dpll *pll,
346 struct intel_shared_dpll_state *shared_dpll_state);
347 void icl_set_active_port_dpll(struct intel_crtc_state *crtc_state,
348 enum icl_port_dpll_id port_dpll_id);
349 void intel_update_active_dpll(struct intel_atomic_state *state,
350 struct intel_crtc *crtc,
351 struct intel_encoder *encoder);
352 int intel_dpll_get_freq(struct drm_i915_private *i915,
353 const struct intel_shared_dpll *pll,
354 const struct intel_dpll_hw_state *pll_state);
355 bool intel_dpll_get_hw_state(struct drm_i915_private *i915,
356 struct intel_shared_dpll *pll,
357 struct intel_dpll_hw_state *hw_state);
358 void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state);
359 void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state);
360 void intel_shared_dpll_swap_state(struct intel_atomic_state *state);
361 void intel_shared_dpll_init(struct drm_i915_private *dev_priv);
362 void intel_dpll_update_ref_clks(struct drm_i915_private *dev_priv);
363 void intel_dpll_readout_hw_state(struct drm_i915_private *dev_priv);
364 void intel_dpll_sanitize_state(struct drm_i915_private *dev_priv);
366 void intel_dpll_dump_hw_state(struct drm_i915_private *dev_priv,
367 const struct intel_dpll_hw_state *hw_state);
368 enum intel_dpll_id icl_tc_port_to_pll_id(enum tc_port tc_port);
369 bool intel_dpll_is_combophy(enum intel_dpll_id id);
371 void intel_shared_dpll_state_verify(struct intel_crtc *crtc,
372 struct intel_crtc_state *old_crtc_state,
373 struct intel_crtc_state *new_crtc_state);
374 void intel_shared_dpll_verify_disabled(struct drm_i915_private *i915);
376 #endif /* _INTEL_DPLL_MGR_H_ */