drivers/gpu/drm/i915/display/intel_display_power.h

   1 /* SPDX-License-Identifier: MIT */
   2 /*
   3  * Copyright © 2019 Intel Corporation
   4  */
   5
   6 #ifndef __INTEL_DISPLAY_POWER_H__
   7 #define __INTEL_DISPLAY_POWER_H__
   8
   9 #include "intel_wakeref.h"
  10
  11 enum aux_ch;
  12 enum dpio_channel;
  13 enum dpio_phy;
  14 enum i915_drm_suspend_mode;
  15 enum port;
  16 struct drm_i915_private;
  17 struct i915_power_well;
  18 struct intel_encoder;
  19
  20 /*
  21  * Keep the pipe, transcoder, port (DDI_LANES,DDI_IO,AUX) domain instances
  22  * consecutive, so that the pipe,transcoder,port -> power domain macros
  23  * work correctly.
  24  */
  25 enum intel_display_power_domain {
  26         POWER_DOMAIN_DISPLAY_CORE,
  27         POWER_DOMAIN_PIPE_A,
  28         POWER_DOMAIN_PIPE_B,
  29         POWER_DOMAIN_PIPE_C,
  30         POWER_DOMAIN_PIPE_D,
  31         POWER_DOMAIN_PIPE_PANEL_FITTER_A,
  32         POWER_DOMAIN_PIPE_PANEL_FITTER_B,
  33         POWER_DOMAIN_PIPE_PANEL_FITTER_C,
  34         POWER_DOMAIN_PIPE_PANEL_FITTER_D,
  35         POWER_DOMAIN_TRANSCODER_A,
  36         POWER_DOMAIN_TRANSCODER_B,
  37         POWER_DOMAIN_TRANSCODER_C,
  38         POWER_DOMAIN_TRANSCODER_D,
  39         POWER_DOMAIN_TRANSCODER_EDP,
  40         POWER_DOMAIN_TRANSCODER_DSI_A,
  41         POWER_DOMAIN_TRANSCODER_DSI_C,
  42
  43         /* VDSC/joining for eDP/DSI transcoder (ICL) or pipe A (TGL) */
  44         POWER_DOMAIN_TRANSCODER_VDSC_PW2,
  45
  46         POWER_DOMAIN_PORT_DDI_LANES_A,
  47         POWER_DOMAIN_PORT_DDI_LANES_B,
  48         POWER_DOMAIN_PORT_DDI_LANES_C,
  49         POWER_DOMAIN_PORT_DDI_LANES_D,
  50         POWER_DOMAIN_PORT_DDI_LANES_E,
  51         POWER_DOMAIN_PORT_DDI_LANES_F,
  52
  53         POWER_DOMAIN_PORT_DDI_LANES_TC1,
  54         POWER_DOMAIN_PORT_DDI_LANES_TC2,
  55         POWER_DOMAIN_PORT_DDI_LANES_TC3,
  56         POWER_DOMAIN_PORT_DDI_LANES_TC4,
  57         POWER_DOMAIN_PORT_DDI_LANES_TC5,
  58         POWER_DOMAIN_PORT_DDI_LANES_TC6,
  59
  60         POWER_DOMAIN_PORT_DDI_IO_A,
  61         POWER_DOMAIN_PORT_DDI_IO_B,
  62         POWER_DOMAIN_PORT_DDI_IO_C,
  63         POWER_DOMAIN_PORT_DDI_IO_D,
  64         POWER_DOMAIN_PORT_DDI_IO_E,
  65         POWER_DOMAIN_PORT_DDI_IO_F,
  66
  67         POWER_DOMAIN_PORT_DDI_IO_TC1,
  68         POWER_DOMAIN_PORT_DDI_IO_TC2,
  69         POWER_DOMAIN_PORT_DDI_IO_TC3,
  70         POWER_DOMAIN_PORT_DDI_IO_TC4,
  71         POWER_DOMAIN_PORT_DDI_IO_TC5,
  72         POWER_DOMAIN_PORT_DDI_IO_TC6,
  73
  74         POWER_DOMAIN_PORT_DSI,
  75         POWER_DOMAIN_PORT_CRT,
  76         POWER_DOMAIN_PORT_OTHER,
  77         POWER_DOMAIN_VGA,
  78         POWER_DOMAIN_AUDIO_MMIO,
  79         POWER_DOMAIN_AUDIO_PLAYBACK,
  80
  81         POWER_DOMAIN_AUX_IO_A,
  82         POWER_DOMAIN_AUX_IO_B,
  83         POWER_DOMAIN_AUX_IO_C,
  84         POWER_DOMAIN_AUX_IO_D,
  85         POWER_DOMAIN_AUX_IO_E,
  86         POWER_DOMAIN_AUX_IO_F,
  87
  88         POWER_DOMAIN_AUX_A,
  89         POWER_DOMAIN_AUX_B,
  90         POWER_DOMAIN_AUX_C,
  91         POWER_DOMAIN_AUX_D,
  92         POWER_DOMAIN_AUX_E,
  93         POWER_DOMAIN_AUX_F,
  94
  95         POWER_DOMAIN_AUX_USBC1,
  96         POWER_DOMAIN_AUX_USBC2,
  97         POWER_DOMAIN_AUX_USBC3,
  98         POWER_DOMAIN_AUX_USBC4,
  99         POWER_DOMAIN_AUX_USBC5,
 100         POWER_DOMAIN_AUX_USBC6,
 101
 102         POWER_DOMAIN_AUX_TBT1,
 103         POWER_DOMAIN_AUX_TBT2,
 104         POWER_DOMAIN_AUX_TBT3,
 105         POWER_DOMAIN_AUX_TBT4,
 106         POWER_DOMAIN_AUX_TBT5,
 107         POWER_DOMAIN_AUX_TBT6,
 108
 109         POWER_DOMAIN_GMBUS,
 110         POWER_DOMAIN_MODESET,
 111         POWER_DOMAIN_GT_IRQ,
 112         POWER_DOMAIN_DC_OFF,
 113         POWER_DOMAIN_TC_COLD_OFF,
 114         POWER_DOMAIN_INIT,
 115
 116         POWER_DOMAIN_NUM,
 117         POWER_DOMAIN_INVALID = POWER_DOMAIN_NUM,
 118 };
 119
 120 #define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
 121 #define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
 122                 ((pipe) + POWER_DOMAIN_PIPE_PANEL_FITTER_A)
 123 #define POWER_DOMAIN_TRANSCODER(tran) \
 124         ((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
 125          (tran) + POWER_DOMAIN_TRANSCODER_A)
 126
 127 struct intel_power_domain_mask {
 128         DECLARE_BITMAP(bits, POWER_DOMAIN_NUM);
 129 };
 130
 131 struct i915_power_domains {
 132         /*
 133          * Power wells needed for initialization at driver init and suspend
 134          * time are on. They are kept on until after the first modeset.
 135          */
 136         bool initializing;
 137         bool display_core_suspended;
 138         int power_well_count;
 139
 140         u32 dc_state;
 141         u32 target_dc_state;
 142         u32 allowed_dc_mask;
 143
 144         intel_wakeref_t init_wakeref;
 145         intel_wakeref_t disable_wakeref;
 146
 147         struct mutex lock;
 148         int domain_use_count[POWER_DOMAIN_NUM];
 149
 150         struct delayed_work async_put_work;
 151         intel_wakeref_t async_put_wakeref;
 152         struct intel_power_domain_mask async_put_domains[2];
 153
 154         struct i915_power_well *power_wells;
 155 };
 156
 157 struct intel_display_power_domain_set {
 158         struct intel_power_domain_mask mask;
 159 #ifdef CONFIG_DRM_I915_DEBUG_RUNTIME_PM
 160         intel_wakeref_t wakerefs[POWER_DOMAIN_NUM];
 161 #endif
 162 };
 163
 164 #define for_each_power_domain(__domain, __mask)                         \
 165         for ((__domain) = 0; (__domain) < POWER_DOMAIN_NUM; (__domain)++)       \
 166                 for_each_if(test_bit((__domain), (__mask)->bits))
 167
 168 int intel_power_domains_init(struct drm_i915_private *dev_priv);
 169 void intel_power_domains_cleanup(struct drm_i915_private *dev_priv);
 170 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume);
 171 void intel_power_domains_driver_remove(struct drm_i915_private *dev_priv);
 172 void intel_power_domains_enable(struct drm_i915_private *dev_priv);
 173 void intel_power_domains_disable(struct drm_i915_private *dev_priv);
 174 void intel_power_domains_suspend(struct drm_i915_private *dev_priv, bool s2idle);
 175 void intel_power_domains_resume(struct drm_i915_private *dev_priv);
 176 void intel_power_domains_sanitize_state(struct drm_i915_private *dev_priv);
 177
 178 void intel_display_power_suspend_late(struct drm_i915_private *i915);
 179 void intel_display_power_resume_early(struct drm_i915_private *i915);
 180 void intel_display_power_suspend(struct drm_i915_private *i915);
 181 void intel_display_power_resume(struct drm_i915_private *i915);
 182 void intel_display_power_set_target_dc_state(struct drm_i915_private *dev_priv,
 183                                              u32 state);
 184
 185 const char *
 186 intel_display_power_domain_str(enum intel_display_power_domain domain);
 187
 188 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
 189                                     enum intel_display_power_domain domain);
 190 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
 191                                       enum intel_display_power_domain domain);
 192 intel_wakeref_t intel_display_power_get(struct drm_i915_private *dev_priv,
 193                                         enum intel_display_power_domain domain);
 194 intel_wakeref_t
 195 intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv,
 196                                    enum intel_display_power_domain domain);
 197 void __intel_display_power_put_async(struct drm_i915_private *i915,
 198                                      enum intel_display_power_domain domain,
 199                                      intel_wakeref_t wakeref);
 200 void intel_display_power_flush_work(struct drm_i915_private *i915);
 201 #if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
 202 void intel_display_power_put(struct drm_i915_private *dev_priv,
 203                              enum intel_display_power_domain domain,
 204                              intel_wakeref_t wakeref);
 205 static inline void
 206 intel_display_power_put_async(struct drm_i915_private *i915,
 207                               enum intel_display_power_domain domain,
 208                               intel_wakeref_t wakeref)
 209 {
 210         __intel_display_power_put_async(i915, domain, wakeref);
 211 }
 212 #else
 213 void intel_display_power_put_unchecked(struct drm_i915_private *dev_priv,
 214                                        enum intel_display_power_domain domain);
 215
 216 static inline void
 217 intel_display_power_put(struct drm_i915_private *i915,
 218                         enum intel_display_power_domain domain,
 219                         intel_wakeref_t wakeref)
 220 {
 221         intel_display_power_put_unchecked(i915, domain);
 222 }
 223
 224 static inline void
 225 intel_display_power_put_async(struct drm_i915_private *i915,
 226                               enum intel_display_power_domain domain,
 227                               intel_wakeref_t wakeref)
 228 {
 229         __intel_display_power_put_async(i915, domain, -1);
 230 }
 231 #endif
 232
 233 void
 234 intel_display_power_get_in_set(struct drm_i915_private *i915,
 235                                struct intel_display_power_domain_set *power_domain_set,
 236                                enum intel_display_power_domain domain);
 237
 238 bool
 239 intel_display_power_get_in_set_if_enabled(struct drm_i915_private *i915,
 240                                           struct intel_display_power_domain_set *power_domain_set,
 241                                           enum intel_display_power_domain domain);
 242
 243 void
 244 intel_display_power_put_mask_in_set(struct drm_i915_private *i915,
 245                                     struct intel_display_power_domain_set *power_domain_set,
 246                                     struct intel_power_domain_mask *mask);
 247
 248 static inline void
 249 intel_display_power_put_all_in_set(struct drm_i915_private *i915,
 250                                    struct intel_display_power_domain_set *power_domain_set)
 251 {
 252         intel_display_power_put_mask_in_set(i915, power_domain_set, &power_domain_set->mask);
 253 }
 254
 255 void intel_display_power_debug(struct drm_i915_private *i915, struct seq_file *m);
 256
 257 enum intel_display_power_domain
 258 intel_display_power_ddi_lanes_domain(struct drm_i915_private *i915, enum port port);
 259 enum intel_display_power_domain
 260 intel_display_power_ddi_io_domain(struct drm_i915_private *i915, enum port port);
 261 enum intel_display_power_domain
 262 intel_display_power_aux_io_domain(struct drm_i915_private *i915, enum aux_ch aux_ch);
 263 enum intel_display_power_domain
 264 intel_display_power_legacy_aux_domain(struct drm_i915_private *i915, enum aux_ch aux_ch);
 265 enum intel_display_power_domain
 266 intel_display_power_tbt_aux_domain(struct drm_i915_private *i915, enum aux_ch aux_ch);
 267
 268 /*
 269  * FIXME: We should probably switch this to a 0-based scheme to be consistent
 270  * with how we now name/number DBUF_CTL instances.
 271  */
 272 enum dbuf_slice {
 273         DBUF_S1,
 274         DBUF_S2,
 275         DBUF_S3,
 276         DBUF_S4,
 277         I915_MAX_DBUF_SLICES
 278 };
 279
 280 void gen9_dbuf_slices_update(struct drm_i915_private *dev_priv,
 281                              u8 req_slices);
 282
 283 #define with_intel_display_power(i915, domain, wf) \
 284         for ((wf) = intel_display_power_get((i915), (domain)); (wf); \
 285              intel_display_power_put_async((i915), (domain), (wf)), (wf) = 0)
 286
 287 #define with_intel_display_power_if_enabled(i915, domain, wf) \
 288         for ((wf) = intel_display_power_get_if_enabled((i915), (domain)); (wf); \
 289              intel_display_power_put_async((i915), (domain), (wf)), (wf) = 0)
 290
 291 #endif /* __INTEL_DISPLAY_POWER_H__ */