drivers/gpu/drm/i915/display/intel_display_driver.c

   1 // SPDX-License-Identifier: MIT
   2 /*
   3  * Copyright © 2022-2023 Intel Corporation
   4  *
   5  * High level display driver entry points. This is a layer between top level
   6  * driver code and low level display functionality; no low level display code or
   7  * details here.
   8  */
   9
  10 #include <linux/vga_switcheroo.h>
  11 #include <acpi/video.h>
  12 #include <drm/display/drm_dp_mst_helper.h>
  13 #include <drm/drm_atomic_helper.h>
  14 #include <drm/drm_mode_config.h>
  15 #include <drm/drm_privacy_screen_consumer.h>
  16 #include <drm/drm_probe_helper.h>
  17 #include <drm/drm_vblank.h>
  18
  19 #include "i915_drv.h"
  20 #include "i9xx_wm.h"
  21 #include "intel_acpi.h"
  22 #include "intel_atomic.h"
  23 #include "intel_audio.h"
  24 #include "intel_bios.h"
  25 #include "intel_bw.h"
  26 #include "intel_cdclk.h"
  27 #include "intel_color.h"
  28 #include "intel_crtc.h"
  29 #include "intel_display_debugfs.h"
  30 #include "intel_display_driver.h"
  31 #include "intel_display_power.h"
  32 #include "intel_display_types.h"
  33 #include "intel_dkl_phy.h"
  34 #include "intel_dmc.h"
  35 #include "intel_dp.h"
  36 #include "intel_dpll.h"
  37 #include "intel_dpll_mgr.h"
  38 #include "intel_fb.h"
  39 #include "intel_fbc.h"
  40 #include "intel_fbdev.h"
  41 #include "intel_fdi.h"
  42 #include "intel_gmbus.h"
  43 #include "intel_hdcp.h"
  44 #include "intel_hotplug.h"
  45 #include "intel_hti.h"
  46 #include "intel_modeset_setup.h"
  47 #include "intel_opregion.h"
  48 #include "intel_overlay.h"
  49 #include "intel_plane_initial.h"
  50 #include "intel_pps.h"
  51 #include "intel_quirks.h"
  52 #include "intel_vga.h"
  53 #include "intel_wm.h"
  54 #include "skl_watermark.h"
  55
  56 bool intel_display_driver_probe_defer(struct pci_dev *pdev)
  57 {
  58         struct drm_privacy_screen *privacy_screen;
  59
  60         /*
  61          * apple-gmux is needed on dual GPU MacBook Pro
  62          * to probe the panel if we're the inactive GPU.
  63          */
  64         if (vga_switcheroo_client_probe_defer(pdev))
  65                 return true;
  66
  67         /* If the LCD panel has a privacy-screen, wait for it */
  68         privacy_screen = drm_privacy_screen_get(&pdev->dev, NULL);
  69         if (IS_ERR(privacy_screen) && PTR_ERR(privacy_screen) == -EPROBE_DEFER)
  70                 return true;
  71
  72         drm_privacy_screen_put(privacy_screen);
  73
  74         return false;
  75 }
  76
  77 void intel_display_driver_init_hw(struct drm_i915_private *i915)
  78 {
  79         struct intel_cdclk_state *cdclk_state;
  80
  81         if (!HAS_DISPLAY(i915))
  82                 return;
  83
  84         cdclk_state = to_intel_cdclk_state(i915->display.cdclk.obj.state);
  85
  86         intel_update_cdclk(i915);
  87         intel_cdclk_dump_config(i915, &i915->display.cdclk.hw, "Current CDCLK");
  88         cdclk_state->logical = cdclk_state->actual = i915->display.cdclk.hw;
  89 }
  90
  91 static const struct drm_mode_config_funcs intel_mode_funcs = {
  92         .fb_create = intel_user_framebuffer_create,
  93         .get_format_info = intel_fb_get_format_info,
  94         .output_poll_changed = intel_fbdev_output_poll_changed,
  95         .mode_valid = intel_mode_valid,
  96         .atomic_check = intel_atomic_check,
  97         .atomic_commit = intel_atomic_commit,
  98         .atomic_state_alloc = intel_atomic_state_alloc,
  99         .atomic_state_clear = intel_atomic_state_clear,
 100         .atomic_state_free = intel_atomic_state_free,
 101 };
 102
 103 static const struct drm_mode_config_helper_funcs intel_mode_config_funcs = {
 104         .atomic_commit_setup = drm_dp_mst_atomic_setup_commit,
 105 };
 106
 107 static void intel_mode_config_init(struct drm_i915_private *i915)
 108 {
 109         struct drm_mode_config *mode_config = &i915->drm.mode_config;
 110
 111         drm_mode_config_init(&i915->drm);
 112         INIT_LIST_HEAD(&i915->display.global.obj_list);
 113
 114         mode_config->min_width = 0;
 115         mode_config->min_height = 0;
 116
 117         mode_config->preferred_depth = 24;
 118         mode_config->prefer_shadow = 1;
 119
 120         mode_config->funcs = &intel_mode_funcs;
 121         mode_config->helper_private = &intel_mode_config_funcs;
 122
 123         mode_config->async_page_flip = HAS_ASYNC_FLIPS(i915);
 124
 125         /*
 126          * Maximum framebuffer dimensions, chosen to match
 127          * the maximum render engine surface size on gen4+.
 128          */
 129         if (DISPLAY_VER(i915) >= 7) {
 130                 mode_config->max_width = 16384;
 131                 mode_config->max_height = 16384;
 132         } else if (DISPLAY_VER(i915) >= 4) {
 133                 mode_config->max_width = 8192;
 134                 mode_config->max_height = 8192;
 135         } else if (DISPLAY_VER(i915) == 3) {
 136                 mode_config->max_width = 4096;
 137                 mode_config->max_height = 4096;
 138         } else {
 139                 mode_config->max_width = 2048;
 140                 mode_config->max_height = 2048;
 141         }
 142
 143         if (IS_I845G(i915) || IS_I865G(i915)) {
 144                 mode_config->cursor_width = IS_I845G(i915) ? 64 : 512;
 145                 mode_config->cursor_height = 1023;
 146         } else if (IS_I830(i915) || IS_I85X(i915) ||
 147                    IS_I915G(i915) || IS_I915GM(i915)) {
 148                 mode_config->cursor_width = 64;
 149                 mode_config->cursor_height = 64;
 150         } else {
 151                 mode_config->cursor_width = 256;
 152                 mode_config->cursor_height = 256;
 153         }
 154 }
 155
 156 static void intel_mode_config_cleanup(struct drm_i915_private *i915)
 157 {
 158         intel_atomic_global_obj_cleanup(i915);
 159         drm_mode_config_cleanup(&i915->drm);
 160 }
 161
 162 static void intel_plane_possible_crtcs_init(struct drm_i915_private *dev_priv)
 163 {
 164         struct intel_plane *plane;
 165
 166         for_each_intel_plane(&dev_priv->drm, plane) {
 167                 struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv,
 168                                                               plane->pipe);
 169
 170                 plane->base.possible_crtcs = drm_crtc_mask(&crtc->base);
 171         }
 172 }
 173
 174 void intel_display_driver_early_probe(struct drm_i915_private *i915)
 175 {
 176         if (!HAS_DISPLAY(i915))
 177                 return;
 178
 179         intel_dkl_phy_init(i915);
 180         intel_color_init_hooks(i915);
 181         intel_init_cdclk_hooks(i915);
 182         intel_audio_hooks_init(i915);
 183         intel_dpll_init_clock_hook(i915);
 184         intel_init_display_hooks(i915);
 185         intel_fdi_init_hook(i915);
 186 }
 187
 188 /* part #1: call before irq install */
 189 int intel_display_driver_probe_noirq(struct drm_i915_private *i915)
 190 {
 191         int ret;
 192
 193         if (i915_inject_probe_failure(i915))
 194                 return -ENODEV;
 195
 196         if (HAS_DISPLAY(i915)) {
 197                 ret = drm_vblank_init(&i915->drm,
 198                                       INTEL_NUM_PIPES(i915));
 199                 if (ret)
 200                         return ret;
 201         }
 202
 203         intel_bios_init(i915);
 204
 205         ret = intel_vga_register(i915);
 206         if (ret)
 207                 goto cleanup_bios;
 208
 209         /* FIXME: completely on the wrong abstraction layer */
 210         ret = intel_power_domains_init(i915);
 211         if (ret < 0)
 212                 goto cleanup_vga;
 213
 214         intel_power_domains_init_hw(i915, false);
 215
 216         if (!HAS_DISPLAY(i915))
 217                 return 0;
 218
 219         intel_dmc_init(i915);
 220
 221         i915->display.wq.modeset = alloc_ordered_workqueue("i915_modeset", 0);
 222         i915->display.wq.flip = alloc_workqueue("i915_flip", WQ_HIGHPRI |
 223                                                 WQ_UNBOUND, WQ_UNBOUND_MAX_ACTIVE);
 224
 225         intel_mode_config_init(i915);
 226
 227         ret = intel_cdclk_init(i915);
 228         if (ret)
 229                 goto cleanup_vga_client_pw_domain_dmc;
 230
 231         ret = intel_color_init(i915);
 232         if (ret)
 233                 goto cleanup_vga_client_pw_domain_dmc;
 234
 235         ret = intel_dbuf_init(i915);
 236         if (ret)
 237                 goto cleanup_vga_client_pw_domain_dmc;
 238
 239         ret = intel_bw_init(i915);
 240         if (ret)
 241                 goto cleanup_vga_client_pw_domain_dmc;
 242
 243         init_llist_head(&i915->display.atomic_helper.free_list);
 244         INIT_WORK(&i915->display.atomic_helper.free_work,
 245                   intel_atomic_helper_free_state_worker);
 246
 247         intel_init_quirks(i915);
 248
 249         intel_fbc_init(i915);
 250
 251         return 0;
 252
 253 cleanup_vga_client_pw_domain_dmc:
 254         intel_dmc_fini(i915);
 255         intel_power_domains_driver_remove(i915);
 256 cleanup_vga:
 257         intel_vga_unregister(i915);
 258 cleanup_bios:
 259         intel_bios_driver_remove(i915);
 260
 261         return ret;
 262 }
 263
 264 /* part #2: call after irq install, but before gem init */
 265 int intel_display_driver_probe_nogem(struct drm_i915_private *i915)
 266 {
 267         struct drm_device *dev = &i915->drm;
 268         enum pipe pipe;
 269         struct intel_crtc *crtc;
 270         int ret;
 271
 272         if (!HAS_DISPLAY(i915))
 273                 return 0;
 274
 275         intel_wm_init(i915);
 276
 277         intel_panel_sanitize_ssc(i915);
 278
 279         intel_pps_setup(i915);
 280
 281         intel_gmbus_setup(i915);
 282
 283         drm_dbg_kms(&i915->drm, "%d display pipe%s available.\n",
 284                     INTEL_NUM_PIPES(i915),
 285                     INTEL_NUM_PIPES(i915) > 1 ? "s" : "");
 286
 287         for_each_pipe(i915, pipe) {
 288                 ret = intel_crtc_init(i915, pipe);
 289                 if (ret) {
 290                         intel_mode_config_cleanup(i915);
 291                         return ret;
 292                 }
 293         }
 294
 295         intel_plane_possible_crtcs_init(i915);
 296         intel_shared_dpll_init(i915);
 297         intel_fdi_pll_freq_update(i915);
 298
 299         intel_update_czclk(i915);
 300         intel_display_driver_init_hw(i915);
 301         intel_dpll_update_ref_clks(i915);
 302
 303         intel_hdcp_component_init(i915);
 304
 305         if (i915->display.cdclk.max_cdclk_freq == 0)
 306                 intel_update_max_cdclk(i915);
 307
 308         intel_hti_init(i915);
 309
 310         /* Just disable it once at startup */
 311         intel_vga_disable(i915);
 312         intel_setup_outputs(i915);
 313
 314         drm_modeset_lock_all(dev);
 315         intel_modeset_setup_hw_state(i915, dev->mode_config.acquire_ctx);
 316         intel_acpi_assign_connector_fwnodes(i915);
 317         drm_modeset_unlock_all(dev);
 318
 319         for_each_intel_crtc(dev, crtc) {
 320                 if (!to_intel_crtc_state(crtc->base.state)->uapi.active)
 321                         continue;
 322                 intel_crtc_initial_plane_config(crtc);
 323         }
 324
 325         /*
 326          * Make sure hardware watermarks really match the state we read out.
 327          * Note that we need to do this after reconstructing the BIOS fb's
 328          * since the watermark calculation done here will use pstate->fb.
 329          */
 330         if (!HAS_GMCH(i915))
 331                 ilk_wm_sanitize(i915);
 332
 333         return 0;
 334 }
 335
 336 /* part #3: call after gem init */
 337 int intel_display_driver_probe(struct drm_i915_private *i915)
 338 {
 339         int ret;
 340
 341         if (!HAS_DISPLAY(i915))
 342                 return 0;
 343
 344         /*
 345          * Force all active planes to recompute their states. So that on
 346          * mode_setcrtc after probe, all the intel_plane_state variables
 347          * are already calculated and there is no assert_plane warnings
 348          * during bootup.
 349          */
 350         ret = intel_initial_commit(&i915->drm);
 351         if (ret)
 352                 drm_dbg_kms(&i915->drm, "Initial modeset failed, %d\n", ret);
 353
 354         intel_overlay_setup(i915);
 355
 356         ret = intel_fbdev_init(&i915->drm);
 357         if (ret)
 358                 return ret;
 359
 360         /* Only enable hotplug handling once the fbdev is fully set up. */
 361         intel_hpd_init(i915);
 362         intel_hpd_poll_disable(i915);
 363
 364         skl_watermark_ipc_init(i915);
 365
 366         return 0;
 367 }
 368
 369 void intel_display_driver_register(struct drm_i915_private *i915)
 370 {
 371         if (!HAS_DISPLAY(i915))
 372                 return;
 373
 374         /* Must be done after probing outputs */
 375         intel_opregion_register(i915);
 376         intel_acpi_video_register(i915);
 377
 378         intel_audio_init(i915);
 379
 380         intel_display_debugfs_register(i915);
 381
 382         /*
 383          * Some ports require correctly set-up hpd registers for
 384          * detection to work properly (leading to ghost connected
 385          * connector status), e.g. VGA on gm45.  Hence we can only set
 386          * up the initial fbdev config after hpd irqs are fully
 387          * enabled. We do it last so that the async config cannot run
 388          * before the connectors are registered.
 389          */
 390         intel_fbdev_initial_config_async(i915);
 391
 392         /*
 393          * We need to coordinate the hotplugs with the asynchronous
 394          * fbdev configuration, for which we use the
 395          * fbdev->async_cookie.
 396          */
 397         drm_kms_helper_poll_init(&i915->drm);
 398 }
 399
 400 /* part #1: call before irq uninstall */
 401 void intel_display_driver_remove(struct drm_i915_private *i915)
 402 {
 403         if (!HAS_DISPLAY(i915))
 404                 return;
 405
 406         flush_workqueue(i915->display.wq.flip);
 407         flush_workqueue(i915->display.wq.modeset);
 408
 409         flush_work(&i915->display.atomic_helper.free_work);
 410         drm_WARN_ON(&i915->drm, !llist_empty(&i915->display.atomic_helper.free_list));
 411
 412         /*
 413          * MST topology needs to be suspended so we don't have any calls to
 414          * fbdev after it's finalized. MST will be destroyed later as part of
 415          * drm_mode_config_cleanup()
 416          */
 417         intel_dp_mst_suspend(i915);
 418 }
 419
 420 /* part #2: call after irq uninstall */
 421 void intel_display_driver_remove_noirq(struct drm_i915_private *i915)
 422 {
 423         if (!HAS_DISPLAY(i915))
 424                 return;
 425
 426         /*
 427          * Due to the hpd irq storm handling the hotplug work can re-arm the
 428          * poll handlers. Hence disable polling after hpd handling is shut down.
 429          */
 430         intel_hpd_poll_fini(i915);
 431
 432         /* poll work can call into fbdev, hence clean that up afterwards */
 433         intel_fbdev_fini(i915);
 434
 435         intel_unregister_dsm_handler();
 436
 437         /* flush any delayed tasks or pending work */
 438         flush_scheduled_work();
 439
 440         intel_hdcp_component_fini(i915);
 441
 442         intel_mode_config_cleanup(i915);
 443
 444         intel_overlay_cleanup(i915);
 445
 446         intel_gmbus_teardown(i915);
 447
 448         destroy_workqueue(i915->display.wq.flip);
 449         destroy_workqueue(i915->display.wq.modeset);
 450
 451         intel_fbc_cleanup(i915);
 452 }
 453
 454 /* part #3: call after gem init */
 455 void intel_display_driver_remove_nogem(struct drm_i915_private *i915)
 456 {
 457         intel_dmc_fini(i915);
 458
 459         intel_power_domains_driver_remove(i915);
 460
 461         intel_vga_unregister(i915);
 462
 463         intel_bios_driver_remove(i915);
 464 }
 465
 466 void intel_display_driver_unregister(struct drm_i915_private *i915)
 467 {
 468         if (!HAS_DISPLAY(i915))
 469                 return;
 470
 471         intel_fbdev_unregister(i915);
 472         intel_audio_deinit(i915);
 473
 474         /*
 475          * After flushing the fbdev (incl. a late async config which
 476          * will have delayed queuing of a hotplug event), then flush
 477          * the hotplug events.
 478          */
 479         drm_kms_helper_poll_fini(&i915->drm);
 480         drm_atomic_helper_shutdown(&i915->drm);
 481
 482         acpi_video_unregister();
 483         intel_opregion_unregister(i915);
 484 }
 485
 486 /*
 487  * turn all crtc's off, but do not adjust state
 488  * This has to be paired with a call to intel_modeset_setup_hw_state.
 489  */
 490 int intel_display_driver_suspend(struct drm_i915_private *i915)
 491 {
 492         struct drm_atomic_state *state;
 493         int ret;
 494
 495         if (!HAS_DISPLAY(i915))
 496                 return 0;
 497
 498         state = drm_atomic_helper_suspend(&i915->drm);
 499         ret = PTR_ERR_OR_ZERO(state);
 500         if (ret)
 501                 drm_err(&i915->drm, "Suspending crtc's failed with %i\n",
 502                         ret);
 503         else
 504                 i915->display.restore.modeset_state = state;
 505         return ret;
 506 }
 507
 508 int
 509 __intel_display_driver_resume(struct drm_i915_private *i915,
 510                               struct drm_atomic_state *state,
 511                               struct drm_modeset_acquire_ctx *ctx)
 512 {
 513         struct drm_crtc_state *crtc_state;
 514         struct drm_crtc *crtc;
 515         int ret, i;
 516
 517         intel_modeset_setup_hw_state(i915, ctx);
 518         intel_vga_redisable(i915);
 519
 520         if (!state)
 521                 return 0;
 522
 523         /*
 524          * We've duplicated the state, pointers to the old state are invalid.
 525          *
 526          * Don't attempt to use the old state until we commit the duplicated state.
 527          */
 528         for_each_new_crtc_in_state(state, crtc, crtc_state, i) {
 529                 /*
 530                  * Force recalculation even if we restore
 531                  * current state. With fast modeset this may not result
 532                  * in a modeset when the state is compatible.
 533                  */
 534                 crtc_state->mode_changed = true;
 535         }
 536
 537         /* ignore any reset values/BIOS leftovers in the WM registers */
 538         if (!HAS_GMCH(i915))
 539                 to_intel_atomic_state(state)->skip_intermediate_wm = true;
 540
 541         ret = drm_atomic_helper_commit_duplicated_state(state, ctx);
 542
 543         drm_WARN_ON(&i915->drm, ret == -EDEADLK);
 544
 545         return ret;
 546 }
 547
 548 void intel_display_driver_resume(struct drm_i915_private *i915)
 549 {
 550         struct drm_atomic_state *state = i915->display.restore.modeset_state;
 551         struct drm_modeset_acquire_ctx ctx;
 552         int ret;
 553
 554         if (!HAS_DISPLAY(i915))
 555                 return;
 556
 557         i915->display.restore.modeset_state = NULL;
 558         if (state)
 559                 state->acquire_ctx = &ctx;
 560
 561         drm_modeset_acquire_init(&ctx, 0);
 562
 563         while (1) {
 564                 ret = drm_modeset_lock_all_ctx(&i915->drm, &ctx);
 565                 if (ret != -EDEADLK)
 566                         break;
 567
 568                 drm_modeset_backoff(&ctx);
 569         }
 570
 571         if (!ret)
 572                 ret = __intel_display_driver_resume(i915, state, &ctx);
 573
 574         skl_watermark_ipc_update(i915);
 575         drm_modeset_drop_locks(&ctx);
 576         drm_modeset_acquire_fini(&ctx);
 577
 578         if (ret)
 579                 drm_err(&i915->drm,
 580                         "Restoring old state failed with %i\n", ret);
 581         if (state)
 582                 drm_atomic_state_put(state);
 583 }