drivers/gpu/drm/i915/display/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <[email protected]>
  25  */
  26
  27 #include <linux/dma-resv.h>
  28 #include <linux/i2c.h>
  29 #include <linux/input.h>
  30 #include <linux/kernel.h>
  31 #include <linux/module.h>
  32 #include <linux/slab.h>
  33 #include <linux/string_helpers.h>
  34
  35 #include <drm/display/drm_dp_helper.h>
  36 #include <drm/drm_atomic.h>
  37 #include <drm/drm_atomic_helper.h>
  38 #include <drm/drm_atomic_uapi.h>
  39 #include <drm/drm_damage_helper.h>
  40 #include <drm/drm_edid.h>
  41 #include <drm/drm_fourcc.h>
  42 #include <drm/drm_probe_helper.h>
  43 #include <drm/drm_rect.h>
  44
  45 #include "gem/i915_gem_lmem.h"
  46 #include "gem/i915_gem_object.h"
  47
  48 #include "g4x_dp.h"
  49 #include "g4x_hdmi.h"
  50 #include "hsw_ips.h"
  51 #include "i915_drv.h"
  52 #include "i915_reg.h"
  53 #include "i915_utils.h"
  54 #include "i9xx_plane.h"
  55 #include "i9xx_wm.h"
  56 #include "icl_dsi.h"
  57 #include "intel_atomic.h"
  58 #include "intel_atomic_plane.h"
  59 #include "intel_audio.h"
  60 #include "intel_bw.h"
  61 #include "intel_cdclk.h"
  62 #include "intel_clock_gating.h"
  63 #include "intel_color.h"
  64 #include "intel_crt.h"
  65 #include "intel_crtc.h"
  66 #include "intel_crtc_state_dump.h"
  67 #include "intel_ddi.h"
  68 #include "intel_de.h"
  69 #include "intel_display_driver.h"
  70 #include "intel_display_power.h"
  71 #include "intel_display_types.h"
  72 #include "intel_dmc.h"
  73 #include "intel_dp.h"
  74 #include "intel_dp_link_training.h"
  75 #include "intel_dp_mst.h"
  76 #include "intel_dpio_phy.h"
  77 #include "intel_dpll.h"
  78 #include "intel_dpll_mgr.h"
  79 #include "intel_dpt.h"
  80 #include "intel_drrs.h"
  81 #include "intel_dsi.h"
  82 #include "intel_dvo.h"
  83 #include "intel_fb.h"
  84 #include "intel_fbc.h"
  85 #include "intel_fbdev.h"
  86 #include "intel_fdi.h"
  87 #include "intel_fifo_underrun.h"
  88 #include "intel_frontbuffer.h"
  89 #include "intel_hdmi.h"
  90 #include "intel_hotplug.h"
  91 #include "intel_lvds.h"
  92 #include "intel_lvds_regs.h"
  93 #include "intel_modeset_setup.h"
  94 #include "intel_modeset_verify.h"
  95 #include "intel_overlay.h"
  96 #include "intel_panel.h"
  97 #include "intel_pch_display.h"
  98 #include "intel_pch_refclk.h"
  99 #include "intel_pcode.h"
 100 #include "intel_pipe_crc.h"
 101 #include "intel_plane_initial.h"
 102 #include "intel_pps.h"
 103 #include "intel_psr.h"
 104 #include "intel_sdvo.h"
 105 #include "intel_snps_phy.h"
 106 #include "intel_tc.h"
 107 #include "intel_tv.h"
 108 #include "intel_vblank.h"
 109 #include "intel_vdsc.h"
 110 #include "intel_vdsc_regs.h"
 111 #include "intel_vga.h"
 112 #include "intel_vrr.h"
 113 #include "intel_wm.h"
 114 #include "skl_scaler.h"
 115 #include "skl_universal_plane.h"
 116 #include "skl_watermark.h"
 117 #include "vlv_dsi.h"
 118 #include "vlv_dsi_pll.h"
 119 #include "vlv_dsi_regs.h"
 120 #include "vlv_sideband.h"
 121
 122 static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state);
 123 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state);
 124 static void hsw_set_transconf(const struct intel_crtc_state *crtc_state);
 125 static void bdw_set_pipe_misc(const struct intel_crtc_state *crtc_state);
 126
 127 /* returns HPLL frequency in kHz */
 128 int vlv_get_hpll_vco(struct drm_i915_private *dev_priv)
 129 {
 130         int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
 131
 132         /* Obtain SKU information */
 133         hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
 134                 CCK_FUSE_HPLL_FREQ_MASK;
 135
 136         return vco_freq[hpll_freq] * 1000;
 137 }
 138
 139 int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
 140                       const char *name, u32 reg, int ref_freq)
 141 {
 142         u32 val;
 143         int divider;
 144
 145         val = vlv_cck_read(dev_priv, reg);
 146         divider = val & CCK_FREQUENCY_VALUES;
 147
 148         drm_WARN(&dev_priv->drm, (val & CCK_FREQUENCY_STATUS) !=
 149                  (divider << CCK_FREQUENCY_STATUS_SHIFT),
 150                  "%s change in progress\n", name);
 151
 152         return DIV_ROUND_CLOSEST(ref_freq << 1, divider + 1);
 153 }
 154
 155 int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
 156                            const char *name, u32 reg)
 157 {
 158         int hpll;
 159
 160         vlv_cck_get(dev_priv);
 161
 162         if (dev_priv->hpll_freq == 0)
 163                 dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv);
 164
 165         hpll = vlv_get_cck_clock(dev_priv, name, reg, dev_priv->hpll_freq);
 166
 167         vlv_cck_put(dev_priv);
 168
 169         return hpll;
 170 }
 171
 172 void intel_update_czclk(struct drm_i915_private *dev_priv)
 173 {
 174         if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)))
 175                 return;
 176
 177         dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk",
 178                                                       CCK_CZ_CLOCK_CONTROL);
 179
 180         drm_dbg(&dev_priv->drm, "CZ clock rate: %d kHz\n",
 181                 dev_priv->czclk_freq);
 182 }
 183
 184 static bool is_hdr_mode(const struct intel_crtc_state *crtc_state)
 185 {
 186         return (crtc_state->active_planes &
 187                 ~(icl_hdr_plane_mask() | BIT(PLANE_CURSOR))) == 0;
 188 }
 189
 190 /* WA Display #0827: Gen9:all */
 191 static void
 192 skl_wa_827(struct drm_i915_private *dev_priv, enum pipe pipe, bool enable)
 193 {
 194         if (enable)
 195                 intel_de_rmw(dev_priv, CLKGATE_DIS_PSL(pipe),
 196                              0, DUPS1_GATING_DIS | DUPS2_GATING_DIS);
 197         else
 198                 intel_de_rmw(dev_priv, CLKGATE_DIS_PSL(pipe),
 199                              DUPS1_GATING_DIS | DUPS2_GATING_DIS, 0);
 200 }
 201
 202 /* Wa_2006604312:icl,ehl */
 203 static void
 204 icl_wa_scalerclkgating(struct drm_i915_private *dev_priv, enum pipe pipe,
 205                        bool enable)
 206 {
 207         if (enable)
 208                 intel_de_rmw(dev_priv, CLKGATE_DIS_PSL(pipe), 0, DPFR_GATING_DIS);
 209         else
 210                 intel_de_rmw(dev_priv, CLKGATE_DIS_PSL(pipe), DPFR_GATING_DIS, 0);
 211 }
 212
 213 /* Wa_1604331009:icl,jsl,ehl */
 214 static void
 215 icl_wa_cursorclkgating(struct drm_i915_private *dev_priv, enum pipe pipe,
 216                        bool enable)
 217 {
 218         intel_de_rmw(dev_priv, CLKGATE_DIS_PSL(pipe), CURSOR_GATING_DIS,
 219                      enable ? CURSOR_GATING_DIS : 0);
 220 }
 221
 222 static bool
 223 is_trans_port_sync_slave(const struct intel_crtc_state *crtc_state)
 224 {
 225         return crtc_state->master_transcoder != INVALID_TRANSCODER;
 226 }
 227
 228 bool
 229 is_trans_port_sync_master(const struct intel_crtc_state *crtc_state)
 230 {
 231         return crtc_state->sync_mode_slaves_mask != 0;
 232 }
 233
 234 bool
 235 is_trans_port_sync_mode(const struct intel_crtc_state *crtc_state)
 236 {
 237         return is_trans_port_sync_master(crtc_state) ||
 238                 is_trans_port_sync_slave(crtc_state);
 239 }
 240
 241 static enum pipe bigjoiner_master_pipe(const struct intel_crtc_state *crtc_state)
 242 {
 243         return ffs(crtc_state->bigjoiner_pipes) - 1;
 244 }
 245
 246 u8 intel_crtc_bigjoiner_slave_pipes(const struct intel_crtc_state *crtc_state)
 247 {
 248         if (crtc_state->bigjoiner_pipes)
 249                 return crtc_state->bigjoiner_pipes & ~BIT(bigjoiner_master_pipe(crtc_state));
 250         else
 251                 return 0;
 252 }
 253
 254 bool intel_crtc_is_bigjoiner_slave(const struct intel_crtc_state *crtc_state)
 255 {
 256         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 257
 258         return crtc_state->bigjoiner_pipes &&
 259                 crtc->pipe != bigjoiner_master_pipe(crtc_state);
 260 }
 261
 262 bool intel_crtc_is_bigjoiner_master(const struct intel_crtc_state *crtc_state)
 263 {
 264         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 265
 266         return crtc_state->bigjoiner_pipes &&
 267                 crtc->pipe == bigjoiner_master_pipe(crtc_state);
 268 }
 269
 270 static int intel_bigjoiner_num_pipes(const struct intel_crtc_state *crtc_state)
 271 {
 272         return hweight8(crtc_state->bigjoiner_pipes);
 273 }
 274
 275 struct intel_crtc *intel_master_crtc(const struct intel_crtc_state *crtc_state)
 276 {
 277         struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
 278
 279         if (intel_crtc_is_bigjoiner_slave(crtc_state))
 280                 return intel_crtc_for_pipe(i915, bigjoiner_master_pipe(crtc_state));
 281         else
 282                 return to_intel_crtc(crtc_state->uapi.crtc);
 283 }
 284
 285 static void
 286 intel_wait_for_pipe_off(const struct intel_crtc_state *old_crtc_state)
 287 {
 288         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
 289         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 290
 291         if (DISPLAY_VER(dev_priv) >= 4) {
 292                 enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
 293
 294                 /* Wait for the Pipe State to go off */
 295                 if (intel_de_wait_for_clear(dev_priv, TRANSCONF(cpu_transcoder),
 296                                             TRANSCONF_STATE_ENABLE, 100))
 297                         drm_WARN(&dev_priv->drm, 1, "pipe_off wait timed out\n");
 298         } else {
 299                 intel_wait_for_pipe_scanline_stopped(crtc);
 300         }
 301 }
 302
 303 void assert_transcoder(struct drm_i915_private *dev_priv,
 304                        enum transcoder cpu_transcoder, bool state)
 305 {
 306         bool cur_state;
 307         enum intel_display_power_domain power_domain;
 308         intel_wakeref_t wakeref;
 309
 310         /* we keep both pipes enabled on 830 */
 311         if (IS_I830(dev_priv))
 312                 state = true;
 313
 314         power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
 315         wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
 316         if (wakeref) {
 317                 u32 val = intel_de_read(dev_priv, TRANSCONF(cpu_transcoder));
 318                 cur_state = !!(val & TRANSCONF_ENABLE);
 319
 320                 intel_display_power_put(dev_priv, power_domain, wakeref);
 321         } else {
 322                 cur_state = false;
 323         }
 324
 325         I915_STATE_WARN(dev_priv, cur_state != state,
 326                         "transcoder %s assertion failure (expected %s, current %s)\n",
 327                         transcoder_name(cpu_transcoder), str_on_off(state),
 328                         str_on_off(cur_state));
 329 }
 330
 331 static void assert_plane(struct intel_plane *plane, bool state)
 332 {
 333         struct drm_i915_private *i915 = to_i915(plane->base.dev);
 334         enum pipe pipe;
 335         bool cur_state;
 336
 337         cur_state = plane->get_hw_state(plane, &pipe);
 338
 339         I915_STATE_WARN(i915, cur_state != state,
 340                         "%s assertion failure (expected %s, current %s)\n",
 341                         plane->base.name, str_on_off(state),
 342                         str_on_off(cur_state));
 343 }
 344
 345 #define assert_plane_enabled(p) assert_plane(p, true)
 346 #define assert_plane_disabled(p) assert_plane(p, false)
 347
 348 static void assert_planes_disabled(struct intel_crtc *crtc)
 349 {
 350         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 351         struct intel_plane *plane;
 352
 353         for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane)
 354                 assert_plane_disabled(plane);
 355 }
 356
 357 void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
 358                          struct intel_digital_port *dig_port,
 359                          unsigned int expected_mask)
 360 {
 361         u32 port_mask;
 362         i915_reg_t dpll_reg;
 363
 364         switch (dig_port->base.port) {
 365         default:
 366                 MISSING_CASE(dig_port->base.port);
 367                 fallthrough;
 368         case PORT_B:
 369                 port_mask = DPLL_PORTB_READY_MASK;
 370                 dpll_reg = DPLL(0);
 371                 break;
 372         case PORT_C:
 373                 port_mask = DPLL_PORTC_READY_MASK;
 374                 dpll_reg = DPLL(0);
 375                 expected_mask <<= 4;
 376                 break;
 377         case PORT_D:
 378                 port_mask = DPLL_PORTD_READY_MASK;
 379                 dpll_reg = DPIO_PHY_STATUS;
 380                 break;
 381         }
 382
 383         if (intel_de_wait_for_register(dev_priv, dpll_reg,
 384                                        port_mask, expected_mask, 1000))
 385                 drm_WARN(&dev_priv->drm, 1,
 386                          "timed out waiting for [ENCODER:%d:%s] port ready: got 0x%x, expected 0x%x\n",
 387                          dig_port->base.base.base.id, dig_port->base.base.name,
 388                          intel_de_read(dev_priv, dpll_reg) & port_mask,
 389                          expected_mask);
 390 }
 391
 392 void intel_enable_transcoder(const struct intel_crtc_state *new_crtc_state)
 393 {
 394         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
 395         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 396         enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
 397         enum pipe pipe = crtc->pipe;
 398         i915_reg_t reg;
 399         u32 val;
 400
 401         drm_dbg_kms(&dev_priv->drm, "enabling pipe %c\n", pipe_name(pipe));
 402
 403         assert_planes_disabled(crtc);
 404
 405         /*
 406          * A pipe without a PLL won't actually be able to drive bits from
 407          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
 408          * need the check.
 409          */
 410         if (HAS_GMCH(dev_priv)) {
 411                 if (intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI))
 412                         assert_dsi_pll_enabled(dev_priv);
 413                 else
 414                         assert_pll_enabled(dev_priv, pipe);
 415         } else {
 416                 if (new_crtc_state->has_pch_encoder) {
 417                         /* if driving the PCH, we need FDI enabled */
 418                         assert_fdi_rx_pll_enabled(dev_priv,
 419                                                   intel_crtc_pch_transcoder(crtc));
 420                         assert_fdi_tx_pll_enabled(dev_priv,
 421                                                   (enum pipe) cpu_transcoder);
 422                 }
 423                 /* FIXME: assert CPU port conditions for SNB+ */
 424         }
 425
 426         /* Wa_22012358565:adl-p */
 427         if (DISPLAY_VER(dev_priv) == 13)
 428                 intel_de_rmw(dev_priv, PIPE_ARB_CTL(pipe),
 429                              0, PIPE_ARB_USE_PROG_SLOTS);
 430
 431         reg = TRANSCONF(cpu_transcoder);
 432         val = intel_de_read(dev_priv, reg);
 433         if (val & TRANSCONF_ENABLE) {
 434                 /* we keep both pipes enabled on 830 */
 435                 drm_WARN_ON(&dev_priv->drm, !IS_I830(dev_priv));
 436                 return;
 437         }
 438
 439         intel_de_write(dev_priv, reg, val | TRANSCONF_ENABLE);
 440         intel_de_posting_read(dev_priv, reg);
 441
 442         /*
 443          * Until the pipe starts PIPEDSL reads will return a stale value,
 444          * which causes an apparent vblank timestamp jump when PIPEDSL
 445          * resets to its proper value. That also messes up the frame count
 446          * when it's derived from the timestamps. So let's wait for the
 447          * pipe to start properly before we call drm_crtc_vblank_on()
 448          */
 449         if (intel_crtc_max_vblank_count(new_crtc_state) == 0)
 450                 intel_wait_for_pipe_scanline_moving(crtc);
 451 }
 452
 453 void intel_disable_transcoder(const struct intel_crtc_state *old_crtc_state)
 454 {
 455         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
 456         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 457         enum transcoder cpu_transcoder = old_crtc_state->cpu_transcoder;
 458         enum pipe pipe = crtc->pipe;
 459         i915_reg_t reg;
 460         u32 val;
 461
 462         drm_dbg_kms(&dev_priv->drm, "disabling pipe %c\n", pipe_name(pipe));
 463
 464         /*
 465          * Make sure planes won't keep trying to pump pixels to us,
 466          * or we might hang the display.
 467          */
 468         assert_planes_disabled(crtc);
 469
 470         reg = TRANSCONF(cpu_transcoder);
 471         val = intel_de_read(dev_priv, reg);
 472         if ((val & TRANSCONF_ENABLE) == 0)
 473                 return;
 474
 475         /*
 476          * Double wide has implications for planes
 477          * so best keep it disabled when not needed.
 478          */
 479         if (old_crtc_state->double_wide)
 480                 val &= ~TRANSCONF_DOUBLE_WIDE;
 481
 482         /* Don't disable pipe or pipe PLLs if needed */
 483         if (!IS_I830(dev_priv))
 484                 val &= ~TRANSCONF_ENABLE;
 485
 486         if (DISPLAY_VER(dev_priv) >= 14)
 487                 intel_de_rmw(dev_priv, MTL_CHICKEN_TRANS(cpu_transcoder),
 488                              FECSTALL_DIS_DPTSTREAM_DPTTG, 0);
 489         else if (DISPLAY_VER(dev_priv) >= 12)
 490                 intel_de_rmw(dev_priv, CHICKEN_TRANS(cpu_transcoder),
 491                              FECSTALL_DIS_DPTSTREAM_DPTTG, 0);
 492
 493         intel_de_write(dev_priv, reg, val);
 494         if ((val & TRANSCONF_ENABLE) == 0)
 495                 intel_wait_for_pipe_off(old_crtc_state);
 496 }
 497
 498 unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info)
 499 {
 500         unsigned int size = 0;
 501         int i;
 502
 503         for (i = 0 ; i < ARRAY_SIZE(rot_info->plane); i++)
 504                 size += rot_info->plane[i].dst_stride * rot_info->plane[i].width;
 505
 506         return size;
 507 }
 508
 509 unsigned int intel_remapped_info_size(const struct intel_remapped_info *rem_info)
 510 {
 511         unsigned int size = 0;
 512         int i;
 513
 514         for (i = 0 ; i < ARRAY_SIZE(rem_info->plane); i++) {
 515                 unsigned int plane_size;
 516
 517                 if (rem_info->plane[i].linear)
 518                         plane_size = rem_info->plane[i].size;
 519                 else
 520                         plane_size = rem_info->plane[i].dst_stride * rem_info->plane[i].height;
 521
 522                 if (plane_size == 0)
 523                         continue;
 524
 525                 if (rem_info->plane_alignment)
 526                         size = ALIGN(size, rem_info->plane_alignment);
 527
 528                 size += plane_size;
 529         }
 530
 531         return size;
 532 }
 533
 534 bool intel_plane_uses_fence(const struct intel_plane_state *plane_state)
 535 {
 536         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
 537         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 538
 539         return DISPLAY_VER(dev_priv) < 4 ||
 540                 (plane->fbc &&
 541                  plane_state->view.gtt.type == I915_GTT_VIEW_NORMAL);
 542 }
 543
 544 /*
 545  * Convert the x/y offsets into a linear offset.
 546  * Only valid with 0/180 degree rotation, which is fine since linear
 547  * offset is only used with linear buffers on pre-hsw and tiled buffers
 548  * with gen2/3, and 90/270 degree rotations isn't supported on any of them.
 549  */
 550 u32 intel_fb_xy_to_linear(int x, int y,
 551                           const struct intel_plane_state *state,
 552                           int color_plane)
 553 {
 554         const struct drm_framebuffer *fb = state->hw.fb;
 555         unsigned int cpp = fb->format->cpp[color_plane];
 556         unsigned int pitch = state->view.color_plane[color_plane].mapping_stride;
 557
 558         return y * pitch + x * cpp;
 559 }
 560
 561 /*
 562  * Add the x/y offsets derived from fb->offsets[] to the user
 563  * specified plane src x/y offsets. The resulting x/y offsets
 564  * specify the start of scanout from the beginning of the gtt mapping.
 565  */
 566 void intel_add_fb_offsets(int *x, int *y,
 567                           const struct intel_plane_state *state,
 568                           int color_plane)
 569
 570 {
 571         *x += state->view.color_plane[color_plane].x;
 572         *y += state->view.color_plane[color_plane].y;
 573 }
 574
 575 u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
 576                               u32 pixel_format, u64 modifier)
 577 {
 578         struct intel_crtc *crtc;
 579         struct intel_plane *plane;
 580
 581         if (!HAS_DISPLAY(dev_priv))
 582                 return 0;
 583
 584         /*
 585          * We assume the primary plane for pipe A has
 586          * the highest stride limits of them all,
 587          * if in case pipe A is disabled, use the first pipe from pipe_mask.
 588          */
 589         crtc = intel_first_crtc(dev_priv);
 590         if (!crtc)
 591                 return 0;
 592
 593         plane = to_intel_plane(crtc->base.primary);
 594
 595         return plane->max_stride(plane, pixel_format, modifier,
 596                                  DRM_MODE_ROTATE_0);
 597 }
 598
 599 void intel_set_plane_visible(struct intel_crtc_state *crtc_state,
 600                              struct intel_plane_state *plane_state,
 601                              bool visible)
 602 {
 603         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
 604
 605         plane_state->uapi.visible = visible;
 606
 607         if (visible)
 608                 crtc_state->uapi.plane_mask |= drm_plane_mask(&plane->base);
 609         else
 610                 crtc_state->uapi.plane_mask &= ~drm_plane_mask(&plane->base);
 611 }
 612
 613 void intel_plane_fixup_bitmasks(struct intel_crtc_state *crtc_state)
 614 {
 615         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
 616         struct drm_plane *plane;
 617
 618         /*
 619          * Active_planes aliases if multiple "primary" or cursor planes
 620          * have been used on the same (or wrong) pipe. plane_mask uses
 621          * unique ids, hence we can use that to reconstruct active_planes.
 622          */
 623         crtc_state->enabled_planes = 0;
 624         crtc_state->active_planes = 0;
 625
 626         drm_for_each_plane_mask(plane, &dev_priv->drm,
 627                                 crtc_state->uapi.plane_mask) {
 628                 crtc_state->enabled_planes |= BIT(to_intel_plane(plane)->id);
 629                 crtc_state->active_planes |= BIT(to_intel_plane(plane)->id);
 630         }
 631 }
 632
 633 void intel_plane_disable_noatomic(struct intel_crtc *crtc,
 634                                   struct intel_plane *plane)
 635 {
 636         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 637         struct intel_crtc_state *crtc_state =
 638                 to_intel_crtc_state(crtc->base.state);
 639         struct intel_plane_state *plane_state =
 640                 to_intel_plane_state(plane->base.state);
 641
 642         drm_dbg_kms(&dev_priv->drm,
 643                     "Disabling [PLANE:%d:%s] on [CRTC:%d:%s]\n",
 644                     plane->base.base.id, plane->base.name,
 645                     crtc->base.base.id, crtc->base.name);
 646
 647         intel_set_plane_visible(crtc_state, plane_state, false);
 648         intel_plane_fixup_bitmasks(crtc_state);
 649         crtc_state->data_rate[plane->id] = 0;
 650         crtc_state->data_rate_y[plane->id] = 0;
 651         crtc_state->rel_data_rate[plane->id] = 0;
 652         crtc_state->rel_data_rate_y[plane->id] = 0;
 653         crtc_state->min_cdclk[plane->id] = 0;
 654
 655         if ((crtc_state->active_planes & ~BIT(PLANE_CURSOR)) == 0 &&
 656             hsw_ips_disable(crtc_state)) {
 657                 crtc_state->ips_enabled = false;
 658                 intel_crtc_wait_for_next_vblank(crtc);
 659         }
 660
 661         /*
 662          * Vblank time updates from the shadow to live plane control register
 663          * are blocked if the memory self-refresh mode is active at that
 664          * moment. So to make sure the plane gets truly disabled, disable
 665          * first the self-refresh mode. The self-refresh enable bit in turn
 666          * will be checked/applied by the HW only at the next frame start
 667          * event which is after the vblank start event, so we need to have a
 668          * wait-for-vblank between disabling the plane and the pipe.
 669          */
 670         if (HAS_GMCH(dev_priv) &&
 671             intel_set_memory_cxsr(dev_priv, false))
 672                 intel_crtc_wait_for_next_vblank(crtc);
 673
 674         /*
 675          * Gen2 reports pipe underruns whenever all planes are disabled.
 676          * So disable underrun reporting before all the planes get disabled.
 677          */
 678         if (DISPLAY_VER(dev_priv) == 2 && !crtc_state->active_planes)
 679                 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false);
 680
 681         intel_plane_disable_arm(plane, crtc_state);
 682         intel_crtc_wait_for_next_vblank(crtc);
 683 }
 684
 685 unsigned int
 686 intel_plane_fence_y_offset(const struct intel_plane_state *plane_state)
 687 {
 688         int x = 0, y = 0;
 689
 690         intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0,
 691                                           plane_state->view.color_plane[0].offset, 0);
 692
 693         return y;
 694 }
 695
 696 static void icl_set_pipe_chicken(const struct intel_crtc_state *crtc_state)
 697 {
 698         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 699         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 700         enum pipe pipe = crtc->pipe;
 701         u32 tmp;
 702
 703         tmp = intel_de_read(dev_priv, PIPE_CHICKEN(pipe));
 704
 705         /*
 706          * Display WA #1153: icl
 707          * enable hardware to bypass the alpha math
 708          * and rounding for per-pixel values 00 and 0xff
 709          */
 710         tmp |= PER_PIXEL_ALPHA_BYPASS_EN;
 711         /*
 712          * Display WA # 1605353570: icl
 713          * Set the pixel rounding bit to 1 for allowing
 714          * passthrough of Frame buffer pixels unmodified
 715          * across pipe
 716          */
 717         tmp |= PIXEL_ROUNDING_TRUNC_FB_PASSTHRU;
 718
 719         /*
 720          * Underrun recovery must always be disabled on display 13+.
 721          * DG2 chicken bit meaning is inverted compared to other platforms.
 722          */
 723         if (IS_DG2(dev_priv))
 724                 tmp &= ~UNDERRUN_RECOVERY_ENABLE_DG2;
 725         else if (DISPLAY_VER(dev_priv) >= 13)
 726                 tmp |= UNDERRUN_RECOVERY_DISABLE_ADLP;
 727
 728         /* Wa_14010547955:dg2 */
 729         if (IS_DG2_DISPLAY_STEP(dev_priv, STEP_B0, STEP_FOREVER))
 730                 tmp |= DG2_RENDER_CCSTAG_4_3_EN;
 731
 732         intel_de_write(dev_priv, PIPE_CHICKEN(pipe), tmp);
 733 }
 734
 735 bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv)
 736 {
 737         struct drm_crtc *crtc;
 738         bool cleanup_done;
 739
 740         drm_for_each_crtc(crtc, &dev_priv->drm) {
 741                 struct drm_crtc_commit *commit;
 742                 spin_lock(&crtc->commit_lock);
 743                 commit = list_first_entry_or_null(&crtc->commit_list,
 744                                                   struct drm_crtc_commit, commit_entry);
 745                 cleanup_done = commit ?
 746                         try_wait_for_completion(&commit->cleanup_done) : true;
 747                 spin_unlock(&crtc->commit_lock);
 748
 749                 if (cleanup_done)
 750                         continue;
 751
 752                 intel_crtc_wait_for_next_vblank(to_intel_crtc(crtc));
 753
 754                 return true;
 755         }
 756
 757         return false;
 758 }
 759
 760 /*
 761  * Finds the encoder associated with the given CRTC. This can only be
 762  * used when we know that the CRTC isn't feeding multiple encoders!
 763  */
 764 struct intel_encoder *
 765 intel_get_crtc_new_encoder(const struct intel_atomic_state *state,
 766                            const struct intel_crtc_state *crtc_state)
 767 {
 768         const struct drm_connector_state *connector_state;
 769         const struct drm_connector *connector;
 770         struct intel_encoder *encoder = NULL;
 771         struct intel_crtc *master_crtc;
 772         int num_encoders = 0;
 773         int i;
 774
 775         master_crtc = intel_master_crtc(crtc_state);
 776
 777         for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
 778                 if (connector_state->crtc != &master_crtc->base)
 779                         continue;
 780
 781                 encoder = to_intel_encoder(connector_state->best_encoder);
 782                 num_encoders++;
 783         }
 784
 785         drm_WARN(state->base.dev, num_encoders != 1,
 786                  "%d encoders for pipe %c\n",
 787                  num_encoders, pipe_name(master_crtc->pipe));
 788
 789         return encoder;
 790 }
 791
 792 static void ilk_pfit_enable(const struct intel_crtc_state *crtc_state)
 793 {
 794         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 795         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 796         const struct drm_rect *dst = &crtc_state->pch_pfit.dst;
 797         enum pipe pipe = crtc->pipe;
 798         int width = drm_rect_width(dst);
 799         int height = drm_rect_height(dst);
 800         int x = dst->x1;
 801         int y = dst->y1;
 802
 803         if (!crtc_state->pch_pfit.enabled)
 804                 return;
 805
 806         /* Force use of hard-coded filter coefficients
 807          * as some pre-programmed values are broken,
 808          * e.g. x201.
 809          */
 810         if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv))
 811                 intel_de_write_fw(dev_priv, PF_CTL(pipe), PF_ENABLE |
 812                                   PF_FILTER_MED_3x3 | PF_PIPE_SEL_IVB(pipe));
 813         else
 814                 intel_de_write_fw(dev_priv, PF_CTL(pipe), PF_ENABLE |
 815                                   PF_FILTER_MED_3x3);
 816         intel_de_write_fw(dev_priv, PF_WIN_POS(pipe),
 817                           PF_WIN_XPOS(x) | PF_WIN_YPOS(y));
 818         intel_de_write_fw(dev_priv, PF_WIN_SZ(pipe),
 819                           PF_WIN_XSIZE(width) | PF_WIN_YSIZE(height));
 820 }
 821
 822 static void intel_crtc_dpms_overlay_disable(struct intel_crtc *crtc)
 823 {
 824         if (crtc->overlay)
 825                 (void) intel_overlay_switch_off(crtc->overlay);
 826
 827         /* Let userspace switch the overlay on again. In most cases userspace
 828          * has to recompute where to put it anyway.
 829          */
 830 }
 831
 832 static bool needs_nv12_wa(const struct intel_crtc_state *crtc_state)
 833 {
 834         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
 835
 836         if (!crtc_state->nv12_planes)
 837                 return false;
 838
 839         /* WA Display #0827: Gen9:all */
 840         if (DISPLAY_VER(dev_priv) == 9)
 841                 return true;
 842
 843         return false;
 844 }
 845
 846 static bool needs_scalerclk_wa(const struct intel_crtc_state *crtc_state)
 847 {
 848         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
 849
 850         /* Wa_2006604312:icl,ehl */
 851         if (crtc_state->scaler_state.scaler_users > 0 && DISPLAY_VER(dev_priv) == 11)
 852                 return true;
 853
 854         return false;
 855 }
 856
 857 static bool needs_cursorclk_wa(const struct intel_crtc_state *crtc_state)
 858 {
 859         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
 860
 861         /* Wa_1604331009:icl,jsl,ehl */
 862         if (is_hdr_mode(crtc_state) &&
 863             crtc_state->active_planes & BIT(PLANE_CURSOR) &&
 864             DISPLAY_VER(dev_priv) == 11)
 865                 return true;
 866
 867         return false;
 868 }
 869
 870 static void intel_async_flip_vtd_wa(struct drm_i915_private *i915,
 871                                     enum pipe pipe, bool enable)
 872 {
 873         if (DISPLAY_VER(i915) == 9) {
 874                 /*
 875                  * "Plane N strech max must be programmed to 11b (x1)
 876                  *  when Async flips are enabled on that plane."
 877                  */
 878                 intel_de_rmw(i915, CHICKEN_PIPESL_1(pipe),
 879                              SKL_PLANE1_STRETCH_MAX_MASK,
 880                              enable ? SKL_PLANE1_STRETCH_MAX_X1 : SKL_PLANE1_STRETCH_MAX_X8);
 881         } else {
 882                 /* Also needed on HSW/BDW albeit undocumented */
 883                 intel_de_rmw(i915, CHICKEN_PIPESL_1(pipe),
 884                              HSW_PRI_STRETCH_MAX_MASK,
 885                              enable ? HSW_PRI_STRETCH_MAX_X1 : HSW_PRI_STRETCH_MAX_X8);
 886         }
 887 }
 888
 889 static bool needs_async_flip_vtd_wa(const struct intel_crtc_state *crtc_state)
 890 {
 891         struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
 892
 893         return crtc_state->uapi.async_flip && i915_vtd_active(i915) &&
 894                 (DISPLAY_VER(i915) == 9 || IS_BROADWELL(i915) || IS_HASWELL(i915));
 895 }
 896
 897 #define is_enabling(feature, old_crtc_state, new_crtc_state) \
 898         ((!(old_crtc_state)->feature || intel_crtc_needs_modeset(new_crtc_state)) && \
 899          (new_crtc_state)->feature)
 900 #define is_disabling(feature, old_crtc_state, new_crtc_state) \
 901         ((old_crtc_state)->feature && \
 902          (!(new_crtc_state)->feature || intel_crtc_needs_modeset(new_crtc_state)))
 903
 904 static bool planes_enabling(const struct intel_crtc_state *old_crtc_state,
 905                             const struct intel_crtc_state *new_crtc_state)
 906 {
 907         return is_enabling(active_planes, old_crtc_state, new_crtc_state);
 908 }
 909
 910 static bool planes_disabling(const struct intel_crtc_state *old_crtc_state,
 911                              const struct intel_crtc_state *new_crtc_state)
 912 {
 913         return is_disabling(active_planes, old_crtc_state, new_crtc_state);
 914 }
 915
 916 static bool vrr_enabling(const struct intel_crtc_state *old_crtc_state,
 917                          const struct intel_crtc_state *new_crtc_state)
 918 {
 919         return is_enabling(vrr.enable, old_crtc_state, new_crtc_state);
 920 }
 921
 922 static bool vrr_disabling(const struct intel_crtc_state *old_crtc_state,
 923                           const struct intel_crtc_state *new_crtc_state)
 924 {
 925         return is_disabling(vrr.enable, old_crtc_state, new_crtc_state);
 926 }
 927
 928 #undef is_disabling
 929 #undef is_enabling
 930
 931 static void intel_post_plane_update(struct intel_atomic_state *state,
 932                                     struct intel_crtc *crtc)
 933 {
 934         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
 935         const struct intel_crtc_state *old_crtc_state =
 936                 intel_atomic_get_old_crtc_state(state, crtc);
 937         const struct intel_crtc_state *new_crtc_state =
 938                 intel_atomic_get_new_crtc_state(state, crtc);
 939         enum pipe pipe = crtc->pipe;
 940
 941         intel_frontbuffer_flip(dev_priv, new_crtc_state->fb_bits);
 942
 943         if (new_crtc_state->update_wm_post && new_crtc_state->hw.active)
 944                 intel_update_watermarks(dev_priv);
 945
 946         intel_fbc_post_update(state, crtc);
 947
 948         if (needs_async_flip_vtd_wa(old_crtc_state) &&
 949             !needs_async_flip_vtd_wa(new_crtc_state))
 950                 intel_async_flip_vtd_wa(dev_priv, pipe, false);
 951
 952         if (needs_nv12_wa(old_crtc_state) &&
 953             !needs_nv12_wa(new_crtc_state))
 954                 skl_wa_827(dev_priv, pipe, false);
 955
 956         if (needs_scalerclk_wa(old_crtc_state) &&
 957             !needs_scalerclk_wa(new_crtc_state))
 958                 icl_wa_scalerclkgating(dev_priv, pipe, false);
 959
 960         if (needs_cursorclk_wa(old_crtc_state) &&
 961             !needs_cursorclk_wa(new_crtc_state))
 962                 icl_wa_cursorclkgating(dev_priv, pipe, false);
 963
 964         if (intel_crtc_needs_color_update(new_crtc_state))
 965                 intel_color_post_update(new_crtc_state);
 966 }
 967
 968 static void intel_crtc_enable_flip_done(struct intel_atomic_state *state,
 969                                         struct intel_crtc *crtc)
 970 {
 971         const struct intel_crtc_state *crtc_state =
 972                 intel_atomic_get_new_crtc_state(state, crtc);
 973         u8 update_planes = crtc_state->update_planes;
 974         const struct intel_plane_state *plane_state;
 975         struct intel_plane *plane;
 976         int i;
 977
 978         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
 979                 if (plane->pipe == crtc->pipe &&
 980                     update_planes & BIT(plane->id))
 981                         plane->enable_flip_done(plane);
 982         }
 983 }
 984
 985 static void intel_crtc_disable_flip_done(struct intel_atomic_state *state,
 986                                          struct intel_crtc *crtc)
 987 {
 988         const struct intel_crtc_state *crtc_state =
 989                 intel_atomic_get_new_crtc_state(state, crtc);
 990         u8 update_planes = crtc_state->update_planes;
 991         const struct intel_plane_state *plane_state;
 992         struct intel_plane *plane;
 993         int i;
 994
 995         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
 996                 if (plane->pipe == crtc->pipe &&
 997                     update_planes & BIT(plane->id))
 998                         plane->disable_flip_done(plane);
 999         }
1000 }
1001
1002 static void intel_crtc_async_flip_disable_wa(struct intel_atomic_state *state,
1003                                              struct intel_crtc *crtc)
1004 {
1005         const struct intel_crtc_state *old_crtc_state =
1006                 intel_atomic_get_old_crtc_state(state, crtc);
1007         const struct intel_crtc_state *new_crtc_state =
1008                 intel_atomic_get_new_crtc_state(state, crtc);
1009         u8 disable_async_flip_planes = old_crtc_state->async_flip_planes &
1010                                        ~new_crtc_state->async_flip_planes;
1011         const struct intel_plane_state *old_plane_state;
1012         struct intel_plane *plane;
1013         bool need_vbl_wait = false;
1014         int i;
1015
1016         for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) {
1017                 if (plane->need_async_flip_disable_wa &&
1018                     plane->pipe == crtc->pipe &&
1019                     disable_async_flip_planes & BIT(plane->id)) {
1020                         /*
1021                          * Apart from the async flip bit we want to
1022                          * preserve the old state for the plane.
1023                          */
1024                         plane->async_flip(plane, old_crtc_state,
1025                                           old_plane_state, false);
1026                         need_vbl_wait = true;
1027                 }
1028         }
1029
1030         if (need_vbl_wait)
1031                 intel_crtc_wait_for_next_vblank(crtc);
1032 }
1033
1034 static void intel_pre_plane_update(struct intel_atomic_state *state,
1035                                    struct intel_crtc *crtc)
1036 {
1037         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
1038         const struct intel_crtc_state *old_crtc_state =
1039                 intel_atomic_get_old_crtc_state(state, crtc);
1040         const struct intel_crtc_state *new_crtc_state =
1041                 intel_atomic_get_new_crtc_state(state, crtc);
1042         enum pipe pipe = crtc->pipe;
1043
1044         if (vrr_disabling(old_crtc_state, new_crtc_state)) {
1045                 intel_vrr_disable(old_crtc_state);
1046                 intel_crtc_update_active_timings(old_crtc_state, false);
1047         }
1048
1049         intel_drrs_deactivate(old_crtc_state);
1050
1051         intel_psr_pre_plane_update(state, crtc);
1052
1053         if (hsw_ips_pre_update(state, crtc))
1054                 intel_crtc_wait_for_next_vblank(crtc);
1055
1056         if (intel_fbc_pre_update(state, crtc))
1057                 intel_crtc_wait_for_next_vblank(crtc);
1058
1059         if (!needs_async_flip_vtd_wa(old_crtc_state) &&
1060             needs_async_flip_vtd_wa(new_crtc_state))
1061                 intel_async_flip_vtd_wa(dev_priv, pipe, true);
1062
1063         /* Display WA 827 */
1064         if (!needs_nv12_wa(old_crtc_state) &&
1065             needs_nv12_wa(new_crtc_state))
1066                 skl_wa_827(dev_priv, pipe, true);
1067
1068         /* Wa_2006604312:icl,ehl */
1069         if (!needs_scalerclk_wa(old_crtc_state) &&
1070             needs_scalerclk_wa(new_crtc_state))
1071                 icl_wa_scalerclkgating(dev_priv, pipe, true);
1072
1073         /* Wa_1604331009:icl,jsl,ehl */
1074         if (!needs_cursorclk_wa(old_crtc_state) &&
1075             needs_cursorclk_wa(new_crtc_state))
1076                 icl_wa_cursorclkgating(dev_priv, pipe, true);
1077
1078         /*
1079          * Vblank time updates from the shadow to live plane control register
1080          * are blocked if the memory self-refresh mode is active at that
1081          * moment. So to make sure the plane gets truly disabled, disable
1082          * first the self-refresh mode. The self-refresh enable bit in turn
1083          * will be checked/applied by the HW only at the next frame start
1084          * event which is after the vblank start event, so we need to have a
1085          * wait-for-vblank between disabling the plane and the pipe.
1086          */
1087         if (HAS_GMCH(dev_priv) && old_crtc_state->hw.active &&
1088             new_crtc_state->disable_cxsr && intel_set_memory_cxsr(dev_priv, false))
1089                 intel_crtc_wait_for_next_vblank(crtc);
1090
1091         /*
1092          * IVB workaround: must disable low power watermarks for at least
1093          * one frame before enabling scaling.  LP watermarks can be re-enabled
1094          * when scaling is disabled.
1095          *
1096          * WaCxSRDisabledForSpriteScaling:ivb
1097          */
1098         if (old_crtc_state->hw.active &&
1099             new_crtc_state->disable_lp_wm && ilk_disable_lp_wm(dev_priv))
1100                 intel_crtc_wait_for_next_vblank(crtc);
1101
1102         /*
1103          * If we're doing a modeset we don't need to do any
1104          * pre-vblank watermark programming here.
1105          */
1106         if (!intel_crtc_needs_modeset(new_crtc_state)) {
1107                 /*
1108                  * For platforms that support atomic watermarks, program the
1109                  * 'intermediate' watermarks immediately.  On pre-gen9 platforms, these
1110                  * will be the intermediate values that are safe for both pre- and
1111                  * post- vblank; when vblank happens, the 'active' values will be set
1112                  * to the final 'target' values and we'll do this again to get the
1113                  * optimal watermarks.  For gen9+ platforms, the values we program here
1114                  * will be the final target values which will get automatically latched
1115                  * at vblank time; no further programming will be necessary.
1116                  *
1117                  * If a platform hasn't been transitioned to atomic watermarks yet,
1118                  * we'll continue to update watermarks the old way, if flags tell
1119                  * us to.
1120                  */
1121                 if (!intel_initial_watermarks(state, crtc))
1122                         if (new_crtc_state->update_wm_pre)
1123                                 intel_update_watermarks(dev_priv);
1124         }
1125
1126         /*
1127          * Gen2 reports pipe underruns whenever all planes are disabled.
1128          * So disable underrun reporting before all the planes get disabled.
1129          *
1130          * We do this after .initial_watermarks() so that we have a
1131          * chance of catching underruns with the intermediate watermarks
1132          * vs. the old plane configuration.
1133          */
1134         if (DISPLAY_VER(dev_priv) == 2 && planes_disabling(old_crtc_state, new_crtc_state))
1135                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
1136
1137         /*
1138          * WA for platforms where async address update enable bit
1139          * is double buffered and only latched at start of vblank.
1140          */
1141         if (old_crtc_state->async_flip_planes & ~new_crtc_state->async_flip_planes)
1142                 intel_crtc_async_flip_disable_wa(state, crtc);
1143 }
1144
1145 static void intel_crtc_disable_planes(struct intel_atomic_state *state,
1146                                       struct intel_crtc *crtc)
1147 {
1148         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1149         const struct intel_crtc_state *new_crtc_state =
1150                 intel_atomic_get_new_crtc_state(state, crtc);
1151         unsigned int update_mask = new_crtc_state->update_planes;
1152         const struct intel_plane_state *old_plane_state;
1153         struct intel_plane *plane;
1154         unsigned fb_bits = 0;
1155         int i;
1156
1157         intel_crtc_dpms_overlay_disable(crtc);
1158
1159         for_each_old_intel_plane_in_state(state, plane, old_plane_state, i) {
1160                 if (crtc->pipe != plane->pipe ||
1161                     !(update_mask & BIT(plane->id)))
1162                         continue;
1163
1164                 intel_plane_disable_arm(plane, new_crtc_state);
1165
1166                 if (old_plane_state->uapi.visible)
1167                         fb_bits |= plane->frontbuffer_bit;
1168         }
1169
1170         intel_frontbuffer_flip(dev_priv, fb_bits);
1171 }
1172
1173 static void intel_encoders_update_prepare(struct intel_atomic_state *state)
1174 {
1175         struct drm_i915_private *i915 = to_i915(state->base.dev);
1176         struct intel_crtc_state *new_crtc_state, *old_crtc_state;
1177         struct intel_crtc *crtc;
1178         int i;
1179
1180         /*
1181          * Make sure the DPLL state is up-to-date for fastset TypeC ports after non-blocking commits.
1182          * TODO: Update the DPLL state for all cases in the encoder->update_prepare() hook.
1183          */
1184         if (i915->display.dpll.mgr) {
1185                 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
1186                         if (intel_crtc_needs_modeset(new_crtc_state))
1187                                 continue;
1188
1189                         new_crtc_state->shared_dpll = old_crtc_state->shared_dpll;
1190                         new_crtc_state->dpll_hw_state = old_crtc_state->dpll_hw_state;
1191                 }
1192         }
1193 }
1194
1195 static void intel_encoders_pre_pll_enable(struct intel_atomic_state *state,
1196                                           struct intel_crtc *crtc)
1197 {
1198         const struct intel_crtc_state *crtc_state =
1199                 intel_atomic_get_new_crtc_state(state, crtc);
1200         const struct drm_connector_state *conn_state;
1201         struct drm_connector *conn;
1202         int i;
1203
1204         for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
1205                 struct intel_encoder *encoder =
1206                         to_intel_encoder(conn_state->best_encoder);
1207
1208                 if (conn_state->crtc != &crtc->base)
1209                         continue;
1210
1211                 if (encoder->pre_pll_enable)
1212                         encoder->pre_pll_enable(state, encoder,
1213                                                 crtc_state, conn_state);
1214         }
1215 }
1216
1217 static void intel_encoders_pre_enable(struct intel_atomic_state *state,
1218                                       struct intel_crtc *crtc)
1219 {
1220         const struct intel_crtc_state *crtc_state =
1221                 intel_atomic_get_new_crtc_state(state, crtc);
1222         const struct drm_connector_state *conn_state;
1223         struct drm_connector *conn;
1224         int i;
1225
1226         for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
1227                 struct intel_encoder *encoder =
1228                         to_intel_encoder(conn_state->best_encoder);
1229
1230                 if (conn_state->crtc != &crtc->base)
1231                         continue;
1232
1233                 if (encoder->pre_enable)
1234                         encoder->pre_enable(state, encoder,
1235                                             crtc_state, conn_state);
1236         }
1237 }
1238
1239 static void intel_encoders_enable(struct intel_atomic_state *state,
1240                                   struct intel_crtc *crtc)
1241 {
1242         const struct intel_crtc_state *crtc_state =
1243                 intel_atomic_get_new_crtc_state(state, crtc);
1244         const struct drm_connector_state *conn_state;
1245         struct drm_connector *conn;
1246         int i;
1247
1248         for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
1249                 struct intel_encoder *encoder =
1250                         to_intel_encoder(conn_state->best_encoder);
1251
1252                 if (conn_state->crtc != &crtc->base)
1253                         continue;
1254
1255                 if (encoder->enable)
1256                         encoder->enable(state, encoder,
1257                                         crtc_state, conn_state);
1258                 intel_opregion_notify_encoder(encoder, true);
1259         }
1260 }
1261
1262 static void intel_encoders_disable(struct intel_atomic_state *state,
1263                                    struct intel_crtc *crtc)
1264 {
1265         const struct intel_crtc_state *old_crtc_state =
1266                 intel_atomic_get_old_crtc_state(state, crtc);
1267         const struct drm_connector_state *old_conn_state;
1268         struct drm_connector *conn;
1269         int i;
1270
1271         for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
1272                 struct intel_encoder *encoder =
1273                         to_intel_encoder(old_conn_state->best_encoder);
1274
1275                 if (old_conn_state->crtc != &crtc->base)
1276                         continue;
1277
1278                 intel_opregion_notify_encoder(encoder, false);
1279                 if (encoder->disable)
1280                         encoder->disable(state, encoder,
1281                                          old_crtc_state, old_conn_state);
1282         }
1283 }
1284
1285 static void intel_encoders_post_disable(struct intel_atomic_state *state,
1286                                         struct intel_crtc *crtc)
1287 {
1288         const struct intel_crtc_state *old_crtc_state =
1289                 intel_atomic_get_old_crtc_state(state, crtc);
1290         const struct drm_connector_state *old_conn_state;
1291         struct drm_connector *conn;
1292         int i;
1293
1294         for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
1295                 struct intel_encoder *encoder =
1296                         to_intel_encoder(old_conn_state->best_encoder);
1297
1298                 if (old_conn_state->crtc != &crtc->base)
1299                         continue;
1300
1301                 if (encoder->post_disable)
1302                         encoder->post_disable(state, encoder,
1303                                               old_crtc_state, old_conn_state);
1304         }
1305 }
1306
1307 static void intel_encoders_post_pll_disable(struct intel_atomic_state *state,
1308                                             struct intel_crtc *crtc)
1309 {
1310         const struct intel_crtc_state *old_crtc_state =
1311                 intel_atomic_get_old_crtc_state(state, crtc);
1312         const struct drm_connector_state *old_conn_state;
1313         struct drm_connector *conn;
1314         int i;
1315
1316         for_each_old_connector_in_state(&state->base, conn, old_conn_state, i) {
1317                 struct intel_encoder *encoder =
1318                         to_intel_encoder(old_conn_state->best_encoder);
1319
1320                 if (old_conn_state->crtc != &crtc->base)
1321                         continue;
1322
1323                 if (encoder->post_pll_disable)
1324                         encoder->post_pll_disable(state, encoder,
1325                                                   old_crtc_state, old_conn_state);
1326         }
1327 }
1328
1329 static void intel_encoders_update_pipe(struct intel_atomic_state *state,
1330                                        struct intel_crtc *crtc)
1331 {
1332         const struct intel_crtc_state *crtc_state =
1333                 intel_atomic_get_new_crtc_state(state, crtc);
1334         const struct drm_connector_state *conn_state;
1335         struct drm_connector *conn;
1336         int i;
1337
1338         for_each_new_connector_in_state(&state->base, conn, conn_state, i) {
1339                 struct intel_encoder *encoder =
1340                         to_intel_encoder(conn_state->best_encoder);
1341
1342                 if (conn_state->crtc != &crtc->base)
1343                         continue;
1344
1345                 if (encoder->update_pipe)
1346                         encoder->update_pipe(state, encoder,
1347                                              crtc_state, conn_state);
1348         }
1349 }
1350
1351 static void intel_disable_primary_plane(const struct intel_crtc_state *crtc_state)
1352 {
1353         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1354         struct intel_plane *plane = to_intel_plane(crtc->base.primary);
1355
1356         plane->disable_arm(plane, crtc_state);
1357 }
1358
1359 static void ilk_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state)
1360 {
1361         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1362         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1363
1364         if (crtc_state->has_pch_encoder) {
1365                 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder,
1366                                                &crtc_state->fdi_m_n);
1367         } else if (intel_crtc_has_dp_encoder(crtc_state)) {
1368                 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder,
1369                                                &crtc_state->dp_m_n);
1370                 intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder,
1371                                                &crtc_state->dp_m2_n2);
1372         }
1373
1374         intel_set_transcoder_timings(crtc_state);
1375
1376         ilk_set_pipeconf(crtc_state);
1377 }
1378
1379 static void ilk_crtc_enable(struct intel_atomic_state *state,
1380                             struct intel_crtc *crtc)
1381 {
1382         const struct intel_crtc_state *new_crtc_state =
1383                 intel_atomic_get_new_crtc_state(state, crtc);
1384         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1385         enum pipe pipe = crtc->pipe;
1386
1387         if (drm_WARN_ON(&dev_priv->drm, crtc->active))
1388                 return;
1389
1390         /*
1391          * Sometimes spurious CPU pipe underruns happen during FDI
1392          * training, at least with VGA+HDMI cloning. Suppress them.
1393          *
1394          * On ILK we get an occasional spurious CPU pipe underruns
1395          * between eDP port A enable and vdd enable. Also PCH port
1396          * enable seems to result in the occasional CPU pipe underrun.
1397          *
1398          * Spurious PCH underruns also occur during PCH enabling.
1399          */
1400         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
1401         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
1402
1403         ilk_configure_cpu_transcoder(new_crtc_state);
1404
1405         intel_set_pipe_src_size(new_crtc_state);
1406
1407         crtc->active = true;
1408
1409         intel_encoders_pre_enable(state, crtc);
1410
1411         if (new_crtc_state->has_pch_encoder) {
1412                 ilk_pch_pre_enable(state, crtc);
1413         } else {
1414                 assert_fdi_tx_disabled(dev_priv, pipe);
1415                 assert_fdi_rx_disabled(dev_priv, pipe);
1416         }
1417
1418         ilk_pfit_enable(new_crtc_state);
1419
1420         /*
1421          * On ILK+ LUT must be loaded before the pipe is running but with
1422          * clocks enabled
1423          */
1424         intel_color_load_luts(new_crtc_state);
1425         intel_color_commit_noarm(new_crtc_state);
1426         intel_color_commit_arm(new_crtc_state);
1427         /* update DSPCNTR to configure gamma for pipe bottom color */
1428         intel_disable_primary_plane(new_crtc_state);
1429
1430         intel_initial_watermarks(state, crtc);
1431         intel_enable_transcoder(new_crtc_state);
1432
1433         if (new_crtc_state->has_pch_encoder)
1434                 ilk_pch_enable(state, crtc);
1435
1436         intel_crtc_vblank_on(new_crtc_state);
1437
1438         intel_encoders_enable(state, crtc);
1439
1440         if (HAS_PCH_CPT(dev_priv))
1441                 intel_wait_for_pipe_scanline_moving(crtc);
1442
1443         /*
1444          * Must wait for vblank to avoid spurious PCH FIFO underruns.
1445          * And a second vblank wait is needed at least on ILK with
1446          * some interlaced HDMI modes. Let's do the double wait always
1447          * in case there are more corner cases we don't know about.
1448          */
1449         if (new_crtc_state->has_pch_encoder) {
1450                 intel_crtc_wait_for_next_vblank(crtc);
1451                 intel_crtc_wait_for_next_vblank(crtc);
1452         }
1453         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
1454         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
1455 }
1456
1457 static void glk_pipe_scaler_clock_gating_wa(struct drm_i915_private *dev_priv,
1458                                             enum pipe pipe, bool apply)
1459 {
1460         u32 val = intel_de_read(dev_priv, CLKGATE_DIS_PSL(pipe));
1461         u32 mask = DPF_GATING_DIS | DPF_RAM_GATING_DIS | DPFR_GATING_DIS;
1462
1463         if (apply)
1464                 val |= mask;
1465         else
1466                 val &= ~mask;
1467
1468         intel_de_write(dev_priv, CLKGATE_DIS_PSL(pipe), val);
1469 }
1470
1471 static void hsw_set_linetime_wm(const struct intel_crtc_state *crtc_state)
1472 {
1473         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1474         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1475
1476         intel_de_write(dev_priv, WM_LINETIME(crtc->pipe),
1477                        HSW_LINETIME(crtc_state->linetime) |
1478                        HSW_IPS_LINETIME(crtc_state->ips_linetime));
1479 }
1480
1481 static void hsw_set_frame_start_delay(const struct intel_crtc_state *crtc_state)
1482 {
1483         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1484         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1485         enum transcoder transcoder = crtc_state->cpu_transcoder;
1486         i915_reg_t reg = DISPLAY_VER(dev_priv) >= 14 ? MTL_CHICKEN_TRANS(transcoder) :
1487                          CHICKEN_TRANS(transcoder);
1488
1489         intel_de_rmw(dev_priv, reg,
1490                      HSW_FRAME_START_DELAY_MASK,
1491                      HSW_FRAME_START_DELAY(crtc_state->framestart_delay - 1));
1492 }
1493
1494 static void icl_ddi_bigjoiner_pre_enable(struct intel_atomic_state *state,
1495                                          const struct intel_crtc_state *crtc_state)
1496 {
1497         struct intel_crtc *master_crtc = intel_master_crtc(crtc_state);
1498
1499         /*
1500          * Enable sequence steps 1-7 on bigjoiner master
1501          */
1502         if (intel_crtc_is_bigjoiner_slave(crtc_state))
1503                 intel_encoders_pre_pll_enable(state, master_crtc);
1504
1505         if (crtc_state->shared_dpll)
1506                 intel_enable_shared_dpll(crtc_state);
1507
1508         if (intel_crtc_is_bigjoiner_slave(crtc_state))
1509                 intel_encoders_pre_enable(state, master_crtc);
1510 }
1511
1512 static void hsw_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state)
1513 {
1514         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1515         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1516         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1517
1518         if (crtc_state->has_pch_encoder) {
1519                 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder,
1520                                                &crtc_state->fdi_m_n);
1521         } else if (intel_crtc_has_dp_encoder(crtc_state)) {
1522                 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder,
1523                                                &crtc_state->dp_m_n);
1524                 intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder,
1525                                                &crtc_state->dp_m2_n2);
1526         }
1527
1528         intel_set_transcoder_timings(crtc_state);
1529         if (HAS_VRR(dev_priv))
1530                 intel_vrr_set_transcoder_timings(crtc_state);
1531
1532         if (cpu_transcoder != TRANSCODER_EDP)
1533                 intel_de_write(dev_priv, TRANS_MULT(cpu_transcoder),
1534                                crtc_state->pixel_multiplier - 1);
1535
1536         hsw_set_frame_start_delay(crtc_state);
1537
1538         hsw_set_transconf(crtc_state);
1539 }
1540
1541 static void hsw_crtc_enable(struct intel_atomic_state *state,
1542                             struct intel_crtc *crtc)
1543 {
1544         const struct intel_crtc_state *new_crtc_state =
1545                 intel_atomic_get_new_crtc_state(state, crtc);
1546         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1547         enum pipe pipe = crtc->pipe, hsw_workaround_pipe;
1548         enum transcoder cpu_transcoder = new_crtc_state->cpu_transcoder;
1549         bool psl_clkgate_wa;
1550
1551         if (drm_WARN_ON(&dev_priv->drm, crtc->active))
1552                 return;
1553
1554         intel_dmc_enable_pipe(dev_priv, crtc->pipe);
1555
1556         if (!new_crtc_state->bigjoiner_pipes) {
1557                 intel_encoders_pre_pll_enable(state, crtc);
1558
1559                 if (new_crtc_state->shared_dpll)
1560                         intel_enable_shared_dpll(new_crtc_state);
1561
1562                 intel_encoders_pre_enable(state, crtc);
1563         } else {
1564                 icl_ddi_bigjoiner_pre_enable(state, new_crtc_state);
1565         }
1566
1567         intel_dsc_enable(new_crtc_state);
1568
1569         if (DISPLAY_VER(dev_priv) >= 13)
1570                 intel_uncompressed_joiner_enable(new_crtc_state);
1571
1572         intel_set_pipe_src_size(new_crtc_state);
1573         if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
1574                 bdw_set_pipe_misc(new_crtc_state);
1575
1576         if (!intel_crtc_is_bigjoiner_slave(new_crtc_state) &&
1577             !transcoder_is_dsi(cpu_transcoder))
1578                 hsw_configure_cpu_transcoder(new_crtc_state);
1579
1580         crtc->active = true;
1581
1582         /* Display WA #1180: WaDisableScalarClockGating: glk */
1583         psl_clkgate_wa = DISPLAY_VER(dev_priv) == 10 &&
1584                 new_crtc_state->pch_pfit.enabled;
1585         if (psl_clkgate_wa)
1586                 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, true);
1587
1588         if (DISPLAY_VER(dev_priv) >= 9)
1589                 skl_pfit_enable(new_crtc_state);
1590         else
1591                 ilk_pfit_enable(new_crtc_state);
1592
1593         /*
1594          * On ILK+ LUT must be loaded before the pipe is running but with
1595          * clocks enabled
1596          */
1597         intel_color_load_luts(new_crtc_state);
1598         intel_color_commit_noarm(new_crtc_state);
1599         intel_color_commit_arm(new_crtc_state);
1600         /* update DSPCNTR to configure gamma/csc for pipe bottom color */
1601         if (DISPLAY_VER(dev_priv) < 9)
1602                 intel_disable_primary_plane(new_crtc_state);
1603
1604         hsw_set_linetime_wm(new_crtc_state);
1605
1606         if (DISPLAY_VER(dev_priv) >= 11)
1607                 icl_set_pipe_chicken(new_crtc_state);
1608
1609         intel_initial_watermarks(state, crtc);
1610
1611         if (intel_crtc_is_bigjoiner_slave(new_crtc_state))
1612                 intel_crtc_vblank_on(new_crtc_state);
1613
1614         intel_encoders_enable(state, crtc);
1615
1616         if (psl_clkgate_wa) {
1617                 intel_crtc_wait_for_next_vblank(crtc);
1618                 glk_pipe_scaler_clock_gating_wa(dev_priv, pipe, false);
1619         }
1620
1621         /* If we change the relative order between pipe/planes enabling, we need
1622          * to change the workaround. */
1623         hsw_workaround_pipe = new_crtc_state->hsw_workaround_pipe;
1624         if (IS_HASWELL(dev_priv) && hsw_workaround_pipe != INVALID_PIPE) {
1625                 struct intel_crtc *wa_crtc;
1626
1627                 wa_crtc = intel_crtc_for_pipe(dev_priv, hsw_workaround_pipe);
1628
1629                 intel_crtc_wait_for_next_vblank(wa_crtc);
1630                 intel_crtc_wait_for_next_vblank(wa_crtc);
1631         }
1632 }
1633
1634 void ilk_pfit_disable(const struct intel_crtc_state *old_crtc_state)
1635 {
1636         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
1637         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1638         enum pipe pipe = crtc->pipe;
1639
1640         /* To avoid upsetting the power well on haswell only disable the pfit if
1641          * it's in use. The hw state code will make sure we get this right. */
1642         if (!old_crtc_state->pch_pfit.enabled)
1643                 return;
1644
1645         intel_de_write_fw(dev_priv, PF_CTL(pipe), 0);
1646         intel_de_write_fw(dev_priv, PF_WIN_POS(pipe), 0);
1647         intel_de_write_fw(dev_priv, PF_WIN_SZ(pipe), 0);
1648 }
1649
1650 static void ilk_crtc_disable(struct intel_atomic_state *state,
1651                              struct intel_crtc *crtc)
1652 {
1653         const struct intel_crtc_state *old_crtc_state =
1654                 intel_atomic_get_old_crtc_state(state, crtc);
1655         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1656         enum pipe pipe = crtc->pipe;
1657
1658         /*
1659          * Sometimes spurious CPU pipe underruns happen when the
1660          * pipe is already disabled, but FDI RX/TX is still enabled.
1661          * Happens at least with VGA+HDMI cloning. Suppress them.
1662          */
1663         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
1664         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, false);
1665
1666         intel_encoders_disable(state, crtc);
1667
1668         intel_crtc_vblank_off(old_crtc_state);
1669
1670         intel_disable_transcoder(old_crtc_state);
1671
1672         ilk_pfit_disable(old_crtc_state);
1673
1674         if (old_crtc_state->has_pch_encoder)
1675                 ilk_pch_disable(state, crtc);
1676
1677         intel_encoders_post_disable(state, crtc);
1678
1679         if (old_crtc_state->has_pch_encoder)
1680                 ilk_pch_post_disable(state, crtc);
1681
1682         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
1683         intel_set_pch_fifo_underrun_reporting(dev_priv, pipe, true);
1684
1685         intel_disable_shared_dpll(old_crtc_state);
1686 }
1687
1688 static void hsw_crtc_disable(struct intel_atomic_state *state,
1689                              struct intel_crtc *crtc)
1690 {
1691         const struct intel_crtc_state *old_crtc_state =
1692                 intel_atomic_get_old_crtc_state(state, crtc);
1693         struct drm_i915_private *i915 = to_i915(crtc->base.dev);
1694
1695         /*
1696          * FIXME collapse everything to one hook.
1697          * Need care with mst->ddi interactions.
1698          */
1699         if (!intel_crtc_is_bigjoiner_slave(old_crtc_state)) {
1700                 intel_encoders_disable(state, crtc);
1701                 intel_encoders_post_disable(state, crtc);
1702         }
1703
1704         intel_disable_shared_dpll(old_crtc_state);
1705
1706         if (!intel_crtc_is_bigjoiner_slave(old_crtc_state)) {
1707                 struct intel_crtc *slave_crtc;
1708
1709                 intel_encoders_post_pll_disable(state, crtc);
1710
1711                 intel_dmc_disable_pipe(i915, crtc->pipe);
1712
1713                 for_each_intel_crtc_in_pipe_mask(&i915->drm, slave_crtc,
1714                                                  intel_crtc_bigjoiner_slave_pipes(old_crtc_state))
1715                         intel_dmc_disable_pipe(i915, slave_crtc->pipe);
1716         }
1717 }
1718
1719 static void i9xx_pfit_enable(const struct intel_crtc_state *crtc_state)
1720 {
1721         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1722         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1723
1724         if (!crtc_state->gmch_pfit.control)
1725                 return;
1726
1727         /*
1728          * The panel fitter should only be adjusted whilst the pipe is disabled,
1729          * according to register description and PRM.
1730          */
1731         drm_WARN_ON(&dev_priv->drm,
1732                     intel_de_read(dev_priv, PFIT_CONTROL) & PFIT_ENABLE);
1733         assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder);
1734
1735         intel_de_write(dev_priv, PFIT_PGM_RATIOS,
1736                        crtc_state->gmch_pfit.pgm_ratios);
1737         intel_de_write(dev_priv, PFIT_CONTROL, crtc_state->gmch_pfit.control);
1738
1739         /* Border color in case we don't scale up to the full screen. Black by
1740          * default, change to something else for debugging. */
1741         intel_de_write(dev_priv, BCLRPAT(crtc->pipe), 0);
1742 }
1743
1744 bool intel_phy_is_combo(struct drm_i915_private *dev_priv, enum phy phy)
1745 {
1746         if (phy == PHY_NONE)
1747                 return false;
1748         else if (IS_ALDERLAKE_S(dev_priv))
1749                 return phy <= PHY_E;
1750         else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv))
1751                 return phy <= PHY_D;
1752         else if (IS_JSL_EHL(dev_priv))
1753                 return phy <= PHY_C;
1754         else if (IS_ALDERLAKE_P(dev_priv) || IS_DISPLAY_VER(dev_priv, 11, 12))
1755                 return phy <= PHY_B;
1756         else
1757                 /*
1758                  * DG2 outputs labelled as "combo PHY" in the bspec use
1759                  * SNPS PHYs with completely different programming,
1760                  * hence we always return false here.
1761                  */
1762                 return false;
1763 }
1764
1765 bool intel_phy_is_tc(struct drm_i915_private *dev_priv, enum phy phy)
1766 {
1767         if (IS_DG2(dev_priv))
1768                 /* DG2's "TC1" output uses a SNPS PHY */
1769                 return false;
1770         else if (IS_ALDERLAKE_P(dev_priv) || IS_METEORLAKE(dev_priv))
1771                 return phy >= PHY_F && phy <= PHY_I;
1772         else if (IS_TIGERLAKE(dev_priv))
1773                 return phy >= PHY_D && phy <= PHY_I;
1774         else if (IS_ICELAKE(dev_priv))
1775                 return phy >= PHY_C && phy <= PHY_F;
1776         else
1777                 return false;
1778 }
1779
1780 bool intel_phy_is_snps(struct drm_i915_private *dev_priv, enum phy phy)
1781 {
1782         if (phy == PHY_NONE)
1783                 return false;
1784         else if (IS_DG2(dev_priv))
1785                 /*
1786                  * All four "combo" ports and the TC1 port (PHY E) use
1787                  * Synopsis PHYs.
1788                  */
1789                 return phy <= PHY_E;
1790
1791         return false;
1792 }
1793
1794 enum phy intel_port_to_phy(struct drm_i915_private *i915, enum port port)
1795 {
1796         if (DISPLAY_VER(i915) >= 13 && port >= PORT_D_XELPD)
1797                 return PHY_D + port - PORT_D_XELPD;
1798         else if (DISPLAY_VER(i915) >= 13 && port >= PORT_TC1)
1799                 return PHY_F + port - PORT_TC1;
1800         else if (IS_ALDERLAKE_S(i915) && port >= PORT_TC1)
1801                 return PHY_B + port - PORT_TC1;
1802         else if ((IS_DG1(i915) || IS_ROCKETLAKE(i915)) && port >= PORT_TC1)
1803                 return PHY_C + port - PORT_TC1;
1804         else if (IS_JSL_EHL(i915) && port == PORT_D)
1805                 return PHY_A;
1806
1807         return PHY_A + port - PORT_A;
1808 }
1809
1810 enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port)
1811 {
1812         if (!intel_phy_is_tc(dev_priv, intel_port_to_phy(dev_priv, port)))
1813                 return TC_PORT_NONE;
1814
1815         if (DISPLAY_VER(dev_priv) >= 12)
1816                 return TC_PORT_1 + port - PORT_TC1;
1817         else
1818                 return TC_PORT_1 + port - PORT_C;
1819 }
1820
1821 enum intel_display_power_domain
1822 intel_aux_power_domain(struct intel_digital_port *dig_port)
1823 {
1824         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1825
1826         if (intel_tc_port_in_tbt_alt_mode(dig_port))
1827                 return intel_display_power_tbt_aux_domain(i915, dig_port->aux_ch);
1828
1829         return intel_display_power_legacy_aux_domain(i915, dig_port->aux_ch);
1830 }
1831
1832 static void get_crtc_power_domains(struct intel_crtc_state *crtc_state,
1833                                    struct intel_power_domain_mask *mask)
1834 {
1835         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1836         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1837         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1838         struct drm_encoder *encoder;
1839         enum pipe pipe = crtc->pipe;
1840
1841         bitmap_zero(mask->bits, POWER_DOMAIN_NUM);
1842
1843         if (!crtc_state->hw.active)
1844                 return;
1845
1846         set_bit(POWER_DOMAIN_PIPE(pipe), mask->bits);
1847         set_bit(POWER_DOMAIN_TRANSCODER(cpu_transcoder), mask->bits);
1848         if (crtc_state->pch_pfit.enabled ||
1849             crtc_state->pch_pfit.force_thru)
1850                 set_bit(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe), mask->bits);
1851
1852         drm_for_each_encoder_mask(encoder, &dev_priv->drm,
1853                                   crtc_state->uapi.encoder_mask) {
1854                 struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
1855
1856                 set_bit(intel_encoder->power_domain, mask->bits);
1857         }
1858
1859         if (HAS_DDI(dev_priv) && crtc_state->has_audio)
1860                 set_bit(POWER_DOMAIN_AUDIO_MMIO, mask->bits);
1861
1862         if (crtc_state->shared_dpll)
1863                 set_bit(POWER_DOMAIN_DISPLAY_CORE, mask->bits);
1864
1865         if (crtc_state->dsc.compression_enable)
1866                 set_bit(intel_dsc_power_domain(crtc, cpu_transcoder), mask->bits);
1867 }
1868
1869 void intel_modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state,
1870                                           struct intel_power_domain_mask *old_domains)
1871 {
1872         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1873         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1874         enum intel_display_power_domain domain;
1875         struct intel_power_domain_mask domains, new_domains;
1876
1877         get_crtc_power_domains(crtc_state, &domains);
1878
1879         bitmap_andnot(new_domains.bits,
1880                       domains.bits,
1881                       crtc->enabled_power_domains.mask.bits,
1882                       POWER_DOMAIN_NUM);
1883         bitmap_andnot(old_domains->bits,
1884                       crtc->enabled_power_domains.mask.bits,
1885                       domains.bits,
1886                       POWER_DOMAIN_NUM);
1887
1888         for_each_power_domain(domain, &new_domains)
1889                 intel_display_power_get_in_set(dev_priv,
1890                                                &crtc->enabled_power_domains,
1891                                                domain);
1892 }
1893
1894 void intel_modeset_put_crtc_power_domains(struct intel_crtc *crtc,
1895                                           struct intel_power_domain_mask *domains)
1896 {
1897         intel_display_power_put_mask_in_set(to_i915(crtc->base.dev),
1898                                             &crtc->enabled_power_domains,
1899                                             domains);
1900 }
1901
1902 static void i9xx_configure_cpu_transcoder(const struct intel_crtc_state *crtc_state)
1903 {
1904         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1905         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
1906
1907         if (intel_crtc_has_dp_encoder(crtc_state)) {
1908                 intel_cpu_transcoder_set_m1_n1(crtc, cpu_transcoder,
1909                                                &crtc_state->dp_m_n);
1910                 intel_cpu_transcoder_set_m2_n2(crtc, cpu_transcoder,
1911                                                &crtc_state->dp_m2_n2);
1912         }
1913
1914         intel_set_transcoder_timings(crtc_state);
1915
1916         i9xx_set_pipeconf(crtc_state);
1917 }
1918
1919 static void valleyview_crtc_enable(struct intel_atomic_state *state,
1920                                    struct intel_crtc *crtc)
1921 {
1922         const struct intel_crtc_state *new_crtc_state =
1923                 intel_atomic_get_new_crtc_state(state, crtc);
1924         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1925         enum pipe pipe = crtc->pipe;
1926
1927         if (drm_WARN_ON(&dev_priv->drm, crtc->active))
1928                 return;
1929
1930         i9xx_configure_cpu_transcoder(new_crtc_state);
1931
1932         intel_set_pipe_src_size(new_crtc_state);
1933
1934         intel_de_write(dev_priv, VLV_PIPE_MSA_MISC(pipe), 0);
1935
1936         if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
1937                 intel_de_write(dev_priv, CHV_BLEND(pipe), CHV_BLEND_LEGACY);
1938                 intel_de_write(dev_priv, CHV_CANVAS(pipe), 0);
1939         }
1940
1941         crtc->active = true;
1942
1943         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
1944
1945         intel_encoders_pre_pll_enable(state, crtc);
1946
1947         if (IS_CHERRYVIEW(dev_priv))
1948                 chv_enable_pll(new_crtc_state);
1949         else
1950                 vlv_enable_pll(new_crtc_state);
1951
1952         intel_encoders_pre_enable(state, crtc);
1953
1954         i9xx_pfit_enable(new_crtc_state);
1955
1956         intel_color_load_luts(new_crtc_state);
1957         intel_color_commit_noarm(new_crtc_state);
1958         intel_color_commit_arm(new_crtc_state);
1959         /* update DSPCNTR to configure gamma for pipe bottom color */
1960         intel_disable_primary_plane(new_crtc_state);
1961
1962         intel_initial_watermarks(state, crtc);
1963         intel_enable_transcoder(new_crtc_state);
1964
1965         intel_crtc_vblank_on(new_crtc_state);
1966
1967         intel_encoders_enable(state, crtc);
1968 }
1969
1970 static void i9xx_crtc_enable(struct intel_atomic_state *state,
1971                              struct intel_crtc *crtc)
1972 {
1973         const struct intel_crtc_state *new_crtc_state =
1974                 intel_atomic_get_new_crtc_state(state, crtc);
1975         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
1976         enum pipe pipe = crtc->pipe;
1977
1978         if (drm_WARN_ON(&dev_priv->drm, crtc->active))
1979                 return;
1980
1981         i9xx_configure_cpu_transcoder(new_crtc_state);
1982
1983         intel_set_pipe_src_size(new_crtc_state);
1984
1985         crtc->active = true;
1986
1987         if (DISPLAY_VER(dev_priv) != 2)
1988                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
1989
1990         intel_encoders_pre_enable(state, crtc);
1991
1992         i9xx_enable_pll(new_crtc_state);
1993
1994         i9xx_pfit_enable(new_crtc_state);
1995
1996         intel_color_load_luts(new_crtc_state);
1997         intel_color_commit_noarm(new_crtc_state);
1998         intel_color_commit_arm(new_crtc_state);
1999         /* update DSPCNTR to configure gamma for pipe bottom color */
2000         intel_disable_primary_plane(new_crtc_state);
2001
2002         if (!intel_initial_watermarks(state, crtc))
2003                 intel_update_watermarks(dev_priv);
2004         intel_enable_transcoder(new_crtc_state);
2005
2006         intel_crtc_vblank_on(new_crtc_state);
2007
2008         intel_encoders_enable(state, crtc);
2009
2010         /* prevents spurious underruns */
2011         if (DISPLAY_VER(dev_priv) == 2)
2012                 intel_crtc_wait_for_next_vblank(crtc);
2013 }
2014
2015 static void i9xx_pfit_disable(const struct intel_crtc_state *old_crtc_state)
2016 {
2017         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
2018         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2019
2020         if (!old_crtc_state->gmch_pfit.control)
2021                 return;
2022
2023         assert_transcoder_disabled(dev_priv, old_crtc_state->cpu_transcoder);
2024
2025         drm_dbg_kms(&dev_priv->drm, "disabling pfit, current: 0x%08x\n",
2026                     intel_de_read(dev_priv, PFIT_CONTROL));
2027         intel_de_write(dev_priv, PFIT_CONTROL, 0);
2028 }
2029
2030 static void i9xx_crtc_disable(struct intel_atomic_state *state,
2031                               struct intel_crtc *crtc)
2032 {
2033         struct intel_crtc_state *old_crtc_state =
2034                 intel_atomic_get_old_crtc_state(state, crtc);
2035         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2036         enum pipe pipe = crtc->pipe;
2037
2038         /*
2039          * On gen2 planes are double buffered but the pipe isn't, so we must
2040          * wait for planes to fully turn off before disabling the pipe.
2041          */
2042         if (DISPLAY_VER(dev_priv) == 2)
2043                 intel_crtc_wait_for_next_vblank(crtc);
2044
2045         intel_encoders_disable(state, crtc);
2046
2047         intel_crtc_vblank_off(old_crtc_state);
2048
2049         intel_disable_transcoder(old_crtc_state);
2050
2051         i9xx_pfit_disable(old_crtc_state);
2052
2053         intel_encoders_post_disable(state, crtc);
2054
2055         if (!intel_crtc_has_type(old_crtc_state, INTEL_OUTPUT_DSI)) {
2056                 if (IS_CHERRYVIEW(dev_priv))
2057                         chv_disable_pll(dev_priv, pipe);
2058                 else if (IS_VALLEYVIEW(dev_priv))
2059                         vlv_disable_pll(dev_priv, pipe);
2060                 else
2061                         i9xx_disable_pll(old_crtc_state);
2062         }
2063
2064         intel_encoders_post_pll_disable(state, crtc);
2065
2066         if (DISPLAY_VER(dev_priv) != 2)
2067                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
2068
2069         if (!dev_priv->display.funcs.wm->initial_watermarks)
2070                 intel_update_watermarks(dev_priv);
2071
2072         /* clock the pipe down to 640x480@60 to potentially save power */
2073         if (IS_I830(dev_priv))
2074                 i830_enable_pipe(dev_priv, pipe);
2075 }
2076
2077 void intel_encoder_destroy(struct drm_encoder *encoder)
2078 {
2079         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
2080
2081         drm_encoder_cleanup(encoder);
2082         kfree(intel_encoder);
2083 }
2084
2085 static bool intel_crtc_supports_double_wide(const struct intel_crtc *crtc)
2086 {
2087         const struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2088
2089         /* GDG double wide on either pipe, otherwise pipe A only */
2090         return DISPLAY_VER(dev_priv) < 4 &&
2091                 (crtc->pipe == PIPE_A || IS_I915G(dev_priv));
2092 }
2093
2094 static u32 ilk_pipe_pixel_rate(const struct intel_crtc_state *crtc_state)
2095 {
2096         u32 pixel_rate = crtc_state->hw.pipe_mode.crtc_clock;
2097         struct drm_rect src;
2098
2099         /*
2100          * We only use IF-ID interlacing. If we ever use
2101          * PF-ID we'll need to adjust the pixel_rate here.
2102          */
2103
2104         if (!crtc_state->pch_pfit.enabled)
2105                 return pixel_rate;
2106
2107         drm_rect_init(&src, 0, 0,
2108                       drm_rect_width(&crtc_state->pipe_src) << 16,
2109                       drm_rect_height(&crtc_state->pipe_src) << 16);
2110
2111         return intel_adjusted_rate(&src, &crtc_state->pch_pfit.dst,
2112                                    pixel_rate);
2113 }
2114
2115 static void intel_mode_from_crtc_timings(struct drm_display_mode *mode,
2116                                          const struct drm_display_mode *timings)
2117 {
2118         mode->hdisplay = timings->crtc_hdisplay;
2119         mode->htotal = timings->crtc_htotal;
2120         mode->hsync_start = timings->crtc_hsync_start;
2121         mode->hsync_end = timings->crtc_hsync_end;
2122
2123         mode->vdisplay = timings->crtc_vdisplay;
2124         mode->vtotal = timings->crtc_vtotal;
2125         mode->vsync_start = timings->crtc_vsync_start;
2126         mode->vsync_end = timings->crtc_vsync_end;
2127
2128         mode->flags = timings->flags;
2129         mode->type = DRM_MODE_TYPE_DRIVER;
2130
2131         mode->clock = timings->crtc_clock;
2132
2133         drm_mode_set_name(mode);
2134 }
2135
2136 static void intel_crtc_compute_pixel_rate(struct intel_crtc_state *crtc_state)
2137 {
2138         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
2139
2140         if (HAS_GMCH(dev_priv))
2141                 /* FIXME calculate proper pipe pixel rate for GMCH pfit */
2142                 crtc_state->pixel_rate =
2143                         crtc_state->hw.pipe_mode.crtc_clock;
2144         else
2145                 crtc_state->pixel_rate =
2146                         ilk_pipe_pixel_rate(crtc_state);
2147 }
2148
2149 static void intel_bigjoiner_adjust_timings(const struct intel_crtc_state *crtc_state,
2150                                            struct drm_display_mode *mode)
2151 {
2152         int num_pipes = intel_bigjoiner_num_pipes(crtc_state);
2153
2154         if (num_pipes < 2)
2155                 return;
2156
2157         mode->crtc_clock /= num_pipes;
2158         mode->crtc_hdisplay /= num_pipes;
2159         mode->crtc_hblank_start /= num_pipes;
2160         mode->crtc_hblank_end /= num_pipes;
2161         mode->crtc_hsync_start /= num_pipes;
2162         mode->crtc_hsync_end /= num_pipes;
2163         mode->crtc_htotal /= num_pipes;
2164 }
2165
2166 static void intel_splitter_adjust_timings(const struct intel_crtc_state *crtc_state,
2167                                           struct drm_display_mode *mode)
2168 {
2169         int overlap = crtc_state->splitter.pixel_overlap;
2170         int n = crtc_state->splitter.link_count;
2171
2172         if (!crtc_state->splitter.enable)
2173                 return;
2174
2175         /*
2176          * eDP MSO uses segment timings from EDID for transcoder
2177          * timings, but full mode for everything else.
2178          *
2179          * h_full = (h_segment - pixel_overlap) * link_count
2180          */
2181         mode->crtc_hdisplay = (mode->crtc_hdisplay - overlap) * n;
2182         mode->crtc_hblank_start = (mode->crtc_hblank_start - overlap) * n;
2183         mode->crtc_hblank_end = (mode->crtc_hblank_end - overlap) * n;
2184         mode->crtc_hsync_start = (mode->crtc_hsync_start - overlap) * n;
2185         mode->crtc_hsync_end = (mode->crtc_hsync_end - overlap) * n;
2186         mode->crtc_htotal = (mode->crtc_htotal - overlap) * n;
2187         mode->crtc_clock *= n;
2188 }
2189
2190 static void intel_crtc_readout_derived_state(struct intel_crtc_state *crtc_state)
2191 {
2192         struct drm_display_mode *mode = &crtc_state->hw.mode;
2193         struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode;
2194         struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
2195
2196         /*
2197          * Start with the adjusted_mode crtc timings, which
2198          * have been filled with the transcoder timings.
2199          */
2200         drm_mode_copy(pipe_mode, adjusted_mode);
2201
2202         /* Expand MSO per-segment transcoder timings to full */
2203         intel_splitter_adjust_timings(crtc_state, pipe_mode);
2204
2205         /*
2206          * We want the full numbers in adjusted_mode normal timings,
2207          * adjusted_mode crtc timings are left with the raw transcoder
2208          * timings.
2209          */
2210         intel_mode_from_crtc_timings(adjusted_mode, pipe_mode);
2211
2212         /* Populate the "user" mode with full numbers */
2213         drm_mode_copy(mode, pipe_mode);
2214         intel_mode_from_crtc_timings(mode, mode);
2215         mode->hdisplay = drm_rect_width(&crtc_state->pipe_src) *
2216                 (intel_bigjoiner_num_pipes(crtc_state) ?: 1);
2217         mode->vdisplay = drm_rect_height(&crtc_state->pipe_src);
2218
2219         /* Derive per-pipe timings in case bigjoiner is used */
2220         intel_bigjoiner_adjust_timings(crtc_state, pipe_mode);
2221         intel_mode_from_crtc_timings(pipe_mode, pipe_mode);
2222
2223         intel_crtc_compute_pixel_rate(crtc_state);
2224 }
2225
2226 void intel_encoder_get_config(struct intel_encoder *encoder,
2227                               struct intel_crtc_state *crtc_state)
2228 {
2229         encoder->get_config(encoder, crtc_state);
2230
2231         intel_crtc_readout_derived_state(crtc_state);
2232 }
2233
2234 static void intel_bigjoiner_compute_pipe_src(struct intel_crtc_state *crtc_state)
2235 {
2236         int num_pipes = intel_bigjoiner_num_pipes(crtc_state);
2237         int width, height;
2238
2239         if (num_pipes < 2)
2240                 return;
2241
2242         width = drm_rect_width(&crtc_state->pipe_src);
2243         height = drm_rect_height(&crtc_state->pipe_src);
2244
2245         drm_rect_init(&crtc_state->pipe_src, 0, 0,
2246                       width / num_pipes, height);
2247 }
2248
2249 static int intel_crtc_compute_pipe_src(struct intel_crtc_state *crtc_state)
2250 {
2251         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2252         struct drm_i915_private *i915 = to_i915(crtc->base.dev);
2253
2254         intel_bigjoiner_compute_pipe_src(crtc_state);
2255
2256         /*
2257          * Pipe horizontal size must be even in:
2258          * - DVO ganged mode
2259          * - LVDS dual channel mode
2260          * - Double wide pipe
2261          */
2262         if (drm_rect_width(&crtc_state->pipe_src) & 1) {
2263                 if (crtc_state->double_wide) {
2264                         drm_dbg_kms(&i915->drm,
2265                                     "[CRTC:%d:%s] Odd pipe source width not supported with double wide pipe\n",
2266                                     crtc->base.base.id, crtc->base.name);
2267                         return -EINVAL;
2268                 }
2269
2270                 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) &&
2271                     intel_is_dual_link_lvds(i915)) {
2272                         drm_dbg_kms(&i915->drm,
2273                                     "[CRTC:%d:%s] Odd pipe source width not supported with dual link LVDS\n",
2274                                     crtc->base.base.id, crtc->base.name);
2275                         return -EINVAL;
2276                 }
2277         }
2278
2279         return 0;
2280 }
2281
2282 static int intel_crtc_compute_pipe_mode(struct intel_crtc_state *crtc_state)
2283 {
2284         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2285         struct drm_i915_private *i915 = to_i915(crtc->base.dev);
2286         struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
2287         struct drm_display_mode *pipe_mode = &crtc_state->hw.pipe_mode;
2288         int clock_limit = i915->max_dotclk_freq;
2289
2290         /*
2291          * Start with the adjusted_mode crtc timings, which
2292          * have been filled with the transcoder timings.
2293          */
2294         drm_mode_copy(pipe_mode, adjusted_mode);
2295
2296         /* Expand MSO per-segment transcoder timings to full */
2297         intel_splitter_adjust_timings(crtc_state, pipe_mode);
2298
2299         /* Derive per-pipe timings in case bigjoiner is used */
2300         intel_bigjoiner_adjust_timings(crtc_state, pipe_mode);
2301         intel_mode_from_crtc_timings(pipe_mode, pipe_mode);
2302
2303         if (DISPLAY_VER(i915) < 4) {
2304                 clock_limit = i915->display.cdclk.max_cdclk_freq * 9 / 10;
2305
2306                 /*
2307                  * Enable double wide mode when the dot clock
2308                  * is > 90% of the (display) core speed.
2309                  */
2310                 if (intel_crtc_supports_double_wide(crtc) &&
2311                     pipe_mode->crtc_clock > clock_limit) {
2312                         clock_limit = i915->max_dotclk_freq;
2313                         crtc_state->double_wide = true;
2314                 }
2315         }
2316
2317         if (pipe_mode->crtc_clock > clock_limit) {
2318                 drm_dbg_kms(&i915->drm,
2319                             "[CRTC:%d:%s] requested pixel clock (%d kHz) too high (max: %d kHz, double wide: %s)\n",
2320                             crtc->base.base.id, crtc->base.name,
2321                             pipe_mode->crtc_clock, clock_limit,
2322                             str_yes_no(crtc_state->double_wide));
2323                 return -EINVAL;
2324         }
2325
2326         return 0;
2327 }
2328
2329 static int intel_crtc_compute_config(struct intel_atomic_state *state,
2330                                      struct intel_crtc *crtc)
2331 {
2332         struct intel_crtc_state *crtc_state =
2333                 intel_atomic_get_new_crtc_state(state, crtc);
2334         int ret;
2335
2336         ret = intel_dpll_crtc_compute_clock(state, crtc);
2337         if (ret)
2338                 return ret;
2339
2340         ret = intel_crtc_compute_pipe_src(crtc_state);
2341         if (ret)
2342                 return ret;
2343
2344         ret = intel_crtc_compute_pipe_mode(crtc_state);
2345         if (ret)
2346                 return ret;
2347
2348         intel_crtc_compute_pixel_rate(crtc_state);
2349
2350         if (crtc_state->has_pch_encoder)
2351                 return ilk_fdi_compute_config(crtc, crtc_state);
2352
2353         return 0;
2354 }
2355
2356 static void
2357 intel_reduce_m_n_ratio(u32 *num, u32 *den)
2358 {
2359         while (*num > DATA_LINK_M_N_MASK ||
2360                *den > DATA_LINK_M_N_MASK) {
2361                 *num >>= 1;
2362                 *den >>= 1;
2363         }
2364 }
2365
2366 static void compute_m_n(u32 *ret_m, u32 *ret_n,
2367                         u32 m, u32 n, u32 constant_n)
2368 {
2369         if (constant_n)
2370                 *ret_n = constant_n;
2371         else
2372                 *ret_n = min_t(unsigned int, roundup_pow_of_two(n), DATA_LINK_N_MAX);
2373
2374         *ret_m = div_u64(mul_u32_u32(m, *ret_n), n);
2375         intel_reduce_m_n_ratio(ret_m, ret_n);
2376 }
2377
2378 void
2379 intel_link_compute_m_n(u16 bits_per_pixel, int nlanes,
2380                        int pixel_clock, int link_clock,
2381                        struct intel_link_m_n *m_n,
2382                        bool fec_enable)
2383 {
2384         u32 data_clock = bits_per_pixel * pixel_clock;
2385
2386         if (fec_enable)
2387                 data_clock = intel_dp_mode_to_fec_clock(data_clock);
2388
2389         /*
2390          * Windows/BIOS uses fixed M/N values always. Follow suit.
2391          *
2392          * Also several DP dongles in particular seem to be fussy
2393          * about too large link M/N values. Presumably the 20bit
2394          * value used by Windows/BIOS is acceptable to everyone.
2395          */
2396         m_n->tu = 64;
2397         compute_m_n(&m_n->data_m, &m_n->data_n,
2398                     data_clock, link_clock * nlanes * 8,
2399                     0x8000000);
2400
2401         compute_m_n(&m_n->link_m, &m_n->link_n,
2402                     pixel_clock, link_clock,
2403                     0x80000);
2404 }
2405
2406 void intel_panel_sanitize_ssc(struct drm_i915_private *dev_priv)
2407 {
2408         /*
2409          * There may be no VBT; and if the BIOS enabled SSC we can
2410          * just keep using it to avoid unnecessary flicker.  Whereas if the
2411          * BIOS isn't using it, don't assume it will work even if the VBT
2412          * indicates as much.
2413          */
2414         if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
2415                 bool bios_lvds_use_ssc = intel_de_read(dev_priv,
2416                                                        PCH_DREF_CONTROL) &
2417                         DREF_SSC1_ENABLE;
2418
2419                 if (dev_priv->display.vbt.lvds_use_ssc != bios_lvds_use_ssc) {
2420                         drm_dbg_kms(&dev_priv->drm,
2421                                     "SSC %s by BIOS, overriding VBT which says %s\n",
2422                                     str_enabled_disabled(bios_lvds_use_ssc),
2423                                     str_enabled_disabled(dev_priv->display.vbt.lvds_use_ssc));
2424                         dev_priv->display.vbt.lvds_use_ssc = bios_lvds_use_ssc;
2425                 }
2426         }
2427 }
2428
2429 void intel_zero_m_n(struct intel_link_m_n *m_n)
2430 {
2431         /* corresponds to 0 register value */
2432         memset(m_n, 0, sizeof(*m_n));
2433         m_n->tu = 1;
2434 }
2435
2436 void intel_set_m_n(struct drm_i915_private *i915,
2437                    const struct intel_link_m_n *m_n,
2438                    i915_reg_t data_m_reg, i915_reg_t data_n_reg,
2439                    i915_reg_t link_m_reg, i915_reg_t link_n_reg)
2440 {
2441         intel_de_write(i915, data_m_reg, TU_SIZE(m_n->tu) | m_n->data_m);
2442         intel_de_write(i915, data_n_reg, m_n->data_n);
2443         intel_de_write(i915, link_m_reg, m_n->link_m);
2444         /*
2445          * On BDW+ writing LINK_N arms the double buffered update
2446          * of all the M/N registers, so it must be written last.
2447          */
2448         intel_de_write(i915, link_n_reg, m_n->link_n);
2449 }
2450
2451 bool intel_cpu_transcoder_has_m2_n2(struct drm_i915_private *dev_priv,
2452                                     enum transcoder transcoder)
2453 {
2454         if (IS_HASWELL(dev_priv))
2455                 return transcoder == TRANSCODER_EDP;
2456
2457         return IS_DISPLAY_VER(dev_priv, 5, 7) || IS_CHERRYVIEW(dev_priv);
2458 }
2459
2460 void intel_cpu_transcoder_set_m1_n1(struct intel_crtc *crtc,
2461                                     enum transcoder transcoder,
2462                                     const struct intel_link_m_n *m_n)
2463 {
2464         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2465         enum pipe pipe = crtc->pipe;
2466
2467         if (DISPLAY_VER(dev_priv) >= 5)
2468                 intel_set_m_n(dev_priv, m_n,
2469                               PIPE_DATA_M1(transcoder), PIPE_DATA_N1(transcoder),
2470                               PIPE_LINK_M1(transcoder), PIPE_LINK_N1(transcoder));
2471         else
2472                 intel_set_m_n(dev_priv, m_n,
2473                               PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe),
2474                               PIPE_LINK_M_G4X(pipe), PIPE_LINK_N_G4X(pipe));
2475 }
2476
2477 void intel_cpu_transcoder_set_m2_n2(struct intel_crtc *crtc,
2478                                     enum transcoder transcoder,
2479                                     const struct intel_link_m_n *m_n)
2480 {
2481         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2482
2483         if (!intel_cpu_transcoder_has_m2_n2(dev_priv, transcoder))
2484                 return;
2485
2486         intel_set_m_n(dev_priv, m_n,
2487                       PIPE_DATA_M2(transcoder), PIPE_DATA_N2(transcoder),
2488                       PIPE_LINK_M2(transcoder), PIPE_LINK_N2(transcoder));
2489 }
2490
2491 static void intel_set_transcoder_timings(const struct intel_crtc_state *crtc_state)
2492 {
2493         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2494         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2495         enum pipe pipe = crtc->pipe;
2496         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2497         const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
2498         u32 crtc_vdisplay, crtc_vtotal, crtc_vblank_start, crtc_vblank_end;
2499         int vsyncshift = 0;
2500
2501         /* We need to be careful not to changed the adjusted mode, for otherwise
2502          * the hw state checker will get angry at the mismatch. */
2503         crtc_vdisplay = adjusted_mode->crtc_vdisplay;
2504         crtc_vtotal = adjusted_mode->crtc_vtotal;
2505         crtc_vblank_start = adjusted_mode->crtc_vblank_start;
2506         crtc_vblank_end = adjusted_mode->crtc_vblank_end;
2507
2508         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
2509                 /* the chip adds 2 halflines automatically */
2510                 crtc_vtotal -= 1;
2511                 crtc_vblank_end -= 1;
2512
2513                 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
2514                         vsyncshift = (adjusted_mode->crtc_htotal - 1) / 2;
2515                 else
2516                         vsyncshift = adjusted_mode->crtc_hsync_start -
2517                                 adjusted_mode->crtc_htotal / 2;
2518                 if (vsyncshift < 0)
2519                         vsyncshift += adjusted_mode->crtc_htotal;
2520         }
2521
2522         /*
2523          * VBLANK_START no longer works on ADL+, instead we must use
2524          * TRANS_SET_CONTEXT_LATENCY to configure the pipe vblank start.
2525          */
2526         if (DISPLAY_VER(dev_priv) >= 13) {
2527                 intel_de_write(dev_priv, TRANS_SET_CONTEXT_LATENCY(cpu_transcoder),
2528                                crtc_vblank_start - crtc_vdisplay);
2529
2530                 /*
2531                  * VBLANK_START not used by hw, just clear it
2532                  * to make it stand out in register dumps.
2533                  */
2534                 crtc_vblank_start = 1;
2535         }
2536
2537         if (DISPLAY_VER(dev_priv) > 3)
2538                 intel_de_write(dev_priv, TRANS_VSYNCSHIFT(cpu_transcoder),
2539                                vsyncshift);
2540
2541         intel_de_write(dev_priv, TRANS_HTOTAL(cpu_transcoder),
2542                        HACTIVE(adjusted_mode->crtc_hdisplay - 1) |
2543                        HTOTAL(adjusted_mode->crtc_htotal - 1));
2544         intel_de_write(dev_priv, TRANS_HBLANK(cpu_transcoder),
2545                        HBLANK_START(adjusted_mode->crtc_hblank_start - 1) |
2546                        HBLANK_END(adjusted_mode->crtc_hblank_end - 1));
2547         intel_de_write(dev_priv, TRANS_HSYNC(cpu_transcoder),
2548                        HSYNC_START(adjusted_mode->crtc_hsync_start - 1) |
2549                        HSYNC_END(adjusted_mode->crtc_hsync_end - 1));
2550
2551         intel_de_write(dev_priv, TRANS_VTOTAL(cpu_transcoder),
2552                        VACTIVE(crtc_vdisplay - 1) |
2553                        VTOTAL(crtc_vtotal - 1));
2554         intel_de_write(dev_priv, TRANS_VBLANK(cpu_transcoder),
2555                        VBLANK_START(crtc_vblank_start - 1) |
2556                        VBLANK_END(crtc_vblank_end - 1));
2557         intel_de_write(dev_priv, TRANS_VSYNC(cpu_transcoder),
2558                        VSYNC_START(adjusted_mode->crtc_vsync_start - 1) |
2559                        VSYNC_END(adjusted_mode->crtc_vsync_end - 1));
2560
2561         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
2562          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
2563          * documented on the DDI_FUNC_CTL register description, EDP Input Select
2564          * bits. */
2565         if (IS_HASWELL(dev_priv) && cpu_transcoder == TRANSCODER_EDP &&
2566             (pipe == PIPE_B || pipe == PIPE_C))
2567                 intel_de_write(dev_priv, TRANS_VTOTAL(pipe),
2568                                VACTIVE(crtc_vdisplay - 1) |
2569                                VTOTAL(crtc_vtotal - 1));
2570 }
2571
2572 static void intel_set_pipe_src_size(const struct intel_crtc_state *crtc_state)
2573 {
2574         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2575         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2576         int width = drm_rect_width(&crtc_state->pipe_src);
2577         int height = drm_rect_height(&crtc_state->pipe_src);
2578         enum pipe pipe = crtc->pipe;
2579
2580         /* pipesrc controls the size that is scaled from, which should
2581          * always be the user's requested size.
2582          */
2583         intel_de_write(dev_priv, PIPESRC(pipe),
2584                        PIPESRC_WIDTH(width - 1) | PIPESRC_HEIGHT(height - 1));
2585 }
2586
2587 static bool intel_pipe_is_interlaced(const struct intel_crtc_state *crtc_state)
2588 {
2589         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
2590         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2591
2592         if (DISPLAY_VER(dev_priv) == 2)
2593                 return false;
2594
2595         if (DISPLAY_VER(dev_priv) >= 9 ||
2596             IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
2597                 return intel_de_read(dev_priv, TRANSCONF(cpu_transcoder)) & TRANSCONF_INTERLACE_MASK_HSW;
2598         else
2599                 return intel_de_read(dev_priv, TRANSCONF(cpu_transcoder)) & TRANSCONF_INTERLACE_MASK;
2600 }
2601
2602 static void intel_get_transcoder_timings(struct intel_crtc *crtc,
2603                                          struct intel_crtc_state *pipe_config)
2604 {
2605         struct drm_device *dev = crtc->base.dev;
2606         struct drm_i915_private *dev_priv = to_i915(dev);
2607         enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
2608         struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
2609         u32 tmp;
2610
2611         tmp = intel_de_read(dev_priv, TRANS_HTOTAL(cpu_transcoder));
2612         adjusted_mode->crtc_hdisplay = REG_FIELD_GET(HACTIVE_MASK, tmp) + 1;
2613         adjusted_mode->crtc_htotal = REG_FIELD_GET(HTOTAL_MASK, tmp) + 1;
2614
2615         if (!transcoder_is_dsi(cpu_transcoder)) {
2616                 tmp = intel_de_read(dev_priv, TRANS_HBLANK(cpu_transcoder));
2617                 adjusted_mode->crtc_hblank_start = REG_FIELD_GET(HBLANK_START_MASK, tmp) + 1;
2618                 adjusted_mode->crtc_hblank_end = REG_FIELD_GET(HBLANK_END_MASK, tmp) + 1;
2619         }
2620
2621         tmp = intel_de_read(dev_priv, TRANS_HSYNC(cpu_transcoder));
2622         adjusted_mode->crtc_hsync_start = REG_FIELD_GET(HSYNC_START_MASK, tmp) + 1;
2623         adjusted_mode->crtc_hsync_end = REG_FIELD_GET(HSYNC_END_MASK, tmp) + 1;
2624
2625         tmp = intel_de_read(dev_priv, TRANS_VTOTAL(cpu_transcoder));
2626         adjusted_mode->crtc_vdisplay = REG_FIELD_GET(VACTIVE_MASK, tmp) + 1;
2627         adjusted_mode->crtc_vtotal = REG_FIELD_GET(VTOTAL_MASK, tmp) + 1;
2628
2629         /* FIXME TGL+ DSI transcoders have this! */
2630         if (!transcoder_is_dsi(cpu_transcoder)) {
2631                 tmp = intel_de_read(dev_priv, TRANS_VBLANK(cpu_transcoder));
2632                 adjusted_mode->crtc_vblank_start = REG_FIELD_GET(VBLANK_START_MASK, tmp) + 1;
2633                 adjusted_mode->crtc_vblank_end = REG_FIELD_GET(VBLANK_END_MASK, tmp) + 1;
2634         }
2635         tmp = intel_de_read(dev_priv, TRANS_VSYNC(cpu_transcoder));
2636         adjusted_mode->crtc_vsync_start = REG_FIELD_GET(VSYNC_START_MASK, tmp) + 1;
2637         adjusted_mode->crtc_vsync_end = REG_FIELD_GET(VSYNC_END_MASK, tmp) + 1;
2638
2639         if (intel_pipe_is_interlaced(pipe_config)) {
2640                 adjusted_mode->flags |= DRM_MODE_FLAG_INTERLACE;
2641                 adjusted_mode->crtc_vtotal += 1;
2642                 adjusted_mode->crtc_vblank_end += 1;
2643         }
2644
2645         if (DISPLAY_VER(dev_priv) >= 13 && !transcoder_is_dsi(cpu_transcoder))
2646                 adjusted_mode->crtc_vblank_start =
2647                         adjusted_mode->crtc_vdisplay +
2648                         intel_de_read(dev_priv, TRANS_SET_CONTEXT_LATENCY(cpu_transcoder));
2649 }
2650
2651 static void intel_bigjoiner_adjust_pipe_src(struct intel_crtc_state *crtc_state)
2652 {
2653         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2654         int num_pipes = intel_bigjoiner_num_pipes(crtc_state);
2655         enum pipe master_pipe, pipe = crtc->pipe;
2656         int width;
2657
2658         if (num_pipes < 2)
2659                 return;
2660
2661         master_pipe = bigjoiner_master_pipe(crtc_state);
2662         width = drm_rect_width(&crtc_state->pipe_src);
2663
2664         drm_rect_translate_to(&crtc_state->pipe_src,
2665                               (pipe - master_pipe) * width, 0);
2666 }
2667
2668 static void intel_get_pipe_src_size(struct intel_crtc *crtc,
2669                                     struct intel_crtc_state *pipe_config)
2670 {
2671         struct drm_device *dev = crtc->base.dev;
2672         struct drm_i915_private *dev_priv = to_i915(dev);
2673         u32 tmp;
2674
2675         tmp = intel_de_read(dev_priv, PIPESRC(crtc->pipe));
2676
2677         drm_rect_init(&pipe_config->pipe_src, 0, 0,
2678                       REG_FIELD_GET(PIPESRC_WIDTH_MASK, tmp) + 1,
2679                       REG_FIELD_GET(PIPESRC_HEIGHT_MASK, tmp) + 1);
2680
2681         intel_bigjoiner_adjust_pipe_src(pipe_config);
2682 }
2683
2684 void i9xx_set_pipeconf(const struct intel_crtc_state *crtc_state)
2685 {
2686         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2687         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2688         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
2689         u32 val = 0;
2690
2691         /*
2692          * - We keep both pipes enabled on 830
2693          * - During modeset the pipe is still disabled and must remain so
2694          * - During fastset the pipe is already enabled and must remain so
2695          */
2696         if (IS_I830(dev_priv) || !intel_crtc_needs_modeset(crtc_state))
2697                 val |= TRANSCONF_ENABLE;
2698
2699         if (crtc_state->double_wide)
2700                 val |= TRANSCONF_DOUBLE_WIDE;
2701
2702         /* only g4x and later have fancy bpc/dither controls */
2703         if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
2704             IS_CHERRYVIEW(dev_priv)) {
2705                 /* Bspec claims that we can't use dithering for 30bpp pipes. */
2706                 if (crtc_state->dither && crtc_state->pipe_bpp != 30)
2707                         val |= TRANSCONF_DITHER_EN |
2708                                 TRANSCONF_DITHER_TYPE_SP;
2709
2710                 switch (crtc_state->pipe_bpp) {
2711                 default:
2712                         /* Case prevented by intel_choose_pipe_bpp_dither. */
2713                         MISSING_CASE(crtc_state->pipe_bpp);
2714                         fallthrough;
2715                 case 18:
2716                         val |= TRANSCONF_BPC_6;
2717                         break;
2718                 case 24:
2719                         val |= TRANSCONF_BPC_8;
2720                         break;
2721                 case 30:
2722                         val |= TRANSCONF_BPC_10;
2723                         break;
2724                 }
2725         }
2726
2727         if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
2728                 if (DISPLAY_VER(dev_priv) < 4 ||
2729                     intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
2730                         val |= TRANSCONF_INTERLACE_W_FIELD_INDICATION;
2731                 else
2732                         val |= TRANSCONF_INTERLACE_W_SYNC_SHIFT;
2733         } else {
2734                 val |= TRANSCONF_INTERLACE_PROGRESSIVE;
2735         }
2736
2737         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
2738              crtc_state->limited_color_range)
2739                 val |= TRANSCONF_COLOR_RANGE_SELECT;
2740
2741         val |= TRANSCONF_GAMMA_MODE(crtc_state->gamma_mode);
2742
2743         if (crtc_state->wgc_enable)
2744                 val |= TRANSCONF_WGC_ENABLE;
2745
2746         val |= TRANSCONF_FRAME_START_DELAY(crtc_state->framestart_delay - 1);
2747
2748         intel_de_write(dev_priv, TRANSCONF(cpu_transcoder), val);
2749         intel_de_posting_read(dev_priv, TRANSCONF(cpu_transcoder));
2750 }
2751
2752 static bool i9xx_has_pfit(struct drm_i915_private *dev_priv)
2753 {
2754         if (IS_I830(dev_priv))
2755                 return false;
2756
2757         return DISPLAY_VER(dev_priv) >= 4 ||
2758                 IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv);
2759 }
2760
2761 static void i9xx_get_pfit_config(struct intel_crtc_state *crtc_state)
2762 {
2763         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2764         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2765         enum pipe pipe;
2766         u32 tmp;
2767
2768         if (!i9xx_has_pfit(dev_priv))
2769                 return;
2770
2771         tmp = intel_de_read(dev_priv, PFIT_CONTROL);
2772         if (!(tmp & PFIT_ENABLE))
2773                 return;
2774
2775         /* Check whether the pfit is attached to our pipe. */
2776         if (DISPLAY_VER(dev_priv) >= 4)
2777                 pipe = REG_FIELD_GET(PFIT_PIPE_MASK, tmp);
2778         else
2779                 pipe = PIPE_B;
2780
2781         if (pipe != crtc->pipe)
2782                 return;
2783
2784         crtc_state->gmch_pfit.control = tmp;
2785         crtc_state->gmch_pfit.pgm_ratios =
2786                 intel_de_read(dev_priv, PFIT_PGM_RATIOS);
2787 }
2788
2789 static void vlv_crtc_clock_get(struct intel_crtc *crtc,
2790                                struct intel_crtc_state *pipe_config)
2791 {
2792         struct drm_device *dev = crtc->base.dev;
2793         struct drm_i915_private *dev_priv = to_i915(dev);
2794         enum pipe pipe = crtc->pipe;
2795         struct dpll clock;
2796         u32 mdiv;
2797         int refclk = 100000;
2798
2799         /* In case of DSI, DPLL will not be used */
2800         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
2801                 return;
2802
2803         vlv_dpio_get(dev_priv);
2804         mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
2805         vlv_dpio_put(dev_priv);
2806
2807         clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
2808         clock.m2 = mdiv & DPIO_M2DIV_MASK;
2809         clock.n = (mdiv >> DPIO_N_SHIFT) & 0xf;
2810         clock.p1 = (mdiv >> DPIO_P1_SHIFT) & 7;
2811         clock.p2 = (mdiv >> DPIO_P2_SHIFT) & 0x1f;
2812
2813         pipe_config->port_clock = vlv_calc_dpll_params(refclk, &clock);
2814 }
2815
2816 static void chv_crtc_clock_get(struct intel_crtc *crtc,
2817                                struct intel_crtc_state *pipe_config)
2818 {
2819         struct drm_device *dev = crtc->base.dev;
2820         struct drm_i915_private *dev_priv = to_i915(dev);
2821         enum pipe pipe = crtc->pipe;
2822         enum dpio_channel port = vlv_pipe_to_channel(pipe);
2823         struct dpll clock;
2824         u32 cmn_dw13, pll_dw0, pll_dw1, pll_dw2, pll_dw3;
2825         int refclk = 100000;
2826
2827         /* In case of DSI, DPLL will not be used */
2828         if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
2829                 return;
2830
2831         vlv_dpio_get(dev_priv);
2832         cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
2833         pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
2834         pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
2835         pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
2836         pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
2837         vlv_dpio_put(dev_priv);
2838
2839         clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
2840         clock.m2 = (pll_dw0 & 0xff) << 22;
2841         if (pll_dw3 & DPIO_CHV_FRAC_DIV_EN)
2842                 clock.m2 |= pll_dw2 & 0x3fffff;
2843         clock.n = (pll_dw1 >> DPIO_CHV_N_DIV_SHIFT) & 0xf;
2844         clock.p1 = (cmn_dw13 >> DPIO_CHV_P1_DIV_SHIFT) & 0x7;
2845         clock.p2 = (cmn_dw13 >> DPIO_CHV_P2_DIV_SHIFT) & 0x1f;
2846
2847         pipe_config->port_clock = chv_calc_dpll_params(refclk, &clock);
2848 }
2849
2850 static enum intel_output_format
2851 bdw_get_pipe_misc_output_format(struct intel_crtc *crtc)
2852 {
2853         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2854         u32 tmp;
2855
2856         tmp = intel_de_read(dev_priv, PIPE_MISC(crtc->pipe));
2857
2858         if (tmp & PIPE_MISC_YUV420_ENABLE) {
2859                 /* We support 4:2:0 in full blend mode only */
2860                 drm_WARN_ON(&dev_priv->drm,
2861                             (tmp & PIPE_MISC_YUV420_MODE_FULL_BLEND) == 0);
2862
2863                 return INTEL_OUTPUT_FORMAT_YCBCR420;
2864         } else if (tmp & PIPE_MISC_OUTPUT_COLORSPACE_YUV) {
2865                 return INTEL_OUTPUT_FORMAT_YCBCR444;
2866         } else {
2867                 return INTEL_OUTPUT_FORMAT_RGB;
2868         }
2869 }
2870
2871 static void i9xx_get_pipe_color_config(struct intel_crtc_state *crtc_state)
2872 {
2873         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2874         struct intel_plane *plane = to_intel_plane(crtc->base.primary);
2875         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2876         enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
2877         u32 tmp;
2878
2879         tmp = intel_de_read(dev_priv, DSPCNTR(i9xx_plane));
2880
2881         if (tmp & DISP_PIPE_GAMMA_ENABLE)
2882                 crtc_state->gamma_enable = true;
2883
2884         if (!HAS_GMCH(dev_priv) &&
2885             tmp & DISP_PIPE_CSC_ENABLE)
2886                 crtc_state->csc_enable = true;
2887 }
2888
2889 static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
2890                                  struct intel_crtc_state *pipe_config)
2891 {
2892         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2893         enum intel_display_power_domain power_domain;
2894         intel_wakeref_t wakeref;
2895         u32 tmp;
2896         bool ret;
2897
2898         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
2899         wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
2900         if (!wakeref)
2901                 return false;
2902
2903         pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
2904         pipe_config->sink_format = pipe_config->output_format;
2905         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
2906         pipe_config->shared_dpll = NULL;
2907
2908         ret = false;
2909
2910         tmp = intel_de_read(dev_priv, TRANSCONF(pipe_config->cpu_transcoder));
2911         if (!(tmp & TRANSCONF_ENABLE))
2912                 goto out;
2913
2914         if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
2915             IS_CHERRYVIEW(dev_priv)) {
2916                 switch (tmp & TRANSCONF_BPC_MASK) {
2917                 case TRANSCONF_BPC_6:
2918                         pipe_config->pipe_bpp = 18;
2919                         break;
2920                 case TRANSCONF_BPC_8:
2921                         pipe_config->pipe_bpp = 24;
2922                         break;
2923                 case TRANSCONF_BPC_10:
2924                         pipe_config->pipe_bpp = 30;
2925                         break;
2926                 default:
2927                         MISSING_CASE(tmp);
2928                         break;
2929                 }
2930         }
2931
2932         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
2933             (tmp & TRANSCONF_COLOR_RANGE_SELECT))
2934                 pipe_config->limited_color_range = true;
2935
2936         pipe_config->gamma_mode = REG_FIELD_GET(TRANSCONF_GAMMA_MODE_MASK_I9XX, tmp);
2937
2938         pipe_config->framestart_delay = REG_FIELD_GET(TRANSCONF_FRAME_START_DELAY_MASK, tmp) + 1;
2939
2940         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
2941             (tmp & TRANSCONF_WGC_ENABLE))
2942                 pipe_config->wgc_enable = true;
2943
2944         if (IS_CHERRYVIEW(dev_priv))
2945                 pipe_config->cgm_mode = intel_de_read(dev_priv,
2946                                                       CGM_PIPE_MODE(crtc->pipe));
2947
2948         i9xx_get_pipe_color_config(pipe_config);
2949         intel_color_get_config(pipe_config);
2950
2951         if (DISPLAY_VER(dev_priv) < 4)
2952                 pipe_config->double_wide = tmp & TRANSCONF_DOUBLE_WIDE;
2953
2954         intel_get_transcoder_timings(crtc, pipe_config);
2955         intel_get_pipe_src_size(crtc, pipe_config);
2956
2957         i9xx_get_pfit_config(pipe_config);
2958
2959         if (DISPLAY_VER(dev_priv) >= 4) {
2960                 /* No way to read it out on pipes B and C */
2961                 if (IS_CHERRYVIEW(dev_priv) && crtc->pipe != PIPE_A)
2962                         tmp = dev_priv->display.state.chv_dpll_md[crtc->pipe];
2963                 else
2964                         tmp = intel_de_read(dev_priv, DPLL_MD(crtc->pipe));
2965                 pipe_config->pixel_multiplier =
2966                         ((tmp & DPLL_MD_UDI_MULTIPLIER_MASK)
2967                          >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
2968                 pipe_config->dpll_hw_state.dpll_md = tmp;
2969         } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
2970                    IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
2971                 tmp = intel_de_read(dev_priv, DPLL(crtc->pipe));
2972                 pipe_config->pixel_multiplier =
2973                         ((tmp & SDVO_MULTIPLIER_MASK)
2974                          >> SDVO_MULTIPLIER_SHIFT_HIRES) + 1;
2975         } else {
2976                 /* Note that on i915G/GM the pixel multiplier is in the sdvo
2977                  * port and will be fixed up in the encoder->get_config
2978                  * function. */
2979                 pipe_config->pixel_multiplier = 1;
2980         }
2981         pipe_config->dpll_hw_state.dpll = intel_de_read(dev_priv,
2982                                                         DPLL(crtc->pipe));
2983         if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv)) {
2984                 pipe_config->dpll_hw_state.fp0 = intel_de_read(dev_priv,
2985                                                                FP0(crtc->pipe));
2986                 pipe_config->dpll_hw_state.fp1 = intel_de_read(dev_priv,
2987                                                                FP1(crtc->pipe));
2988         } else {
2989                 /* Mask out read-only status bits. */
2990                 pipe_config->dpll_hw_state.dpll &= ~(DPLL_LOCK_VLV |
2991                                                      DPLL_PORTC_READY_MASK |
2992                                                      DPLL_PORTB_READY_MASK);
2993         }
2994
2995         if (IS_CHERRYVIEW(dev_priv))
2996                 chv_crtc_clock_get(crtc, pipe_config);
2997         else if (IS_VALLEYVIEW(dev_priv))
2998                 vlv_crtc_clock_get(crtc, pipe_config);
2999         else
3000                 i9xx_crtc_clock_get(crtc, pipe_config);
3001
3002         /*
3003          * Normally the dotclock is filled in by the encoder .get_config()
3004          * but in case the pipe is enabled w/o any ports we need a sane
3005          * default.
3006          */
3007         pipe_config->hw.adjusted_mode.crtc_clock =
3008                 pipe_config->port_clock / pipe_config->pixel_multiplier;
3009
3010         ret = true;
3011
3012 out:
3013         intel_display_power_put(dev_priv, power_domain, wakeref);
3014
3015         return ret;
3016 }
3017
3018 void ilk_set_pipeconf(const struct intel_crtc_state *crtc_state)
3019 {
3020         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3021         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3022         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
3023         u32 val = 0;
3024
3025         /*
3026          * - During modeset the pipe is still disabled and must remain so
3027          * - During fastset the pipe is already enabled and must remain so
3028          */
3029         if (!intel_crtc_needs_modeset(crtc_state))
3030                 val |= TRANSCONF_ENABLE;
3031
3032         switch (crtc_state->pipe_bpp) {
3033         default:
3034                 /* Case prevented by intel_choose_pipe_bpp_dither. */
3035                 MISSING_CASE(crtc_state->pipe_bpp);
3036                 fallthrough;
3037         case 18:
3038                 val |= TRANSCONF_BPC_6;
3039                 break;
3040         case 24:
3041                 val |= TRANSCONF_BPC_8;
3042                 break;
3043         case 30:
3044                 val |= TRANSCONF_BPC_10;
3045                 break;
3046         case 36:
3047                 val |= TRANSCONF_BPC_12;
3048                 break;
3049         }
3050
3051         if (crtc_state->dither)
3052                 val |= TRANSCONF_DITHER_EN | TRANSCONF_DITHER_TYPE_SP;
3053
3054         if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
3055                 val |= TRANSCONF_INTERLACE_IF_ID_ILK;
3056         else
3057                 val |= TRANSCONF_INTERLACE_PF_PD_ILK;
3058
3059         /*
3060          * This would end up with an odd purple hue over
3061          * the entire display. Make sure we don't do it.
3062          */
3063         drm_WARN_ON(&dev_priv->drm, crtc_state->limited_color_range &&
3064                     crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB);
3065
3066         if (crtc_state->limited_color_range &&
3067             !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO))
3068                 val |= TRANSCONF_COLOR_RANGE_SELECT;
3069
3070         if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
3071                 val |= TRANSCONF_OUTPUT_COLORSPACE_YUV709;
3072
3073         val |= TRANSCONF_GAMMA_MODE(crtc_state->gamma_mode);
3074
3075         val |= TRANSCONF_FRAME_START_DELAY(crtc_state->framestart_delay - 1);
3076         val |= TRANSCONF_MSA_TIMING_DELAY(crtc_state->msa_timing_delay);
3077
3078         intel_de_write(dev_priv, TRANSCONF(cpu_transcoder), val);
3079         intel_de_posting_read(dev_priv, TRANSCONF(cpu_transcoder));
3080 }
3081
3082 static void hsw_set_transconf(const struct intel_crtc_state *crtc_state)
3083 {
3084         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3085         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3086         enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
3087         u32 val = 0;
3088
3089         /*
3090          * - During modeset the pipe is still disabled and must remain so
3091          * - During fastset the pipe is already enabled and must remain so
3092          */
3093         if (!intel_crtc_needs_modeset(crtc_state))
3094                 val |= TRANSCONF_ENABLE;
3095
3096         if (IS_HASWELL(dev_priv) && crtc_state->dither)
3097                 val |= TRANSCONF_DITHER_EN | TRANSCONF_DITHER_TYPE_SP;
3098
3099         if (crtc_state->hw.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
3100                 val |= TRANSCONF_INTERLACE_IF_ID_ILK;
3101         else
3102                 val |= TRANSCONF_INTERLACE_PF_PD_ILK;
3103
3104         if (IS_HASWELL(dev_priv) &&
3105             crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB)
3106                 val |= TRANSCONF_OUTPUT_COLORSPACE_YUV_HSW;
3107
3108         intel_de_write(dev_priv, TRANSCONF(cpu_transcoder), val);
3109         intel_de_posting_read(dev_priv, TRANSCONF(cpu_transcoder));
3110 }
3111
3112 static void bdw_set_pipe_misc(const struct intel_crtc_state *crtc_state)
3113 {
3114         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3115         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3116         u32 val = 0;
3117
3118         switch (crtc_state->pipe_bpp) {
3119         case 18:
3120                 val |= PIPE_MISC_BPC_6;
3121                 break;
3122         case 24:
3123                 val |= PIPE_MISC_BPC_8;
3124                 break;
3125         case 30:
3126                 val |= PIPE_MISC_BPC_10;
3127                 break;
3128         case 36:
3129                 /* Port output 12BPC defined for ADLP+ */
3130                 if (DISPLAY_VER(dev_priv) > 12)
3131                         val |= PIPE_MISC_BPC_12_ADLP;
3132                 break;
3133         default:
3134                 MISSING_CASE(crtc_state->pipe_bpp);
3135                 break;
3136         }
3137
3138         if (crtc_state->dither)
3139                 val |= PIPE_MISC_DITHER_ENABLE | PIPE_MISC_DITHER_TYPE_SP;
3140
3141         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 ||
3142             crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444)
3143                 val |= PIPE_MISC_OUTPUT_COLORSPACE_YUV;
3144
3145         if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420)
3146                 val |= PIPE_MISC_YUV420_ENABLE |
3147                         PIPE_MISC_YUV420_MODE_FULL_BLEND;
3148
3149         if (DISPLAY_VER(dev_priv) >= 11 && is_hdr_mode(crtc_state))
3150                 val |= PIPE_MISC_HDR_MODE_PRECISION;
3151
3152         if (DISPLAY_VER(dev_priv) >= 12)
3153                 val |= PIPE_MISC_PIXEL_ROUNDING_TRUNC;
3154
3155         intel_de_write(dev_priv, PIPE_MISC(crtc->pipe), val);
3156 }
3157
3158 int bdw_get_pipe_misc_bpp(struct intel_crtc *crtc)
3159 {
3160         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3161         u32 tmp;
3162
3163         tmp = intel_de_read(dev_priv, PIPE_MISC(crtc->pipe));
3164
3165         switch (tmp & PIPE_MISC_BPC_MASK) {
3166         case PIPE_MISC_BPC_6:
3167                 return 18;
3168         case PIPE_MISC_BPC_8:
3169                 return 24;
3170         case PIPE_MISC_BPC_10:
3171                 return 30;
3172         /*
3173          * PORT OUTPUT 12 BPC defined for ADLP+.
3174          *
3175          * TODO:
3176          * For previous platforms with DSI interface, bits 5:7
3177          * are used for storing pipe_bpp irrespective of dithering.
3178          * Since the value of 12 BPC is not defined for these bits
3179          * on older platforms, need to find a workaround for 12 BPC
3180          * MIPI DSI HW readout.
3181          */
3182         case PIPE_MISC_BPC_12_ADLP:
3183                 if (DISPLAY_VER(dev_priv) > 12)
3184                         return 36;
3185                 fallthrough;
3186         default:
3187                 MISSING_CASE(tmp);
3188                 return 0;
3189         }
3190 }
3191
3192 int ilk_get_lanes_required(int target_clock, int link_bw, int bpp)
3193 {
3194         /*
3195          * Account for spread spectrum to avoid
3196          * oversubscribing the link. Max center spread
3197          * is 2.5%; use 5% for safety's sake.
3198          */
3199         u32 bps = target_clock * bpp * 21 / 20;
3200         return DIV_ROUND_UP(bps, link_bw * 8);
3201 }
3202
3203 void intel_get_m_n(struct drm_i915_private *i915,
3204                    struct intel_link_m_n *m_n,
3205                    i915_reg_t data_m_reg, i915_reg_t data_n_reg,
3206                    i915_reg_t link_m_reg, i915_reg_t link_n_reg)
3207 {
3208         m_n->link_m = intel_de_read(i915, link_m_reg) & DATA_LINK_M_N_MASK;
3209         m_n->link_n = intel_de_read(i915, link_n_reg) & DATA_LINK_M_N_MASK;
3210         m_n->data_m = intel_de_read(i915, data_m_reg) & DATA_LINK_M_N_MASK;
3211         m_n->data_n = intel_de_read(i915, data_n_reg) & DATA_LINK_M_N_MASK;
3212         m_n->tu = REG_FIELD_GET(TU_SIZE_MASK, intel_de_read(i915, data_m_reg)) + 1;
3213 }
3214
3215 void intel_cpu_transcoder_get_m1_n1(struct intel_crtc *crtc,
3216                                     enum transcoder transcoder,
3217                                     struct intel_link_m_n *m_n)
3218 {
3219         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3220         enum pipe pipe = crtc->pipe;
3221
3222         if (DISPLAY_VER(dev_priv) >= 5)
3223                 intel_get_m_n(dev_priv, m_n,
3224                               PIPE_DATA_M1(transcoder), PIPE_DATA_N1(transcoder),
3225                               PIPE_LINK_M1(transcoder), PIPE_LINK_N1(transcoder));
3226         else
3227                 intel_get_m_n(dev_priv, m_n,
3228                               PIPE_DATA_M_G4X(pipe), PIPE_DATA_N_G4X(pipe),
3229                               PIPE_LINK_M_G4X(pipe), PIPE_LINK_N_G4X(pipe));
3230 }
3231
3232 void intel_cpu_transcoder_get_m2_n2(struct intel_crtc *crtc,
3233                                     enum transcoder transcoder,
3234                                     struct intel_link_m_n *m_n)
3235 {
3236         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3237
3238         if (!intel_cpu_transcoder_has_m2_n2(dev_priv, transcoder))
3239                 return;
3240
3241         intel_get_m_n(dev_priv, m_n,
3242                       PIPE_DATA_M2(transcoder), PIPE_DATA_N2(transcoder),
3243                       PIPE_LINK_M2(transcoder), PIPE_LINK_N2(transcoder));
3244 }
3245
3246 static void ilk_get_pfit_config(struct intel_crtc_state *crtc_state)
3247 {
3248         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3249         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3250         u32 ctl, pos, size;
3251         enum pipe pipe;
3252
3253         ctl = intel_de_read(dev_priv, PF_CTL(crtc->pipe));
3254         if ((ctl & PF_ENABLE) == 0)
3255                 return;
3256
3257         if (IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv))
3258                 pipe = REG_FIELD_GET(PF_PIPE_SEL_MASK_IVB, ctl);
3259         else
3260                 pipe = crtc->pipe;
3261
3262         crtc_state->pch_pfit.enabled = true;
3263
3264         pos = intel_de_read(dev_priv, PF_WIN_POS(crtc->pipe));
3265         size = intel_de_read(dev_priv, PF_WIN_SZ(crtc->pipe));
3266
3267         drm_rect_init(&crtc_state->pch_pfit.dst,
3268                       REG_FIELD_GET(PF_WIN_XPOS_MASK, pos),
3269                       REG_FIELD_GET(PF_WIN_YPOS_MASK, pos),
3270                       REG_FIELD_GET(PF_WIN_XSIZE_MASK, size),
3271                       REG_FIELD_GET(PF_WIN_YSIZE_MASK, size));
3272
3273         /*
3274          * We currently do not free assignements of panel fitters on
3275          * ivb/hsw (since we don't use the higher upscaling modes which
3276          * differentiates them) so just WARN about this case for now.
3277          */
3278         drm_WARN_ON(&dev_priv->drm, pipe != crtc->pipe);
3279 }
3280
3281 static bool ilk_get_pipe_config(struct intel_crtc *crtc,
3282                                 struct intel_crtc_state *pipe_config)
3283 {
3284         struct drm_device *dev = crtc->base.dev;
3285         struct drm_i915_private *dev_priv = to_i915(dev);
3286         enum intel_display_power_domain power_domain;
3287         intel_wakeref_t wakeref;
3288         u32 tmp;
3289         bool ret;
3290
3291         power_domain = POWER_DOMAIN_PIPE(crtc->pipe);
3292         wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
3293         if (!wakeref)
3294                 return false;
3295
3296         pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe;
3297         pipe_config->shared_dpll = NULL;
3298
3299         ret = false;
3300         tmp = intel_de_read(dev_priv, TRANSCONF(pipe_config->cpu_transcoder));
3301         if (!(tmp & TRANSCONF_ENABLE))
3302                 goto out;
3303
3304         switch (tmp & TRANSCONF_BPC_MASK) {
3305         case TRANSCONF_BPC_6:
3306                 pipe_config->pipe_bpp = 18;
3307                 break;
3308         case TRANSCONF_BPC_8:
3309                 pipe_config->pipe_bpp = 24;
3310                 break;
3311         case TRANSCONF_BPC_10:
3312                 pipe_config->pipe_bpp = 30;
3313                 break;
3314         case TRANSCONF_BPC_12:
3315                 pipe_config->pipe_bpp = 36;
3316                 break;
3317         default:
3318                 break;
3319         }
3320
3321         if (tmp & TRANSCONF_COLOR_RANGE_SELECT)
3322                 pipe_config->limited_color_range = true;
3323
3324         switch (tmp & TRANSCONF_OUTPUT_COLORSPACE_MASK) {
3325         case TRANSCONF_OUTPUT_COLORSPACE_YUV601:
3326         case TRANSCONF_OUTPUT_COLORSPACE_YUV709:
3327                 pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444;
3328                 break;
3329         default:
3330                 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
3331                 break;
3332         }
3333
3334         pipe_config->sink_format = pipe_config->output_format;
3335
3336         pipe_config->gamma_mode = REG_FIELD_GET(TRANSCONF_GAMMA_MODE_MASK_ILK, tmp);
3337
3338         pipe_config->framestart_delay = REG_FIELD_GET(TRANSCONF_FRAME_START_DELAY_MASK, tmp) + 1;
3339
3340         pipe_config->msa_timing_delay = REG_FIELD_GET(TRANSCONF_MSA_TIMING_DELAY_MASK, tmp);
3341
3342         pipe_config->csc_mode = intel_de_read(dev_priv,
3343                                               PIPE_CSC_MODE(crtc->pipe));
3344
3345         i9xx_get_pipe_color_config(pipe_config);
3346         intel_color_get_config(pipe_config);
3347
3348         pipe_config->pixel_multiplier = 1;
3349
3350         ilk_pch_get_config(pipe_config);
3351
3352         intel_get_transcoder_timings(crtc, pipe_config);
3353         intel_get_pipe_src_size(crtc, pipe_config);
3354
3355         ilk_get_pfit_config(pipe_config);
3356
3357         ret = true;
3358
3359 out:
3360         intel_display_power_put(dev_priv, power_domain, wakeref);
3361
3362         return ret;
3363 }
3364
3365 static u8 bigjoiner_pipes(struct drm_i915_private *i915)
3366 {
3367         u8 pipes;
3368
3369         if (DISPLAY_VER(i915) >= 12)
3370                 pipes = BIT(PIPE_A) | BIT(PIPE_B) | BIT(PIPE_C) | BIT(PIPE_D);
3371         else if (DISPLAY_VER(i915) >= 11)
3372                 pipes = BIT(PIPE_B) | BIT(PIPE_C);
3373         else
3374                 pipes = 0;
3375
3376         return pipes & DISPLAY_RUNTIME_INFO(i915)->pipe_mask;
3377 }
3378
3379 static bool transcoder_ddi_func_is_enabled(struct drm_i915_private *dev_priv,
3380                                            enum transcoder cpu_transcoder)
3381 {
3382         enum intel_display_power_domain power_domain;
3383         intel_wakeref_t wakeref;
3384         u32 tmp = 0;
3385
3386         power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
3387
3388         with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref)
3389                 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
3390
3391         return tmp & TRANS_DDI_FUNC_ENABLE;
3392 }
3393
3394 static void enabled_bigjoiner_pipes(struct drm_i915_private *dev_priv,
3395                                     u8 *master_pipes, u8 *slave_pipes)
3396 {
3397         struct intel_crtc *crtc;
3398
3399         *master_pipes = 0;
3400         *slave_pipes = 0;
3401
3402         for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc,
3403                                          bigjoiner_pipes(dev_priv)) {
3404                 enum intel_display_power_domain power_domain;
3405                 enum pipe pipe = crtc->pipe;
3406                 intel_wakeref_t wakeref;
3407
3408                 power_domain = intel_dsc_power_domain(crtc, (enum transcoder) pipe);
3409                 with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref) {
3410                         u32 tmp = intel_de_read(dev_priv, ICL_PIPE_DSS_CTL1(pipe));
3411
3412                         if (!(tmp & BIG_JOINER_ENABLE))
3413                                 continue;
3414
3415                         if (tmp & MASTER_BIG_JOINER_ENABLE)
3416                                 *master_pipes |= BIT(pipe);
3417                         else
3418                                 *slave_pipes |= BIT(pipe);
3419                 }
3420
3421                 if (DISPLAY_VER(dev_priv) < 13)
3422                         continue;
3423
3424                 power_domain = POWER_DOMAIN_PIPE(pipe);
3425                 with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref) {
3426                         u32 tmp = intel_de_read(dev_priv, ICL_PIPE_DSS_CTL1(pipe));
3427
3428                         if (tmp & UNCOMPRESSED_JOINER_MASTER)
3429                                 *master_pipes |= BIT(pipe);
3430                         if (tmp & UNCOMPRESSED_JOINER_SLAVE)
3431                                 *slave_pipes |= BIT(pipe);
3432                 }
3433         }
3434
3435         /* Bigjoiner pipes should always be consecutive master and slave */
3436         drm_WARN(&dev_priv->drm, *slave_pipes != *master_pipes << 1,
3437                  "Bigjoiner misconfigured (master pipes 0x%x, slave pipes 0x%x)\n",
3438                  *master_pipes, *slave_pipes);
3439 }
3440
3441 static enum pipe get_bigjoiner_master_pipe(enum pipe pipe, u8 master_pipes, u8 slave_pipes)
3442 {
3443         if ((slave_pipes & BIT(pipe)) == 0)
3444                 return pipe;
3445
3446         /* ignore everything above our pipe */
3447         master_pipes &= ~GENMASK(7, pipe);
3448
3449         /* highest remaining bit should be our master pipe */
3450         return fls(master_pipes) - 1;
3451 }
3452
3453 static u8 get_bigjoiner_slave_pipes(enum pipe pipe, u8 master_pipes, u8 slave_pipes)
3454 {
3455         enum pipe master_pipe, next_master_pipe;
3456
3457         master_pipe = get_bigjoiner_master_pipe(pipe, master_pipes, slave_pipes);
3458
3459         if ((master_pipes & BIT(master_pipe)) == 0)
3460                 return 0;
3461
3462         /* ignore our master pipe and everything below it */
3463         master_pipes &= ~GENMASK(master_pipe, 0);
3464         /* make sure a high bit is set for the ffs() */
3465         master_pipes |= BIT(7);
3466         /* lowest remaining bit should be the next master pipe */
3467         next_master_pipe = ffs(master_pipes) - 1;
3468
3469         return slave_pipes & GENMASK(next_master_pipe - 1, master_pipe);
3470 }
3471
3472 static u8 hsw_panel_transcoders(struct drm_i915_private *i915)
3473 {
3474         u8 panel_transcoder_mask = BIT(TRANSCODER_EDP);
3475
3476         if (DISPLAY_VER(i915) >= 11)
3477                 panel_transcoder_mask |= BIT(TRANSCODER_DSI_0) | BIT(TRANSCODER_DSI_1);
3478
3479         return panel_transcoder_mask;
3480 }
3481
3482 static u8 hsw_enabled_transcoders(struct intel_crtc *crtc)
3483 {
3484         struct drm_device *dev = crtc->base.dev;
3485         struct drm_i915_private *dev_priv = to_i915(dev);
3486         u8 panel_transcoder_mask = hsw_panel_transcoders(dev_priv);
3487         enum transcoder cpu_transcoder;
3488         u8 master_pipes, slave_pipes;
3489         u8 enabled_transcoders = 0;
3490
3491         /*
3492          * XXX: Do intel_display_power_get_if_enabled before reading this (for
3493          * consistency and less surprising code; it's in always on power).
3494          */
3495         for_each_cpu_transcoder_masked(dev_priv, cpu_transcoder,
3496                                        panel_transcoder_mask) {
3497                 enum intel_display_power_domain power_domain;
3498                 intel_wakeref_t wakeref;
3499                 enum pipe trans_pipe;
3500                 u32 tmp = 0;
3501
3502                 power_domain = POWER_DOMAIN_TRANSCODER(cpu_transcoder);
3503                 with_intel_display_power_if_enabled(dev_priv, power_domain, wakeref)
3504                         tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(cpu_transcoder));
3505
3506                 if (!(tmp & TRANS_DDI_FUNC_ENABLE))
3507                         continue;
3508
3509                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
3510                 default:
3511                         drm_WARN(dev, 1,
3512                                  "unknown pipe linked to transcoder %s\n",
3513                                  transcoder_name(cpu_transcoder));
3514                         fallthrough;
3515                 case TRANS_DDI_EDP_INPUT_A_ONOFF:
3516                 case TRANS_DDI_EDP_INPUT_A_ON:
3517                         trans_pipe = PIPE_A;
3518                         break;
3519                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
3520                         trans_pipe = PIPE_B;
3521                         break;
3522                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
3523                         trans_pipe = PIPE_C;
3524                         break;
3525                 case TRANS_DDI_EDP_INPUT_D_ONOFF:
3526                         trans_pipe = PIPE_D;
3527                         break;
3528                 }
3529
3530                 if (trans_pipe == crtc->pipe)
3531                         enabled_transcoders |= BIT(cpu_transcoder);
3532         }
3533
3534         /* single pipe or bigjoiner master */
3535         cpu_transcoder = (enum transcoder) crtc->pipe;
3536         if (transcoder_ddi_func_is_enabled(dev_priv, cpu_transcoder))
3537                 enabled_transcoders |= BIT(cpu_transcoder);
3538
3539         /* bigjoiner slave -> consider the master pipe's transcoder as well */
3540         enabled_bigjoiner_pipes(dev_priv, &master_pipes, &slave_pipes);
3541         if (slave_pipes & BIT(crtc->pipe)) {
3542                 cpu_transcoder = (enum transcoder)
3543                         get_bigjoiner_master_pipe(crtc->pipe, master_pipes, slave_pipes);
3544                 if (transcoder_ddi_func_is_enabled(dev_priv, cpu_transcoder))
3545                         enabled_transcoders |= BIT(cpu_transcoder);
3546         }
3547
3548         return enabled_transcoders;
3549 }
3550
3551 static bool has_edp_transcoders(u8 enabled_transcoders)
3552 {
3553         return enabled_transcoders & BIT(TRANSCODER_EDP);
3554 }
3555
3556 static bool has_dsi_transcoders(u8 enabled_transcoders)
3557 {
3558         return enabled_transcoders & (BIT(TRANSCODER_DSI_0) |
3559                                       BIT(TRANSCODER_DSI_1));
3560 }
3561
3562 static bool has_pipe_transcoders(u8 enabled_transcoders)
3563 {
3564         return enabled_transcoders & ~(BIT(TRANSCODER_EDP) |
3565                                        BIT(TRANSCODER_DSI_0) |
3566                                        BIT(TRANSCODER_DSI_1));
3567 }
3568
3569 static void assert_enabled_transcoders(struct drm_i915_private *i915,
3570                                        u8 enabled_transcoders)
3571 {
3572         /* Only one type of transcoder please */
3573         drm_WARN_ON(&i915->drm,
3574                     has_edp_transcoders(enabled_transcoders) +
3575                     has_dsi_transcoders(enabled_transcoders) +
3576                     has_pipe_transcoders(enabled_transcoders) > 1);
3577
3578         /* Only DSI transcoders can be ganged */
3579         drm_WARN_ON(&i915->drm,
3580                     !has_dsi_transcoders(enabled_transcoders) &&
3581                     !is_power_of_2(enabled_transcoders));
3582 }
3583
3584 static bool hsw_get_transcoder_state(struct intel_crtc *crtc,
3585                                      struct intel_crtc_state *pipe_config,
3586                                      struct intel_display_power_domain_set *power_domain_set)
3587 {
3588         struct drm_device *dev = crtc->base.dev;
3589         struct drm_i915_private *dev_priv = to_i915(dev);
3590         unsigned long enabled_transcoders;
3591         u32 tmp;
3592
3593         enabled_transcoders = hsw_enabled_transcoders(crtc);
3594         if (!enabled_transcoders)
3595                 return false;
3596
3597         assert_enabled_transcoders(dev_priv, enabled_transcoders);
3598
3599         /*
3600          * With the exception of DSI we should only ever have
3601          * a single enabled transcoder. With DSI let's just
3602          * pick the first one.
3603          */
3604         pipe_config->cpu_transcoder = ffs(enabled_transcoders) - 1;
3605
3606         if (!intel_display_power_get_in_set_if_enabled(dev_priv, power_domain_set,
3607                                                        POWER_DOMAIN_TRANSCODER(pipe_config->cpu_transcoder)))
3608                 return false;
3609
3610         if (hsw_panel_transcoders(dev_priv) & BIT(pipe_config->cpu_transcoder)) {
3611                 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(pipe_config->cpu_transcoder));
3612
3613                 if ((tmp & TRANS_DDI_EDP_INPUT_MASK) == TRANS_DDI_EDP_INPUT_A_ONOFF)
3614                         pipe_config->pch_pfit.force_thru = true;
3615         }
3616
3617         tmp = intel_de_read(dev_priv, TRANSCONF(pipe_config->cpu_transcoder));
3618
3619         return tmp & TRANSCONF_ENABLE;
3620 }
3621
3622 static bool bxt_get_dsi_transcoder_state(struct intel_crtc *crtc,
3623                                          struct intel_crtc_state *pipe_config,
3624                                          struct intel_display_power_domain_set *power_domain_set)
3625 {
3626         struct drm_device *dev = crtc->base.dev;
3627         struct drm_i915_private *dev_priv = to_i915(dev);
3628         enum transcoder cpu_transcoder;
3629         enum port port;
3630         u32 tmp;
3631
3632         for_each_port_masked(port, BIT(PORT_A) | BIT(PORT_C)) {
3633                 if (port == PORT_A)
3634                         cpu_transcoder = TRANSCODER_DSI_A;
3635                 else
3636                         cpu_transcoder = TRANSCODER_DSI_C;
3637
3638                 if (!intel_display_power_get_in_set_if_enabled(dev_priv, power_domain_set,
3639                                                                POWER_DOMAIN_TRANSCODER(cpu_transcoder)))
3640                         continue;
3641
3642                 /*
3643                  * The PLL needs to be enabled with a valid divider
3644                  * configuration, otherwise accessing DSI registers will hang
3645                  * the machine. See BSpec North Display Engine
3646                  * registers/MIPI[BXT]. We can break out here early, since we
3647                  * need the same DSI PLL to be enabled for both DSI ports.
3648                  */
3649                 if (!bxt_dsi_pll_is_enabled(dev_priv))
3650                         break;
3651
3652                 /* XXX: this works for video mode only */
3653                 tmp = intel_de_read(dev_priv, BXT_MIPI_PORT_CTRL(port));
3654                 if (!(tmp & DPI_ENABLE))
3655                         continue;
3656
3657                 tmp = intel_de_read(dev_priv, MIPI_CTRL(port));
3658                 if ((tmp & BXT_PIPE_SELECT_MASK) != BXT_PIPE_SELECT(crtc->pipe))
3659                         continue;
3660
3661                 pipe_config->cpu_transcoder = cpu_transcoder;
3662                 break;
3663         }
3664
3665         return transcoder_is_dsi(pipe_config->cpu_transcoder);
3666 }
3667
3668 static void intel_bigjoiner_get_config(struct intel_crtc_state *crtc_state)
3669 {
3670         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3671         struct drm_i915_private *i915 = to_i915(crtc->base.dev);
3672         u8 master_pipes, slave_pipes;
3673         enum pipe pipe = crtc->pipe;
3674
3675         enabled_bigjoiner_pipes(i915, &master_pipes, &slave_pipes);
3676
3677         if (((master_pipes | slave_pipes) & BIT(pipe)) == 0)
3678                 return;
3679
3680         crtc_state->bigjoiner_pipes =
3681                 BIT(get_bigjoiner_master_pipe(pipe, master_pipes, slave_pipes)) |
3682                 get_bigjoiner_slave_pipes(pipe, master_pipes, slave_pipes);
3683 }
3684
3685 static bool hsw_get_pipe_config(struct intel_crtc *crtc,
3686                                 struct intel_crtc_state *pipe_config)
3687 {
3688         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3689         bool active;
3690         u32 tmp;
3691
3692         if (!intel_display_power_get_in_set_if_enabled(dev_priv, &crtc->hw_readout_power_domains,
3693                                                        POWER_DOMAIN_PIPE(crtc->pipe)))
3694                 return false;
3695
3696         pipe_config->shared_dpll = NULL;
3697
3698         active = hsw_get_transcoder_state(crtc, pipe_config, &crtc->hw_readout_power_domains);
3699
3700         if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) &&
3701             bxt_get_dsi_transcoder_state(crtc, pipe_config, &crtc->hw_readout_power_domains)) {
3702                 drm_WARN_ON(&dev_priv->drm, active);
3703                 active = true;
3704         }
3705
3706         if (!active)
3707                 goto out;
3708
3709         intel_dsc_get_config(pipe_config);
3710         intel_bigjoiner_get_config(pipe_config);
3711
3712         if (!transcoder_is_dsi(pipe_config->cpu_transcoder) ||
3713             DISPLAY_VER(dev_priv) >= 11)
3714                 intel_get_transcoder_timings(crtc, pipe_config);
3715
3716         if (HAS_VRR(dev_priv) && !transcoder_is_dsi(pipe_config->cpu_transcoder))
3717                 intel_vrr_get_config(pipe_config);
3718
3719         intel_get_pipe_src_size(crtc, pipe_config);
3720
3721         if (IS_HASWELL(dev_priv)) {
3722                 u32 tmp = intel_de_read(dev_priv,
3723                                         TRANSCONF(pipe_config->cpu_transcoder));
3724
3725                 if (tmp & TRANSCONF_OUTPUT_COLORSPACE_YUV_HSW)
3726                         pipe_config->output_format = INTEL_OUTPUT_FORMAT_YCBCR444;
3727                 else
3728                         pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
3729         } else {
3730                 pipe_config->output_format =
3731                         bdw_get_pipe_misc_output_format(crtc);
3732         }
3733
3734         pipe_config->sink_format = pipe_config->output_format;
3735
3736         pipe_config->gamma_mode = intel_de_read(dev_priv,
3737                                                 GAMMA_MODE(crtc->pipe));
3738
3739         pipe_config->csc_mode = intel_de_read(dev_priv,
3740                                               PIPE_CSC_MODE(crtc->pipe));
3741
3742         if (DISPLAY_VER(dev_priv) >= 9) {
3743                 tmp = intel_de_read(dev_priv, SKL_BOTTOM_COLOR(crtc->pipe));
3744
3745                 if (tmp & SKL_BOTTOM_COLOR_GAMMA_ENABLE)
3746                         pipe_config->gamma_enable = true;
3747
3748                 if (tmp & SKL_BOTTOM_COLOR_CSC_ENABLE)
3749                         pipe_config->csc_enable = true;
3750         } else {
3751                 i9xx_get_pipe_color_config(pipe_config);
3752         }
3753
3754         intel_color_get_config(pipe_config);
3755
3756         tmp = intel_de_read(dev_priv, WM_LINETIME(crtc->pipe));
3757         pipe_config->linetime = REG_FIELD_GET(HSW_LINETIME_MASK, tmp);
3758         if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
3759                 pipe_config->ips_linetime =
3760                         REG_FIELD_GET(HSW_IPS_LINETIME_MASK, tmp);
3761
3762         if (intel_display_power_get_in_set_if_enabled(dev_priv, &crtc->hw_readout_power_domains,
3763                                                       POWER_DOMAIN_PIPE_PANEL_FITTER(crtc->pipe))) {
3764                 if (DISPLAY_VER(dev_priv) >= 9)
3765                         skl_scaler_get_config(pipe_config);
3766                 else
3767                         ilk_get_pfit_config(pipe_config);
3768         }
3769
3770         hsw_ips_get_config(pipe_config);
3771
3772         if (pipe_config->cpu_transcoder != TRANSCODER_EDP &&
3773             !transcoder_is_dsi(pipe_config->cpu_transcoder)) {
3774                 pipe_config->pixel_multiplier =
3775                         intel_de_read(dev_priv,
3776                                       TRANS_MULT(pipe_config->cpu_transcoder)) + 1;
3777         } else {
3778                 pipe_config->pixel_multiplier = 1;
3779         }
3780
3781         if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) {
3782                 tmp = intel_de_read(dev_priv, DISPLAY_VER(dev_priv) >= 14 ?
3783                                     MTL_CHICKEN_TRANS(pipe_config->cpu_transcoder) :
3784                                     CHICKEN_TRANS(pipe_config->cpu_transcoder));
3785
3786                 pipe_config->framestart_delay = REG_FIELD_GET(HSW_FRAME_START_DELAY_MASK, tmp) + 1;
3787         } else {
3788                 /* no idea if this is correct */
3789                 pipe_config->framestart_delay = 1;
3790         }
3791
3792 out:
3793         intel_display_power_put_all_in_set(dev_priv, &crtc->hw_readout_power_domains);
3794
3795         return active;
3796 }
3797
3798 bool intel_crtc_get_pipe_config(struct intel_crtc_state *crtc_state)
3799 {
3800         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
3801         struct drm_i915_private *i915 = to_i915(crtc->base.dev);
3802
3803         if (!i915->display.funcs.display->get_pipe_config(crtc, crtc_state))
3804                 return false;
3805
3806         crtc_state->hw.active = true;
3807
3808         intel_crtc_readout_derived_state(crtc_state);
3809
3810         return true;
3811 }
3812
3813 static int i9xx_pll_refclk(struct drm_device *dev,
3814                            const struct intel_crtc_state *pipe_config)
3815 {
3816         struct drm_i915_private *dev_priv = to_i915(dev);
3817         u32 dpll = pipe_config->dpll_hw_state.dpll;
3818
3819         if ((dpll & PLL_REF_INPUT_MASK) == PLLB_REF_INPUT_SPREADSPECTRUMIN)
3820                 return dev_priv->display.vbt.lvds_ssc_freq;
3821         else if (HAS_PCH_SPLIT(dev_priv))
3822                 return 120000;
3823         else if (DISPLAY_VER(dev_priv) != 2)
3824                 return 96000;
3825         else
3826                 return 48000;
3827 }
3828
3829 /* Returns the clock of the currently programmed mode of the given pipe. */
3830 void i9xx_crtc_clock_get(struct intel_crtc *crtc,
3831                          struct intel_crtc_state *pipe_config)
3832 {
3833         struct drm_device *dev = crtc->base.dev;
3834         struct drm_i915_private *dev_priv = to_i915(dev);
3835         u32 dpll = pipe_config->dpll_hw_state.dpll;
3836         u32 fp;
3837         struct dpll clock;
3838         int port_clock;
3839         int refclk = i9xx_pll_refclk(dev, pipe_config);
3840
3841         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
3842                 fp = pipe_config->dpll_hw_state.fp0;
3843         else
3844                 fp = pipe_config->dpll_hw_state.fp1;
3845
3846         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
3847         if (IS_PINEVIEW(dev_priv)) {
3848                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
3849                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
3850         } else {
3851                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
3852                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
3853         }
3854
3855         if (DISPLAY_VER(dev_priv) != 2) {
3856                 if (IS_PINEVIEW(dev_priv))
3857                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
3858                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
3859                 else
3860                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
3861                                DPLL_FPA01_P1_POST_DIV_SHIFT);
3862
3863                 switch (dpll & DPLL_MODE_MASK) {
3864                 case DPLLB_MODE_DAC_SERIAL:
3865                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
3866                                 5 : 10;
3867                         break;
3868                 case DPLLB_MODE_LVDS:
3869                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
3870                                 7 : 14;
3871                         break;
3872                 default:
3873                         drm_dbg_kms(&dev_priv->drm,
3874                                     "Unknown DPLL mode %08x in programmed "
3875                                     "mode\n", (int)(dpll & DPLL_MODE_MASK));
3876                         return;
3877                 }
3878
3879                 if (IS_PINEVIEW(dev_priv))
3880                         port_clock = pnv_calc_dpll_params(refclk, &clock);
3881                 else
3882                         port_clock = i9xx_calc_dpll_params(refclk, &clock);
3883         } else {
3884                 enum pipe lvds_pipe;
3885
3886                 if (IS_I85X(dev_priv) &&
3887                     intel_lvds_port_enabled(dev_priv, LVDS, &lvds_pipe) &&
3888                     lvds_pipe == crtc->pipe) {
3889                         u32 lvds = intel_de_read(dev_priv, LVDS);
3890
3891                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
3892                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
3893
3894                         if (lvds & LVDS_CLKB_POWER_UP)
3895                                 clock.p2 = 7;
3896                         else
3897                                 clock.p2 = 14;
3898                 } else {
3899                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
3900                                 clock.p1 = 2;
3901                         else {
3902                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
3903                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
3904                         }
3905                         if (dpll & PLL_P2_DIVIDE_BY_4)
3906                                 clock.p2 = 4;
3907                         else
3908                                 clock.p2 = 2;
3909                 }
3910
3911                 port_clock = i9xx_calc_dpll_params(refclk, &clock);
3912         }
3913
3914         /*
3915          * This value includes pixel_multiplier. We will use
3916          * port_clock to compute adjusted_mode.crtc_clock in the
3917          * encoder's get_config() function.
3918          */
3919         pipe_config->port_clock = port_clock;
3920 }
3921
3922 int intel_dotclock_calculate(int link_freq,
3923                              const struct intel_link_m_n *m_n)
3924 {
3925         /*
3926          * The calculation for the data clock is:
3927          * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
3928          * But we want to avoid losing precison if possible, so:
3929          * pixel_clock = ((m * link_clock * nr_lanes)/(n*bpp))
3930          *
3931          * and the link clock is simpler:
3932          * link_clock = (m * link_clock) / n
3933          */
3934
3935         if (!m_n->link_n)
3936                 return 0;
3937
3938         return DIV_ROUND_UP_ULL(mul_u32_u32(m_n->link_m, link_freq),
3939                                 m_n->link_n);
3940 }
3941
3942 int intel_crtc_dotclock(const struct intel_crtc_state *pipe_config)
3943 {
3944         int dotclock;
3945
3946         if (intel_crtc_has_dp_encoder(pipe_config))
3947                 dotclock = intel_dotclock_calculate(pipe_config->port_clock,
3948                                                     &pipe_config->dp_m_n);
3949         else if (pipe_config->has_hdmi_sink && pipe_config->pipe_bpp > 24)
3950                 dotclock = DIV_ROUND_CLOSEST(pipe_config->port_clock * 24,
3951                                              pipe_config->pipe_bpp);
3952         else
3953                 dotclock = pipe_config->port_clock;
3954
3955         if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 &&
3956             !intel_crtc_has_dp_encoder(pipe_config))
3957                 dotclock *= 2;
3958
3959         if (pipe_config->pixel_multiplier)
3960                 dotclock /= pipe_config->pixel_multiplier;
3961
3962         return dotclock;
3963 }
3964
3965 /* Returns the currently programmed mode of the given encoder. */
3966 struct drm_display_mode *
3967 intel_encoder_current_mode(struct intel_encoder *encoder)
3968 {
3969         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3970         struct intel_crtc_state *crtc_state;
3971         struct drm_display_mode *mode;
3972         struct intel_crtc *crtc;
3973         enum pipe pipe;
3974
3975         if (!encoder->get_hw_state(encoder, &pipe))
3976                 return NULL;
3977
3978         crtc = intel_crtc_for_pipe(dev_priv, pipe);
3979
3980         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
3981         if (!mode)
3982                 return NULL;
3983
3984         crtc_state = intel_crtc_state_alloc(crtc);
3985         if (!crtc_state) {
3986                 kfree(mode);
3987                 return NULL;
3988         }
3989
3990         if (!intel_crtc_get_pipe_config(crtc_state)) {
3991                 kfree(crtc_state);
3992                 kfree(mode);
3993                 return NULL;
3994         }
3995
3996         intel_encoder_get_config(encoder, crtc_state);
3997
3998         intel_mode_from_crtc_timings(mode, &crtc_state->hw.adjusted_mode);
3999
4000         kfree(crtc_state);
4001
4002         return mode;
4003 }
4004
4005 static bool encoders_cloneable(const struct intel_encoder *a,
4006                                const struct intel_encoder *b)
4007 {
4008         /* masks could be asymmetric, so check both ways */
4009         return a == b || (a->cloneable & BIT(b->type) &&
4010                           b->cloneable & BIT(a->type));
4011 }
4012
4013 static bool check_single_encoder_cloning(struct intel_atomic_state *state,
4014                                          struct intel_crtc *crtc,
4015                                          struct intel_encoder *encoder)
4016 {
4017         struct intel_encoder *source_encoder;
4018         struct drm_connector *connector;
4019         struct drm_connector_state *connector_state;
4020         int i;
4021
4022         for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
4023                 if (connector_state->crtc != &crtc->base)
4024                         continue;
4025
4026                 source_encoder =
4027                         to_intel_encoder(connector_state->best_encoder);
4028                 if (!encoders_cloneable(encoder, source_encoder))
4029                         return false;
4030         }
4031
4032         return true;
4033 }
4034
4035 static int icl_add_linked_planes(struct intel_atomic_state *state)
4036 {
4037         struct intel_plane *plane, *linked;
4038         struct intel_plane_state *plane_state, *linked_plane_state;
4039         int i;
4040
4041         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
4042                 linked = plane_state->planar_linked_plane;
4043
4044                 if (!linked)
4045                         continue;
4046
4047                 linked_plane_state = intel_atomic_get_plane_state(state, linked);
4048                 if (IS_ERR(linked_plane_state))
4049                         return PTR_ERR(linked_plane_state);
4050
4051                 drm_WARN_ON(state->base.dev,
4052                             linked_plane_state->planar_linked_plane != plane);
4053                 drm_WARN_ON(state->base.dev,
4054                             linked_plane_state->planar_slave == plane_state->planar_slave);
4055         }
4056
4057         return 0;
4058 }
4059
4060 static int icl_check_nv12_planes(struct intel_crtc_state *crtc_state)
4061 {
4062         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
4063         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4064         struct intel_atomic_state *state = to_intel_atomic_state(crtc_state->uapi.state);
4065         struct intel_plane *plane, *linked;
4066         struct intel_plane_state *plane_state;
4067         int i;
4068
4069         if (DISPLAY_VER(dev_priv) < 11)
4070                 return 0;
4071
4072         /*
4073          * Destroy all old plane links and make the slave plane invisible
4074          * in the crtc_state->active_planes mask.
4075          */
4076         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
4077                 if (plane->pipe != crtc->pipe || !plane_state->planar_linked_plane)
4078                         continue;
4079
4080                 plane_state->planar_linked_plane = NULL;
4081                 if (plane_state->planar_slave && !plane_state->uapi.visible) {
4082                         crtc_state->enabled_planes &= ~BIT(plane->id);
4083                         crtc_state->active_planes &= ~BIT(plane->id);
4084                         crtc_state->update_planes |= BIT(plane->id);
4085                         crtc_state->data_rate[plane->id] = 0;
4086                         crtc_state->rel_data_rate[plane->id] = 0;
4087                 }
4088
4089                 plane_state->planar_slave = false;
4090         }
4091
4092         if (!crtc_state->nv12_planes)
4093                 return 0;
4094
4095         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
4096                 struct intel_plane_state *linked_state = NULL;
4097
4098                 if (plane->pipe != crtc->pipe ||
4099                     !(crtc_state->nv12_planes & BIT(plane->id)))
4100                         continue;
4101
4102                 for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, linked) {
4103                         if (!icl_is_nv12_y_plane(dev_priv, linked->id))
4104                                 continue;
4105
4106                         if (crtc_state->active_planes & BIT(linked->id))
4107                                 continue;
4108
4109                         linked_state = intel_atomic_get_plane_state(state, linked);
4110                         if (IS_ERR(linked_state))
4111                                 return PTR_ERR(linked_state);
4112
4113                         break;
4114                 }
4115
4116                 if (!linked_state) {
4117                         drm_dbg_kms(&dev_priv->drm,
4118                                     "Need %d free Y planes for planar YUV\n",
4119                                     hweight8(crtc_state->nv12_planes));
4120
4121                         return -EINVAL;
4122                 }
4123
4124                 plane_state->planar_linked_plane = linked;
4125
4126                 linked_state->planar_slave = true;
4127                 linked_state->planar_linked_plane = plane;
4128                 crtc_state->enabled_planes |= BIT(linked->id);
4129                 crtc_state->active_planes |= BIT(linked->id);
4130                 crtc_state->update_planes |= BIT(linked->id);
4131                 crtc_state->data_rate[linked->id] =
4132                         crtc_state->data_rate_y[plane->id];
4133                 crtc_state->rel_data_rate[linked->id] =
4134                         crtc_state->rel_data_rate_y[plane->id];
4135                 drm_dbg_kms(&dev_priv->drm, "Using %s as Y plane for %s\n",
4136                             linked->base.name, plane->base.name);
4137
4138                 /* Copy parameters to slave plane */
4139                 linked_state->ctl = plane_state->ctl | PLANE_CTL_YUV420_Y_PLANE;
4140                 linked_state->color_ctl = plane_state->color_ctl;
4141                 linked_state->view = plane_state->view;
4142                 linked_state->decrypt = plane_state->decrypt;
4143
4144                 intel_plane_copy_hw_state(linked_state, plane_state);
4145                 linked_state->uapi.src = plane_state->uapi.src;
4146                 linked_state->uapi.dst = plane_state->uapi.dst;
4147
4148                 if (icl_is_hdr_plane(dev_priv, plane->id)) {
4149                         if (linked->id == PLANE_SPRITE5)
4150                                 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_7_ICL;
4151                         else if (linked->id == PLANE_SPRITE4)
4152                                 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_6_ICL;
4153                         else if (linked->id == PLANE_SPRITE3)
4154                                 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_5_RKL;
4155                         else if (linked->id == PLANE_SPRITE2)
4156                                 plane_state->cus_ctl |= PLANE_CUS_Y_PLANE_4_RKL;
4157                         else
4158                                 MISSING_CASE(linked->id);
4159                 }
4160         }
4161
4162         return 0;
4163 }
4164
4165 static bool c8_planes_changed(const struct intel_crtc_state *new_crtc_state)
4166 {
4167         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
4168         struct intel_atomic_state *state =
4169                 to_intel_atomic_state(new_crtc_state->uapi.state);
4170         const struct intel_crtc_state *old_crtc_state =
4171                 intel_atomic_get_old_crtc_state(state, crtc);
4172
4173         return !old_crtc_state->c8_planes != !new_crtc_state->c8_planes;
4174 }
4175
4176 static u16 hsw_linetime_wm(const struct intel_crtc_state *crtc_state)
4177 {
4178         const struct drm_display_mode *pipe_mode =
4179                 &crtc_state->hw.pipe_mode;
4180         int linetime_wm;
4181
4182         if (!crtc_state->hw.enable)
4183                 return 0;
4184
4185         linetime_wm = DIV_ROUND_CLOSEST(pipe_mode->crtc_htotal * 1000 * 8,
4186                                         pipe_mode->crtc_clock);
4187
4188         return min(linetime_wm, 0x1ff);
4189 }
4190
4191 static u16 hsw_ips_linetime_wm(const struct intel_crtc_state *crtc_state,
4192                                const struct intel_cdclk_state *cdclk_state)
4193 {
4194         const struct drm_display_mode *pipe_mode =
4195                 &crtc_state->hw.pipe_mode;
4196         int linetime_wm;
4197
4198         if (!crtc_state->hw.enable)
4199                 return 0;
4200
4201         linetime_wm = DIV_ROUND_CLOSEST(pipe_mode->crtc_htotal * 1000 * 8,
4202                                         cdclk_state->logical.cdclk);
4203
4204         return min(linetime_wm, 0x1ff);
4205 }
4206
4207 static u16 skl_linetime_wm(const struct intel_crtc_state *crtc_state)
4208 {
4209         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
4210         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4211         const struct drm_display_mode *pipe_mode =
4212                 &crtc_state->hw.pipe_mode;
4213         int linetime_wm;
4214
4215         if (!crtc_state->hw.enable)
4216                 return 0;
4217
4218         linetime_wm = DIV_ROUND_UP(pipe_mode->crtc_htotal * 1000 * 8,
4219                                    crtc_state->pixel_rate);
4220
4221         /* Display WA #1135: BXT:ALL GLK:ALL */
4222         if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) &&
4223             skl_watermark_ipc_enabled(dev_priv))
4224                 linetime_wm /= 2;
4225
4226         return min(linetime_wm, 0x1ff);
4227 }
4228
4229 static int hsw_compute_linetime_wm(struct intel_atomic_state *state,
4230                                    struct intel_crtc *crtc)
4231 {
4232         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4233         struct intel_crtc_state *crtc_state =
4234                 intel_atomic_get_new_crtc_state(state, crtc);
4235         const struct intel_cdclk_state *cdclk_state;
4236
4237         if (DISPLAY_VER(dev_priv) >= 9)
4238                 crtc_state->linetime = skl_linetime_wm(crtc_state);
4239         else
4240                 crtc_state->linetime = hsw_linetime_wm(crtc_state);
4241
4242         if (!hsw_crtc_supports_ips(crtc))
4243                 return 0;
4244
4245         cdclk_state = intel_atomic_get_cdclk_state(state);
4246         if (IS_ERR(cdclk_state))
4247                 return PTR_ERR(cdclk_state);
4248
4249         crtc_state->ips_linetime = hsw_ips_linetime_wm(crtc_state,
4250                                                        cdclk_state);
4251
4252         return 0;
4253 }
4254
4255 static int intel_crtc_atomic_check(struct intel_atomic_state *state,
4256                                    struct intel_crtc *crtc)
4257 {
4258         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4259         struct intel_crtc_state *crtc_state =
4260                 intel_atomic_get_new_crtc_state(state, crtc);
4261         int ret;
4262
4263         if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv) &&
4264             intel_crtc_needs_modeset(crtc_state) &&
4265             !crtc_state->hw.active)
4266                 crtc_state->update_wm_post = true;
4267
4268         if (intel_crtc_needs_modeset(crtc_state)) {
4269                 ret = intel_dpll_crtc_get_shared_dpll(state, crtc);
4270                 if (ret)
4271                         return ret;
4272         }
4273
4274         /*
4275          * May need to update pipe gamma enable bits
4276          * when C8 planes are getting enabled/disabled.
4277          */
4278         if (c8_planes_changed(crtc_state))
4279                 crtc_state->uapi.color_mgmt_changed = true;
4280
4281         if (intel_crtc_needs_color_update(crtc_state)) {
4282                 ret = intel_color_check(crtc_state);
4283                 if (ret)
4284                         return ret;
4285         }
4286
4287         ret = intel_compute_pipe_wm(state, crtc);
4288         if (ret) {
4289                 drm_dbg_kms(&dev_priv->drm,
4290                             "Target pipe watermarks are invalid\n");
4291                 return ret;
4292         }
4293
4294         /*
4295          * Calculate 'intermediate' watermarks that satisfy both the
4296          * old state and the new state.  We can program these
4297          * immediately.
4298          */
4299         ret = intel_compute_intermediate_wm(state, crtc);
4300         if (ret) {
4301                 drm_dbg_kms(&dev_priv->drm,
4302                             "No valid intermediate pipe watermarks are possible\n");
4303                 return ret;
4304         }
4305
4306         if (DISPLAY_VER(dev_priv) >= 9) {
4307                 if (intel_crtc_needs_modeset(crtc_state) ||
4308                     intel_crtc_needs_fastset(crtc_state)) {
4309                         ret = skl_update_scaler_crtc(crtc_state);
4310                         if (ret)
4311                                 return ret;
4312                 }
4313
4314                 ret = intel_atomic_setup_scalers(dev_priv, crtc, crtc_state);
4315                 if (ret)
4316                         return ret;
4317         }
4318
4319         if (HAS_IPS(dev_priv)) {
4320                 ret = hsw_ips_compute_config(state, crtc);
4321                 if (ret)
4322                         return ret;
4323         }
4324
4325         if (DISPLAY_VER(dev_priv) >= 9 ||
4326             IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
4327                 ret = hsw_compute_linetime_wm(state, crtc);
4328                 if (ret)
4329                         return ret;
4330
4331         }
4332
4333         ret = intel_psr2_sel_fetch_update(state, crtc);
4334         if (ret)
4335                 return ret;
4336
4337         return 0;
4338 }
4339
4340 static int
4341 compute_sink_pipe_bpp(const struct drm_connector_state *conn_state,
4342                       struct intel_crtc_state *crtc_state)
4343 {
4344         struct drm_connector *connector = conn_state->connector;
4345         struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
4346         const struct drm_display_info *info = &connector->display_info;
4347         int bpp;
4348
4349         switch (conn_state->max_bpc) {
4350         case 6 ... 7:
4351                 bpp = 6 * 3;
4352                 break;
4353         case 8 ... 9:
4354                 bpp = 8 * 3;
4355                 break;
4356         case 10 ... 11:
4357                 bpp = 10 * 3;
4358                 break;
4359         case 12 ... 16:
4360                 bpp = 12 * 3;
4361                 break;
4362         default:
4363                 MISSING_CASE(conn_state->max_bpc);
4364                 return -EINVAL;
4365         }
4366
4367         if (bpp < crtc_state->pipe_bpp) {
4368                 drm_dbg_kms(&i915->drm,
4369                             "[CONNECTOR:%d:%s] Limiting display bpp to %d "
4370                             "(EDID bpp %d, max requested bpp %d, max platform bpp %d)\n",
4371                             connector->base.id, connector->name,
4372                             bpp, 3 * info->bpc,
4373                             3 * conn_state->max_requested_bpc,
4374                             crtc_state->pipe_bpp);
4375
4376                 crtc_state->pipe_bpp = bpp;
4377         }
4378
4379         return 0;
4380 }
4381
4382 static int
4383 compute_baseline_pipe_bpp(struct intel_atomic_state *state,
4384                           struct intel_crtc *crtc)
4385 {
4386         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4387         struct intel_crtc_state *crtc_state =
4388                 intel_atomic_get_new_crtc_state(state, crtc);
4389         struct drm_connector *connector;
4390         struct drm_connector_state *connector_state;
4391         int bpp, i;
4392
4393         if ((IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
4394             IS_CHERRYVIEW(dev_priv)))
4395                 bpp = 10*3;
4396         else if (DISPLAY_VER(dev_priv) >= 5)
4397                 bpp = 12*3;
4398         else
4399                 bpp = 8*3;
4400
4401         crtc_state->pipe_bpp = bpp;
4402
4403         /* Clamp display bpp to connector max bpp */
4404         for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
4405                 int ret;
4406
4407                 if (connector_state->crtc != &crtc->base)
4408                         continue;
4409
4410                 ret = compute_sink_pipe_bpp(connector_state, crtc_state);
4411                 if (ret)
4412                         return ret;
4413         }
4414
4415         return 0;
4416 }
4417
4418 static bool check_digital_port_conflicts(struct intel_atomic_state *state)
4419 {
4420         struct drm_device *dev = state->base.dev;
4421         struct drm_connector *connector;
4422         struct drm_connector_list_iter conn_iter;
4423         unsigned int used_ports = 0;
4424         unsigned int used_mst_ports = 0;
4425         bool ret = true;
4426
4427         /*
4428          * We're going to peek into connector->state,
4429          * hence connection_mutex must be held.
4430          */
4431         drm_modeset_lock_assert_held(&dev->mode_config.connection_mutex);
4432
4433         /*
4434          * Walk the connector list instead of the encoder
4435          * list to detect the problem on ddi platforms
4436          * where there's just one encoder per digital port.
4437          */
4438         drm_connector_list_iter_begin(dev, &conn_iter);
4439         drm_for_each_connector_iter(connector, &conn_iter) {
4440                 struct drm_connector_state *connector_state;
4441                 struct intel_encoder *encoder;
4442
4443                 connector_state =
4444                         drm_atomic_get_new_connector_state(&state->base,
4445                                                            connector);
4446                 if (!connector_state)
4447                         connector_state = connector->state;
4448
4449                 if (!connector_state->best_encoder)
4450                         continue;
4451
4452                 encoder = to_intel_encoder(connector_state->best_encoder);
4453
4454                 drm_WARN_ON(dev, !connector_state->crtc);
4455
4456                 switch (encoder->type) {
4457                 case INTEL_OUTPUT_DDI:
4458                         if (drm_WARN_ON(dev, !HAS_DDI(to_i915(dev))))
4459                                 break;
4460                         fallthrough;
4461                 case INTEL_OUTPUT_DP:
4462                 case INTEL_OUTPUT_HDMI:
4463                 case INTEL_OUTPUT_EDP:
4464                         /* the same port mustn't appear more than once */
4465                         if (used_ports & BIT(encoder->port))
4466                                 ret = false;
4467
4468                         used_ports |= BIT(encoder->port);
4469                         break;
4470                 case INTEL_OUTPUT_DP_MST:
4471                         used_mst_ports |=
4472                                 1 << encoder->port;
4473                         break;
4474                 default:
4475                         break;
4476                 }
4477         }
4478         drm_connector_list_iter_end(&conn_iter);
4479
4480         /* can't mix MST and SST/HDMI on the same port */
4481         if (used_ports & used_mst_ports)
4482                 return false;
4483
4484         return ret;
4485 }
4486
4487 static void
4488 intel_crtc_copy_uapi_to_hw_state_nomodeset(struct intel_atomic_state *state,
4489                                            struct intel_crtc *crtc)
4490 {
4491         struct intel_crtc_state *crtc_state =
4492                 intel_atomic_get_new_crtc_state(state, crtc);
4493
4494         WARN_ON(intel_crtc_is_bigjoiner_slave(crtc_state));
4495
4496         drm_property_replace_blob(&crtc_state->hw.degamma_lut,
4497                                   crtc_state->uapi.degamma_lut);
4498         drm_property_replace_blob(&crtc_state->hw.gamma_lut,
4499                                   crtc_state->uapi.gamma_lut);
4500         drm_property_replace_blob(&crtc_state->hw.ctm,
4501                                   crtc_state->uapi.ctm);
4502 }
4503
4504 static void
4505 intel_crtc_copy_uapi_to_hw_state_modeset(struct intel_atomic_state *state,
4506                                          struct intel_crtc *crtc)
4507 {
4508         struct intel_crtc_state *crtc_state =
4509                 intel_atomic_get_new_crtc_state(state, crtc);
4510
4511         WARN_ON(intel_crtc_is_bigjoiner_slave(crtc_state));
4512
4513         crtc_state->hw.enable = crtc_state->uapi.enable;
4514         crtc_state->hw.active = crtc_state->uapi.active;
4515         drm_mode_copy(&crtc_state->hw.mode,
4516                       &crtc_state->uapi.mode);
4517         drm_mode_copy(&crtc_state->hw.adjusted_mode,
4518                       &crtc_state->uapi.adjusted_mode);
4519         crtc_state->hw.scaling_filter = crtc_state->uapi.scaling_filter;
4520
4521         intel_crtc_copy_uapi_to_hw_state_nomodeset(state, crtc);
4522 }
4523
4524 static void
4525 copy_bigjoiner_crtc_state_nomodeset(struct intel_atomic_state *state,
4526                                     struct intel_crtc *slave_crtc)
4527 {
4528         struct intel_crtc_state *slave_crtc_state =
4529                 intel_atomic_get_new_crtc_state(state, slave_crtc);
4530         struct intel_crtc *master_crtc = intel_master_crtc(slave_crtc_state);
4531         const struct intel_crtc_state *master_crtc_state =
4532                 intel_atomic_get_new_crtc_state(state, master_crtc);
4533
4534         drm_property_replace_blob(&slave_crtc_state->hw.degamma_lut,
4535                                   master_crtc_state->hw.degamma_lut);
4536         drm_property_replace_blob(&slave_crtc_state->hw.gamma_lut,
4537                                   master_crtc_state->hw.gamma_lut);
4538         drm_property_replace_blob(&slave_crtc_state->hw.ctm,
4539                                   master_crtc_state->hw.ctm);
4540
4541         slave_crtc_state->uapi.color_mgmt_changed = master_crtc_state->uapi.color_mgmt_changed;
4542 }
4543
4544 static int
4545 copy_bigjoiner_crtc_state_modeset(struct intel_atomic_state *state,
4546                                   struct intel_crtc *slave_crtc)
4547 {
4548         struct intel_crtc_state *slave_crtc_state =
4549                 intel_atomic_get_new_crtc_state(state, slave_crtc);
4550         struct intel_crtc *master_crtc = intel_master_crtc(slave_crtc_state);
4551         const struct intel_crtc_state *master_crtc_state =
4552                 intel_atomic_get_new_crtc_state(state, master_crtc);
4553         struct intel_crtc_state *saved_state;
4554
4555         WARN_ON(master_crtc_state->bigjoiner_pipes !=
4556                 slave_crtc_state->bigjoiner_pipes);
4557
4558         saved_state = kmemdup(master_crtc_state, sizeof(*saved_state), GFP_KERNEL);
4559         if (!saved_state)
4560                 return -ENOMEM;
4561
4562         /* preserve some things from the slave's original crtc state */
4563         saved_state->uapi = slave_crtc_state->uapi;
4564         saved_state->scaler_state = slave_crtc_state->scaler_state;
4565         saved_state->shared_dpll = slave_crtc_state->shared_dpll;
4566         saved_state->dpll_hw_state = slave_crtc_state->dpll_hw_state;
4567         saved_state->crc_enabled = slave_crtc_state->crc_enabled;
4568
4569         intel_crtc_free_hw_state(slave_crtc_state);
4570         memcpy(slave_crtc_state, saved_state, sizeof(*slave_crtc_state));
4571         kfree(saved_state);
4572
4573         /* Re-init hw state */
4574         memset(&slave_crtc_state->hw, 0, sizeof(slave_crtc_state->hw));
4575         slave_crtc_state->hw.enable = master_crtc_state->hw.enable;
4576         slave_crtc_state->hw.active = master_crtc_state->hw.active;
4577         drm_mode_copy(&slave_crtc_state->hw.mode,
4578                       &master_crtc_state->hw.mode);
4579         drm_mode_copy(&slave_crtc_state->hw.pipe_mode,
4580                       &master_crtc_state->hw.pipe_mode);
4581         drm_mode_copy(&slave_crtc_state->hw.adjusted_mode,
4582                       &master_crtc_state->hw.adjusted_mode);
4583         slave_crtc_state->hw.scaling_filter = master_crtc_state->hw.scaling_filter;
4584
4585         copy_bigjoiner_crtc_state_nomodeset(state, slave_crtc);
4586
4587         slave_crtc_state->uapi.mode_changed = master_crtc_state->uapi.mode_changed;
4588         slave_crtc_state->uapi.connectors_changed = master_crtc_state->uapi.connectors_changed;
4589         slave_crtc_state->uapi.active_changed = master_crtc_state->uapi.active_changed;
4590
4591         WARN_ON(master_crtc_state->bigjoiner_pipes !=
4592                 slave_crtc_state->bigjoiner_pipes);
4593
4594         return 0;
4595 }
4596
4597 static int
4598 intel_crtc_prepare_cleared_state(struct intel_atomic_state *state,
4599                                  struct intel_crtc *crtc)
4600 {
4601         struct intel_crtc_state *crtc_state =
4602                 intel_atomic_get_new_crtc_state(state, crtc);
4603         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4604         struct intel_crtc_state *saved_state;
4605
4606         saved_state = intel_crtc_state_alloc(crtc);
4607         if (!saved_state)
4608                 return -ENOMEM;
4609
4610         /* free the old crtc_state->hw members */
4611         intel_crtc_free_hw_state(crtc_state);
4612
4613         /* FIXME: before the switch to atomic started, a new pipe_config was
4614          * kzalloc'd. Code that depends on any field being zero should be
4615          * fixed, so that the crtc_state can be safely duplicated. For now,
4616          * only fields that are know to not cause problems are preserved. */
4617
4618         saved_state->uapi = crtc_state->uapi;
4619         saved_state->inherited = crtc_state->inherited;
4620         saved_state->scaler_state = crtc_state->scaler_state;
4621         saved_state->shared_dpll = crtc_state->shared_dpll;
4622         saved_state->dpll_hw_state = crtc_state->dpll_hw_state;
4623         memcpy(saved_state->icl_port_dplls, crtc_state->icl_port_dplls,
4624                sizeof(saved_state->icl_port_dplls));
4625         saved_state->crc_enabled = crtc_state->crc_enabled;
4626         if (IS_G4X(dev_priv) ||
4627             IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
4628                 saved_state->wm = crtc_state->wm;
4629
4630         memcpy(crtc_state, saved_state, sizeof(*crtc_state));
4631         kfree(saved_state);
4632
4633         intel_crtc_copy_uapi_to_hw_state_modeset(state, crtc);
4634
4635         return 0;
4636 }
4637
4638 static int
4639 intel_modeset_pipe_config(struct intel_atomic_state *state,
4640                           struct intel_crtc *crtc)
4641 {
4642         struct drm_i915_private *i915 = to_i915(crtc->base.dev);
4643         struct intel_crtc_state *crtc_state =
4644                 intel_atomic_get_new_crtc_state(state, crtc);
4645         struct drm_connector *connector;
4646         struct drm_connector_state *connector_state;
4647         int pipe_src_w, pipe_src_h;
4648         int base_bpp, ret, i;
4649         bool retry = true;
4650
4651         crtc_state->cpu_transcoder = (enum transcoder) crtc->pipe;
4652
4653         crtc_state->framestart_delay = 1;
4654
4655         /*
4656          * Sanitize sync polarity flags based on requested ones. If neither
4657          * positive or negative polarity is requested, treat this as meaning
4658          * negative polarity.
4659          */
4660         if (!(crtc_state->hw.adjusted_mode.flags &
4661               (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC)))
4662                 crtc_state->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NHSYNC;
4663
4664         if (!(crtc_state->hw.adjusted_mode.flags &
4665               (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC)))
4666                 crtc_state->hw.adjusted_mode.flags |= DRM_MODE_FLAG_NVSYNC;
4667
4668         ret = compute_baseline_pipe_bpp(state, crtc);
4669         if (ret)
4670                 return ret;
4671
4672         base_bpp = crtc_state->pipe_bpp;
4673
4674         /*
4675          * Determine the real pipe dimensions. Note that stereo modes can
4676          * increase the actual pipe size due to the frame doubling and
4677          * insertion of additional space for blanks between the frame. This
4678          * is stored in the crtc timings. We use the requested mode to do this
4679          * computation to clearly distinguish it from the adjusted mode, which
4680          * can be changed by the connectors in the below retry loop.
4681          */
4682         drm_mode_get_hv_timing(&crtc_state->hw.mode,
4683                                &pipe_src_w, &pipe_src_h);
4684         drm_rect_init(&crtc_state->pipe_src, 0, 0,
4685                       pipe_src_w, pipe_src_h);
4686
4687         for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
4688                 struct intel_encoder *encoder =
4689                         to_intel_encoder(connector_state->best_encoder);
4690
4691                 if (connector_state->crtc != &crtc->base)
4692                         continue;
4693
4694                 if (!check_single_encoder_cloning(state, crtc, encoder)) {
4695                         drm_dbg_kms(&i915->drm,
4696                                     "[ENCODER:%d:%s] rejecting invalid cloning configuration\n",
4697                                     encoder->base.base.id, encoder->base.name);
4698                         return -EINVAL;
4699                 }
4700
4701                 /*
4702                  * Determine output_types before calling the .compute_config()
4703                  * hooks so that the hooks can use this information safely.
4704                  */
4705                 if (encoder->compute_output_type)
4706                         crtc_state->output_types |=
4707                                 BIT(encoder->compute_output_type(encoder, crtc_state,
4708                                                                  connector_state));
4709                 else
4710                         crtc_state->output_types |= BIT(encoder->type);
4711         }
4712
4713 encoder_retry:
4714         /* Ensure the port clock defaults are reset when retrying. */
4715         crtc_state->port_clock = 0;
4716         crtc_state->pixel_multiplier = 1;
4717
4718         /* Fill in default crtc timings, allow encoders to overwrite them. */
4719         drm_mode_set_crtcinfo(&crtc_state->hw.adjusted_mode,
4720                               CRTC_STEREO_DOUBLE);
4721
4722         /* Pass our mode to the connectors and the CRTC to give them a chance to
4723          * adjust it according to limitations or connector properties, and also
4724          * a chance to reject the mode entirely.
4725          */
4726         for_each_new_connector_in_state(&state->base, connector, connector_state, i) {
4727                 struct intel_encoder *encoder =
4728                         to_intel_encoder(connector_state->best_encoder);
4729
4730                 if (connector_state->crtc != &crtc->base)
4731                         continue;
4732
4733                 ret = encoder->compute_config(encoder, crtc_state,
4734                                               connector_state);
4735                 if (ret == -EDEADLK)
4736                         return ret;
4737                 if (ret < 0) {
4738                         drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] config failure: %d\n",
4739                                     encoder->base.base.id, encoder->base.name, ret);
4740                         return ret;
4741                 }
4742         }
4743
4744         /* Set default port clock if not overwritten by the encoder. Needs to be
4745          * done afterwards in case the encoder adjusts the mode. */
4746         if (!crtc_state->port_clock)
4747                 crtc_state->port_clock = crtc_state->hw.adjusted_mode.crtc_clock
4748                         * crtc_state->pixel_multiplier;
4749
4750         ret = intel_crtc_compute_config(state, crtc);
4751         if (ret == -EDEADLK)
4752                 return ret;
4753         if (ret == -EAGAIN) {
4754                 if (drm_WARN(&i915->drm, !retry,
4755                              "[CRTC:%d:%s] loop in pipe configuration computation\n",
4756                              crtc->base.base.id, crtc->base.name))
4757                         return -EINVAL;
4758
4759                 drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] bw constrained, retrying\n",
4760                             crtc->base.base.id, crtc->base.name);
4761                 retry = false;
4762                 goto encoder_retry;
4763         }
4764         if (ret < 0) {
4765                 drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] config failure: %d\n",
4766                             crtc->base.base.id, crtc->base.name, ret);
4767                 return ret;
4768         }
4769
4770         /* Dithering seems to not pass-through bits correctly when it should, so
4771          * only enable it on 6bpc panels and when its not a compliance
4772          * test requesting 6bpc video pattern.
4773          */
4774         crtc_state->dither = (crtc_state->pipe_bpp == 6*3) &&
4775                 !crtc_state->dither_force_disable;
4776         drm_dbg_kms(&i915->drm,
4777                     "[CRTC:%d:%s] hw max bpp: %i, pipe bpp: %i, dithering: %i\n",
4778                     crtc->base.base.id, crtc->base.name,
4779                     base_bpp, crtc_state->pipe_bpp, crtc_state->dither);
4780
4781         return 0;
4782 }
4783
4784 static int
4785 intel_modeset_pipe_config_late(struct intel_atomic_state *state,
4786                                struct intel_crtc *crtc)
4787 {
4788         struct intel_crtc_state *crtc_state =
4789                 intel_atomic_get_new_crtc_state(state, crtc);
4790         struct drm_connector_state *conn_state;
4791         struct drm_connector *connector;
4792         int i;
4793
4794         intel_bigjoiner_adjust_pipe_src(crtc_state);
4795
4796         for_each_new_connector_in_state(&state->base, connector,
4797                                         conn_state, i) {
4798                 struct intel_encoder *encoder =
4799                         to_intel_encoder(conn_state->best_encoder);
4800                 int ret;
4801
4802                 if (conn_state->crtc != &crtc->base ||
4803                     !encoder->compute_config_late)
4804                         continue;
4805
4806                 ret = encoder->compute_config_late(encoder, crtc_state,
4807                                                    conn_state);
4808                 if (ret)
4809                         return ret;
4810         }
4811
4812         return 0;
4813 }
4814
4815 bool intel_fuzzy_clock_check(int clock1, int clock2)
4816 {
4817         int diff;
4818
4819         if (clock1 == clock2)
4820                 return true;
4821
4822         if (!clock1 || !clock2)
4823                 return false;
4824
4825         diff = abs(clock1 - clock2);
4826
4827         if (((((diff + clock1 + clock2) * 100)) / (clock1 + clock2)) < 105)
4828                 return true;
4829
4830         return false;
4831 }
4832
4833 static bool
4834 intel_compare_link_m_n(const struct intel_link_m_n *m_n,
4835                        const struct intel_link_m_n *m2_n2)
4836 {
4837         return m_n->tu == m2_n2->tu &&
4838                 m_n->data_m == m2_n2->data_m &&
4839                 m_n->data_n == m2_n2->data_n &&
4840                 m_n->link_m == m2_n2->link_m &&
4841                 m_n->link_n == m2_n2->link_n;
4842 }
4843
4844 static bool
4845 intel_compare_infoframe(const union hdmi_infoframe *a,
4846                         const union hdmi_infoframe *b)
4847 {
4848         return memcmp(a, b, sizeof(*a)) == 0;
4849 }
4850
4851 static bool
4852 intel_compare_dp_vsc_sdp(const struct drm_dp_vsc_sdp *a,
4853                          const struct drm_dp_vsc_sdp *b)
4854 {
4855         return memcmp(a, b, sizeof(*a)) == 0;
4856 }
4857
4858 static bool
4859 intel_compare_buffer(const u8 *a, const u8 *b, size_t len)
4860 {
4861         return memcmp(a, b, len) == 0;
4862 }
4863
4864 static void
4865 pipe_config_infoframe_mismatch(struct drm_i915_private *dev_priv,
4866                                bool fastset, const char *name,
4867                                const union hdmi_infoframe *a,
4868                                const union hdmi_infoframe *b)
4869 {
4870         if (fastset) {
4871                 if (!drm_debug_enabled(DRM_UT_KMS))
4872                         return;
4873
4874                 drm_dbg_kms(&dev_priv->drm,
4875                             "fastset requirement not met in %s infoframe\n", name);
4876                 drm_dbg_kms(&dev_priv->drm, "expected:\n");
4877                 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, a);
4878                 drm_dbg_kms(&dev_priv->drm, "found:\n");
4879                 hdmi_infoframe_log(KERN_DEBUG, dev_priv->drm.dev, b);
4880         } else {
4881                 drm_err(&dev_priv->drm, "mismatch in %s infoframe\n", name);
4882                 drm_err(&dev_priv->drm, "expected:\n");
4883                 hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, a);
4884                 drm_err(&dev_priv->drm, "found:\n");
4885                 hdmi_infoframe_log(KERN_ERR, dev_priv->drm.dev, b);
4886         }
4887 }
4888
4889 static void
4890 pipe_config_dp_vsc_sdp_mismatch(struct drm_i915_private *dev_priv,
4891                                 bool fastset, const char *name,
4892                                 const struct drm_dp_vsc_sdp *a,
4893                                 const struct drm_dp_vsc_sdp *b)
4894 {
4895         if (fastset) {
4896                 if (!drm_debug_enabled(DRM_UT_KMS))
4897                         return;
4898
4899                 drm_dbg_kms(&dev_priv->drm,
4900                             "fastset requirement not met in %s dp sdp\n", name);
4901                 drm_dbg_kms(&dev_priv->drm, "expected:\n");
4902                 drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, a);
4903                 drm_dbg_kms(&dev_priv->drm, "found:\n");
4904                 drm_dp_vsc_sdp_log(KERN_DEBUG, dev_priv->drm.dev, b);
4905         } else {
4906                 drm_err(&dev_priv->drm, "mismatch in %s dp sdp\n", name);
4907                 drm_err(&dev_priv->drm, "expected:\n");
4908                 drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, a);
4909                 drm_err(&dev_priv->drm, "found:\n");
4910                 drm_dp_vsc_sdp_log(KERN_ERR, dev_priv->drm.dev, b);
4911         }
4912 }
4913
4914 /* Returns the length up to and including the last differing byte */
4915 static size_t
4916 memcmp_diff_len(const u8 *a, const u8 *b, size_t len)
4917 {
4918         int i;
4919
4920         for (i = len - 1; i >= 0; i--) {
4921                 if (a[i] != b[i])
4922                         return i + 1;
4923         }
4924
4925         return 0;
4926 }
4927
4928 static void
4929 pipe_config_buffer_mismatch(struct drm_i915_private *dev_priv,
4930                             bool fastset, const char *name,
4931                             const u8 *a, const u8 *b, size_t len)
4932 {
4933         if (fastset) {
4934                 if (!drm_debug_enabled(DRM_UT_KMS))
4935                         return;
4936
4937                 /* only dump up to the last difference */
4938                 len = memcmp_diff_len(a, b, len);
4939
4940                 drm_dbg_kms(&dev_priv->drm,
4941                             "fastset requirement not met in %s buffer\n", name);
4942                 print_hex_dump(KERN_DEBUG, "expected: ", DUMP_PREFIX_NONE,
4943                                16, 0, a, len, false);
4944                 print_hex_dump(KERN_DEBUG, "found: ", DUMP_PREFIX_NONE,
4945                                16, 0, b, len, false);
4946         } else {
4947                 /* only dump up to the last difference */
4948                 len = memcmp_diff_len(a, b, len);
4949
4950                 drm_err(&dev_priv->drm, "mismatch in %s buffer\n", name);
4951                 print_hex_dump(KERN_ERR, "expected: ", DUMP_PREFIX_NONE,
4952                                16, 0, a, len, false);
4953                 print_hex_dump(KERN_ERR, "found: ", DUMP_PREFIX_NONE,
4954                                16, 0, b, len, false);
4955         }
4956 }
4957
4958 static void __printf(4, 5)
4959 pipe_config_mismatch(bool fastset, const struct intel_crtc *crtc,
4960                      const char *name, const char *format, ...)
4961 {
4962         struct drm_i915_private *i915 = to_i915(crtc->base.dev);
4963         struct va_format vaf;
4964         va_list args;
4965
4966         va_start(args, format);
4967         vaf.fmt = format;
4968         vaf.va = &args;
4969
4970         if (fastset)
4971                 drm_dbg_kms(&i915->drm,
4972                             "[CRTC:%d:%s] fastset requirement not met in %s %pV\n",
4973                             crtc->base.base.id, crtc->base.name, name, &vaf);
4974         else
4975                 drm_err(&i915->drm, "[CRTC:%d:%s] mismatch in %s %pV\n",
4976                         crtc->base.base.id, crtc->base.name, name, &vaf);
4977
4978         va_end(args);
4979 }
4980
4981 static bool fastboot_enabled(struct drm_i915_private *dev_priv)
4982 {
4983         if (dev_priv->params.fastboot != -1)
4984                 return dev_priv->params.fastboot;
4985
4986         /* Enable fastboot by default on Skylake and newer */
4987         if (DISPLAY_VER(dev_priv) >= 9)
4988                 return true;
4989
4990         /* Enable fastboot by default on VLV and CHV */
4991         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
4992                 return true;
4993
4994         /* Disabled by default on all others */
4995         return false;
4996 }
4997
4998 bool
4999 intel_pipe_config_compare(const struct intel_crtc_state *current_config,
5000                           const struct intel_crtc_state *pipe_config,
5001                           bool fastset)
5002 {
5003         struct drm_i915_private *dev_priv = to_i915(current_config->uapi.crtc->dev);
5004         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
5005         bool ret = true;
5006         bool fixup_inherited = fastset &&
5007                 current_config->inherited && !pipe_config->inherited;
5008
5009         if (fixup_inherited && !fastboot_enabled(dev_priv)) {
5010                 drm_dbg_kms(&dev_priv->drm,
5011                             "initial modeset and fastboot not set\n");
5012                 ret = false;
5013         }
5014
5015 #define PIPE_CONF_CHECK_X(name) do { \
5016         if (current_config->name != pipe_config->name) { \
5017                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
5018                                      "(expected 0x%08x, found 0x%08x)", \
5019                                      current_config->name, \
5020                                      pipe_config->name); \
5021                 ret = false; \
5022         } \
5023 } while (0)
5024
5025 #define PIPE_CONF_CHECK_X_WITH_MASK(name, mask) do { \
5026         if ((current_config->name & (mask)) != (pipe_config->name & (mask))) { \
5027                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
5028                                      "(expected 0x%08x, found 0x%08x)", \
5029                                      current_config->name & (mask), \
5030                                      pipe_config->name & (mask)); \
5031                 ret = false; \
5032         } \
5033 } while (0)
5034
5035 #define PIPE_CONF_CHECK_I(name) do { \
5036         if (current_config->name != pipe_config->name) { \
5037                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
5038                                      "(expected %i, found %i)", \
5039                                      current_config->name, \
5040                                      pipe_config->name); \
5041                 ret = false; \
5042         } \
5043 } while (0)
5044
5045 #define PIPE_CONF_CHECK_BOOL(name) do { \
5046         if (current_config->name != pipe_config->name) { \
5047                 pipe_config_mismatch(fastset, crtc,  __stringify(name), \
5048                                      "(expected %s, found %s)", \
5049                                      str_yes_no(current_config->name), \
5050                                      str_yes_no(pipe_config->name)); \
5051                 ret = false; \
5052         } \
5053 } while (0)
5054
5055 /*
5056  * Checks state where we only read out the enabling, but not the entire
5057  * state itself (like full infoframes or ELD for audio). These states
5058  * require a full modeset on bootup to fix up.
5059  */
5060 #define PIPE_CONF_CHECK_BOOL_INCOMPLETE(name) do { \
5061         if (!fixup_inherited || (!current_config->name && !pipe_config->name)) { \
5062                 PIPE_CONF_CHECK_BOOL(name); \
5063         } else { \
5064                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
5065                                      "unable to verify whether state matches exactly, forcing modeset (expected %s, found %s)", \
5066                                      str_yes_no(current_config->name), \
5067                                      str_yes_no(pipe_config->name)); \
5068                 ret = false; \
5069         } \
5070 } while (0)
5071
5072 #define PIPE_CONF_CHECK_P(name) do { \
5073         if (current_config->name != pipe_config->name) { \
5074                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
5075                                      "(expected %p, found %p)", \
5076                                      current_config->name, \
5077                                      pipe_config->name); \
5078                 ret = false; \
5079         } \
5080 } while (0)
5081
5082 #define PIPE_CONF_CHECK_M_N(name) do { \
5083         if (!intel_compare_link_m_n(&current_config->name, \
5084                                     &pipe_config->name)) { \
5085                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
5086                                      "(expected tu %i data %i/%i link %i/%i, " \
5087                                      "found tu %i, data %i/%i link %i/%i)", \
5088                                      current_config->name.tu, \
5089                                      current_config->name.data_m, \
5090                                      current_config->name.data_n, \
5091                                      current_config->name.link_m, \
5092                                      current_config->name.link_n, \
5093                                      pipe_config->name.tu, \
5094                                      pipe_config->name.data_m, \
5095                                      pipe_config->name.data_n, \
5096                                      pipe_config->name.link_m, \
5097                                      pipe_config->name.link_n); \
5098                 ret = false; \
5099         } \
5100 } while (0)
5101
5102 #define PIPE_CONF_CHECK_TIMINGS(name) do { \
5103         PIPE_CONF_CHECK_I(name.crtc_hdisplay); \
5104         PIPE_CONF_CHECK_I(name.crtc_htotal); \
5105         PIPE_CONF_CHECK_I(name.crtc_hblank_start); \
5106         PIPE_CONF_CHECK_I(name.crtc_hblank_end); \
5107         PIPE_CONF_CHECK_I(name.crtc_hsync_start); \
5108         PIPE_CONF_CHECK_I(name.crtc_hsync_end); \
5109         PIPE_CONF_CHECK_I(name.crtc_vdisplay); \
5110         PIPE_CONF_CHECK_I(name.crtc_vtotal); \
5111         PIPE_CONF_CHECK_I(name.crtc_vblank_start); \
5112         PIPE_CONF_CHECK_I(name.crtc_vblank_end); \
5113         PIPE_CONF_CHECK_I(name.crtc_vsync_start); \
5114         PIPE_CONF_CHECK_I(name.crtc_vsync_end); \
5115 } while (0)
5116
5117 #define PIPE_CONF_CHECK_RECT(name) do { \
5118         PIPE_CONF_CHECK_I(name.x1); \
5119         PIPE_CONF_CHECK_I(name.x2); \
5120         PIPE_CONF_CHECK_I(name.y1); \
5121         PIPE_CONF_CHECK_I(name.y2); \
5122 } while (0)
5123
5124 #define PIPE_CONF_CHECK_FLAGS(name, mask) do { \
5125         if ((current_config->name ^ pipe_config->name) & (mask)) { \
5126                 pipe_config_mismatch(fastset, crtc, __stringify(name), \
5127                                      "(%x) (expected %i, found %i)", \
5128                                      (mask), \
5129                                      current_config->name & (mask), \
5130                                      pipe_config->name & (mask)); \
5131                 ret = false; \
5132         } \
5133 } while (0)
5134
5135 #define PIPE_CONF_CHECK_INFOFRAME(name) do { \
5136         if (!intel_compare_infoframe(&current_config->infoframes.name, \
5137                                      &pipe_config->infoframes.name)) { \
5138                 pipe_config_infoframe_mismatch(dev_priv, fastset, __stringify(name), \
5139                                                &current_config->infoframes.name, \
5140                                                &pipe_config->infoframes.name); \
5141                 ret = false; \
5142         } \
5143 } while (0)
5144
5145 #define PIPE_CONF_CHECK_DP_VSC_SDP(name) do { \
5146         if (!current_config->has_psr && !pipe_config->has_psr && \
5147             !intel_compare_dp_vsc_sdp(&current_config->infoframes.name, \
5148                                       &pipe_config->infoframes.name)) { \
5149                 pipe_config_dp_vsc_sdp_mismatch(dev_priv, fastset, __stringify(name), \
5150                                                 &current_config->infoframes.name, \
5151                                                 &pipe_config->infoframes.name); \
5152                 ret = false; \
5153         } \
5154 } while (0)
5155
5156 #define PIPE_CONF_CHECK_BUFFER(name, len) do { \
5157         BUILD_BUG_ON(sizeof(current_config->name) != (len)); \
5158         BUILD_BUG_ON(sizeof(pipe_config->name) != (len)); \
5159         if (!intel_compare_buffer(current_config->name, pipe_config->name, (len))) { \
5160                 pipe_config_buffer_mismatch(dev_priv, fastset, __stringify(name), \
5161                                             current_config->name, \
5162                                             pipe_config->name, \
5163                                             (len)); \
5164                 ret = false; \
5165         } \
5166 } while (0)
5167
5168 #define PIPE_CONF_CHECK_COLOR_LUT(lut, is_pre_csc_lut) do { \
5169         if (current_config->gamma_mode == pipe_config->gamma_mode && \
5170             !intel_color_lut_equal(current_config, \
5171                                    current_config->lut, pipe_config->lut, \
5172                                    is_pre_csc_lut)) {   \
5173                 pipe_config_mismatch(fastset, crtc, __stringify(lut), \
5174                                      "hw_state doesn't match sw_state"); \
5175                 ret = false; \
5176         } \
5177 } while (0)
5178
5179 #define PIPE_CONF_CHECK_CSC(name) do { \
5180         PIPE_CONF_CHECK_X(name.preoff[0]); \
5181         PIPE_CONF_CHECK_X(name.preoff[1]); \
5182         PIPE_CONF_CHECK_X(name.preoff[2]); \
5183         PIPE_CONF_CHECK_X(name.coeff[0]); \
5184         PIPE_CONF_CHECK_X(name.coeff[1]); \
5185         PIPE_CONF_CHECK_X(name.coeff[2]); \
5186         PIPE_CONF_CHECK_X(name.coeff[3]); \
5187         PIPE_CONF_CHECK_X(name.coeff[4]); \
5188         PIPE_CONF_CHECK_X(name.coeff[5]); \
5189         PIPE_CONF_CHECK_X(name.coeff[6]); \
5190         PIPE_CONF_CHECK_X(name.coeff[7]); \
5191         PIPE_CONF_CHECK_X(name.coeff[8]); \
5192         PIPE_CONF_CHECK_X(name.postoff[0]); \
5193         PIPE_CONF_CHECK_X(name.postoff[1]); \
5194         PIPE_CONF_CHECK_X(name.postoff[2]); \
5195 } while (0)
5196
5197 #define PIPE_CONF_QUIRK(quirk) \
5198         ((current_config->quirks | pipe_config->quirks) & (quirk))
5199
5200         PIPE_CONF_CHECK_I(hw.enable);
5201         PIPE_CONF_CHECK_I(hw.active);
5202
5203         PIPE_CONF_CHECK_I(cpu_transcoder);
5204         PIPE_CONF_CHECK_I(mst_master_transcoder);
5205
5206         PIPE_CONF_CHECK_BOOL(has_pch_encoder);
5207         PIPE_CONF_CHECK_I(fdi_lanes);
5208         PIPE_CONF_CHECK_M_N(fdi_m_n);
5209
5210         PIPE_CONF_CHECK_I(lane_count);
5211         PIPE_CONF_CHECK_X(lane_lat_optim_mask);
5212
5213         if (HAS_DOUBLE_BUFFERED_M_N(dev_priv)) {
5214                 if (!fastset || !pipe_config->seamless_m_n)
5215                         PIPE_CONF_CHECK_M_N(dp_m_n);
5216         } else {
5217                 PIPE_CONF_CHECK_M_N(dp_m_n);
5218                 PIPE_CONF_CHECK_M_N(dp_m2_n2);
5219         }
5220
5221         PIPE_CONF_CHECK_X(output_types);
5222
5223         PIPE_CONF_CHECK_I(framestart_delay);
5224         PIPE_CONF_CHECK_I(msa_timing_delay);
5225
5226         PIPE_CONF_CHECK_TIMINGS(hw.pipe_mode);
5227         PIPE_CONF_CHECK_TIMINGS(hw.adjusted_mode);
5228
5229         PIPE_CONF_CHECK_I(pixel_multiplier);
5230
5231         PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
5232                               DRM_MODE_FLAG_INTERLACE);
5233
5234         if (!PIPE_CONF_QUIRK(PIPE_CONFIG_QUIRK_MODE_SYNC_FLAGS)) {
5235                 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
5236                                       DRM_MODE_FLAG_PHSYNC);
5237                 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
5238                                       DRM_MODE_FLAG_NHSYNC);
5239                 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
5240                                       DRM_MODE_FLAG_PVSYNC);
5241                 PIPE_CONF_CHECK_FLAGS(hw.adjusted_mode.flags,
5242                                       DRM_MODE_FLAG_NVSYNC);
5243         }
5244
5245         PIPE_CONF_CHECK_I(output_format);
5246         PIPE_CONF_CHECK_BOOL(has_hdmi_sink);
5247         if ((DISPLAY_VER(dev_priv) < 8 && !IS_HASWELL(dev_priv)) ||
5248             IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5249                 PIPE_CONF_CHECK_BOOL(limited_color_range);
5250
5251         PIPE_CONF_CHECK_BOOL(hdmi_scrambling);
5252         PIPE_CONF_CHECK_BOOL(hdmi_high_tmds_clock_ratio);
5253         PIPE_CONF_CHECK_BOOL(has_infoframe);
5254         PIPE_CONF_CHECK_BOOL(fec_enable);
5255
5256         PIPE_CONF_CHECK_BOOL_INCOMPLETE(has_audio);
5257         PIPE_CONF_CHECK_BUFFER(eld, MAX_ELD_BYTES);
5258
5259         PIPE_CONF_CHECK_X(gmch_pfit.control);
5260         /* pfit ratios are autocomputed by the hw on gen4+ */
5261         if (DISPLAY_VER(dev_priv) < 4)
5262                 PIPE_CONF_CHECK_X(gmch_pfit.pgm_ratios);
5263         PIPE_CONF_CHECK_X(gmch_pfit.lvds_border_bits);
5264
5265         /*
5266          * Changing the EDP transcoder input mux
5267          * (A_ONOFF vs. A_ON) requires a full modeset.
5268          */
5269         PIPE_CONF_CHECK_BOOL(pch_pfit.force_thru);
5270
5271         if (!fastset) {
5272                 PIPE_CONF_CHECK_RECT(pipe_src);
5273
5274                 PIPE_CONF_CHECK_BOOL(pch_pfit.enabled);
5275                 PIPE_CONF_CHECK_RECT(pch_pfit.dst);
5276
5277                 PIPE_CONF_CHECK_I(scaler_state.scaler_id);
5278                 PIPE_CONF_CHECK_I(pixel_rate);
5279
5280                 PIPE_CONF_CHECK_X(gamma_mode);
5281                 if (IS_CHERRYVIEW(dev_priv))
5282                         PIPE_CONF_CHECK_X(cgm_mode);
5283                 else
5284                         PIPE_CONF_CHECK_X(csc_mode);
5285                 PIPE_CONF_CHECK_BOOL(gamma_enable);
5286                 PIPE_CONF_CHECK_BOOL(csc_enable);
5287                 PIPE_CONF_CHECK_BOOL(wgc_enable);
5288
5289                 PIPE_CONF_CHECK_I(linetime);
5290                 PIPE_CONF_CHECK_I(ips_linetime);
5291
5292                 PIPE_CONF_CHECK_COLOR_LUT(pre_csc_lut, true);
5293                 PIPE_CONF_CHECK_COLOR_LUT(post_csc_lut, false);
5294
5295                 PIPE_CONF_CHECK_CSC(csc);
5296                 PIPE_CONF_CHECK_CSC(output_csc);
5297
5298                 if (current_config->active_planes) {
5299                         PIPE_CONF_CHECK_BOOL(has_psr);
5300                         PIPE_CONF_CHECK_BOOL(has_psr2);
5301                         PIPE_CONF_CHECK_BOOL(enable_psr2_sel_fetch);
5302                         PIPE_CONF_CHECK_I(dc3co_exitline);
5303                 }
5304         }
5305
5306         PIPE_CONF_CHECK_BOOL(double_wide);
5307
5308         if (dev_priv->display.dpll.mgr) {
5309                 PIPE_CONF_CHECK_P(shared_dpll);
5310
5311                 PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
5312                 PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
5313                 PIPE_CONF_CHECK_X(dpll_hw_state.fp0);
5314                 PIPE_CONF_CHECK_X(dpll_hw_state.fp1);
5315                 PIPE_CONF_CHECK_X(dpll_hw_state.wrpll);
5316                 PIPE_CONF_CHECK_X(dpll_hw_state.spll);
5317                 PIPE_CONF_CHECK_X(dpll_hw_state.ctrl1);
5318                 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr1);
5319                 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr2);
5320                 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr0);
5321                 PIPE_CONF_CHECK_X(dpll_hw_state.div0);
5322                 PIPE_CONF_CHECK_X(dpll_hw_state.ebb0);
5323                 PIPE_CONF_CHECK_X(dpll_hw_state.ebb4);
5324                 PIPE_CONF_CHECK_X(dpll_hw_state.pll0);
5325                 PIPE_CONF_CHECK_X(dpll_hw_state.pll1);
5326                 PIPE_CONF_CHECK_X(dpll_hw_state.pll2);
5327                 PIPE_CONF_CHECK_X(dpll_hw_state.pll3);
5328                 PIPE_CONF_CHECK_X(dpll_hw_state.pll6);
5329                 PIPE_CONF_CHECK_X(dpll_hw_state.pll8);
5330                 PIPE_CONF_CHECK_X(dpll_hw_state.pll9);
5331                 PIPE_CONF_CHECK_X(dpll_hw_state.pll10);
5332                 PIPE_CONF_CHECK_X(dpll_hw_state.pcsdw12);
5333                 PIPE_CONF_CHECK_X(dpll_hw_state.mg_refclkin_ctl);
5334                 PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_coreclkctl1);
5335                 PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_hsclkctl);
5336                 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div0);
5337                 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_div1);
5338                 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_lf);
5339                 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_frac_lock);
5340                 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_ssc);
5341                 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_bias);
5342                 PIPE_CONF_CHECK_X(dpll_hw_state.mg_pll_tdc_coldst_bias);
5343         }
5344
5345         PIPE_CONF_CHECK_X(dsi_pll.ctrl);
5346         PIPE_CONF_CHECK_X(dsi_pll.div);
5347
5348         if (IS_G4X(dev_priv) || DISPLAY_VER(dev_priv) >= 5)
5349                 PIPE_CONF_CHECK_I(pipe_bpp);
5350
5351         if (!fastset || !pipe_config->seamless_m_n) {
5352                 PIPE_CONF_CHECK_I(hw.pipe_mode.crtc_clock);
5353                 PIPE_CONF_CHECK_I(hw.adjusted_mode.crtc_clock);
5354         }
5355         PIPE_CONF_CHECK_I(port_clock);
5356
5357         PIPE_CONF_CHECK_I(min_voltage_level);
5358
5359         if (current_config->has_psr || pipe_config->has_psr)
5360                 PIPE_CONF_CHECK_X_WITH_MASK(infoframes.enable,
5361                                             ~intel_hdmi_infoframe_enable(DP_SDP_VSC));
5362         else
5363                 PIPE_CONF_CHECK_X(infoframes.enable);
5364
5365         PIPE_CONF_CHECK_X(infoframes.gcp);
5366         PIPE_CONF_CHECK_INFOFRAME(avi);
5367         PIPE_CONF_CHECK_INFOFRAME(spd);
5368         PIPE_CONF_CHECK_INFOFRAME(hdmi);
5369         PIPE_CONF_CHECK_INFOFRAME(drm);
5370         PIPE_CONF_CHECK_DP_VSC_SDP(vsc);
5371
5372         PIPE_CONF_CHECK_X(sync_mode_slaves_mask);
5373         PIPE_CONF_CHECK_I(master_transcoder);
5374         PIPE_CONF_CHECK_X(bigjoiner_pipes);
5375
5376         PIPE_CONF_CHECK_I(dsc.compression_enable);
5377         PIPE_CONF_CHECK_I(dsc.dsc_split);
5378         PIPE_CONF_CHECK_I(dsc.compressed_bpp);
5379
5380         PIPE_CONF_CHECK_BOOL(splitter.enable);
5381         PIPE_CONF_CHECK_I(splitter.link_count);
5382         PIPE_CONF_CHECK_I(splitter.pixel_overlap);
5383
5384         if (!fastset)
5385                 PIPE_CONF_CHECK_BOOL(vrr.enable);
5386         PIPE_CONF_CHECK_I(vrr.vmin);
5387         PIPE_CONF_CHECK_I(vrr.vmax);
5388         PIPE_CONF_CHECK_I(vrr.flipline);
5389         PIPE_CONF_CHECK_I(vrr.pipeline_full);
5390         PIPE_CONF_CHECK_I(vrr.guardband);
5391
5392 #undef PIPE_CONF_CHECK_X
5393 #undef PIPE_CONF_CHECK_I
5394 #undef PIPE_CONF_CHECK_BOOL
5395 #undef PIPE_CONF_CHECK_BOOL_INCOMPLETE
5396 #undef PIPE_CONF_CHECK_P
5397 #undef PIPE_CONF_CHECK_FLAGS
5398 #undef PIPE_CONF_CHECK_COLOR_LUT
5399 #undef PIPE_CONF_CHECK_TIMINGS
5400 #undef PIPE_CONF_CHECK_RECT
5401 #undef PIPE_CONF_QUIRK
5402
5403         return ret;
5404 }
5405
5406 static void
5407 intel_verify_planes(struct intel_atomic_state *state)
5408 {
5409         struct intel_plane *plane;
5410         const struct intel_plane_state *plane_state;
5411         int i;
5412
5413         for_each_new_intel_plane_in_state(state, plane,
5414                                           plane_state, i)
5415                 assert_plane(plane, plane_state->planar_slave ||
5416                              plane_state->uapi.visible);
5417 }
5418
5419 int intel_modeset_all_pipes(struct intel_atomic_state *state,
5420                             const char *reason)
5421 {
5422         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
5423         struct intel_crtc *crtc;
5424
5425         /*
5426          * Add all pipes to the state, and force
5427          * a modeset on all the active ones.
5428          */
5429         for_each_intel_crtc(&dev_priv->drm, crtc) {
5430                 struct intel_crtc_state *crtc_state;
5431                 int ret;
5432
5433                 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
5434                 if (IS_ERR(crtc_state))
5435                         return PTR_ERR(crtc_state);
5436
5437                 if (!crtc_state->hw.active ||
5438                     intel_crtc_needs_modeset(crtc_state))
5439                         continue;
5440
5441                 drm_dbg_kms(&dev_priv->drm, "[CRTC:%d:%s] Full modeset due to %s\n",
5442                             crtc->base.base.id, crtc->base.name, reason);
5443
5444                 crtc_state->uapi.mode_changed = true;
5445                 crtc_state->update_pipe = false;
5446
5447                 ret = drm_atomic_add_affected_connectors(&state->base,
5448                                                          &crtc->base);
5449                 if (ret)
5450                         return ret;
5451
5452                 ret = intel_dp_mst_add_topology_state_for_crtc(state, crtc);
5453                 if (ret)
5454                         return ret;
5455
5456                 ret = intel_atomic_add_affected_planes(state, crtc);
5457                 if (ret)
5458                         return ret;
5459
5460                 crtc_state->update_planes |= crtc_state->active_planes;
5461                 crtc_state->async_flip_planes = 0;
5462                 crtc_state->do_async_flip = false;
5463         }
5464
5465         return 0;
5466 }
5467
5468 /*
5469  * This implements the workaround described in the "notes" section of the mode
5470  * set sequence documentation. When going from no pipes or single pipe to
5471  * multiple pipes, and planes are enabled after the pipe, we need to wait at
5472  * least 2 vblanks on the first pipe before enabling planes on the second pipe.
5473  */
5474 static int hsw_mode_set_planes_workaround(struct intel_atomic_state *state)
5475 {
5476         struct intel_crtc_state *crtc_state;
5477         struct intel_crtc *crtc;
5478         struct intel_crtc_state *first_crtc_state = NULL;
5479         struct intel_crtc_state *other_crtc_state = NULL;
5480         enum pipe first_pipe = INVALID_PIPE, enabled_pipe = INVALID_PIPE;
5481         int i;
5482
5483         /* look at all crtc's that are going to be enabled in during modeset */
5484         for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
5485                 if (!crtc_state->hw.active ||
5486                     !intel_crtc_needs_modeset(crtc_state))
5487                         continue;
5488
5489                 if (first_crtc_state) {
5490                         other_crtc_state = crtc_state;
5491                         break;
5492                 } else {
5493                         first_crtc_state = crtc_state;
5494                         first_pipe = crtc->pipe;
5495                 }
5496         }
5497
5498         /* No workaround needed? */
5499         if (!first_crtc_state)
5500                 return 0;
5501
5502         /* w/a possibly needed, check how many crtc's are already enabled. */
5503         for_each_intel_crtc(state->base.dev, crtc) {
5504                 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
5505                 if (IS_ERR(crtc_state))
5506                         return PTR_ERR(crtc_state);
5507
5508                 crtc_state->hsw_workaround_pipe = INVALID_PIPE;
5509
5510                 if (!crtc_state->hw.active ||
5511                     intel_crtc_needs_modeset(crtc_state))
5512                         continue;
5513
5514                 /* 2 or more enabled crtcs means no need for w/a */
5515                 if (enabled_pipe != INVALID_PIPE)
5516                         return 0;
5517
5518                 enabled_pipe = crtc->pipe;
5519         }
5520
5521         if (enabled_pipe != INVALID_PIPE)
5522                 first_crtc_state->hsw_workaround_pipe = enabled_pipe;
5523         else if (other_crtc_state)
5524                 other_crtc_state->hsw_workaround_pipe = first_pipe;
5525
5526         return 0;
5527 }
5528
5529 u8 intel_calc_active_pipes(struct intel_atomic_state *state,
5530                            u8 active_pipes)
5531 {
5532         const struct intel_crtc_state *crtc_state;
5533         struct intel_crtc *crtc;
5534         int i;
5535
5536         for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
5537                 if (crtc_state->hw.active)
5538                         active_pipes |= BIT(crtc->pipe);
5539                 else
5540                         active_pipes &= ~BIT(crtc->pipe);
5541         }
5542
5543         return active_pipes;
5544 }
5545
5546 static int intel_modeset_checks(struct intel_atomic_state *state)
5547 {
5548         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
5549
5550         state->modeset = true;
5551
5552         if (IS_HASWELL(dev_priv))
5553                 return hsw_mode_set_planes_workaround(state);
5554
5555         return 0;
5556 }
5557
5558 static void intel_crtc_check_fastset(const struct intel_crtc_state *old_crtc_state,
5559                                      struct intel_crtc_state *new_crtc_state)
5560 {
5561         struct drm_i915_private *i915 = to_i915(old_crtc_state->uapi.crtc->dev);
5562
5563         if (!intel_pipe_config_compare(old_crtc_state, new_crtc_state, true)) {
5564                 drm_dbg_kms(&i915->drm, "fastset requirement not met, forcing full modeset\n");
5565
5566                 return;
5567         }
5568
5569         new_crtc_state->uapi.mode_changed = false;
5570         if (!intel_crtc_needs_modeset(new_crtc_state))
5571                 new_crtc_state->update_pipe = true;
5572 }
5573
5574 static int intel_crtc_add_planes_to_state(struct intel_atomic_state *state,
5575                                           struct intel_crtc *crtc,
5576                                           u8 plane_ids_mask)
5577 {
5578         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
5579         struct intel_plane *plane;
5580
5581         for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane) {
5582                 struct intel_plane_state *plane_state;
5583
5584                 if ((plane_ids_mask & BIT(plane->id)) == 0)
5585                         continue;
5586
5587                 plane_state = intel_atomic_get_plane_state(state, plane);
5588                 if (IS_ERR(plane_state))
5589                         return PTR_ERR(plane_state);
5590         }
5591
5592         return 0;
5593 }
5594
5595 int intel_atomic_add_affected_planes(struct intel_atomic_state *state,
5596                                      struct intel_crtc *crtc)
5597 {
5598         const struct intel_crtc_state *old_crtc_state =
5599                 intel_atomic_get_old_crtc_state(state, crtc);
5600         const struct intel_crtc_state *new_crtc_state =
5601                 intel_atomic_get_new_crtc_state(state, crtc);
5602
5603         return intel_crtc_add_planes_to_state(state, crtc,
5604                                               old_crtc_state->enabled_planes |
5605                                               new_crtc_state->enabled_planes);
5606 }
5607
5608 static bool active_planes_affects_min_cdclk(struct drm_i915_private *dev_priv)
5609 {
5610         /* See {hsw,vlv,ivb}_plane_ratio() */
5611         return IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv) ||
5612                 IS_CHERRYVIEW(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
5613                 IS_IVYBRIDGE(dev_priv);
5614 }
5615
5616 static int intel_crtc_add_bigjoiner_planes(struct intel_atomic_state *state,
5617                                            struct intel_crtc *crtc,
5618                                            struct intel_crtc *other)
5619 {
5620         const struct intel_plane_state *plane_state;
5621         struct intel_plane *plane;
5622         u8 plane_ids = 0;
5623         int i;
5624
5625         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
5626                 if (plane->pipe == crtc->pipe)
5627                         plane_ids |= BIT(plane->id);
5628         }
5629
5630         return intel_crtc_add_planes_to_state(state, other, plane_ids);
5631 }
5632
5633 static int intel_bigjoiner_add_affected_planes(struct intel_atomic_state *state)
5634 {
5635         struct drm_i915_private *i915 = to_i915(state->base.dev);
5636         const struct intel_crtc_state *crtc_state;
5637         struct intel_crtc *crtc;
5638         int i;
5639
5640         for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
5641                 struct intel_crtc *other;
5642
5643                 for_each_intel_crtc_in_pipe_mask(&i915->drm, other,
5644                                                  crtc_state->bigjoiner_pipes) {
5645                         int ret;
5646
5647                         if (crtc == other)
5648                                 continue;
5649
5650                         ret = intel_crtc_add_bigjoiner_planes(state, crtc, other);
5651                         if (ret)
5652                                 return ret;
5653                 }
5654         }
5655
5656         return 0;
5657 }
5658
5659 static int intel_atomic_check_planes(struct intel_atomic_state *state)
5660 {
5661         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
5662         struct intel_crtc_state *old_crtc_state, *new_crtc_state;
5663         struct intel_plane_state *plane_state;
5664         struct intel_plane *plane;
5665         struct intel_crtc *crtc;
5666         int i, ret;
5667
5668         ret = icl_add_linked_planes(state);
5669         if (ret)
5670                 return ret;
5671
5672         ret = intel_bigjoiner_add_affected_planes(state);
5673         if (ret)
5674                 return ret;
5675
5676         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
5677                 ret = intel_plane_atomic_check(state, plane);
5678                 if (ret) {
5679                         drm_dbg_atomic(&dev_priv->drm,
5680                                        "[PLANE:%d:%s] atomic driver check failed\n",
5681                                        plane->base.base.id, plane->base.name);
5682                         return ret;
5683                 }
5684         }
5685
5686         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
5687                                             new_crtc_state, i) {
5688                 u8 old_active_planes, new_active_planes;
5689
5690                 ret = icl_check_nv12_planes(new_crtc_state);
5691                 if (ret)
5692                         return ret;
5693
5694                 /*
5695                  * On some platforms the number of active planes affects
5696                  * the planes' minimum cdclk calculation. Add such planes
5697                  * to the state before we compute the minimum cdclk.
5698                  */
5699                 if (!active_planes_affects_min_cdclk(dev_priv))
5700                         continue;
5701
5702                 old_active_planes = old_crtc_state->active_planes & ~BIT(PLANE_CURSOR);
5703                 new_active_planes = new_crtc_state->active_planes & ~BIT(PLANE_CURSOR);
5704
5705                 if (hweight8(old_active_planes) == hweight8(new_active_planes))
5706                         continue;
5707
5708                 ret = intel_crtc_add_planes_to_state(state, crtc, new_active_planes);
5709                 if (ret)
5710                         return ret;
5711         }
5712
5713         return 0;
5714 }
5715
5716 static int intel_atomic_check_crtcs(struct intel_atomic_state *state)
5717 {
5718         struct intel_crtc_state *crtc_state;
5719         struct intel_crtc *crtc;
5720         int i;
5721
5722         for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
5723                 struct drm_i915_private *i915 = to_i915(crtc->base.dev);
5724                 int ret;
5725
5726                 ret = intel_crtc_atomic_check(state, crtc);
5727                 if (ret) {
5728                         drm_dbg_atomic(&i915->drm,
5729                                        "[CRTC:%d:%s] atomic driver check failed\n",
5730                                        crtc->base.base.id, crtc->base.name);
5731                         return ret;
5732                 }
5733         }
5734
5735         return 0;
5736 }
5737
5738 static bool intel_cpu_transcoders_need_modeset(struct intel_atomic_state *state,
5739                                                u8 transcoders)
5740 {
5741         const struct intel_crtc_state *new_crtc_state;
5742         struct intel_crtc *crtc;
5743         int i;
5744
5745         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
5746                 if (new_crtc_state->hw.enable &&
5747                     transcoders & BIT(new_crtc_state->cpu_transcoder) &&
5748                     intel_crtc_needs_modeset(new_crtc_state))
5749                         return true;
5750         }
5751
5752         return false;
5753 }
5754
5755 static bool intel_pipes_need_modeset(struct intel_atomic_state *state,
5756                                      u8 pipes)
5757 {
5758         const struct intel_crtc_state *new_crtc_state;
5759         struct intel_crtc *crtc;
5760         int i;
5761
5762         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
5763                 if (new_crtc_state->hw.enable &&
5764                     pipes & BIT(crtc->pipe) &&
5765                     intel_crtc_needs_modeset(new_crtc_state))
5766                         return true;
5767         }
5768
5769         return false;
5770 }
5771
5772 static int intel_atomic_check_bigjoiner(struct intel_atomic_state *state,
5773                                         struct intel_crtc *master_crtc)
5774 {
5775         struct drm_i915_private *i915 = to_i915(state->base.dev);
5776         struct intel_crtc_state *master_crtc_state =
5777                 intel_atomic_get_new_crtc_state(state, master_crtc);
5778         struct intel_crtc *slave_crtc;
5779
5780         if (!master_crtc_state->bigjoiner_pipes)
5781                 return 0;
5782
5783         /* sanity check */
5784         if (drm_WARN_ON(&i915->drm,
5785                         master_crtc->pipe != bigjoiner_master_pipe(master_crtc_state)))
5786                 return -EINVAL;
5787
5788         if (master_crtc_state->bigjoiner_pipes & ~bigjoiner_pipes(i915)) {
5789                 drm_dbg_kms(&i915->drm,
5790                             "[CRTC:%d:%s] Cannot act as big joiner master "
5791                             "(need 0x%x as pipes, only 0x%x possible)\n",
5792                             master_crtc->base.base.id, master_crtc->base.name,
5793                             master_crtc_state->bigjoiner_pipes, bigjoiner_pipes(i915));
5794                 return -EINVAL;
5795         }
5796
5797         for_each_intel_crtc_in_pipe_mask(&i915->drm, slave_crtc,
5798                                          intel_crtc_bigjoiner_slave_pipes(master_crtc_state)) {
5799                 struct intel_crtc_state *slave_crtc_state;
5800                 int ret;
5801
5802                 slave_crtc_state = intel_atomic_get_crtc_state(&state->base, slave_crtc);
5803                 if (IS_ERR(slave_crtc_state))
5804                         return PTR_ERR(slave_crtc_state);
5805
5806                 /* master being enabled, slave was already configured? */
5807                 if (slave_crtc_state->uapi.enable) {
5808                         drm_dbg_kms(&i915->drm,
5809                                     "[CRTC:%d:%s] Slave is enabled as normal CRTC, but "
5810                                     "[CRTC:%d:%s] claiming this CRTC for bigjoiner.\n",
5811                                     slave_crtc->base.base.id, slave_crtc->base.name,
5812                                     master_crtc->base.base.id, master_crtc->base.name);
5813                         return -EINVAL;
5814                 }
5815
5816                 /*
5817                  * The state copy logic assumes the master crtc gets processed
5818                  * before the slave crtc during the main compute_config loop.
5819                  * This works because the crtcs are created in pipe order,
5820                  * and the hardware requires master pipe < slave pipe as well.
5821                  * Should that change we need to rethink the logic.
5822                  */
5823                 if (WARN_ON(drm_crtc_index(&master_crtc->base) >
5824                             drm_crtc_index(&slave_crtc->base)))
5825                         return -EINVAL;
5826
5827                 drm_dbg_kms(&i915->drm,
5828                             "[CRTC:%d:%s] Used as slave for big joiner master [CRTC:%d:%s]\n",
5829                             slave_crtc->base.base.id, slave_crtc->base.name,
5830                             master_crtc->base.base.id, master_crtc->base.name);
5831
5832                 slave_crtc_state->bigjoiner_pipes =
5833                         master_crtc_state->bigjoiner_pipes;
5834
5835                 ret = copy_bigjoiner_crtc_state_modeset(state, slave_crtc);
5836                 if (ret)
5837                         return ret;
5838         }
5839
5840         return 0;
5841 }
5842
5843 static void kill_bigjoiner_slave(struct intel_atomic_state *state,
5844                                  struct intel_crtc *master_crtc)
5845 {
5846         struct drm_i915_private *i915 = to_i915(state->base.dev);
5847         struct intel_crtc_state *master_crtc_state =
5848                 intel_atomic_get_new_crtc_state(state, master_crtc);
5849         struct intel_crtc *slave_crtc;
5850
5851         for_each_intel_crtc_in_pipe_mask(&i915->drm, slave_crtc,
5852                                          intel_crtc_bigjoiner_slave_pipes(master_crtc_state)) {
5853                 struct intel_crtc_state *slave_crtc_state =
5854                         intel_atomic_get_new_crtc_state(state, slave_crtc);
5855
5856                 slave_crtc_state->bigjoiner_pipes = 0;
5857
5858                 intel_crtc_copy_uapi_to_hw_state_modeset(state, slave_crtc);
5859         }
5860
5861         master_crtc_state->bigjoiner_pipes = 0;
5862 }
5863
5864 /**
5865  * DOC: asynchronous flip implementation
5866  *
5867  * Asynchronous page flip is the implementation for the DRM_MODE_PAGE_FLIP_ASYNC
5868  * flag. Currently async flip is only supported via the drmModePageFlip IOCTL.
5869  * Correspondingly, support is currently added for primary plane only.
5870  *
5871  * Async flip can only change the plane surface address, so anything else
5872  * changing is rejected from the intel_async_flip_check_hw() function.
5873  * Once this check is cleared, flip done interrupt is enabled using
5874  * the intel_crtc_enable_flip_done() function.
5875  *
5876  * As soon as the surface address register is written, flip done interrupt is
5877  * generated and the requested events are sent to the usersapce in the interrupt
5878  * handler itself. The timestamp and sequence sent during the flip done event
5879  * correspond to the last vblank and have no relation to the actual time when
5880  * the flip done event was sent.
5881  */
5882 static int intel_async_flip_check_uapi(struct intel_atomic_state *state,
5883                                        struct intel_crtc *crtc)
5884 {
5885         struct drm_i915_private *i915 = to_i915(state->base.dev);
5886         const struct intel_crtc_state *new_crtc_state =
5887                 intel_atomic_get_new_crtc_state(state, crtc);
5888         const struct intel_plane_state *old_plane_state;
5889         struct intel_plane_state *new_plane_state;
5890         struct intel_plane *plane;
5891         int i;
5892
5893         if (!new_crtc_state->uapi.async_flip)
5894                 return 0;
5895
5896         if (!new_crtc_state->uapi.active) {
5897                 drm_dbg_kms(&i915->drm,
5898                             "[CRTC:%d:%s] not active\n",
5899                             crtc->base.base.id, crtc->base.name);
5900                 return -EINVAL;
5901         }
5902
5903         if (intel_crtc_needs_modeset(new_crtc_state)) {
5904                 drm_dbg_kms(&i915->drm,
5905                             "[CRTC:%d:%s] modeset required\n",
5906                             crtc->base.base.id, crtc->base.name);
5907                 return -EINVAL;
5908         }
5909
5910         for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
5911                                              new_plane_state, i) {
5912                 if (plane->pipe != crtc->pipe)
5913                         continue;
5914
5915                 /*
5916                  * TODO: Async flip is only supported through the page flip IOCTL
5917                  * as of now. So support currently added for primary plane only.
5918                  * Support for other planes on platforms on which supports
5919                  * this(vlv/chv and icl+) should be added when async flip is
5920                  * enabled in the atomic IOCTL path.
5921                  */
5922                 if (!plane->async_flip) {
5923                         drm_dbg_kms(&i915->drm,
5924                                     "[PLANE:%d:%s] async flip not supported\n",
5925                                     plane->base.base.id, plane->base.name);
5926                         return -EINVAL;
5927                 }
5928
5929                 if (!old_plane_state->uapi.fb || !new_plane_state->uapi.fb) {
5930                         drm_dbg_kms(&i915->drm,
5931                                     "[PLANE:%d:%s] no old or new framebuffer\n",
5932                                     plane->base.base.id, plane->base.name);
5933                         return -EINVAL;
5934                 }
5935         }
5936
5937         return 0;
5938 }
5939
5940 static int intel_async_flip_check_hw(struct intel_atomic_state *state, struct intel_crtc *crtc)
5941 {
5942         struct drm_i915_private *i915 = to_i915(state->base.dev);
5943         const struct intel_crtc_state *old_crtc_state, *new_crtc_state;
5944         const struct intel_plane_state *new_plane_state, *old_plane_state;
5945         struct intel_plane *plane;
5946         int i;
5947
5948         old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc);
5949         new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
5950
5951         if (!new_crtc_state->uapi.async_flip)
5952                 return 0;
5953
5954         if (!new_crtc_state->hw.active) {
5955                 drm_dbg_kms(&i915->drm,
5956                             "[CRTC:%d:%s] not active\n",
5957                             crtc->base.base.id, crtc->base.name);
5958                 return -EINVAL;
5959         }
5960
5961         if (intel_crtc_needs_modeset(new_crtc_state)) {
5962                 drm_dbg_kms(&i915->drm,
5963                             "[CRTC:%d:%s] modeset required\n",
5964                             crtc->base.base.id, crtc->base.name);
5965                 return -EINVAL;
5966         }
5967
5968         if (old_crtc_state->active_planes != new_crtc_state->active_planes) {
5969                 drm_dbg_kms(&i915->drm,
5970                             "[CRTC:%d:%s] Active planes cannot be in async flip\n",
5971                             crtc->base.base.id, crtc->base.name);
5972                 return -EINVAL;
5973         }
5974
5975         for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
5976                                              new_plane_state, i) {
5977                 if (plane->pipe != crtc->pipe)
5978                         continue;
5979
5980                 /*
5981                  * Only async flip capable planes should be in the state
5982                  * if we're really about to ask the hardware to perform
5983                  * an async flip. We should never get this far otherwise.
5984                  */
5985                 if (drm_WARN_ON(&i915->drm,
5986                                 new_crtc_state->do_async_flip && !plane->async_flip))
5987                         return -EINVAL;
5988
5989                 /*
5990                  * Only check async flip capable planes other planes
5991                  * may be involved in the initial commit due to
5992                  * the wm0/ddb optimization.
5993                  *
5994                  * TODO maybe should track which planes actually
5995                  * were requested to do the async flip...
5996                  */
5997                 if (!plane->async_flip)
5998                         continue;
5999
6000                 /*
6001                  * FIXME: This check is kept generic for all platforms.
6002                  * Need to verify this for all gen9 platforms to enable
6003                  * this selectively if required.
6004                  */
6005                 switch (new_plane_state->hw.fb->modifier) {
6006                 case DRM_FORMAT_MOD_LINEAR:
6007                         /*
6008                          * FIXME: Async on Linear buffer is supported on ICL as
6009                          * but with additional alignment and fbc restrictions
6010                          * need to be taken care of. These aren't applicable for
6011                          * gen12+.
6012                          */
6013                         if (DISPLAY_VER(i915) < 12) {
6014                                 drm_dbg_kms(&i915->drm,
6015                                             "[PLANE:%d:%s] Modifier does not support async flips\n",
6016                                             plane->base.base.id, plane->base.name);
6017                                 return -EINVAL;
6018                         }
6019                         break;
6020
6021                 case I915_FORMAT_MOD_X_TILED:
6022                 case I915_FORMAT_MOD_Y_TILED:
6023                 case I915_FORMAT_MOD_Yf_TILED:
6024                 case I915_FORMAT_MOD_4_TILED:
6025                         break;
6026                 default:
6027                         drm_dbg_kms(&i915->drm,
6028                                     "[PLANE:%d:%s] Modifier does not support async flips\n",
6029                                     plane->base.base.id, plane->base.name);
6030                         return -EINVAL;
6031                 }
6032
6033                 if (new_plane_state->hw.fb->format->num_planes > 1) {
6034                         drm_dbg_kms(&i915->drm,
6035                                     "[PLANE:%d:%s] Planar formats do not support async flips\n",
6036                                     plane->base.base.id, plane->base.name);
6037                         return -EINVAL;
6038                 }
6039
6040                 if (old_plane_state->view.color_plane[0].mapping_stride !=
6041                     new_plane_state->view.color_plane[0].mapping_stride) {
6042                         drm_dbg_kms(&i915->drm,
6043                                     "[PLANE:%d:%s] Stride cannot be changed in async flip\n",
6044                                     plane->base.base.id, plane->base.name);
6045                         return -EINVAL;
6046                 }
6047
6048                 if (old_plane_state->hw.fb->modifier !=
6049                     new_plane_state->hw.fb->modifier) {
6050                         drm_dbg_kms(&i915->drm,
6051                                     "[PLANE:%d:%s] Modifier cannot be changed in async flip\n",
6052                                     plane->base.base.id, plane->base.name);
6053                         return -EINVAL;
6054                 }
6055
6056                 if (old_plane_state->hw.fb->format !=
6057                     new_plane_state->hw.fb->format) {
6058                         drm_dbg_kms(&i915->drm,
6059                                     "[PLANE:%d:%s] Pixel format cannot be changed in async flip\n",
6060                                     plane->base.base.id, plane->base.name);
6061                         return -EINVAL;
6062                 }
6063
6064                 if (old_plane_state->hw.rotation !=
6065                     new_plane_state->hw.rotation) {
6066                         drm_dbg_kms(&i915->drm,
6067                                     "[PLANE:%d:%s] Rotation cannot be changed in async flip\n",
6068                                     plane->base.base.id, plane->base.name);
6069                         return -EINVAL;
6070                 }
6071
6072                 if (!drm_rect_equals(&old_plane_state->uapi.src, &new_plane_state->uapi.src) ||
6073                     !drm_rect_equals(&old_plane_state->uapi.dst, &new_plane_state->uapi.dst)) {
6074                         drm_dbg_kms(&i915->drm,
6075                                     "[PLANE:%d:%s] Size/co-ordinates cannot be changed in async flip\n",
6076                                     plane->base.base.id, plane->base.name);
6077                         return -EINVAL;
6078                 }
6079
6080                 if (old_plane_state->hw.alpha != new_plane_state->hw.alpha) {
6081                         drm_dbg_kms(&i915->drm,
6082                                     "[PLANES:%d:%s] Alpha value cannot be changed in async flip\n",
6083                                     plane->base.base.id, plane->base.name);
6084                         return -EINVAL;
6085                 }
6086
6087                 if (old_plane_state->hw.pixel_blend_mode !=
6088                     new_plane_state->hw.pixel_blend_mode) {
6089                         drm_dbg_kms(&i915->drm,
6090                                     "[PLANE:%d:%s] Pixel blend mode cannot be changed in async flip\n",
6091                                     plane->base.base.id, plane->base.name);
6092                         return -EINVAL;
6093                 }
6094
6095                 if (old_plane_state->hw.color_encoding != new_plane_state->hw.color_encoding) {
6096                         drm_dbg_kms(&i915->drm,
6097                                     "[PLANE:%d:%s] Color encoding cannot be changed in async flip\n",
6098                                     plane->base.base.id, plane->base.name);
6099                         return -EINVAL;
6100                 }
6101
6102                 if (old_plane_state->hw.color_range != new_plane_state->hw.color_range) {
6103                         drm_dbg_kms(&i915->drm,
6104                                     "[PLANE:%d:%s] Color range cannot be changed in async flip\n",
6105                                     plane->base.base.id, plane->base.name);
6106                         return -EINVAL;
6107                 }
6108
6109                 /* plane decryption is allow to change only in synchronous flips */
6110                 if (old_plane_state->decrypt != new_plane_state->decrypt) {
6111                         drm_dbg_kms(&i915->drm,
6112                                     "[PLANE:%d:%s] Decryption cannot be changed in async flip\n",
6113                                     plane->base.base.id, plane->base.name);
6114                         return -EINVAL;
6115                 }
6116         }
6117
6118         return 0;
6119 }
6120
6121 static int intel_bigjoiner_add_affected_crtcs(struct intel_atomic_state *state)
6122 {
6123         struct drm_i915_private *i915 = to_i915(state->base.dev);
6124         struct intel_crtc_state *crtc_state;
6125         struct intel_crtc *crtc;
6126         u8 affected_pipes = 0;
6127         u8 modeset_pipes = 0;
6128         int i;
6129
6130         for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
6131                 affected_pipes |= crtc_state->bigjoiner_pipes;
6132                 if (intel_crtc_needs_modeset(crtc_state))
6133                         modeset_pipes |= crtc_state->bigjoiner_pipes;
6134         }
6135
6136         for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, affected_pipes) {
6137                 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
6138                 if (IS_ERR(crtc_state))
6139                         return PTR_ERR(crtc_state);
6140         }
6141
6142         for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, modeset_pipes) {
6143                 int ret;
6144
6145                 crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
6146
6147                 crtc_state->uapi.mode_changed = true;
6148
6149                 ret = drm_atomic_add_affected_connectors(&state->base, &crtc->base);
6150                 if (ret)
6151                         return ret;
6152
6153                 ret = intel_atomic_add_affected_planes(state, crtc);
6154                 if (ret)
6155                         return ret;
6156         }
6157
6158         for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
6159                 /* Kill old bigjoiner link, we may re-establish afterwards */
6160                 if (intel_crtc_needs_modeset(crtc_state) &&
6161                     intel_crtc_is_bigjoiner_master(crtc_state))
6162                         kill_bigjoiner_slave(state, crtc);
6163         }
6164
6165         return 0;
6166 }
6167
6168 /**
6169  * intel_atomic_check - validate state object
6170  * @dev: drm device
6171  * @_state: state to validate
6172  */
6173 int intel_atomic_check(struct drm_device *dev,
6174                        struct drm_atomic_state *_state)
6175 {
6176         struct drm_i915_private *dev_priv = to_i915(dev);
6177         struct intel_atomic_state *state = to_intel_atomic_state(_state);
6178         struct intel_crtc_state *old_crtc_state, *new_crtc_state;
6179         struct intel_crtc *crtc;
6180         int ret, i;
6181         bool any_ms = false;
6182
6183         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
6184                                             new_crtc_state, i) {
6185                 /*
6186                  * crtc's state no longer considered to be inherited
6187                  * after the first userspace/client initiated commit.
6188                  */
6189                 if (!state->internal)
6190                         new_crtc_state->inherited = false;
6191
6192                 if (new_crtc_state->inherited != old_crtc_state->inherited)
6193                         new_crtc_state->uapi.mode_changed = true;
6194
6195                 if (new_crtc_state->uapi.scaling_filter !=
6196                     old_crtc_state->uapi.scaling_filter)
6197                         new_crtc_state->uapi.mode_changed = true;
6198         }
6199
6200         intel_vrr_check_modeset(state);
6201
6202         ret = drm_atomic_helper_check_modeset(dev, &state->base);
6203         if (ret)
6204                 goto fail;
6205
6206         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
6207                 ret = intel_async_flip_check_uapi(state, crtc);
6208                 if (ret)
6209                         return ret;
6210         }
6211
6212         ret = intel_bigjoiner_add_affected_crtcs(state);
6213         if (ret)
6214                 goto fail;
6215
6216         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
6217                                             new_crtc_state, i) {
6218                 if (!intel_crtc_needs_modeset(new_crtc_state)) {
6219                         if (intel_crtc_is_bigjoiner_slave(new_crtc_state))
6220                                 copy_bigjoiner_crtc_state_nomodeset(state, crtc);
6221                         else
6222                                 intel_crtc_copy_uapi_to_hw_state_nomodeset(state, crtc);
6223                         continue;
6224                 }
6225
6226                 if (intel_crtc_is_bigjoiner_slave(new_crtc_state)) {
6227                         drm_WARN_ON(&dev_priv->drm, new_crtc_state->uapi.enable);
6228                         continue;
6229                 }
6230
6231                 ret = intel_crtc_prepare_cleared_state(state, crtc);
6232                 if (ret)
6233                         goto fail;
6234
6235                 if (!new_crtc_state->hw.enable)
6236                         continue;
6237
6238                 ret = intel_modeset_pipe_config(state, crtc);
6239                 if (ret)
6240                         goto fail;
6241
6242                 ret = intel_atomic_check_bigjoiner(state, crtc);
6243                 if (ret)
6244                         goto fail;
6245         }
6246
6247         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
6248                                             new_crtc_state, i) {
6249                 if (!intel_crtc_needs_modeset(new_crtc_state))
6250                         continue;
6251
6252                 if (new_crtc_state->hw.enable) {
6253                         ret = intel_modeset_pipe_config_late(state, crtc);
6254                         if (ret)
6255                                 goto fail;
6256                 }
6257
6258                 intel_crtc_check_fastset(old_crtc_state, new_crtc_state);
6259         }
6260
6261         /**
6262          * Check if fastset is allowed by external dependencies like other
6263          * pipes and transcoders.
6264          *
6265          * Right now it only forces a fullmodeset when the MST master
6266          * transcoder did not changed but the pipe of the master transcoder
6267          * needs a fullmodeset so all slaves also needs to do a fullmodeset or
6268          * in case of port synced crtcs, if one of the synced crtcs
6269          * needs a full modeset, all other synced crtcs should be
6270          * forced a full modeset.
6271          */
6272         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
6273                 if (!new_crtc_state->hw.enable || intel_crtc_needs_modeset(new_crtc_state))
6274                         continue;
6275
6276                 if (intel_dp_mst_is_slave_trans(new_crtc_state)) {
6277                         enum transcoder master = new_crtc_state->mst_master_transcoder;
6278
6279                         if (intel_cpu_transcoders_need_modeset(state, BIT(master))) {
6280                                 new_crtc_state->uapi.mode_changed = true;
6281                                 new_crtc_state->update_pipe = false;
6282                         }
6283                 }
6284
6285                 if (is_trans_port_sync_mode(new_crtc_state)) {
6286                         u8 trans = new_crtc_state->sync_mode_slaves_mask;
6287
6288                         if (new_crtc_state->master_transcoder != INVALID_TRANSCODER)
6289                                 trans |= BIT(new_crtc_state->master_transcoder);
6290
6291                         if (intel_cpu_transcoders_need_modeset(state, trans)) {
6292                                 new_crtc_state->uapi.mode_changed = true;
6293                                 new_crtc_state->update_pipe = false;
6294                         }
6295                 }
6296
6297                 if (new_crtc_state->bigjoiner_pipes) {
6298                         if (intel_pipes_need_modeset(state, new_crtc_state->bigjoiner_pipes)) {
6299                                 new_crtc_state->uapi.mode_changed = true;
6300                                 new_crtc_state->update_pipe = false;
6301                         }
6302                 }
6303         }
6304
6305         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
6306                                             new_crtc_state, i) {
6307                 if (!intel_crtc_needs_modeset(new_crtc_state))
6308                         continue;
6309
6310                 any_ms = true;
6311
6312                 intel_release_shared_dplls(state, crtc);
6313         }
6314
6315         if (any_ms && !check_digital_port_conflicts(state)) {
6316                 drm_dbg_kms(&dev_priv->drm,
6317                             "rejecting conflicting digital port configuration\n");
6318                 ret = -EINVAL;
6319                 goto fail;
6320         }
6321
6322         ret = drm_dp_mst_atomic_check(&state->base);
6323         if (ret)
6324                 goto fail;
6325
6326         ret = intel_atomic_check_planes(state);
6327         if (ret)
6328                 goto fail;
6329
6330         ret = intel_compute_global_watermarks(state);
6331         if (ret)
6332                 goto fail;
6333
6334         ret = intel_bw_atomic_check(state);
6335         if (ret)
6336                 goto fail;
6337
6338         ret = intel_cdclk_atomic_check(state, &any_ms);
6339         if (ret)
6340                 goto fail;
6341
6342         if (intel_any_crtc_needs_modeset(state))
6343                 any_ms = true;
6344
6345         if (any_ms) {
6346                 ret = intel_modeset_checks(state);
6347                 if (ret)
6348                         goto fail;
6349
6350                 ret = intel_modeset_calc_cdclk(state);
6351                 if (ret)
6352                         return ret;
6353         }
6354
6355         ret = intel_atomic_check_crtcs(state);
6356         if (ret)
6357                 goto fail;
6358
6359         ret = intel_fbc_atomic_check(state);
6360         if (ret)
6361                 goto fail;
6362
6363         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
6364                                             new_crtc_state, i) {
6365                 intel_color_assert_luts(new_crtc_state);
6366
6367                 ret = intel_async_flip_check_hw(state, crtc);
6368                 if (ret)
6369                         goto fail;
6370
6371                 /* Either full modeset or fastset (or neither), never both */
6372                 drm_WARN_ON(&dev_priv->drm,
6373                             intel_crtc_needs_modeset(new_crtc_state) &&
6374                             intel_crtc_needs_fastset(new_crtc_state));
6375
6376                 if (!intel_crtc_needs_modeset(new_crtc_state) &&
6377                     !intel_crtc_needs_fastset(new_crtc_state))
6378                         continue;
6379
6380                 intel_crtc_state_dump(new_crtc_state, state,
6381                                       intel_crtc_needs_modeset(new_crtc_state) ?
6382                                       "modeset" : "fastset");
6383         }
6384
6385         return 0;
6386
6387  fail:
6388         if (ret == -EDEADLK)
6389                 return ret;
6390
6391         /*
6392          * FIXME would probably be nice to know which crtc specifically
6393          * caused the failure, in cases where we can pinpoint it.
6394          */
6395         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
6396                                             new_crtc_state, i)
6397                 intel_crtc_state_dump(new_crtc_state, state, "failed");
6398
6399         return ret;
6400 }
6401
6402 static int intel_atomic_prepare_commit(struct intel_atomic_state *state)
6403 {
6404         struct intel_crtc_state *crtc_state;
6405         struct intel_crtc *crtc;
6406         int i, ret;
6407
6408         ret = drm_atomic_helper_prepare_planes(state->base.dev, &state->base);
6409         if (ret < 0)
6410                 return ret;
6411
6412         for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
6413                 if (intel_crtc_needs_color_update(crtc_state))
6414                         intel_color_prepare_commit(crtc_state);
6415         }
6416
6417         return 0;
6418 }
6419
6420 void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
6421                                   struct intel_crtc_state *crtc_state)
6422 {
6423         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6424
6425         if (DISPLAY_VER(dev_priv) != 2 || crtc_state->active_planes)
6426                 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
6427
6428         if (crtc_state->has_pch_encoder) {
6429                 enum pipe pch_transcoder =
6430                         intel_crtc_pch_transcoder(crtc);
6431
6432                 intel_set_pch_fifo_underrun_reporting(dev_priv, pch_transcoder, true);
6433         }
6434 }
6435
6436 static void intel_pipe_fastset(const struct intel_crtc_state *old_crtc_state,
6437                                const struct intel_crtc_state *new_crtc_state)
6438 {
6439         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
6440         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
6441
6442         /*
6443          * Update pipe size and adjust fitter if needed: the reason for this is
6444          * that in compute_mode_changes we check the native mode (not the pfit
6445          * mode) to see if we can flip rather than do a full mode set. In the
6446          * fastboot case, we'll flip, but if we don't update the pipesrc and
6447          * pfit state, we'll end up with a big fb scanned out into the wrong
6448          * sized surface.
6449          */
6450         intel_set_pipe_src_size(new_crtc_state);
6451
6452         /* on skylake this is done by detaching scalers */
6453         if (DISPLAY_VER(dev_priv) >= 9) {
6454                 if (new_crtc_state->pch_pfit.enabled)
6455                         skl_pfit_enable(new_crtc_state);
6456         } else if (HAS_PCH_SPLIT(dev_priv)) {
6457                 if (new_crtc_state->pch_pfit.enabled)
6458                         ilk_pfit_enable(new_crtc_state);
6459                 else if (old_crtc_state->pch_pfit.enabled)
6460                         ilk_pfit_disable(old_crtc_state);
6461         }
6462
6463         /*
6464          * The register is supposedly single buffered so perhaps
6465          * not 100% correct to do this here. But SKL+ calculate
6466          * this based on the adjust pixel rate so pfit changes do
6467          * affect it and so it must be updated for fastsets.
6468          * HSW/BDW only really need this here for fastboot, after
6469          * that the value should not change without a full modeset.
6470          */
6471         if (DISPLAY_VER(dev_priv) >= 9 ||
6472             IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
6473                 hsw_set_linetime_wm(new_crtc_state);
6474
6475         if (new_crtc_state->seamless_m_n)
6476                 intel_cpu_transcoder_set_m1_n1(crtc, new_crtc_state->cpu_transcoder,
6477                                                &new_crtc_state->dp_m_n);
6478 }
6479
6480 static void commit_pipe_pre_planes(struct intel_atomic_state *state,
6481                                    struct intel_crtc *crtc)
6482 {
6483         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
6484         const struct intel_crtc_state *old_crtc_state =
6485                 intel_atomic_get_old_crtc_state(state, crtc);
6486         const struct intel_crtc_state *new_crtc_state =
6487                 intel_atomic_get_new_crtc_state(state, crtc);
6488         bool modeset = intel_crtc_needs_modeset(new_crtc_state);
6489
6490         /*
6491          * During modesets pipe configuration was programmed as the
6492          * CRTC was enabled.
6493          */
6494         if (!modeset) {
6495                 if (intel_crtc_needs_color_update(new_crtc_state))
6496                         intel_color_commit_arm(new_crtc_state);
6497
6498                 if (DISPLAY_VER(dev_priv) >= 9 || IS_BROADWELL(dev_priv))
6499                         bdw_set_pipe_misc(new_crtc_state);
6500
6501                 if (intel_crtc_needs_fastset(new_crtc_state))
6502                         intel_pipe_fastset(old_crtc_state, new_crtc_state);
6503         }
6504
6505         intel_psr2_program_trans_man_trk_ctl(new_crtc_state);
6506
6507         intel_atomic_update_watermarks(state, crtc);
6508 }
6509
6510 static void commit_pipe_post_planes(struct intel_atomic_state *state,
6511                                     struct intel_crtc *crtc)
6512 {
6513         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
6514         const struct intel_crtc_state *new_crtc_state =
6515                 intel_atomic_get_new_crtc_state(state, crtc);
6516
6517         /*
6518          * Disable the scaler(s) after the plane(s) so that we don't
6519          * get a catastrophic underrun even if the two operations
6520          * end up happening in two different frames.
6521          */
6522         if (DISPLAY_VER(dev_priv) >= 9 &&
6523             !intel_crtc_needs_modeset(new_crtc_state))
6524                 skl_detach_scalers(new_crtc_state);
6525 }
6526
6527 static void intel_enable_crtc(struct intel_atomic_state *state,
6528                               struct intel_crtc *crtc)
6529 {
6530         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
6531         const struct intel_crtc_state *new_crtc_state =
6532                 intel_atomic_get_new_crtc_state(state, crtc);
6533
6534         if (!intel_crtc_needs_modeset(new_crtc_state))
6535                 return;
6536
6537         /* VRR will be enable later, if required */
6538         intel_crtc_update_active_timings(new_crtc_state, false);
6539
6540         dev_priv->display.funcs.display->crtc_enable(state, crtc);
6541
6542         if (intel_crtc_is_bigjoiner_slave(new_crtc_state))
6543                 return;
6544
6545         /* vblanks work again, re-enable pipe CRC. */
6546         intel_crtc_enable_pipe_crc(crtc);
6547 }
6548
6549 static void intel_update_crtc(struct intel_atomic_state *state,
6550                               struct intel_crtc *crtc)
6551 {
6552         struct drm_i915_private *i915 = to_i915(state->base.dev);
6553         const struct intel_crtc_state *old_crtc_state =
6554                 intel_atomic_get_old_crtc_state(state, crtc);
6555         struct intel_crtc_state *new_crtc_state =
6556                 intel_atomic_get_new_crtc_state(state, crtc);
6557         bool modeset = intel_crtc_needs_modeset(new_crtc_state);
6558
6559         if (old_crtc_state->inherited ||
6560             intel_crtc_needs_modeset(new_crtc_state)) {
6561                 if (HAS_DPT(i915))
6562                         intel_dpt_configure(crtc);
6563         }
6564
6565         if (vrr_enabling(old_crtc_state, new_crtc_state)) {
6566                 intel_vrr_enable(new_crtc_state);
6567                 intel_crtc_update_active_timings(new_crtc_state,
6568                                                  new_crtc_state->vrr.enable);
6569         }
6570
6571         if (!modeset) {
6572                 if (new_crtc_state->preload_luts &&
6573                     intel_crtc_needs_color_update(new_crtc_state))
6574                         intel_color_load_luts(new_crtc_state);
6575
6576                 intel_pre_plane_update(state, crtc);
6577
6578                 if (intel_crtc_needs_fastset(new_crtc_state))
6579                         intel_encoders_update_pipe(state, crtc);
6580
6581                 if (DISPLAY_VER(i915) >= 11 &&
6582                     intel_crtc_needs_fastset(new_crtc_state))
6583                         icl_set_pipe_chicken(new_crtc_state);
6584         }
6585
6586         intel_fbc_update(state, crtc);
6587
6588         drm_WARN_ON(&i915->drm, !intel_display_power_is_enabled(i915, POWER_DOMAIN_DC_OFF));
6589
6590         if (!modeset &&
6591             intel_crtc_needs_color_update(new_crtc_state))
6592                 intel_color_commit_noarm(new_crtc_state);
6593
6594         intel_crtc_planes_update_noarm(state, crtc);
6595
6596         /* Perform vblank evasion around commit operation */
6597         intel_pipe_update_start(new_crtc_state);
6598
6599         commit_pipe_pre_planes(state, crtc);
6600
6601         intel_crtc_planes_update_arm(state, crtc);
6602
6603         commit_pipe_post_planes(state, crtc);
6604
6605         intel_pipe_update_end(new_crtc_state);
6606
6607         /*
6608          * We usually enable FIFO underrun interrupts as part of the
6609          * CRTC enable sequence during modesets.  But when we inherit a
6610          * valid pipe configuration from the BIOS we need to take care
6611          * of enabling them on the CRTC's first fastset.
6612          */
6613         if (intel_crtc_needs_fastset(new_crtc_state) && !modeset &&
6614             old_crtc_state->inherited)
6615                 intel_crtc_arm_fifo_underrun(crtc, new_crtc_state);
6616 }
6617
6618 static void intel_old_crtc_state_disables(struct intel_atomic_state *state,
6619                                           struct intel_crtc_state *old_crtc_state,
6620                                           struct intel_crtc_state *new_crtc_state,
6621                                           struct intel_crtc *crtc)
6622 {
6623         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
6624
6625         /*
6626          * We need to disable pipe CRC before disabling the pipe,
6627          * or we race against vblank off.
6628          */
6629         intel_crtc_disable_pipe_crc(crtc);
6630
6631         dev_priv->display.funcs.display->crtc_disable(state, crtc);
6632         crtc->active = false;
6633         intel_fbc_disable(crtc);
6634
6635         if (!new_crtc_state->hw.active)
6636                 intel_initial_watermarks(state, crtc);
6637 }
6638
6639 static void intel_commit_modeset_disables(struct intel_atomic_state *state)
6640 {
6641         struct intel_crtc_state *new_crtc_state, *old_crtc_state;
6642         struct intel_crtc *crtc;
6643         u32 handled = 0;
6644         int i;
6645
6646         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
6647                                             new_crtc_state, i) {
6648                 if (!intel_crtc_needs_modeset(new_crtc_state))
6649                         continue;
6650
6651                 if (!old_crtc_state->hw.active)
6652                         continue;
6653
6654                 intel_pre_plane_update(state, crtc);
6655                 intel_crtc_disable_planes(state, crtc);
6656         }
6657
6658         /* Only disable port sync and MST slaves */
6659         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
6660                                             new_crtc_state, i) {
6661                 if (!intel_crtc_needs_modeset(new_crtc_state))
6662                         continue;
6663
6664                 if (!old_crtc_state->hw.active)
6665                         continue;
6666
6667                 /* In case of Transcoder port Sync master slave CRTCs can be
6668                  * assigned in any order and we need to make sure that
6669                  * slave CRTCs are disabled first and then master CRTC since
6670                  * Slave vblanks are masked till Master Vblanks.
6671                  */
6672                 if (!is_trans_port_sync_slave(old_crtc_state) &&
6673                     !intel_dp_mst_is_slave_trans(old_crtc_state) &&
6674                     !intel_crtc_is_bigjoiner_slave(old_crtc_state))
6675                         continue;
6676
6677                 intel_old_crtc_state_disables(state, old_crtc_state,
6678                                               new_crtc_state, crtc);
6679                 handled |= BIT(crtc->pipe);
6680         }
6681
6682         /* Disable everything else left on */
6683         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
6684                                             new_crtc_state, i) {
6685                 if (!intel_crtc_needs_modeset(new_crtc_state) ||
6686                     (handled & BIT(crtc->pipe)))
6687                         continue;
6688
6689                 if (!old_crtc_state->hw.active)
6690                         continue;
6691
6692                 intel_old_crtc_state_disables(state, old_crtc_state,
6693                                               new_crtc_state, crtc);
6694         }
6695 }
6696
6697 static void intel_commit_modeset_enables(struct intel_atomic_state *state)
6698 {
6699         struct intel_crtc_state *new_crtc_state;
6700         struct intel_crtc *crtc;
6701         int i;
6702
6703         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
6704                 if (!new_crtc_state->hw.active)
6705                         continue;
6706
6707                 intel_enable_crtc(state, crtc);
6708                 intel_update_crtc(state, crtc);
6709         }
6710 }
6711
6712 static void skl_commit_modeset_enables(struct intel_atomic_state *state)
6713 {
6714         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
6715         struct intel_crtc *crtc;
6716         struct intel_crtc_state *old_crtc_state, *new_crtc_state;
6717         struct skl_ddb_entry entries[I915_MAX_PIPES] = {};
6718         u8 update_pipes = 0, modeset_pipes = 0;
6719         int i;
6720
6721         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
6722                 enum pipe pipe = crtc->pipe;
6723
6724                 if (!new_crtc_state->hw.active)
6725                         continue;
6726
6727                 /* ignore allocations for crtc's that have been turned off. */
6728                 if (!intel_crtc_needs_modeset(new_crtc_state)) {
6729                         entries[pipe] = old_crtc_state->wm.skl.ddb;
6730                         update_pipes |= BIT(pipe);
6731                 } else {
6732                         modeset_pipes |= BIT(pipe);
6733                 }
6734         }
6735
6736         /*
6737          * Whenever the number of active pipes changes, we need to make sure we
6738          * update the pipes in the right order so that their ddb allocations
6739          * never overlap with each other between CRTC updates. Otherwise we'll
6740          * cause pipe underruns and other bad stuff.
6741          *
6742          * So first lets enable all pipes that do not need a fullmodeset as
6743          * those don't have any external dependency.
6744          */
6745         while (update_pipes) {
6746                 for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
6747                                                     new_crtc_state, i) {
6748                         enum pipe pipe = crtc->pipe;
6749
6750                         if ((update_pipes & BIT(pipe)) == 0)
6751                                 continue;
6752
6753                         if (skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb,
6754                                                         entries, I915_MAX_PIPES, pipe))
6755                                 continue;
6756
6757                         entries[pipe] = new_crtc_state->wm.skl.ddb;
6758                         update_pipes &= ~BIT(pipe);
6759
6760                         intel_update_crtc(state, crtc);
6761
6762                         /*
6763                          * If this is an already active pipe, it's DDB changed,
6764                          * and this isn't the last pipe that needs updating
6765                          * then we need to wait for a vblank to pass for the
6766                          * new ddb allocation to take effect.
6767                          */
6768                         if (!skl_ddb_entry_equal(&new_crtc_state->wm.skl.ddb,
6769                                                  &old_crtc_state->wm.skl.ddb) &&
6770                             (update_pipes | modeset_pipes))
6771                                 intel_crtc_wait_for_next_vblank(crtc);
6772                 }
6773         }
6774
6775         update_pipes = modeset_pipes;
6776
6777         /*
6778          * Enable all pipes that needs a modeset and do not depends on other
6779          * pipes
6780          */
6781         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
6782                 enum pipe pipe = crtc->pipe;
6783
6784                 if ((modeset_pipes & BIT(pipe)) == 0)
6785                         continue;
6786
6787                 if (intel_dp_mst_is_slave_trans(new_crtc_state) ||
6788                     is_trans_port_sync_master(new_crtc_state) ||
6789                     intel_crtc_is_bigjoiner_master(new_crtc_state))
6790                         continue;
6791
6792                 modeset_pipes &= ~BIT(pipe);
6793
6794                 intel_enable_crtc(state, crtc);
6795         }
6796
6797         /*
6798          * Then we enable all remaining pipes that depend on other
6799          * pipes: MST slaves and port sync masters, big joiner master
6800          */
6801         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
6802                 enum pipe pipe = crtc->pipe;
6803
6804                 if ((modeset_pipes & BIT(pipe)) == 0)
6805                         continue;
6806
6807                 modeset_pipes &= ~BIT(pipe);
6808
6809                 intel_enable_crtc(state, crtc);
6810         }
6811
6812         /*
6813          * Finally we do the plane updates/etc. for all pipes that got enabled.
6814          */
6815         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
6816                 enum pipe pipe = crtc->pipe;
6817
6818                 if ((update_pipes & BIT(pipe)) == 0)
6819                         continue;
6820
6821                 drm_WARN_ON(&dev_priv->drm, skl_ddb_allocation_overlaps(&new_crtc_state->wm.skl.ddb,
6822                                                                         entries, I915_MAX_PIPES, pipe));
6823
6824                 entries[pipe] = new_crtc_state->wm.skl.ddb;
6825                 update_pipes &= ~BIT(pipe);
6826
6827                 intel_update_crtc(state, crtc);
6828         }
6829
6830         drm_WARN_ON(&dev_priv->drm, modeset_pipes);
6831         drm_WARN_ON(&dev_priv->drm, update_pipes);
6832 }
6833
6834 static void intel_atomic_helper_free_state(struct drm_i915_private *dev_priv)
6835 {
6836         struct intel_atomic_state *state, *next;
6837         struct llist_node *freed;
6838
6839         freed = llist_del_all(&dev_priv->display.atomic_helper.free_list);
6840         llist_for_each_entry_safe(state, next, freed, freed)
6841                 drm_atomic_state_put(&state->base);
6842 }
6843
6844 void intel_atomic_helper_free_state_worker(struct work_struct *work)
6845 {
6846         struct drm_i915_private *dev_priv =
6847                 container_of(work, typeof(*dev_priv), display.atomic_helper.free_work);
6848
6849         intel_atomic_helper_free_state(dev_priv);
6850 }
6851
6852 static void intel_atomic_commit_fence_wait(struct intel_atomic_state *intel_state)
6853 {
6854         struct wait_queue_entry wait_fence, wait_reset;
6855         struct drm_i915_private *dev_priv = to_i915(intel_state->base.dev);
6856
6857         init_wait_entry(&wait_fence, 0);
6858         init_wait_entry(&wait_reset, 0);
6859         for (;;) {
6860                 prepare_to_wait(&intel_state->commit_ready.wait,
6861                                 &wait_fence, TASK_UNINTERRUPTIBLE);
6862                 prepare_to_wait(bit_waitqueue(&to_gt(dev_priv)->reset.flags,
6863                                               I915_RESET_MODESET),
6864                                 &wait_reset, TASK_UNINTERRUPTIBLE);
6865
6866
6867                 if (i915_sw_fence_done(&intel_state->commit_ready) ||
6868                     test_bit(I915_RESET_MODESET, &to_gt(dev_priv)->reset.flags))
6869                         break;
6870
6871                 schedule();
6872         }
6873         finish_wait(&intel_state->commit_ready.wait, &wait_fence);
6874         finish_wait(bit_waitqueue(&to_gt(dev_priv)->reset.flags,
6875                                   I915_RESET_MODESET),
6876                     &wait_reset);
6877 }
6878
6879 static void intel_atomic_cleanup_work(struct work_struct *work)
6880 {
6881         struct intel_atomic_state *state =
6882                 container_of(work, struct intel_atomic_state, base.commit_work);
6883         struct drm_i915_private *i915 = to_i915(state->base.dev);
6884         struct intel_crtc_state *old_crtc_state;
6885         struct intel_crtc *crtc;
6886         int i;
6887
6888         for_each_old_intel_crtc_in_state(state, crtc, old_crtc_state, i)
6889                 intel_color_cleanup_commit(old_crtc_state);
6890
6891         drm_atomic_helper_cleanup_planes(&i915->drm, &state->base);
6892         drm_atomic_helper_commit_cleanup_done(&state->base);
6893         drm_atomic_state_put(&state->base);
6894
6895         intel_atomic_helper_free_state(i915);
6896 }
6897
6898 static void intel_atomic_prepare_plane_clear_colors(struct intel_atomic_state *state)
6899 {
6900         struct drm_i915_private *i915 = to_i915(state->base.dev);
6901         struct intel_plane *plane;
6902         struct intel_plane_state *plane_state;
6903         int i;
6904
6905         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
6906                 struct drm_framebuffer *fb = plane_state->hw.fb;
6907                 int cc_plane;
6908                 int ret;
6909
6910                 if (!fb)
6911                         continue;
6912
6913                 cc_plane = intel_fb_rc_ccs_cc_plane(fb);
6914                 if (cc_plane < 0)
6915                         continue;
6916
6917                 /*
6918                  * The layout of the fast clear color value expected by HW
6919                  * (the DRM ABI requiring this value to be located in fb at
6920                  * offset 0 of cc plane, plane #2 previous generations or
6921                  * plane #1 for flat ccs):
6922                  * - 4 x 4 bytes per-channel value
6923                  *   (in surface type specific float/int format provided by the fb user)
6924                  * - 8 bytes native color value used by the display
6925                  *   (converted/written by GPU during a fast clear operation using the
6926                  *    above per-channel values)
6927                  *
6928                  * The commit's FB prepare hook already ensured that FB obj is pinned and the
6929                  * caller made sure that the object is synced wrt. the related color clear value
6930                  * GPU write on it.
6931                  */
6932                 ret = i915_gem_object_read_from_page(intel_fb_obj(fb),
6933                                                      fb->offsets[cc_plane] + 16,
6934                                                      &plane_state->ccval,
6935                                                      sizeof(plane_state->ccval));
6936                 /* The above could only fail if the FB obj has an unexpected backing store type. */
6937                 drm_WARN_ON(&i915->drm, ret);
6938         }
6939 }
6940
6941 static void intel_atomic_commit_tail(struct intel_atomic_state *state)
6942 {
6943         struct drm_device *dev = state->base.dev;
6944         struct drm_i915_private *dev_priv = to_i915(dev);
6945         struct intel_crtc_state *new_crtc_state, *old_crtc_state;
6946         struct intel_crtc *crtc;
6947         struct intel_power_domain_mask put_domains[I915_MAX_PIPES] = {};
6948         intel_wakeref_t wakeref = 0;
6949         int i;
6950
6951         intel_atomic_commit_fence_wait(state);
6952
6953         drm_atomic_helper_wait_for_dependencies(&state->base);
6954         drm_dp_mst_atomic_wait_for_dependencies(&state->base);
6955
6956         /*
6957          * During full modesets we write a lot of registers, wait
6958          * for PLLs, etc. Doing that while DC states are enabled
6959          * is not a good idea.
6960          *
6961          * During fastsets and other updates we also need to
6962          * disable DC states due to the following scenario:
6963          * 1. DC5 exit and PSR exit happen
6964          * 2. Some or all _noarm() registers are written
6965          * 3. Due to some long delay PSR is re-entered
6966          * 4. DC5 entry -> DMC saves the already written new
6967          *    _noarm() registers and the old not yet written
6968          *    _arm() registers
6969          * 5. DC5 exit -> DMC restores a mixture of old and
6970          *    new register values and arms the update
6971          * 6. PSR exit -> hardware latches a mixture of old and
6972          *    new register values -> corrupted frame, or worse
6973          * 7. New _arm() registers are finally written
6974          * 8. Hardware finally latches a complete set of new
6975          *    register values, and subsequent frames will be OK again
6976          *
6977          * Also note that due to the pipe CSC hardware issues on
6978          * SKL/GLK DC states must remain off until the pipe CSC
6979          * state readout has happened. Otherwise we risk corrupting
6980          * the CSC latched register values with the readout (see
6981          * skl_read_csc() and skl_color_commit_noarm()).
6982          */
6983         wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_DC_OFF);
6984
6985         intel_atomic_prepare_plane_clear_colors(state);
6986
6987         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
6988                                             new_crtc_state, i) {
6989                 if (intel_crtc_needs_modeset(new_crtc_state) ||
6990                     intel_crtc_needs_fastset(new_crtc_state))
6991                         intel_modeset_get_crtc_power_domains(new_crtc_state, &put_domains[crtc->pipe]);
6992         }
6993
6994         intel_commit_modeset_disables(state);
6995
6996         /* FIXME: Eventually get rid of our crtc->config pointer */
6997         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
6998                 crtc->config = new_crtc_state;
6999
7000         if (state->modeset) {
7001                 drm_atomic_helper_update_legacy_modeset_state(dev, &state->base);
7002
7003                 intel_set_cdclk_pre_plane_update(state);
7004
7005                 intel_modeset_verify_disabled(dev_priv, state);
7006         }
7007
7008         intel_sagv_pre_plane_update(state);
7009
7010         /* Complete the events for pipes that have now been disabled */
7011         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
7012                 bool modeset = intel_crtc_needs_modeset(new_crtc_state);
7013
7014                 /* Complete events for now disable pipes here. */
7015                 if (modeset && !new_crtc_state->hw.active && new_crtc_state->uapi.event) {
7016                         spin_lock_irq(&dev->event_lock);
7017                         drm_crtc_send_vblank_event(&crtc->base,
7018                                                    new_crtc_state->uapi.event);
7019                         spin_unlock_irq(&dev->event_lock);
7020
7021                         new_crtc_state->uapi.event = NULL;
7022                 }
7023         }
7024
7025         intel_encoders_update_prepare(state);
7026
7027         intel_dbuf_pre_plane_update(state);
7028         intel_mbus_dbox_update(state);
7029
7030         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
7031                 if (new_crtc_state->do_async_flip)
7032                         intel_crtc_enable_flip_done(state, crtc);
7033         }
7034
7035         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
7036         dev_priv->display.funcs.display->commit_modeset_enables(state);
7037
7038         if (state->modeset)
7039                 intel_set_cdclk_post_plane_update(state);
7040
7041         intel_wait_for_vblank_workers(state);
7042
7043         /* FIXME: We should call drm_atomic_helper_commit_hw_done() here
7044          * already, but still need the state for the delayed optimization. To
7045          * fix this:
7046          * - wrap the optimization/post_plane_update stuff into a per-crtc work.
7047          * - schedule that vblank worker _before_ calling hw_done
7048          * - at the start of commit_tail, cancel it _synchrously
7049          * - switch over to the vblank wait helper in the core after that since
7050          *   we don't need out special handling any more.
7051          */
7052         drm_atomic_helper_wait_for_flip_done(dev, &state->base);
7053
7054         for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
7055                 if (new_crtc_state->do_async_flip)
7056                         intel_crtc_disable_flip_done(state, crtc);
7057         }
7058
7059         /*
7060          * Now that the vblank has passed, we can go ahead and program the
7061          * optimal watermarks on platforms that need two-step watermark
7062          * programming.
7063          *
7064          * TODO: Move this (and other cleanup) to an async worker eventually.
7065          */
7066         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
7067                                             new_crtc_state, i) {
7068                 /*
7069                  * Gen2 reports pipe underruns whenever all planes are disabled.
7070                  * So re-enable underrun reporting after some planes get enabled.
7071                  *
7072                  * We do this before .optimize_watermarks() so that we have a
7073                  * chance of catching underruns with the intermediate watermarks
7074                  * vs. the new plane configuration.
7075                  */
7076                 if (DISPLAY_VER(dev_priv) == 2 && planes_enabling(old_crtc_state, new_crtc_state))
7077                         intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true);
7078
7079                 intel_optimize_watermarks(state, crtc);
7080         }
7081
7082         intel_dbuf_post_plane_update(state);
7083         intel_psr_post_plane_update(state);
7084
7085         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
7086                 intel_post_plane_update(state, crtc);
7087
7088                 intel_modeset_put_crtc_power_domains(crtc, &put_domains[crtc->pipe]);
7089
7090                 intel_modeset_verify_crtc(crtc, state, old_crtc_state, new_crtc_state);
7091
7092                 /* Must be done after gamma readout due to HSW split gamma vs. IPS w/a */
7093                 hsw_ips_post_update(state, crtc);
7094
7095                 /*
7096                  * Activate DRRS after state readout to avoid
7097                  * dp_m_n vs. dp_m2_n2 confusion on BDW+.
7098                  */
7099                 intel_drrs_activate(new_crtc_state);
7100
7101                 /*
7102                  * DSB cleanup is done in cleanup_work aligning with framebuffer
7103                  * cleanup. So copy and reset the dsb structure to sync with
7104                  * commit_done and later do dsb cleanup in cleanup_work.
7105                  *
7106                  * FIXME get rid of this funny new->old swapping
7107                  */
7108                 old_crtc_state->dsb = fetch_and_zero(&new_crtc_state->dsb);
7109         }
7110
7111         /* Underruns don't always raise interrupts, so check manually */
7112         intel_check_cpu_fifo_underruns(dev_priv);
7113         intel_check_pch_fifo_underruns(dev_priv);
7114
7115         if (state->modeset)
7116                 intel_verify_planes(state);
7117
7118         intel_sagv_post_plane_update(state);
7119
7120         drm_atomic_helper_commit_hw_done(&state->base);
7121
7122         if (state->modeset) {
7123                 /* As one of the primary mmio accessors, KMS has a high
7124                  * likelihood of triggering bugs in unclaimed access. After we
7125                  * finish modesetting, see if an error has been flagged, and if
7126                  * so enable debugging for the next modeset - and hope we catch
7127                  * the culprit.
7128                  */
7129                 intel_uncore_arm_unclaimed_mmio_detection(&dev_priv->uncore);
7130         }
7131         intel_display_power_put(dev_priv, POWER_DOMAIN_DC_OFF, wakeref);
7132         intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
7133
7134         /*
7135          * Defer the cleanup of the old state to a separate worker to not
7136          * impede the current task (userspace for blocking modesets) that
7137          * are executed inline. For out-of-line asynchronous modesets/flips,
7138          * deferring to a new worker seems overkill, but we would place a
7139          * schedule point (cond_resched()) here anyway to keep latencies
7140          * down.
7141          */
7142         INIT_WORK(&state->base.commit_work, intel_atomic_cleanup_work);
7143         queue_work(system_highpri_wq, &state->base.commit_work);
7144 }
7145
7146 static void intel_atomic_commit_work(struct work_struct *work)
7147 {
7148         struct intel_atomic_state *state =
7149                 container_of(work, struct intel_atomic_state, base.commit_work);
7150
7151         intel_atomic_commit_tail(state);
7152 }
7153
7154 static int
7155 intel_atomic_commit_ready(struct i915_sw_fence *fence,
7156                           enum i915_sw_fence_notify notify)
7157 {
7158         struct intel_atomic_state *state =
7159                 container_of(fence, struct intel_atomic_state, commit_ready);
7160
7161         switch (notify) {
7162         case FENCE_COMPLETE:
7163                 /* we do blocking waits in the worker, nothing to do here */
7164                 break;
7165         case FENCE_FREE:
7166                 {
7167                         struct intel_atomic_helper *helper =
7168                                 &to_i915(state->base.dev)->display.atomic_helper;
7169
7170                         if (llist_add(&state->freed, &helper->free_list))
7171                                 schedule_work(&helper->free_work);
7172                         break;
7173                 }
7174         }
7175
7176         return NOTIFY_DONE;
7177 }
7178
7179 static void intel_atomic_track_fbs(struct intel_atomic_state *state)
7180 {
7181         struct intel_plane_state *old_plane_state, *new_plane_state;
7182         struct intel_plane *plane;
7183         int i;
7184
7185         for_each_oldnew_intel_plane_in_state(state, plane, old_plane_state,
7186                                              new_plane_state, i)
7187                 intel_frontbuffer_track(to_intel_frontbuffer(old_plane_state->hw.fb),
7188                                         to_intel_frontbuffer(new_plane_state->hw.fb),
7189                                         plane->frontbuffer_bit);
7190 }
7191
7192 int intel_atomic_commit(struct drm_device *dev, struct drm_atomic_state *_state,
7193                         bool nonblock)
7194 {
7195         struct intel_atomic_state *state = to_intel_atomic_state(_state);
7196         struct drm_i915_private *dev_priv = to_i915(dev);
7197         int ret = 0;
7198
7199         state->wakeref = intel_runtime_pm_get(&dev_priv->runtime_pm);
7200
7201         drm_atomic_state_get(&state->base);
7202         i915_sw_fence_init(&state->commit_ready,
7203                            intel_atomic_commit_ready);
7204
7205         /*
7206          * The intel_legacy_cursor_update() fast path takes care
7207          * of avoiding the vblank waits for simple cursor
7208          * movement and flips. For cursor on/off and size changes,
7209          * we want to perform the vblank waits so that watermark
7210          * updates happen during the correct frames. Gen9+ have
7211          * double buffered watermarks and so shouldn't need this.
7212          *
7213          * Unset state->legacy_cursor_update before the call to
7214          * drm_atomic_helper_setup_commit() because otherwise
7215          * drm_atomic_helper_wait_for_flip_done() is a noop and
7216          * we get FIFO underruns because we didn't wait
7217          * for vblank.
7218          *
7219          * FIXME doing watermarks and fb cleanup from a vblank worker
7220          * (assuming we had any) would solve these problems.
7221          */
7222         if (DISPLAY_VER(dev_priv) < 9 && state->base.legacy_cursor_update) {
7223                 struct intel_crtc_state *new_crtc_state;
7224                 struct intel_crtc *crtc;
7225                 int i;
7226
7227                 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
7228                         if (new_crtc_state->wm.need_postvbl_update ||
7229                             new_crtc_state->update_wm_post)
7230                                 state->base.legacy_cursor_update = false;
7231         }
7232
7233         ret = intel_atomic_prepare_commit(state);
7234         if (ret) {
7235                 drm_dbg_atomic(&dev_priv->drm,
7236                                "Preparing state failed with %i\n", ret);
7237                 i915_sw_fence_commit(&state->commit_ready);
7238                 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
7239                 return ret;
7240         }
7241
7242         ret = drm_atomic_helper_setup_commit(&state->base, nonblock);
7243         if (!ret)
7244                 ret = drm_atomic_helper_swap_state(&state->base, true);
7245         if (!ret)
7246                 intel_atomic_swap_global_state(state);
7247
7248         if (ret) {
7249                 struct intel_crtc_state *new_crtc_state;
7250                 struct intel_crtc *crtc;
7251                 int i;
7252
7253                 i915_sw_fence_commit(&state->commit_ready);
7254
7255                 for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i)
7256                         intel_color_cleanup_commit(new_crtc_state);
7257
7258                 drm_atomic_helper_cleanup_planes(dev, &state->base);
7259                 intel_runtime_pm_put(&dev_priv->runtime_pm, state->wakeref);
7260                 return ret;
7261         }
7262         intel_shared_dpll_swap_state(state);
7263         intel_atomic_track_fbs(state);
7264
7265         drm_atomic_state_get(&state->base);
7266         INIT_WORK(&state->base.commit_work, intel_atomic_commit_work);
7267
7268         i915_sw_fence_commit(&state->commit_ready);
7269         if (nonblock && state->modeset) {
7270                 queue_work(dev_priv->display.wq.modeset, &state->base.commit_work);
7271         } else if (nonblock) {
7272                 queue_work(dev_priv->display.wq.flip, &state->base.commit_work);
7273         } else {
7274                 if (state->modeset)
7275                         flush_workqueue(dev_priv->display.wq.modeset);
7276                 intel_atomic_commit_tail(state);
7277         }
7278
7279         return 0;
7280 }
7281
7282 /**
7283  * intel_plane_destroy - destroy a plane
7284  * @plane: plane to destroy
7285  *
7286  * Common destruction function for all types of planes (primary, cursor,
7287  * sprite).
7288  */
7289 void intel_plane_destroy(struct drm_plane *plane)
7290 {
7291         drm_plane_cleanup(plane);
7292         kfree(to_intel_plane(plane));
7293 }
7294
7295 int intel_get_pipe_from_crtc_id_ioctl(struct drm_device *dev, void *data,
7296                                       struct drm_file *file)
7297 {
7298         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
7299         struct drm_crtc *drmmode_crtc;
7300         struct intel_crtc *crtc;
7301
7302         drmmode_crtc = drm_crtc_find(dev, file, pipe_from_crtc_id->crtc_id);
7303         if (!drmmode_crtc)
7304                 return -ENOENT;
7305
7306         crtc = to_intel_crtc(drmmode_crtc);
7307         pipe_from_crtc_id->pipe = crtc->pipe;
7308
7309         return 0;
7310 }
7311
7312 static u32 intel_encoder_possible_clones(struct intel_encoder *encoder)
7313 {
7314         struct drm_device *dev = encoder->base.dev;
7315         struct intel_encoder *source_encoder;
7316         u32 possible_clones = 0;
7317
7318         for_each_intel_encoder(dev, source_encoder) {
7319                 if (encoders_cloneable(encoder, source_encoder))
7320                         possible_clones |= drm_encoder_mask(&source_encoder->base);
7321         }
7322
7323         return possible_clones;
7324 }
7325
7326 static u32 intel_encoder_possible_crtcs(struct intel_encoder *encoder)
7327 {
7328         struct drm_device *dev = encoder->base.dev;
7329         struct intel_crtc *crtc;
7330         u32 possible_crtcs = 0;
7331
7332         for_each_intel_crtc_in_pipe_mask(dev, crtc, encoder->pipe_mask)
7333                 possible_crtcs |= drm_crtc_mask(&crtc->base);
7334
7335         return possible_crtcs;
7336 }
7337
7338 static bool ilk_has_edp_a(struct drm_i915_private *dev_priv)
7339 {
7340         if (!IS_MOBILE(dev_priv))
7341                 return false;
7342
7343         if ((intel_de_read(dev_priv, DP_A) & DP_DETECTED) == 0)
7344                 return false;
7345
7346         if (IS_IRONLAKE(dev_priv) && (intel_de_read(dev_priv, FUSE_STRAP) & ILK_eDP_A_DISABLE))
7347                 return false;
7348
7349         return true;
7350 }
7351
7352 static bool intel_ddi_crt_present(struct drm_i915_private *dev_priv)
7353 {
7354         if (DISPLAY_VER(dev_priv) >= 9)
7355                 return false;
7356
7357         if (IS_HSW_ULT(dev_priv) || IS_BDW_ULT(dev_priv))
7358                 return false;
7359
7360         if (HAS_PCH_LPT_H(dev_priv) &&
7361             intel_de_read(dev_priv, SFUSE_STRAP) & SFUSE_STRAP_CRT_DISABLED)
7362                 return false;
7363
7364         /* DDI E can't be used if DDI A requires 4 lanes */
7365         if (intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)
7366                 return false;
7367
7368         if (!dev_priv->display.vbt.int_crt_support)
7369                 return false;
7370
7371         return true;
7372 }
7373
7374 void intel_setup_outputs(struct drm_i915_private *dev_priv)
7375 {
7376         struct intel_encoder *encoder;
7377         bool dpd_is_edp = false;
7378
7379         intel_pps_unlock_regs_wa(dev_priv);
7380
7381         if (!HAS_DISPLAY(dev_priv))
7382                 return;
7383
7384         if (IS_METEORLAKE(dev_priv)) {
7385                 intel_ddi_init(dev_priv, PORT_A);
7386                 intel_ddi_init(dev_priv, PORT_B);
7387                 intel_ddi_init(dev_priv, PORT_TC1);
7388                 intel_ddi_init(dev_priv, PORT_TC2);
7389                 intel_ddi_init(dev_priv, PORT_TC3);
7390                 intel_ddi_init(dev_priv, PORT_TC4);
7391         } else if (IS_DG2(dev_priv)) {
7392                 intel_ddi_init(dev_priv, PORT_A);
7393                 intel_ddi_init(dev_priv, PORT_B);
7394                 intel_ddi_init(dev_priv, PORT_C);
7395                 intel_ddi_init(dev_priv, PORT_D_XELPD);
7396                 intel_ddi_init(dev_priv, PORT_TC1);
7397         } else if (IS_ALDERLAKE_P(dev_priv)) {
7398                 intel_ddi_init(dev_priv, PORT_A);
7399                 intel_ddi_init(dev_priv, PORT_B);
7400                 intel_ddi_init(dev_priv, PORT_TC1);
7401                 intel_ddi_init(dev_priv, PORT_TC2);
7402                 intel_ddi_init(dev_priv, PORT_TC3);
7403                 intel_ddi_init(dev_priv, PORT_TC4);
7404                 icl_dsi_init(dev_priv);
7405         } else if (IS_ALDERLAKE_S(dev_priv)) {
7406                 intel_ddi_init(dev_priv, PORT_A);
7407                 intel_ddi_init(dev_priv, PORT_TC1);
7408                 intel_ddi_init(dev_priv, PORT_TC2);
7409                 intel_ddi_init(dev_priv, PORT_TC3);
7410                 intel_ddi_init(dev_priv, PORT_TC4);
7411         } else if (IS_DG1(dev_priv) || IS_ROCKETLAKE(dev_priv)) {
7412                 intel_ddi_init(dev_priv, PORT_A);
7413                 intel_ddi_init(dev_priv, PORT_B);
7414                 intel_ddi_init(dev_priv, PORT_TC1);
7415                 intel_ddi_init(dev_priv, PORT_TC2);
7416         } else if (DISPLAY_VER(dev_priv) >= 12) {
7417                 intel_ddi_init(dev_priv, PORT_A);
7418                 intel_ddi_init(dev_priv, PORT_B);
7419                 intel_ddi_init(dev_priv, PORT_TC1);
7420                 intel_ddi_init(dev_priv, PORT_TC2);
7421                 intel_ddi_init(dev_priv, PORT_TC3);
7422                 intel_ddi_init(dev_priv, PORT_TC4);
7423                 intel_ddi_init(dev_priv, PORT_TC5);
7424                 intel_ddi_init(dev_priv, PORT_TC6);
7425                 icl_dsi_init(dev_priv);
7426         } else if (IS_JSL_EHL(dev_priv)) {
7427                 intel_ddi_init(dev_priv, PORT_A);
7428                 intel_ddi_init(dev_priv, PORT_B);
7429                 intel_ddi_init(dev_priv, PORT_C);
7430                 intel_ddi_init(dev_priv, PORT_D);
7431                 icl_dsi_init(dev_priv);
7432         } else if (DISPLAY_VER(dev_priv) == 11) {
7433                 intel_ddi_init(dev_priv, PORT_A);
7434                 intel_ddi_init(dev_priv, PORT_B);
7435                 intel_ddi_init(dev_priv, PORT_C);
7436                 intel_ddi_init(dev_priv, PORT_D);
7437                 intel_ddi_init(dev_priv, PORT_E);
7438                 intel_ddi_init(dev_priv, PORT_F);
7439                 icl_dsi_init(dev_priv);
7440         } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
7441                 intel_ddi_init(dev_priv, PORT_A);
7442                 intel_ddi_init(dev_priv, PORT_B);
7443                 intel_ddi_init(dev_priv, PORT_C);
7444                 vlv_dsi_init(dev_priv);
7445         } else if (DISPLAY_VER(dev_priv) >= 9) {
7446                 intel_ddi_init(dev_priv, PORT_A);
7447                 intel_ddi_init(dev_priv, PORT_B);
7448                 intel_ddi_init(dev_priv, PORT_C);
7449                 intel_ddi_init(dev_priv, PORT_D);
7450                 intel_ddi_init(dev_priv, PORT_E);
7451         } else if (HAS_DDI(dev_priv)) {
7452                 u32 found;
7453
7454                 if (intel_ddi_crt_present(dev_priv))
7455                         intel_crt_init(dev_priv);
7456
7457                 /* Haswell uses DDI functions to detect digital outputs. */
7458                 found = intel_de_read(dev_priv, DDI_BUF_CTL(PORT_A)) & DDI_INIT_DISPLAY_DETECTED;
7459                 if (found)
7460                         intel_ddi_init(dev_priv, PORT_A);
7461
7462                 found = intel_de_read(dev_priv, SFUSE_STRAP);
7463                 if (found & SFUSE_STRAP_DDIB_DETECTED)
7464                         intel_ddi_init(dev_priv, PORT_B);
7465                 if (found & SFUSE_STRAP_DDIC_DETECTED)
7466                         intel_ddi_init(dev_priv, PORT_C);
7467                 if (found & SFUSE_STRAP_DDID_DETECTED)
7468                         intel_ddi_init(dev_priv, PORT_D);
7469                 if (found & SFUSE_STRAP_DDIF_DETECTED)
7470                         intel_ddi_init(dev_priv, PORT_F);
7471         } else if (HAS_PCH_SPLIT(dev_priv)) {
7472                 int found;
7473
7474                 /*
7475                  * intel_edp_init_connector() depends on this completing first,
7476                  * to prevent the registration of both eDP and LVDS and the
7477                  * incorrect sharing of the PPS.
7478                  */
7479                 intel_lvds_init(dev_priv);
7480                 intel_crt_init(dev_priv);
7481
7482                 dpd_is_edp = intel_dp_is_port_edp(dev_priv, PORT_D);
7483
7484                 if (ilk_has_edp_a(dev_priv))
7485                         g4x_dp_init(dev_priv, DP_A, PORT_A);
7486
7487                 if (intel_de_read(dev_priv, PCH_HDMIB) & SDVO_DETECTED) {
7488                         /* PCH SDVOB multiplex with HDMIB */
7489                         found = intel_sdvo_init(dev_priv, PCH_SDVOB, PORT_B);
7490                         if (!found)
7491                                 g4x_hdmi_init(dev_priv, PCH_HDMIB, PORT_B);
7492                         if (!found && (intel_de_read(dev_priv, PCH_DP_B) & DP_DETECTED))
7493                                 g4x_dp_init(dev_priv, PCH_DP_B, PORT_B);
7494                 }
7495
7496                 if (intel_de_read(dev_priv, PCH_HDMIC) & SDVO_DETECTED)
7497                         g4x_hdmi_init(dev_priv, PCH_HDMIC, PORT_C);
7498
7499                 if (!dpd_is_edp && intel_de_read(dev_priv, PCH_HDMID) & SDVO_DETECTED)
7500                         g4x_hdmi_init(dev_priv, PCH_HDMID, PORT_D);
7501
7502                 if (intel_de_read(dev_priv, PCH_DP_C) & DP_DETECTED)
7503                         g4x_dp_init(dev_priv, PCH_DP_C, PORT_C);
7504
7505                 if (intel_de_read(dev_priv, PCH_DP_D) & DP_DETECTED)
7506                         g4x_dp_init(dev_priv, PCH_DP_D, PORT_D);
7507         } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
7508                 bool has_edp, has_port;
7509
7510                 if (IS_VALLEYVIEW(dev_priv) && dev_priv->display.vbt.int_crt_support)
7511                         intel_crt_init(dev_priv);
7512
7513                 /*
7514                  * The DP_DETECTED bit is the latched state of the DDC
7515                  * SDA pin at boot. However since eDP doesn't require DDC
7516                  * (no way to plug in a DP->HDMI dongle) the DDC pins for
7517                  * eDP ports may have been muxed to an alternate function.
7518                  * Thus we can't rely on the DP_DETECTED bit alone to detect
7519                  * eDP ports. Consult the VBT as well as DP_DETECTED to
7520                  * detect eDP ports.
7521                  *
7522                  * Sadly the straps seem to be missing sometimes even for HDMI
7523                  * ports (eg. on Voyo V3 - CHT x7-Z8700), so check both strap
7524                  * and VBT for the presence of the port. Additionally we can't
7525                  * trust the port type the VBT declares as we've seen at least
7526                  * HDMI ports that the VBT claim are DP or eDP.
7527                  */
7528                 has_edp = intel_dp_is_port_edp(dev_priv, PORT_B);
7529                 has_port = intel_bios_is_port_present(dev_priv, PORT_B);
7530                 if (intel_de_read(dev_priv, VLV_DP_B) & DP_DETECTED || has_port)
7531                         has_edp &= g4x_dp_init(dev_priv, VLV_DP_B, PORT_B);
7532                 if ((intel_de_read(dev_priv, VLV_HDMIB) & SDVO_DETECTED || has_port) && !has_edp)
7533                         g4x_hdmi_init(dev_priv, VLV_HDMIB, PORT_B);
7534
7535                 has_edp = intel_dp_is_port_edp(dev_priv, PORT_C);
7536                 has_port = intel_bios_is_port_present(dev_priv, PORT_C);
7537                 if (intel_de_read(dev_priv, VLV_DP_C) & DP_DETECTED || has_port)
7538                         has_edp &= g4x_dp_init(dev_priv, VLV_DP_C, PORT_C);
7539                 if ((intel_de_read(dev_priv, VLV_HDMIC) & SDVO_DETECTED || has_port) && !has_edp)
7540                         g4x_hdmi_init(dev_priv, VLV_HDMIC, PORT_C);
7541
7542                 if (IS_CHERRYVIEW(dev_priv)) {
7543                         /*
7544                          * eDP not supported on port D,
7545                          * so no need to worry about it
7546                          */
7547                         has_port = intel_bios_is_port_present(dev_priv, PORT_D);
7548                         if (intel_de_read(dev_priv, CHV_DP_D) & DP_DETECTED || has_port)
7549                                 g4x_dp_init(dev_priv, CHV_DP_D, PORT_D);
7550                         if (intel_de_read(dev_priv, CHV_HDMID) & SDVO_DETECTED || has_port)
7551                                 g4x_hdmi_init(dev_priv, CHV_HDMID, PORT_D);
7552                 }
7553
7554                 vlv_dsi_init(dev_priv);
7555         } else if (IS_PINEVIEW(dev_priv)) {
7556                 intel_lvds_init(dev_priv);
7557                 intel_crt_init(dev_priv);
7558         } else if (IS_DISPLAY_VER(dev_priv, 3, 4)) {
7559                 bool found = false;
7560
7561                 if (IS_MOBILE(dev_priv))
7562                         intel_lvds_init(dev_priv);
7563
7564                 intel_crt_init(dev_priv);
7565
7566                 if (intel_de_read(dev_priv, GEN3_SDVOB) & SDVO_DETECTED) {
7567                         drm_dbg_kms(&dev_priv->drm, "probing SDVOB\n");
7568                         found = intel_sdvo_init(dev_priv, GEN3_SDVOB, PORT_B);
7569                         if (!found && IS_G4X(dev_priv)) {
7570                                 drm_dbg_kms(&dev_priv->drm,
7571                                             "probing HDMI on SDVOB\n");
7572                                 g4x_hdmi_init(dev_priv, GEN4_HDMIB, PORT_B);
7573                         }
7574
7575                         if (!found && IS_G4X(dev_priv))
7576                                 g4x_dp_init(dev_priv, DP_B, PORT_B);
7577                 }
7578
7579                 /* Before G4X SDVOC doesn't have its own detect register */
7580
7581                 if (intel_de_read(dev_priv, GEN3_SDVOB) & SDVO_DETECTED) {
7582                         drm_dbg_kms(&dev_priv->drm, "probing SDVOC\n");
7583                         found = intel_sdvo_init(dev_priv, GEN3_SDVOC, PORT_C);
7584                 }
7585
7586                 if (!found && (intel_de_read(dev_priv, GEN3_SDVOC) & SDVO_DETECTED)) {
7587
7588                         if (IS_G4X(dev_priv)) {
7589                                 drm_dbg_kms(&dev_priv->drm,
7590                                             "probing HDMI on SDVOC\n");
7591                                 g4x_hdmi_init(dev_priv, GEN4_HDMIC, PORT_C);
7592                         }
7593                         if (IS_G4X(dev_priv))
7594                                 g4x_dp_init(dev_priv, DP_C, PORT_C);
7595                 }
7596
7597                 if (IS_G4X(dev_priv) && (intel_de_read(dev_priv, DP_D) & DP_DETECTED))
7598                         g4x_dp_init(dev_priv, DP_D, PORT_D);
7599
7600                 if (SUPPORTS_TV(dev_priv))
7601                         intel_tv_init(dev_priv);
7602         } else if (DISPLAY_VER(dev_priv) == 2) {
7603                 if (IS_I85X(dev_priv))
7604                         intel_lvds_init(dev_priv);
7605
7606                 intel_crt_init(dev_priv);
7607                 intel_dvo_init(dev_priv);
7608         }
7609
7610         for_each_intel_encoder(&dev_priv->drm, encoder) {
7611                 encoder->base.possible_crtcs =
7612                         intel_encoder_possible_crtcs(encoder);
7613                 encoder->base.possible_clones =
7614                         intel_encoder_possible_clones(encoder);
7615         }
7616
7617         intel_init_pch_refclk(dev_priv);
7618
7619         drm_helper_move_panel_connectors_to_head(&dev_priv->drm);
7620 }
7621
7622 static int max_dotclock(struct drm_i915_private *i915)
7623 {
7624         int max_dotclock = i915->max_dotclk_freq;
7625
7626         /* icl+ might use bigjoiner */
7627         if (DISPLAY_VER(i915) >= 11)
7628                 max_dotclock *= 2;
7629
7630         return max_dotclock;
7631 }
7632
7633 enum drm_mode_status intel_mode_valid(struct drm_device *dev,
7634                                       const struct drm_display_mode *mode)
7635 {
7636         struct drm_i915_private *dev_priv = to_i915(dev);
7637         int hdisplay_max, htotal_max;
7638         int vdisplay_max, vtotal_max;
7639
7640         /*
7641          * Can't reject DBLSCAN here because Xorg ddxen can add piles
7642          * of DBLSCAN modes to the output's mode list when they detect
7643          * the scaling mode property on the connector. And they don't
7644          * ask the kernel to validate those modes in any way until
7645          * modeset time at which point the client gets a protocol error.
7646          * So in order to not upset those clients we silently ignore the
7647          * DBLSCAN flag on such connectors. For other connectors we will
7648          * reject modes with the DBLSCAN flag in encoder->compute_config().
7649          * And we always reject DBLSCAN modes in connector->mode_valid()
7650          * as we never want such modes on the connector's mode list.
7651          */
7652
7653         if (mode->vscan > 1)
7654                 return MODE_NO_VSCAN;
7655
7656         if (mode->flags & DRM_MODE_FLAG_HSKEW)
7657                 return MODE_H_ILLEGAL;
7658
7659         if (mode->flags & (DRM_MODE_FLAG_CSYNC |
7660                            DRM_MODE_FLAG_NCSYNC |
7661                            DRM_MODE_FLAG_PCSYNC))
7662                 return MODE_HSYNC;
7663
7664         if (mode->flags & (DRM_MODE_FLAG_BCAST |
7665                            DRM_MODE_FLAG_PIXMUX |
7666                            DRM_MODE_FLAG_CLKDIV2))
7667                 return MODE_BAD;
7668
7669         /*
7670          * Reject clearly excessive dotclocks early to
7671          * avoid having to worry about huge integers later.
7672          */
7673         if (mode->clock > max_dotclock(dev_priv))
7674                 return MODE_CLOCK_HIGH;
7675
7676         /* Transcoder timing limits */
7677         if (DISPLAY_VER(dev_priv) >= 11) {
7678                 hdisplay_max = 16384;
7679                 vdisplay_max = 8192;
7680                 htotal_max = 16384;
7681                 vtotal_max = 8192;
7682         } else if (DISPLAY_VER(dev_priv) >= 9 ||
7683                    IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) {
7684                 hdisplay_max = 8192; /* FDI max 4096 handled elsewhere */
7685                 vdisplay_max = 4096;
7686                 htotal_max = 8192;
7687                 vtotal_max = 8192;
7688         } else if (DISPLAY_VER(dev_priv) >= 3) {
7689                 hdisplay_max = 4096;
7690                 vdisplay_max = 4096;
7691                 htotal_max = 8192;
7692                 vtotal_max = 8192;
7693         } else {
7694                 hdisplay_max = 2048;
7695                 vdisplay_max = 2048;
7696                 htotal_max = 4096;
7697                 vtotal_max = 4096;
7698         }
7699
7700         if (mode->hdisplay > hdisplay_max ||
7701             mode->hsync_start > htotal_max ||
7702             mode->hsync_end > htotal_max ||
7703             mode->htotal > htotal_max)
7704                 return MODE_H_ILLEGAL;
7705
7706         if (mode->vdisplay > vdisplay_max ||
7707             mode->vsync_start > vtotal_max ||
7708             mode->vsync_end > vtotal_max ||
7709             mode->vtotal > vtotal_max)
7710                 return MODE_V_ILLEGAL;
7711
7712         if (DISPLAY_VER(dev_priv) >= 5) {
7713                 if (mode->hdisplay < 64 ||
7714                     mode->htotal - mode->hdisplay < 32)
7715                         return MODE_H_ILLEGAL;
7716
7717                 if (mode->vtotal - mode->vdisplay < 5)
7718                         return MODE_V_ILLEGAL;
7719         } else {
7720                 if (mode->htotal - mode->hdisplay < 32)
7721                         return MODE_H_ILLEGAL;
7722
7723                 if (mode->vtotal - mode->vdisplay < 3)
7724                         return MODE_V_ILLEGAL;
7725         }
7726
7727         /*
7728          * Cantiga+ cannot handle modes with a hsync front porch of 0.
7729          * WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
7730          */
7731         if ((DISPLAY_VER(dev_priv) > 4 || IS_G4X(dev_priv)) &&
7732             mode->hsync_start == mode->hdisplay)
7733                 return MODE_H_ILLEGAL;
7734
7735         return MODE_OK;
7736 }
7737
7738 enum drm_mode_status
7739 intel_mode_valid_max_plane_size(struct drm_i915_private *dev_priv,
7740                                 const struct drm_display_mode *mode,
7741                                 bool bigjoiner)
7742 {
7743         int plane_width_max, plane_height_max;
7744
7745         /*
7746          * intel_mode_valid() should be
7747          * sufficient on older platforms.
7748          */
7749         if (DISPLAY_VER(dev_priv) < 9)
7750                 return MODE_OK;
7751
7752         /*
7753          * Most people will probably want a fullscreen
7754          * plane so let's not advertize modes that are
7755          * too big for that.
7756          */
7757         if (DISPLAY_VER(dev_priv) >= 11) {
7758                 plane_width_max = 5120 << bigjoiner;
7759                 plane_height_max = 4320;
7760         } else {
7761                 plane_width_max = 5120;
7762                 plane_height_max = 4096;
7763         }
7764
7765         if (mode->hdisplay > plane_width_max)
7766                 return MODE_H_ILLEGAL;
7767
7768         if (mode->vdisplay > plane_height_max)
7769                 return MODE_V_ILLEGAL;
7770
7771         return MODE_OK;
7772 }
7773
7774 static const struct intel_display_funcs skl_display_funcs = {
7775         .get_pipe_config = hsw_get_pipe_config,
7776         .crtc_enable = hsw_crtc_enable,
7777         .crtc_disable = hsw_crtc_disable,
7778         .commit_modeset_enables = skl_commit_modeset_enables,
7779         .get_initial_plane_config = skl_get_initial_plane_config,
7780 };
7781
7782 static const struct intel_display_funcs ddi_display_funcs = {
7783         .get_pipe_config = hsw_get_pipe_config,
7784         .crtc_enable = hsw_crtc_enable,
7785         .crtc_disable = hsw_crtc_disable,
7786         .commit_modeset_enables = intel_commit_modeset_enables,
7787         .get_initial_plane_config = i9xx_get_initial_plane_config,
7788 };
7789
7790 static const struct intel_display_funcs pch_split_display_funcs = {
7791         .get_pipe_config = ilk_get_pipe_config,
7792         .crtc_enable = ilk_crtc_enable,
7793         .crtc_disable = ilk_crtc_disable,
7794         .commit_modeset_enables = intel_commit_modeset_enables,
7795         .get_initial_plane_config = i9xx_get_initial_plane_config,
7796 };
7797
7798 static const struct intel_display_funcs vlv_display_funcs = {
7799         .get_pipe_config = i9xx_get_pipe_config,
7800         .crtc_enable = valleyview_crtc_enable,
7801         .crtc_disable = i9xx_crtc_disable,
7802         .commit_modeset_enables = intel_commit_modeset_enables,
7803         .get_initial_plane_config = i9xx_get_initial_plane_config,
7804 };
7805
7806 static const struct intel_display_funcs i9xx_display_funcs = {
7807         .get_pipe_config = i9xx_get_pipe_config,
7808         .crtc_enable = i9xx_crtc_enable,
7809         .crtc_disable = i9xx_crtc_disable,
7810         .commit_modeset_enables = intel_commit_modeset_enables,
7811         .get_initial_plane_config = i9xx_get_initial_plane_config,
7812 };
7813
7814 /**
7815  * intel_init_display_hooks - initialize the display modesetting hooks
7816  * @dev_priv: device private
7817  */
7818 void intel_init_display_hooks(struct drm_i915_private *dev_priv)
7819 {
7820         if (DISPLAY_VER(dev_priv) >= 9) {
7821                 dev_priv->display.funcs.display = &skl_display_funcs;
7822         } else if (HAS_DDI(dev_priv)) {
7823                 dev_priv->display.funcs.display = &ddi_display_funcs;
7824         } else if (HAS_PCH_SPLIT(dev_priv)) {
7825                 dev_priv->display.funcs.display = &pch_split_display_funcs;
7826         } else if (IS_CHERRYVIEW(dev_priv) ||
7827                    IS_VALLEYVIEW(dev_priv)) {
7828                 dev_priv->display.funcs.display = &vlv_display_funcs;
7829         } else {
7830                 dev_priv->display.funcs.display = &i9xx_display_funcs;
7831         }
7832 }
7833
7834 int intel_initial_commit(struct drm_device *dev)
7835 {
7836         struct drm_atomic_state *state = NULL;
7837         struct drm_modeset_acquire_ctx ctx;
7838         struct intel_crtc *crtc;
7839         int ret = 0;
7840
7841         state = drm_atomic_state_alloc(dev);
7842         if (!state)
7843                 return -ENOMEM;
7844
7845         drm_modeset_acquire_init(&ctx, 0);
7846
7847         state->acquire_ctx = &ctx;
7848         to_intel_atomic_state(state)->internal = true;
7849
7850 retry:
7851         for_each_intel_crtc(dev, crtc) {
7852                 struct intel_crtc_state *crtc_state =
7853                         intel_atomic_get_crtc_state(state, crtc);
7854
7855                 if (IS_ERR(crtc_state)) {
7856                         ret = PTR_ERR(crtc_state);
7857                         goto out;
7858                 }
7859
7860                 if (crtc_state->hw.active) {
7861                         struct intel_encoder *encoder;
7862
7863                         ret = drm_atomic_add_affected_planes(state, &crtc->base);
7864                         if (ret)
7865                                 goto out;
7866
7867                         /*
7868                          * FIXME hack to force a LUT update to avoid the
7869                          * plane update forcing the pipe gamma on without
7870                          * having a proper LUT loaded. Remove once we
7871                          * have readout for pipe gamma enable.
7872                          */
7873                         crtc_state->uapi.color_mgmt_changed = true;
7874
7875                         for_each_intel_encoder_mask(dev, encoder,
7876                                                     crtc_state->uapi.encoder_mask) {
7877                                 if (encoder->initial_fastset_check &&
7878                                     !encoder->initial_fastset_check(encoder, crtc_state)) {
7879                                         ret = drm_atomic_add_affected_connectors(state,
7880                                                                                  &crtc->base);
7881                                         if (ret)
7882                                                 goto out;
7883                                 }
7884                         }
7885                 }
7886         }
7887
7888         ret = drm_atomic_commit(state);
7889
7890 out:
7891         if (ret == -EDEADLK) {
7892                 drm_atomic_state_clear(state);
7893                 drm_modeset_backoff(&ctx);
7894                 goto retry;
7895         }
7896
7897         drm_atomic_state_put(state);
7898
7899         drm_modeset_drop_locks(&ctx);
7900         drm_modeset_acquire_fini(&ctx);
7901
7902         return ret;
7903 }
7904
7905 void i830_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
7906 {
7907         struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, pipe);
7908         enum transcoder cpu_transcoder = (enum transcoder)pipe;
7909         /* 640x480@60Hz, ~25175 kHz */
7910         struct dpll clock = {
7911                 .m1 = 18,
7912                 .m2 = 7,
7913                 .p1 = 13,
7914                 .p2 = 4,
7915                 .n = 2,
7916         };
7917         u32 dpll, fp;
7918         int i;
7919
7920         drm_WARN_ON(&dev_priv->drm,
7921                     i9xx_calc_dpll_params(48000, &clock) != 25154);
7922
7923         drm_dbg_kms(&dev_priv->drm,
7924                     "enabling pipe %c due to force quirk (vco=%d dot=%d)\n",
7925                     pipe_name(pipe), clock.vco, clock.dot);
7926
7927         fp = i9xx_dpll_compute_fp(&clock);
7928         dpll = DPLL_DVO_2X_MODE |
7929                 DPLL_VGA_MODE_DIS |
7930                 ((clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT) |
7931                 PLL_P2_DIVIDE_BY_4 |
7932                 PLL_REF_INPUT_DREFCLK |
7933                 DPLL_VCO_ENABLE;
7934
7935         intel_de_write(dev_priv, TRANS_HTOTAL(cpu_transcoder),
7936                        HACTIVE(640 - 1) | HTOTAL(800 - 1));
7937         intel_de_write(dev_priv, TRANS_HBLANK(cpu_transcoder),
7938                        HBLANK_START(640 - 1) | HBLANK_END(800 - 1));
7939         intel_de_write(dev_priv, TRANS_HSYNC(cpu_transcoder),
7940                        HSYNC_START(656 - 1) | HSYNC_END(752 - 1));
7941         intel_de_write(dev_priv, TRANS_VTOTAL(cpu_transcoder),
7942                        VACTIVE(480 - 1) | VTOTAL(525 - 1));
7943         intel_de_write(dev_priv, TRANS_VBLANK(cpu_transcoder),
7944                        VBLANK_START(480 - 1) | VBLANK_END(525 - 1));
7945         intel_de_write(dev_priv, TRANS_VSYNC(cpu_transcoder),
7946                        VSYNC_START(490 - 1) | VSYNC_END(492 - 1));
7947         intel_de_write(dev_priv, PIPESRC(pipe),
7948                        PIPESRC_WIDTH(640 - 1) | PIPESRC_HEIGHT(480 - 1));
7949
7950         intel_de_write(dev_priv, FP0(pipe), fp);
7951         intel_de_write(dev_priv, FP1(pipe), fp);
7952
7953         /*
7954          * Apparently we need to have VGA mode enabled prior to changing
7955          * the P1/P2 dividers. Otherwise the DPLL will keep using the old
7956          * dividers, even though the register value does change.
7957          */
7958         intel_de_write(dev_priv, DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS);
7959         intel_de_write(dev_priv, DPLL(pipe), dpll);
7960
7961         /* Wait for the clocks to stabilize. */
7962         intel_de_posting_read(dev_priv, DPLL(pipe));
7963         udelay(150);
7964
7965         /* The pixel multiplier can only be updated once the
7966          * DPLL is enabled and the clocks are stable.
7967          *
7968          * So write it again.
7969          */
7970         intel_de_write(dev_priv, DPLL(pipe), dpll);
7971
7972         /* We do this three times for luck */
7973         for (i = 0; i < 3 ; i++) {
7974                 intel_de_write(dev_priv, DPLL(pipe), dpll);
7975                 intel_de_posting_read(dev_priv, DPLL(pipe));
7976                 udelay(150); /* wait for warmup */
7977         }
7978
7979         intel_de_write(dev_priv, TRANSCONF(pipe), TRANSCONF_ENABLE);
7980         intel_de_posting_read(dev_priv, TRANSCONF(pipe));
7981
7982         intel_wait_for_pipe_scanline_moving(crtc);
7983 }
7984
7985 void i830_disable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
7986 {
7987         struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, pipe);
7988
7989         drm_dbg_kms(&dev_priv->drm, "disabling pipe %c due to force quirk\n",
7990                     pipe_name(pipe));
7991
7992         drm_WARN_ON(&dev_priv->drm,
7993                     intel_de_read(dev_priv, DSPCNTR(PLANE_A)) & DISP_ENABLE);
7994         drm_WARN_ON(&dev_priv->drm,
7995                     intel_de_read(dev_priv, DSPCNTR(PLANE_B)) & DISP_ENABLE);
7996         drm_WARN_ON(&dev_priv->drm,
7997                     intel_de_read(dev_priv, DSPCNTR(PLANE_C)) & DISP_ENABLE);
7998         drm_WARN_ON(&dev_priv->drm,
7999                     intel_de_read(dev_priv, CURCNTR(PIPE_A)) & MCURSOR_MODE_MASK);
8000         drm_WARN_ON(&dev_priv->drm,
8001                     intel_de_read(dev_priv, CURCNTR(PIPE_B)) & MCURSOR_MODE_MASK);
8002
8003         intel_de_write(dev_priv, TRANSCONF(pipe), 0);
8004         intel_de_posting_read(dev_priv, TRANSCONF(pipe));
8005
8006         intel_wait_for_pipe_scanline_stopped(crtc);
8007
8008         intel_de_write(dev_priv, DPLL(pipe), DPLL_VGA_MODE_DIS);
8009         intel_de_posting_read(dev_priv, DPLL(pipe));
8010 }
8011
8012 void intel_hpd_poll_fini(struct drm_i915_private *i915)
8013 {
8014         struct intel_connector *connector;
8015         struct drm_connector_list_iter conn_iter;
8016
8017         /* Kill all the work that may have been queued by hpd. */
8018         drm_connector_list_iter_begin(&i915->drm, &conn_iter);
8019         for_each_intel_connector_iter(connector, &conn_iter) {
8020                 if (connector->modeset_retry_work.func)
8021                         cancel_work_sync(&connector->modeset_retry_work);
8022                 if (connector->hdcp.shim) {
8023                         cancel_delayed_work_sync(&connector->hdcp.check_work);
8024                         cancel_work_sync(&connector->hdcp.prop_work);
8025                 }
8026         }
8027         drm_connector_list_iter_end(&conn_iter);
8028 }
8029
8030 bool intel_scanout_needs_vtd_wa(struct drm_i915_private *i915)
8031 {
8032         return DISPLAY_VER(i915) >= 6 && i915_vtd_active(i915);
8033 }