drivers/gpu/drm/i915/display/intel_ddi_buf_trans.c

   1 // SPDX-License-Identifier: MIT
   2 /*
   3  * Copyright © 2020 Intel Corporation
   4  */
   5
   6 #include "i915_drv.h"
   7 #include "intel_ddi.h"
   8 #include "intel_ddi_buf_trans.h"
   9 #include "intel_de.h"
  10 #include "intel_display_types.h"
  11 #include "intel_dp.h"
  12 #include "intel_cx0_phy.h"
  13
  14 /* HDMI/DVI modes ignore everything but the last 2 items. So we share
  15  * them for both DP and FDI transports, allowing those ports to
  16  * automatically adapt to HDMI connections as well
  17  */
  18 static const union intel_ddi_buf_trans_entry _hsw_trans_dp[] = {
  19         { .hsw = { 0x00FFFFFF, 0x0006000E, 0x0 } },
  20         { .hsw = { 0x00D75FFF, 0x0005000A, 0x0 } },
  21         { .hsw = { 0x00C30FFF, 0x00040006, 0x0 } },
  22         { .hsw = { 0x80AAAFFF, 0x000B0000, 0x0 } },
  23         { .hsw = { 0x00FFFFFF, 0x0005000A, 0x0 } },
  24         { .hsw = { 0x00D75FFF, 0x000C0004, 0x0 } },
  25         { .hsw = { 0x80C30FFF, 0x000B0000, 0x0 } },
  26         { .hsw = { 0x00FFFFFF, 0x00040006, 0x0 } },
  27         { .hsw = { 0x80D75FFF, 0x000B0000, 0x0 } },
  28 };
  29
  30 static const struct intel_ddi_buf_trans hsw_trans_dp = {
  31         .entries = _hsw_trans_dp,
  32         .num_entries = ARRAY_SIZE(_hsw_trans_dp),
  33 };
  34
  35 static const union intel_ddi_buf_trans_entry _hsw_trans_fdi[] = {
  36         { .hsw = { 0x00FFFFFF, 0x0007000E, 0x0 } },
  37         { .hsw = { 0x00D75FFF, 0x000F000A, 0x0 } },
  38         { .hsw = { 0x00C30FFF, 0x00060006, 0x0 } },
  39         { .hsw = { 0x00AAAFFF, 0x001E0000, 0x0 } },
  40         { .hsw = { 0x00FFFFFF, 0x000F000A, 0x0 } },
  41         { .hsw = { 0x00D75FFF, 0x00160004, 0x0 } },
  42         { .hsw = { 0x00C30FFF, 0x001E0000, 0x0 } },
  43         { .hsw = { 0x00FFFFFF, 0x00060006, 0x0 } },
  44         { .hsw = { 0x00D75FFF, 0x001E0000, 0x0 } },
  45 };
  46
  47 static const struct intel_ddi_buf_trans hsw_trans_fdi = {
  48         .entries = _hsw_trans_fdi,
  49         .num_entries = ARRAY_SIZE(_hsw_trans_fdi),
  50 };
  51
  52 static const union intel_ddi_buf_trans_entry _hsw_trans_hdmi[] = {
  53                                                         /* Idx  NT mV d T mV d  db      */
  54         { .hsw = { 0x00FFFFFF, 0x0006000E, 0x0 } },     /* 0:   400     400     0       */
  55         { .hsw = { 0x00E79FFF, 0x000E000C, 0x0 } },     /* 1:   400     500     2       */
  56         { .hsw = { 0x00D75FFF, 0x0005000A, 0x0 } },     /* 2:   400     600     3.5     */
  57         { .hsw = { 0x00FFFFFF, 0x0005000A, 0x0 } },     /* 3:   600     600     0       */
  58         { .hsw = { 0x00E79FFF, 0x001D0007, 0x0 } },     /* 4:   600     750     2       */
  59         { .hsw = { 0x00D75FFF, 0x000C0004, 0x0 } },     /* 5:   600     900     3.5     */
  60         { .hsw = { 0x00FFFFFF, 0x00040006, 0x0 } },     /* 6:   800     800     0       */
  61         { .hsw = { 0x80E79FFF, 0x00030002, 0x0 } },     /* 7:   800     1000    2       */
  62         { .hsw = { 0x00FFFFFF, 0x00140005, 0x0 } },     /* 8:   850     850     0       */
  63         { .hsw = { 0x00FFFFFF, 0x000C0004, 0x0 } },     /* 9:   900     900     0       */
  64         { .hsw = { 0x00FFFFFF, 0x001C0003, 0x0 } },     /* 10:  950     950     0       */
  65         { .hsw = { 0x80FFFFFF, 0x00030002, 0x0 } },     /* 11:  1000    1000    0       */
  66 };
  67
  68 static const struct intel_ddi_buf_trans hsw_trans_hdmi = {
  69         .entries = _hsw_trans_hdmi,
  70         .num_entries = ARRAY_SIZE(_hsw_trans_hdmi),
  71         .hdmi_default_entry = 6,
  72 };
  73
  74 static const union intel_ddi_buf_trans_entry _bdw_trans_edp[] = {
  75         { .hsw = { 0x00FFFFFF, 0x00000012, 0x0 } },
  76         { .hsw = { 0x00EBAFFF, 0x00020011, 0x0 } },
  77         { .hsw = { 0x00C71FFF, 0x0006000F, 0x0 } },
  78         { .hsw = { 0x00AAAFFF, 0x000E000A, 0x0 } },
  79         { .hsw = { 0x00FFFFFF, 0x00020011, 0x0 } },
  80         { .hsw = { 0x00DB6FFF, 0x0005000F, 0x0 } },
  81         { .hsw = { 0x00BEEFFF, 0x000A000C, 0x0 } },
  82         { .hsw = { 0x00FFFFFF, 0x0005000F, 0x0 } },
  83         { .hsw = { 0x00DB6FFF, 0x000A000C, 0x0 } },
  84 };
  85
  86 static const struct intel_ddi_buf_trans bdw_trans_edp = {
  87         .entries = _bdw_trans_edp,
  88         .num_entries = ARRAY_SIZE(_bdw_trans_edp),
  89 };
  90
  91 static const union intel_ddi_buf_trans_entry _bdw_trans_dp[] = {
  92         { .hsw = { 0x00FFFFFF, 0x0007000E, 0x0 } },
  93         { .hsw = { 0x00D75FFF, 0x000E000A, 0x0 } },
  94         { .hsw = { 0x00BEFFFF, 0x00140006, 0x0 } },
  95         { .hsw = { 0x80B2CFFF, 0x001B0002, 0x0 } },
  96         { .hsw = { 0x00FFFFFF, 0x000E000A, 0x0 } },
  97         { .hsw = { 0x00DB6FFF, 0x00160005, 0x0 } },
  98         { .hsw = { 0x80C71FFF, 0x001A0002, 0x0 } },
  99         { .hsw = { 0x00F7DFFF, 0x00180004, 0x0 } },
 100         { .hsw = { 0x80D75FFF, 0x001B0002, 0x0 } },
 101 };
 102
 103 static const struct intel_ddi_buf_trans bdw_trans_dp = {
 104         .entries = _bdw_trans_dp,
 105         .num_entries = ARRAY_SIZE(_bdw_trans_dp),
 106 };
 107
 108 static const union intel_ddi_buf_trans_entry _bdw_trans_fdi[] = {
 109         { .hsw = { 0x00FFFFFF, 0x0001000E, 0x0 } },
 110         { .hsw = { 0x00D75FFF, 0x0004000A, 0x0 } },
 111         { .hsw = { 0x00C30FFF, 0x00070006, 0x0 } },
 112         { .hsw = { 0x00AAAFFF, 0x000C0000, 0x0 } },
 113         { .hsw = { 0x00FFFFFF, 0x0004000A, 0x0 } },
 114         { .hsw = { 0x00D75FFF, 0x00090004, 0x0 } },
 115         { .hsw = { 0x00C30FFF, 0x000C0000, 0x0 } },
 116         { .hsw = { 0x00FFFFFF, 0x00070006, 0x0 } },
 117         { .hsw = { 0x00D75FFF, 0x000C0000, 0x0 } },
 118 };
 119
 120 static const struct intel_ddi_buf_trans bdw_trans_fdi = {
 121         .entries = _bdw_trans_fdi,
 122         .num_entries = ARRAY_SIZE(_bdw_trans_fdi),
 123 };
 124
 125 static const union intel_ddi_buf_trans_entry _bdw_trans_hdmi[] = {
 126                                                         /* Idx  NT mV d T mV df db      */
 127         { .hsw = { 0x00FFFFFF, 0x0007000E, 0x0 } },     /* 0:   400     400     0       */
 128         { .hsw = { 0x00D75FFF, 0x000E000A, 0x0 } },     /* 1:   400     600     3.5     */
 129         { .hsw = { 0x00BEFFFF, 0x00140006, 0x0 } },     /* 2:   400     800     6       */
 130         { .hsw = { 0x00FFFFFF, 0x0009000D, 0x0 } },     /* 3:   450     450     0       */
 131         { .hsw = { 0x00FFFFFF, 0x000E000A, 0x0 } },     /* 4:   600     600     0       */
 132         { .hsw = { 0x00D7FFFF, 0x00140006, 0x0 } },     /* 5:   600     800     2.5     */
 133         { .hsw = { 0x80CB2FFF, 0x001B0002, 0x0 } },     /* 6:   600     1000    4.5     */
 134         { .hsw = { 0x00FFFFFF, 0x00140006, 0x0 } },     /* 7:   800     800     0       */
 135         { .hsw = { 0x80E79FFF, 0x001B0002, 0x0 } },     /* 8:   800     1000    2       */
 136         { .hsw = { 0x80FFFFFF, 0x001B0002, 0x0 } },     /* 9:   1000    1000    0       */
 137 };
 138
 139 static const struct intel_ddi_buf_trans bdw_trans_hdmi = {
 140         .entries = _bdw_trans_hdmi,
 141         .num_entries = ARRAY_SIZE(_bdw_trans_hdmi),
 142         .hdmi_default_entry = 7,
 143 };
 144
 145 /* Skylake H and S */
 146 static const union intel_ddi_buf_trans_entry _skl_trans_dp[] = {
 147         { .hsw = { 0x00002016, 0x000000A0, 0x0 } },
 148         { .hsw = { 0x00005012, 0x0000009B, 0x0 } },
 149         { .hsw = { 0x00007011, 0x00000088, 0x0 } },
 150         { .hsw = { 0x80009010, 0x000000C0, 0x1 } },
 151         { .hsw = { 0x00002016, 0x0000009B, 0x0 } },
 152         { .hsw = { 0x00005012, 0x00000088, 0x0 } },
 153         { .hsw = { 0x80007011, 0x000000C0, 0x1 } },
 154         { .hsw = { 0x00002016, 0x000000DF, 0x0 } },
 155         { .hsw = { 0x80005012, 0x000000C0, 0x1 } },
 156 };
 157
 158 static const struct intel_ddi_buf_trans skl_trans_dp = {
 159         .entries = _skl_trans_dp,
 160         .num_entries = ARRAY_SIZE(_skl_trans_dp),
 161 };
 162
 163 /* Skylake U */
 164 static const union intel_ddi_buf_trans_entry _skl_u_trans_dp[] = {
 165         { .hsw = { 0x0000201B, 0x000000A2, 0x0 } },
 166         { .hsw = { 0x00005012, 0x00000088, 0x0 } },
 167         { .hsw = { 0x80007011, 0x000000CD, 0x1 } },
 168         { .hsw = { 0x80009010, 0x000000C0, 0x1 } },
 169         { .hsw = { 0x0000201B, 0x0000009D, 0x0 } },
 170         { .hsw = { 0x80005012, 0x000000C0, 0x1 } },
 171         { .hsw = { 0x80007011, 0x000000C0, 0x1 } },
 172         { .hsw = { 0x00002016, 0x00000088, 0x0 } },
 173         { .hsw = { 0x80005012, 0x000000C0, 0x1 } },
 174 };
 175
 176 static const struct intel_ddi_buf_trans skl_u_trans_dp = {
 177         .entries = _skl_u_trans_dp,
 178         .num_entries = ARRAY_SIZE(_skl_u_trans_dp),
 179 };
 180
 181 /* Skylake Y */
 182 static const union intel_ddi_buf_trans_entry _skl_y_trans_dp[] = {
 183         { .hsw = { 0x00000018, 0x000000A2, 0x0 } },
 184         { .hsw = { 0x00005012, 0x00000088, 0x0 } },
 185         { .hsw = { 0x80007011, 0x000000CD, 0x3 } },
 186         { .hsw = { 0x80009010, 0x000000C0, 0x3 } },
 187         { .hsw = { 0x00000018, 0x0000009D, 0x0 } },
 188         { .hsw = { 0x80005012, 0x000000C0, 0x3 } },
 189         { .hsw = { 0x80007011, 0x000000C0, 0x3 } },
 190         { .hsw = { 0x00000018, 0x00000088, 0x0 } },
 191         { .hsw = { 0x80005012, 0x000000C0, 0x3 } },
 192 };
 193
 194 static const struct intel_ddi_buf_trans skl_y_trans_dp = {
 195         .entries = _skl_y_trans_dp,
 196         .num_entries = ARRAY_SIZE(_skl_y_trans_dp),
 197 };
 198
 199 /* Kabylake H and S */
 200 static const union intel_ddi_buf_trans_entry _kbl_trans_dp[] = {
 201         { .hsw = { 0x00002016, 0x000000A0, 0x0 } },
 202         { .hsw = { 0x00005012, 0x0000009B, 0x0 } },
 203         { .hsw = { 0x00007011, 0x00000088, 0x0 } },
 204         { .hsw = { 0x80009010, 0x000000C0, 0x1 } },
 205         { .hsw = { 0x00002016, 0x0000009B, 0x0 } },
 206         { .hsw = { 0x00005012, 0x00000088, 0x0 } },
 207         { .hsw = { 0x80007011, 0x000000C0, 0x1 } },
 208         { .hsw = { 0x00002016, 0x00000097, 0x0 } },
 209         { .hsw = { 0x80005012, 0x000000C0, 0x1 } },
 210 };
 211
 212 static const struct intel_ddi_buf_trans kbl_trans_dp = {
 213         .entries = _kbl_trans_dp,
 214         .num_entries = ARRAY_SIZE(_kbl_trans_dp),
 215 };
 216
 217 /* Kabylake U */
 218 static const union intel_ddi_buf_trans_entry _kbl_u_trans_dp[] = {
 219         { .hsw = { 0x0000201B, 0x000000A1, 0x0 } },
 220         { .hsw = { 0x00005012, 0x00000088, 0x0 } },
 221         { .hsw = { 0x80007011, 0x000000CD, 0x3 } },
 222         { .hsw = { 0x80009010, 0x000000C0, 0x3 } },
 223         { .hsw = { 0x0000201B, 0x0000009D, 0x0 } },
 224         { .hsw = { 0x80005012, 0x000000C0, 0x3 } },
 225         { .hsw = { 0x80007011, 0x000000C0, 0x3 } },
 226         { .hsw = { 0x00002016, 0x0000004F, 0x0 } },
 227         { .hsw = { 0x80005012, 0x000000C0, 0x3 } },
 228 };
 229
 230 static const struct intel_ddi_buf_trans kbl_u_trans_dp = {
 231         .entries = _kbl_u_trans_dp,
 232         .num_entries = ARRAY_SIZE(_kbl_u_trans_dp),
 233 };
 234
 235 /* Kabylake Y */
 236 static const union intel_ddi_buf_trans_entry _kbl_y_trans_dp[] = {
 237         { .hsw = { 0x00001017, 0x000000A1, 0x0 } },
 238         { .hsw = { 0x00005012, 0x00000088, 0x0 } },
 239         { .hsw = { 0x80007011, 0x000000CD, 0x3 } },
 240         { .hsw = { 0x8000800F, 0x000000C0, 0x3 } },
 241         { .hsw = { 0x00001017, 0x0000009D, 0x0 } },
 242         { .hsw = { 0x80005012, 0x000000C0, 0x3 } },
 243         { .hsw = { 0x80007011, 0x000000C0, 0x3 } },
 244         { .hsw = { 0x00001017, 0x0000004C, 0x0 } },
 245         { .hsw = { 0x80005012, 0x000000C0, 0x3 } },
 246 };
 247
 248 static const struct intel_ddi_buf_trans kbl_y_trans_dp = {
 249         .entries = _kbl_y_trans_dp,
 250         .num_entries = ARRAY_SIZE(_kbl_y_trans_dp),
 251 };
 252
 253 /*
 254  * Skylake/Kabylake H and S
 255  * eDP 1.4 low vswing translation parameters
 256  */
 257 static const union intel_ddi_buf_trans_entry _skl_trans_edp[] = {
 258         { .hsw = { 0x00000018, 0x000000A8, 0x0 } },
 259         { .hsw = { 0x00004013, 0x000000A9, 0x0 } },
 260         { .hsw = { 0x00007011, 0x000000A2, 0x0 } },
 261         { .hsw = { 0x00009010, 0x0000009C, 0x0 } },
 262         { .hsw = { 0x00000018, 0x000000A9, 0x0 } },
 263         { .hsw = { 0x00006013, 0x000000A2, 0x0 } },
 264         { .hsw = { 0x00007011, 0x000000A6, 0x0 } },
 265         { .hsw = { 0x00000018, 0x000000AB, 0x0 } },
 266         { .hsw = { 0x00007013, 0x0000009F, 0x0 } },
 267         { .hsw = { 0x00000018, 0x000000DF, 0x0 } },
 268 };
 269
 270 static const struct intel_ddi_buf_trans skl_trans_edp = {
 271         .entries = _skl_trans_edp,
 272         .num_entries = ARRAY_SIZE(_skl_trans_edp),
 273 };
 274
 275 /*
 276  * Skylake/Kabylake U
 277  * eDP 1.4 low vswing translation parameters
 278  */
 279 static const union intel_ddi_buf_trans_entry _skl_u_trans_edp[] = {
 280         { .hsw = { 0x00000018, 0x000000A8, 0x0 } },
 281         { .hsw = { 0x00004013, 0x000000A9, 0x0 } },
 282         { .hsw = { 0x00007011, 0x000000A2, 0x0 } },
 283         { .hsw = { 0x00009010, 0x0000009C, 0x0 } },
 284         { .hsw = { 0x00000018, 0x000000A9, 0x0 } },
 285         { .hsw = { 0x00006013, 0x000000A2, 0x0 } },
 286         { .hsw = { 0x00007011, 0x000000A6, 0x0 } },
 287         { .hsw = { 0x00002016, 0x000000AB, 0x0 } },
 288         { .hsw = { 0x00005013, 0x0000009F, 0x0 } },
 289         { .hsw = { 0x00000018, 0x000000DF, 0x0 } },
 290 };
 291
 292 static const struct intel_ddi_buf_trans skl_u_trans_edp = {
 293         .entries = _skl_u_trans_edp,
 294         .num_entries = ARRAY_SIZE(_skl_u_trans_edp),
 295 };
 296
 297 /*
 298  * Skylake/Kabylake Y
 299  * eDP 1.4 low vswing translation parameters
 300  */
 301 static const union intel_ddi_buf_trans_entry _skl_y_trans_edp[] = {
 302         { .hsw = { 0x00000018, 0x000000A8, 0x0 } },
 303         { .hsw = { 0x00004013, 0x000000AB, 0x0 } },
 304         { .hsw = { 0x00007011, 0x000000A4, 0x0 } },
 305         { .hsw = { 0x00009010, 0x000000DF, 0x0 } },
 306         { .hsw = { 0x00000018, 0x000000AA, 0x0 } },
 307         { .hsw = { 0x00006013, 0x000000A4, 0x0 } },
 308         { .hsw = { 0x00007011, 0x0000009D, 0x0 } },
 309         { .hsw = { 0x00000018, 0x000000A0, 0x0 } },
 310         { .hsw = { 0x00006012, 0x000000DF, 0x0 } },
 311         { .hsw = { 0x00000018, 0x0000008A, 0x0 } },
 312 };
 313
 314 static const struct intel_ddi_buf_trans skl_y_trans_edp = {
 315         .entries = _skl_y_trans_edp,
 316         .num_entries = ARRAY_SIZE(_skl_y_trans_edp),
 317 };
 318
 319 /* Skylake/Kabylake U, H and S */
 320 static const union intel_ddi_buf_trans_entry _skl_trans_hdmi[] = {
 321         { .hsw = { 0x00000018, 0x000000AC, 0x0 } },
 322         { .hsw = { 0x00005012, 0x0000009D, 0x0 } },
 323         { .hsw = { 0x00007011, 0x00000088, 0x0 } },
 324         { .hsw = { 0x00000018, 0x000000A1, 0x0 } },
 325         { .hsw = { 0x00000018, 0x00000098, 0x0 } },
 326         { .hsw = { 0x00004013, 0x00000088, 0x0 } },
 327         { .hsw = { 0x80006012, 0x000000CD, 0x1 } },
 328         { .hsw = { 0x00000018, 0x000000DF, 0x0 } },
 329         { .hsw = { 0x80003015, 0x000000CD, 0x1 } },     /* Default */
 330         { .hsw = { 0x80003015, 0x000000C0, 0x1 } },
 331         { .hsw = { 0x80000018, 0x000000C0, 0x1 } },
 332 };
 333
 334 static const struct intel_ddi_buf_trans skl_trans_hdmi = {
 335         .entries = _skl_trans_hdmi,
 336         .num_entries = ARRAY_SIZE(_skl_trans_hdmi),
 337         .hdmi_default_entry = 8,
 338 };
 339
 340 /* Skylake/Kabylake Y */
 341 static const union intel_ddi_buf_trans_entry _skl_y_trans_hdmi[] = {
 342         { .hsw = { 0x00000018, 0x000000A1, 0x0 } },
 343         { .hsw = { 0x00005012, 0x000000DF, 0x0 } },
 344         { .hsw = { 0x80007011, 0x000000CB, 0x3 } },
 345         { .hsw = { 0x00000018, 0x000000A4, 0x0 } },
 346         { .hsw = { 0x00000018, 0x0000009D, 0x0 } },
 347         { .hsw = { 0x00004013, 0x00000080, 0x0 } },
 348         { .hsw = { 0x80006013, 0x000000C0, 0x3 } },
 349         { .hsw = { 0x00000018, 0x0000008A, 0x0 } },
 350         { .hsw = { 0x80003015, 0x000000C0, 0x3 } },     /* Default */
 351         { .hsw = { 0x80003015, 0x000000C0, 0x3 } },
 352         { .hsw = { 0x80000018, 0x000000C0, 0x3 } },
 353 };
 354
 355 static const struct intel_ddi_buf_trans skl_y_trans_hdmi = {
 356         .entries = _skl_y_trans_hdmi,
 357         .num_entries = ARRAY_SIZE(_skl_y_trans_hdmi),
 358         .hdmi_default_entry = 8,
 359 };
 360
 361 static const union intel_ddi_buf_trans_entry _bxt_trans_dp[] = {
 362                                                 /* Idx  NT mV diff      db  */
 363         { .bxt = { 52,  0x9A, 0, 128, } },      /* 0:   400             0   */
 364         { .bxt = { 78,  0x9A, 0, 85,  } },      /* 1:   400             3.5 */
 365         { .bxt = { 104, 0x9A, 0, 64,  } },      /* 2:   400             6   */
 366         { .bxt = { 154, 0x9A, 0, 43,  } },      /* 3:   400             9.5 */
 367         { .bxt = { 77,  0x9A, 0, 128, } },      /* 4:   600             0   */
 368         { .bxt = { 116, 0x9A, 0, 85,  } },      /* 5:   600             3.5 */
 369         { .bxt = { 154, 0x9A, 0, 64,  } },      /* 6:   600             6   */
 370         { .bxt = { 102, 0x9A, 0, 128, } },      /* 7:   800             0   */
 371         { .bxt = { 154, 0x9A, 0, 85,  } },      /* 8:   800             3.5 */
 372         { .bxt = { 154, 0x9A, 1, 128, } },      /* 9:   1200            0   */
 373 };
 374
 375 static const struct intel_ddi_buf_trans bxt_trans_dp = {
 376         .entries = _bxt_trans_dp,
 377         .num_entries = ARRAY_SIZE(_bxt_trans_dp),
 378 };
 379
 380 static const union intel_ddi_buf_trans_entry _bxt_trans_edp[] = {
 381                                         /* Idx  NT mV diff      db  */
 382         { .bxt = { 26, 0, 0, 128, } },  /* 0:   200             0   */
 383         { .bxt = { 38, 0, 0, 112, } },  /* 1:   200             1.5 */
 384         { .bxt = { 48, 0, 0, 96,  } },  /* 2:   200             4   */
 385         { .bxt = { 54, 0, 0, 69,  } },  /* 3:   200             6   */
 386         { .bxt = { 32, 0, 0, 128, } },  /* 4:   250             0   */
 387         { .bxt = { 48, 0, 0, 104, } },  /* 5:   250             1.5 */
 388         { .bxt = { 54, 0, 0, 85,  } },  /* 6:   250             4   */
 389         { .bxt = { 43, 0, 0, 128, } },  /* 7:   300             0   */
 390         { .bxt = { 54, 0, 0, 101, } },  /* 8:   300             1.5 */
 391         { .bxt = { 48, 0, 0, 128, } },  /* 9:   300             0   */
 392 };
 393
 394 static const struct intel_ddi_buf_trans bxt_trans_edp = {
 395         .entries = _bxt_trans_edp,
 396         .num_entries = ARRAY_SIZE(_bxt_trans_edp),
 397 };
 398
 399 /* BSpec has 2 recommended values - entries 0 and 8.
 400  * Using the entry with higher vswing.
 401  */
 402 static const union intel_ddi_buf_trans_entry _bxt_trans_hdmi[] = {
 403                                                 /* Idx  NT mV diff      db  */
 404         { .bxt = { 52,  0x9A, 0, 128, } },      /* 0:   400             0   */
 405         { .bxt = { 52,  0x9A, 0, 85,  } },      /* 1:   400             3.5 */
 406         { .bxt = { 52,  0x9A, 0, 64,  } },      /* 2:   400             6   */
 407         { .bxt = { 42,  0x9A, 0, 43,  } },      /* 3:   400             9.5 */
 408         { .bxt = { 77,  0x9A, 0, 128, } },      /* 4:   600             0   */
 409         { .bxt = { 77,  0x9A, 0, 85,  } },      /* 5:   600             3.5 */
 410         { .bxt = { 77,  0x9A, 0, 64,  } },      /* 6:   600             6   */
 411         { .bxt = { 102, 0x9A, 0, 128, } },      /* 7:   800             0   */
 412         { .bxt = { 102, 0x9A, 0, 85,  } },      /* 8:   800             3.5 */
 413         { .bxt = { 154, 0x9A, 1, 128, } },      /* 9:   1200            0   */
 414 };
 415
 416 static const struct intel_ddi_buf_trans bxt_trans_hdmi = {
 417         .entries = _bxt_trans_hdmi,
 418         .num_entries = ARRAY_SIZE(_bxt_trans_hdmi),
 419         .hdmi_default_entry = ARRAY_SIZE(_bxt_trans_hdmi) - 1,
 420 };
 421
 422 /* icl_combo_phy_trans */
 423 static const union intel_ddi_buf_trans_entry _icl_combo_phy_trans_dp_hbr2_edp_hbr3[] = {
 424                                                         /* NT mV Trans mV db    */
 425         { .icl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } },     /* 350   350      0.0   */
 426         { .icl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } },     /* 350   500      3.1   */
 427         { .icl = { 0xC, 0x71, 0x2F, 0x00, 0x10 } },     /* 350   700      6.0   */
 428         { .icl = { 0x6, 0x7F, 0x2B, 0x00, 0x14 } },     /* 350   900      8.2   */
 429         { .icl = { 0xA, 0x4C, 0x3F, 0x00, 0x00 } },     /* 500   500      0.0   */
 430         { .icl = { 0xC, 0x73, 0x34, 0x00, 0x0B } },     /* 500   700      2.9   */
 431         { .icl = { 0x6, 0x7F, 0x2F, 0x00, 0x10 } },     /* 500   900      5.1   */
 432         { .icl = { 0xC, 0x6C, 0x3C, 0x00, 0x03 } },     /* 650   700      0.6   */
 433         { .icl = { 0x6, 0x7F, 0x35, 0x00, 0x0A } },     /* 600   900      3.5   */
 434         { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },     /* 900   900      0.0   */
 435 };
 436
 437 static const struct intel_ddi_buf_trans icl_combo_phy_trans_dp_hbr2_edp_hbr3 = {
 438         .entries = _icl_combo_phy_trans_dp_hbr2_edp_hbr3,
 439         .num_entries = ARRAY_SIZE(_icl_combo_phy_trans_dp_hbr2_edp_hbr3),
 440 };
 441
 442 static const union intel_ddi_buf_trans_entry _icl_combo_phy_trans_edp_hbr2[] = {
 443                                                         /* NT mV Trans mV db    */
 444         { .icl = { 0x0, 0x7F, 0x3F, 0x00, 0x00 } },     /* 200   200      0.0   */
 445         { .icl = { 0x8, 0x7F, 0x38, 0x00, 0x07 } },     /* 200   250      1.9   */
 446         { .icl = { 0x1, 0x7F, 0x33, 0x00, 0x0C } },     /* 200   300      3.5   */
 447         { .icl = { 0x9, 0x7F, 0x31, 0x00, 0x0E } },     /* 200   350      4.9   */
 448         { .icl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } },     /* 250   250      0.0   */
 449         { .icl = { 0x1, 0x7F, 0x38, 0x00, 0x07 } },     /* 250   300      1.6   */
 450         { .icl = { 0x9, 0x7F, 0x35, 0x00, 0x0A } },     /* 250   350      2.9   */
 451         { .icl = { 0x1, 0x7F, 0x3F, 0x00, 0x00 } },     /* 300   300      0.0   */
 452         { .icl = { 0x9, 0x7F, 0x38, 0x00, 0x07 } },     /* 300   350      1.3   */
 453         { .icl = { 0x9, 0x7F, 0x3F, 0x00, 0x00 } },     /* 350   350      0.0   */
 454 };
 455
 456 static const struct intel_ddi_buf_trans icl_combo_phy_trans_edp_hbr2 = {
 457         .entries = _icl_combo_phy_trans_edp_hbr2,
 458         .num_entries = ARRAY_SIZE(_icl_combo_phy_trans_edp_hbr2),
 459 };
 460
 461 static const union intel_ddi_buf_trans_entry _icl_combo_phy_trans_hdmi[] = {
 462                                                         /* NT mV Trans mV db    */
 463         { .icl = { 0xA, 0x60, 0x3F, 0x00, 0x00 } },     /* 450   450      0.0   */
 464         { .icl = { 0xB, 0x73, 0x36, 0x00, 0x09 } },     /* 450   650      3.2   */
 465         { .icl = { 0x6, 0x7F, 0x31, 0x00, 0x0E } },     /* 450   850      5.5   */
 466         { .icl = { 0xB, 0x73, 0x3F, 0x00, 0x00 } },     /* 650   650      0.0   ALS */
 467         { .icl = { 0x6, 0x7F, 0x37, 0x00, 0x08 } },     /* 650   850      2.3   */
 468         { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },     /* 850   850      0.0   */
 469         { .icl = { 0x6, 0x7F, 0x35, 0x00, 0x0A } },     /* 600   850      3.0   */
 470 };
 471
 472 static const struct intel_ddi_buf_trans icl_combo_phy_trans_hdmi = {
 473         .entries = _icl_combo_phy_trans_hdmi,
 474         .num_entries = ARRAY_SIZE(_icl_combo_phy_trans_hdmi),
 475         .hdmi_default_entry = ARRAY_SIZE(_icl_combo_phy_trans_hdmi) - 1,
 476 };
 477
 478 static const union intel_ddi_buf_trans_entry _ehl_combo_phy_trans_dp[] = {
 479                                                         /* NT mV Trans mV db    */
 480         { .icl = { 0xA, 0x33, 0x3F, 0x00, 0x00 } },     /* 350   350      0.0   */
 481         { .icl = { 0xA, 0x47, 0x38, 0x00, 0x07 } },     /* 350   500      3.1   */
 482         { .icl = { 0xC, 0x64, 0x33, 0x00, 0x0C } },     /* 350   700      6.0   */
 483         { .icl = { 0x6, 0x7F, 0x2F, 0x00, 0x10 } },     /* 350   900      8.2   */
 484         { .icl = { 0xA, 0x46, 0x3F, 0x00, 0x00 } },     /* 500   500      0.0   */
 485         { .icl = { 0xC, 0x64, 0x37, 0x00, 0x08 } },     /* 500   700      2.9   */
 486         { .icl = { 0x6, 0x7F, 0x32, 0x00, 0x0D } },     /* 500   900      5.1   */
 487         { .icl = { 0xC, 0x61, 0x3F, 0x00, 0x00 } },     /* 650   700      0.6   */
 488         { .icl = { 0x6, 0x7F, 0x37, 0x00, 0x08 } },     /* 600   900      3.5   */
 489         { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },     /* 900   900      0.0   */
 490 };
 491
 492 static const struct intel_ddi_buf_trans ehl_combo_phy_trans_dp = {
 493         .entries = _ehl_combo_phy_trans_dp,
 494         .num_entries = ARRAY_SIZE(_ehl_combo_phy_trans_dp),
 495 };
 496
 497 static const union intel_ddi_buf_trans_entry _ehl_combo_phy_trans_edp_hbr2[] = {
 498                                                         /* NT mV Trans mV db    */
 499         { .icl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } },     /* 200   200      0.0   */
 500         { .icl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } },     /* 200   250      1.9   */
 501         { .icl = { 0x1, 0x7F, 0x3D, 0x00, 0x02 } },     /* 200   300      3.5   */
 502         { .icl = { 0xA, 0x35, 0x39, 0x00, 0x06 } },     /* 200   350      4.9   */
 503         { .icl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } },     /* 250   250      0.0   */
 504         { .icl = { 0x1, 0x7F, 0x3C, 0x00, 0x03 } },     /* 250   300      1.6   */
 505         { .icl = { 0xA, 0x35, 0x39, 0x00, 0x06 } },     /* 250   350      2.9   */
 506         { .icl = { 0x1, 0x7F, 0x3F, 0x00, 0x00 } },     /* 300   300      0.0   */
 507         { .icl = { 0xA, 0x35, 0x38, 0x00, 0x07 } },     /* 300   350      1.3   */
 508         { .icl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } },     /* 350   350      0.0   */
 509 };
 510
 511 static const struct intel_ddi_buf_trans ehl_combo_phy_trans_edp_hbr2 = {
 512         .entries = _ehl_combo_phy_trans_edp_hbr2,
 513         .num_entries = ARRAY_SIZE(_ehl_combo_phy_trans_edp_hbr2),
 514 };
 515
 516 static const union intel_ddi_buf_trans_entry _jsl_combo_phy_trans_edp_hbr[] = {
 517                                                         /* NT mV Trans mV db    */
 518         { .icl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } },     /* 200   200      0.0   */
 519         { .icl = { 0x8, 0x7F, 0x38, 0x00, 0x07 } },     /* 200   250      1.9   */
 520         { .icl = { 0x1, 0x7F, 0x33, 0x00, 0x0C } },     /* 200   300      3.5   */
 521         { .icl = { 0xA, 0x35, 0x36, 0x00, 0x09 } },     /* 200   350      4.9   */
 522         { .icl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } },     /* 250   250      0.0   */
 523         { .icl = { 0x1, 0x7F, 0x38, 0x00, 0x07 } },     /* 250   300      1.6   */
 524         { .icl = { 0xA, 0x35, 0x35, 0x00, 0x0A } },     /* 250   350      2.9   */
 525         { .icl = { 0x1, 0x7F, 0x3F, 0x00, 0x00 } },     /* 300   300      0.0   */
 526         { .icl = { 0xA, 0x35, 0x38, 0x00, 0x07 } },     /* 300   350      1.3   */
 527         { .icl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } },     /* 350   350      0.0   */
 528 };
 529
 530 static const struct intel_ddi_buf_trans jsl_combo_phy_trans_edp_hbr = {
 531         .entries = _jsl_combo_phy_trans_edp_hbr,
 532         .num_entries = ARRAY_SIZE(_jsl_combo_phy_trans_edp_hbr),
 533 };
 534
 535 static const union intel_ddi_buf_trans_entry _jsl_combo_phy_trans_edp_hbr2[] = {
 536                                                         /* NT mV Trans mV db    */
 537         { .icl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } },     /* 200   200      0.0   */
 538         { .icl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } },     /* 200   250      1.9   */
 539         { .icl = { 0x1, 0x7F, 0x3D, 0x00, 0x02 } },     /* 200   300      3.5   */
 540         { .icl = { 0xA, 0x35, 0x38, 0x00, 0x07 } },     /* 200   350      4.9   */
 541         { .icl = { 0x8, 0x7F, 0x3F, 0x00, 0x00 } },     /* 250   250      0.0   */
 542         { .icl = { 0x1, 0x7F, 0x3F, 0x00, 0x00 } },     /* 250   300      1.6   */
 543         { .icl = { 0xA, 0x35, 0x3A, 0x00, 0x05 } },     /* 250   350      2.9   */
 544         { .icl = { 0x1, 0x7F, 0x3F, 0x00, 0x00 } },     /* 300   300      0.0   */
 545         { .icl = { 0xA, 0x35, 0x38, 0x00, 0x07 } },     /* 300   350      1.3   */
 546         { .icl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } },     /* 350   350      0.0   */
 547 };
 548
 549 static const struct intel_ddi_buf_trans jsl_combo_phy_trans_edp_hbr2 = {
 550         .entries = _jsl_combo_phy_trans_edp_hbr2,
 551         .num_entries = ARRAY_SIZE(_jsl_combo_phy_trans_edp_hbr2),
 552 };
 553
 554 static const union intel_ddi_buf_trans_entry _dg1_combo_phy_trans_dp_rbr_hbr[] = {
 555                                                         /* NT mV Trans mV db    */
 556         { .icl = { 0xA, 0x32, 0x3F, 0x00, 0x00 } },     /* 350   350      0.0   */
 557         { .icl = { 0xA, 0x48, 0x35, 0x00, 0x0A } },     /* 350   500      3.1   */
 558         { .icl = { 0xC, 0x63, 0x2F, 0x00, 0x10 } },     /* 350   700      6.0   */
 559         { .icl = { 0x6, 0x7F, 0x2C, 0x00, 0x13 } },     /* 350   900      8.2   */
 560         { .icl = { 0xA, 0x43, 0x3F, 0x00, 0x00 } },     /* 500   500      0.0   */
 561         { .icl = { 0xC, 0x60, 0x36, 0x00, 0x09 } },     /* 500   700      2.9   */
 562         { .icl = { 0x6, 0x7F, 0x30, 0x00, 0x0F } },     /* 500   900      5.1   */
 563         { .icl = { 0xC, 0x60, 0x3F, 0x00, 0x00 } },     /* 650   700      0.6   */
 564         { .icl = { 0x6, 0x7F, 0x37, 0x00, 0x08 } },     /* 600   900      3.5   */
 565         { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },     /* 900   900      0.0   */
 566 };
 567
 568 static const struct intel_ddi_buf_trans dg1_combo_phy_trans_dp_rbr_hbr = {
 569         .entries = _dg1_combo_phy_trans_dp_rbr_hbr,
 570         .num_entries = ARRAY_SIZE(_dg1_combo_phy_trans_dp_rbr_hbr),
 571 };
 572
 573 static const union intel_ddi_buf_trans_entry _dg1_combo_phy_trans_dp_hbr2_hbr3[] = {
 574                                                         /* NT mV Trans mV db    */
 575         { .icl = { 0xA, 0x32, 0x3F, 0x00, 0x00 } },     /* 350   350      0.0   */
 576         { .icl = { 0xA, 0x48, 0x35, 0x00, 0x0A } },     /* 350   500      3.1   */
 577         { .icl = { 0xC, 0x63, 0x2F, 0x00, 0x10 } },     /* 350   700      6.0   */
 578         { .icl = { 0x6, 0x7F, 0x2C, 0x00, 0x13 } },     /* 350   900      8.2   */
 579         { .icl = { 0xA, 0x43, 0x3F, 0x00, 0x00 } },     /* 500   500      0.0   */
 580         { .icl = { 0xC, 0x60, 0x36, 0x00, 0x09 } },     /* 500   700      2.9   */
 581         { .icl = { 0x6, 0x7F, 0x30, 0x00, 0x0F } },     /* 500   900      5.1   */
 582         { .icl = { 0xC, 0x58, 0x3F, 0x00, 0x00 } },     /* 650   700      0.6   */
 583         { .icl = { 0x6, 0x7F, 0x35, 0x00, 0x0A } },     /* 600   900      3.5   */
 584         { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },     /* 900   900      0.0   */
 585 };
 586
 587 static const struct intel_ddi_buf_trans dg1_combo_phy_trans_dp_hbr2_hbr3 = {
 588         .entries = _dg1_combo_phy_trans_dp_hbr2_hbr3,
 589         .num_entries = ARRAY_SIZE(_dg1_combo_phy_trans_dp_hbr2_hbr3),
 590 };
 591
 592 static const union intel_ddi_buf_trans_entry _icl_mg_phy_trans_rbr_hbr[] = {
 593                                         /* Voltage swing  pre-emphasis */
 594         { .mg = { 0x18, 0x00, 0x00 } }, /* 0              0   */
 595         { .mg = { 0x1D, 0x00, 0x05 } }, /* 0              1   */
 596         { .mg = { 0x24, 0x00, 0x0C } }, /* 0              2   */
 597         { .mg = { 0x2B, 0x00, 0x14 } }, /* 0              3   */
 598         { .mg = { 0x21, 0x00, 0x00 } }, /* 1              0   */
 599         { .mg = { 0x2B, 0x00, 0x08 } }, /* 1              1   */
 600         { .mg = { 0x30, 0x00, 0x0F } }, /* 1              2   */
 601         { .mg = { 0x31, 0x00, 0x03 } }, /* 2              0   */
 602         { .mg = { 0x34, 0x00, 0x0B } }, /* 2              1   */
 603         { .mg = { 0x3F, 0x00, 0x00 } }, /* 3              0   */
 604 };
 605
 606 static const struct intel_ddi_buf_trans icl_mg_phy_trans_rbr_hbr = {
 607         .entries = _icl_mg_phy_trans_rbr_hbr,
 608         .num_entries = ARRAY_SIZE(_icl_mg_phy_trans_rbr_hbr),
 609 };
 610
 611 static const union intel_ddi_buf_trans_entry _icl_mg_phy_trans_hbr2_hbr3[] = {
 612                                         /* Voltage swing  pre-emphasis */
 613         { .mg = { 0x18, 0x00, 0x00 } }, /* 0              0   */
 614         { .mg = { 0x1D, 0x00, 0x05 } }, /* 0              1   */
 615         { .mg = { 0x24, 0x00, 0x0C } }, /* 0              2   */
 616         { .mg = { 0x2B, 0x00, 0x14 } }, /* 0              3   */
 617         { .mg = { 0x26, 0x00, 0x00 } }, /* 1              0   */
 618         { .mg = { 0x2C, 0x00, 0x07 } }, /* 1              1   */
 619         { .mg = { 0x33, 0x00, 0x0C } }, /* 1              2   */
 620         { .mg = { 0x2E, 0x00, 0x00 } }, /* 2              0   */
 621         { .mg = { 0x36, 0x00, 0x09 } }, /* 2              1   */
 622         { .mg = { 0x3F, 0x00, 0x00 } }, /* 3              0   */
 623 };
 624
 625 static const struct intel_ddi_buf_trans icl_mg_phy_trans_hbr2_hbr3 = {
 626         .entries = _icl_mg_phy_trans_hbr2_hbr3,
 627         .num_entries = ARRAY_SIZE(_icl_mg_phy_trans_hbr2_hbr3),
 628 };
 629
 630 static const union intel_ddi_buf_trans_entry _icl_mg_phy_trans_hdmi[] = {
 631                                         /* HDMI Preset  VS      Pre-emph */
 632         { .mg = { 0x1A, 0x0, 0x0 } },   /* 1            400mV   0dB */
 633         { .mg = { 0x20, 0x0, 0x0 } },   /* 2            500mV   0dB */
 634         { .mg = { 0x29, 0x0, 0x0 } },   /* 3            650mV   0dB */
 635         { .mg = { 0x32, 0x0, 0x0 } },   /* 4            800mV   0dB */
 636         { .mg = { 0x3F, 0x0, 0x0 } },   /* 5            1000mV  0dB */
 637         { .mg = { 0x3A, 0x0, 0x5 } },   /* 6            Full    -1.5 dB */
 638         { .mg = { 0x39, 0x0, 0x6 } },   /* 7            Full    -1.8 dB */
 639         { .mg = { 0x38, 0x0, 0x7 } },   /* 8            Full    -2 dB */
 640         { .mg = { 0x37, 0x0, 0x8 } },   /* 9            Full    -2.5 dB */
 641         { .mg = { 0x36, 0x0, 0x9 } },   /* 10           Full    -3 dB */
 642 };
 643
 644 static const struct intel_ddi_buf_trans icl_mg_phy_trans_hdmi = {
 645         .entries = _icl_mg_phy_trans_hdmi,
 646         .num_entries = ARRAY_SIZE(_icl_mg_phy_trans_hdmi),
 647         .hdmi_default_entry = ARRAY_SIZE(_icl_mg_phy_trans_hdmi) - 1,
 648 };
 649
 650 static const union intel_ddi_buf_trans_entry _tgl_dkl_phy_trans_dp_hbr[] = {
 651                                         /* VS   pre-emp Non-trans mV    Pre-emph dB */
 652         { .dkl = { 0x7, 0x0, 0x00 } },  /* 0    0       400mV           0 dB */
 653         { .dkl = { 0x5, 0x0, 0x05 } },  /* 0    1       400mV           3.5 dB */
 654         { .dkl = { 0x2, 0x0, 0x0B } },  /* 0    2       400mV           6 dB */
 655         { .dkl = { 0x0, 0x0, 0x18 } },  /* 0    3       400mV           9.5 dB */
 656         { .dkl = { 0x5, 0x0, 0x00 } },  /* 1    0       600mV           0 dB */
 657         { .dkl = { 0x2, 0x0, 0x08 } },  /* 1    1       600mV           3.5 dB */
 658         { .dkl = { 0x0, 0x0, 0x14 } },  /* 1    2       600mV           6 dB */
 659         { .dkl = { 0x2, 0x0, 0x00 } },  /* 2    0       800mV           0 dB */
 660         { .dkl = { 0x0, 0x0, 0x0B } },  /* 2    1       800mV           3.5 dB */
 661         { .dkl = { 0x0, 0x0, 0x00 } },  /* 3    0       1200mV          0 dB HDMI default */
 662 };
 663
 664 static const struct intel_ddi_buf_trans tgl_dkl_phy_trans_dp_hbr = {
 665         .entries = _tgl_dkl_phy_trans_dp_hbr,
 666         .num_entries = ARRAY_SIZE(_tgl_dkl_phy_trans_dp_hbr),
 667 };
 668
 669 static const union intel_ddi_buf_trans_entry _tgl_dkl_phy_trans_dp_hbr2[] = {
 670                                         /* VS   pre-emp Non-trans mV    Pre-emph dB */
 671         { .dkl = { 0x7, 0x0, 0x00 } },  /* 0    0       400mV           0 dB */
 672         { .dkl = { 0x5, 0x0, 0x05 } },  /* 0    1       400mV           3.5 dB */
 673         { .dkl = { 0x2, 0x0, 0x0B } },  /* 0    2       400mV           6 dB */
 674         { .dkl = { 0x0, 0x0, 0x19 } },  /* 0    3       400mV           9.5 dB */
 675         { .dkl = { 0x5, 0x0, 0x00 } },  /* 1    0       600mV           0 dB */
 676         { .dkl = { 0x2, 0x0, 0x08 } },  /* 1    1       600mV           3.5 dB */
 677         { .dkl = { 0x0, 0x0, 0x14 } },  /* 1    2       600mV           6 dB */
 678         { .dkl = { 0x2, 0x0, 0x00 } },  /* 2    0       800mV           0 dB */
 679         { .dkl = { 0x0, 0x0, 0x0B } },  /* 2    1       800mV           3.5 dB */
 680         { .dkl = { 0x0, 0x0, 0x00 } },  /* 3    0       1200mV          0 dB HDMI default */
 681 };
 682
 683 static const struct intel_ddi_buf_trans tgl_dkl_phy_trans_dp_hbr2 = {
 684         .entries = _tgl_dkl_phy_trans_dp_hbr2,
 685         .num_entries = ARRAY_SIZE(_tgl_dkl_phy_trans_dp_hbr2),
 686 };
 687
 688 static const union intel_ddi_buf_trans_entry _tgl_dkl_phy_trans_hdmi[] = {
 689                                         /* HDMI Preset  VS      Pre-emph */
 690         { .dkl = { 0x7, 0x0, 0x0 } },   /* 1            400mV   0dB */
 691         { .dkl = { 0x6, 0x0, 0x0 } },   /* 2            500mV   0dB */
 692         { .dkl = { 0x4, 0x0, 0x0 } },   /* 3            650mV   0dB */
 693         { .dkl = { 0x2, 0x0, 0x0 } },   /* 4            800mV   0dB */
 694         { .dkl = { 0x0, 0x0, 0x0 } },   /* 5            1000mV  0dB */
 695         { .dkl = { 0x0, 0x0, 0x5 } },   /* 6            Full    -1.5 dB */
 696         { .dkl = { 0x0, 0x0, 0x6 } },   /* 7            Full    -1.8 dB */
 697         { .dkl = { 0x0, 0x0, 0x7 } },   /* 8            Full    -2 dB */
 698         { .dkl = { 0x0, 0x0, 0x8 } },   /* 9            Full    -2.5 dB */
 699         { .dkl = { 0x0, 0x0, 0xA } },   /* 10           Full    -3 dB */
 700 };
 701
 702 static const struct intel_ddi_buf_trans tgl_dkl_phy_trans_hdmi = {
 703         .entries = _tgl_dkl_phy_trans_hdmi,
 704         .num_entries = ARRAY_SIZE(_tgl_dkl_phy_trans_hdmi),
 705         .hdmi_default_entry = ARRAY_SIZE(_tgl_dkl_phy_trans_hdmi) - 1,
 706 };
 707
 708 static const union intel_ddi_buf_trans_entry _tgl_combo_phy_trans_dp_hbr[] = {
 709                                                         /* NT mV Trans mV db    */
 710         { .icl = { 0xA, 0x32, 0x3F, 0x00, 0x00 } },     /* 350   350      0.0   */
 711         { .icl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } },     /* 350   500      3.1   */
 712         { .icl = { 0xC, 0x71, 0x2F, 0x00, 0x10 } },     /* 350   700      6.0   */
 713         { .icl = { 0x6, 0x7D, 0x2B, 0x00, 0x14 } },     /* 350   900      8.2   */
 714         { .icl = { 0xA, 0x4C, 0x3F, 0x00, 0x00 } },     /* 500   500      0.0   */
 715         { .icl = { 0xC, 0x73, 0x34, 0x00, 0x0B } },     /* 500   700      2.9   */
 716         { .icl = { 0x6, 0x7F, 0x2F, 0x00, 0x10 } },     /* 500   900      5.1   */
 717         { .icl = { 0xC, 0x6C, 0x3C, 0x00, 0x03 } },     /* 650   700      0.6   */
 718         { .icl = { 0x6, 0x7F, 0x35, 0x00, 0x0A } },     /* 600   900      3.5   */
 719         { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },     /* 900   900      0.0   */
 720 };
 721
 722 static const struct intel_ddi_buf_trans tgl_combo_phy_trans_dp_hbr = {
 723         .entries = _tgl_combo_phy_trans_dp_hbr,
 724         .num_entries = ARRAY_SIZE(_tgl_combo_phy_trans_dp_hbr),
 725 };
 726
 727 static const union intel_ddi_buf_trans_entry _tgl_combo_phy_trans_dp_hbr2[] = {
 728                                                         /* NT mV Trans mV db    */
 729         { .icl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } },     /* 350   350      0.0   */
 730         { .icl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } },     /* 350   500      3.1   */
 731         { .icl = { 0xC, 0x63, 0x2F, 0x00, 0x10 } },     /* 350   700      6.0   */
 732         { .icl = { 0x6, 0x7F, 0x2B, 0x00, 0x14 } },     /* 350   900      8.2   */
 733         { .icl = { 0xA, 0x47, 0x3F, 0x00, 0x00 } },     /* 500   500      0.0   */
 734         { .icl = { 0xC, 0x63, 0x34, 0x00, 0x0B } },     /* 500   700      2.9   */
 735         { .icl = { 0x6, 0x7F, 0x2F, 0x00, 0x10 } },     /* 500   900      5.1   */
 736         { .icl = { 0xC, 0x61, 0x3C, 0x00, 0x03 } },     /* 650   700      0.6   */
 737         { .icl = { 0x6, 0x7B, 0x35, 0x00, 0x0A } },     /* 600   900      3.5   */
 738         { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },     /* 900   900      0.0   */
 739 };
 740
 741 static const struct intel_ddi_buf_trans tgl_combo_phy_trans_dp_hbr2 = {
 742         .entries = _tgl_combo_phy_trans_dp_hbr2,
 743         .num_entries = ARRAY_SIZE(_tgl_combo_phy_trans_dp_hbr2),
 744 };
 745
 746 static const union intel_ddi_buf_trans_entry _tgl_uy_combo_phy_trans_dp_hbr2[] = {
 747                                                         /* NT mV Trans mV db    */
 748         { .icl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } },     /* 350   350      0.0   */
 749         { .icl = { 0xA, 0x4F, 0x36, 0x00, 0x09 } },     /* 350   500      3.1   */
 750         { .icl = { 0xC, 0x60, 0x32, 0x00, 0x0D } },     /* 350   700      6.0   */
 751         { .icl = { 0xC, 0x7F, 0x2D, 0x00, 0x12 } },     /* 350   900      8.2   */
 752         { .icl = { 0xC, 0x47, 0x3F, 0x00, 0x00 } },     /* 500   500      0.0   */
 753         { .icl = { 0xC, 0x6F, 0x36, 0x00, 0x09 } },     /* 500   700      2.9   */
 754         { .icl = { 0x6, 0x7D, 0x32, 0x00, 0x0D } },     /* 500   900      5.1   */
 755         { .icl = { 0x6, 0x60, 0x3C, 0x00, 0x03 } },     /* 650   700      0.6   */
 756         { .icl = { 0x6, 0x7F, 0x34, 0x00, 0x0B } },     /* 600   900      3.5   */
 757         { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },     /* 900   900      0.0   */
 758 };
 759
 760 static const struct intel_ddi_buf_trans tgl_uy_combo_phy_trans_dp_hbr2 = {
 761         .entries = _tgl_uy_combo_phy_trans_dp_hbr2,
 762         .num_entries = ARRAY_SIZE(_tgl_uy_combo_phy_trans_dp_hbr2),
 763 };
 764
 765 /*
 766  * Cloned the HOBL entry to comply with the voltage and pre-emphasis entries
 767  * that DisplayPort specification requires
 768  */
 769 static const union intel_ddi_buf_trans_entry _tgl_combo_phy_trans_edp_hbr2_hobl[] = {
 770                                                         /* VS   pre-emp */
 771         { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },     /* 0    0       */
 772         { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },     /* 0    1       */
 773         { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },     /* 0    2       */
 774         { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },     /* 0    3       */
 775         { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },     /* 1    0       */
 776         { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },     /* 1    1       */
 777         { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },     /* 1    2       */
 778         { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },     /* 2    0       */
 779         { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },     /* 2    1       */
 780 };
 781
 782 static const struct intel_ddi_buf_trans tgl_combo_phy_trans_edp_hbr2_hobl = {
 783         .entries = _tgl_combo_phy_trans_edp_hbr2_hobl,
 784         .num_entries = ARRAY_SIZE(_tgl_combo_phy_trans_edp_hbr2_hobl),
 785 };
 786
 787 static const union intel_ddi_buf_trans_entry _rkl_combo_phy_trans_dp_hbr[] = {
 788                                                         /* NT mV Trans mV db    */
 789         { .icl = { 0xA, 0x2F, 0x3F, 0x00, 0x00 } },     /* 350   350      0.0   */
 790         { .icl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } },     /* 350   500      3.1   */
 791         { .icl = { 0xC, 0x63, 0x2F, 0x00, 0x10 } },     /* 350   700      6.0   */
 792         { .icl = { 0x6, 0x7D, 0x2A, 0x00, 0x15 } },     /* 350   900      8.2   */
 793         { .icl = { 0xA, 0x4C, 0x3F, 0x00, 0x00 } },     /* 500   500      0.0   */
 794         { .icl = { 0xC, 0x73, 0x34, 0x00, 0x0B } },     /* 500   700      2.9   */
 795         { .icl = { 0x6, 0x7F, 0x2F, 0x00, 0x10 } },     /* 500   900      5.1   */
 796         { .icl = { 0xC, 0x6E, 0x3E, 0x00, 0x01 } },     /* 650   700      0.6   */
 797         { .icl = { 0x6, 0x7F, 0x35, 0x00, 0x0A } },     /* 600   900      3.5   */
 798         { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },     /* 900   900      0.0   */
 799 };
 800
 801 static const struct intel_ddi_buf_trans rkl_combo_phy_trans_dp_hbr = {
 802         .entries = _rkl_combo_phy_trans_dp_hbr,
 803         .num_entries = ARRAY_SIZE(_rkl_combo_phy_trans_dp_hbr),
 804 };
 805
 806 static const union intel_ddi_buf_trans_entry _rkl_combo_phy_trans_dp_hbr2_hbr3[] = {
 807                                                         /* NT mV Trans mV db    */
 808         { .icl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } },     /* 350   350      0.0   */
 809         { .icl = { 0xA, 0x50, 0x38, 0x00, 0x07 } },     /* 350   500      3.1   */
 810         { .icl = { 0xC, 0x61, 0x33, 0x00, 0x0C } },     /* 350   700      6.0   */
 811         { .icl = { 0x6, 0x7F, 0x2E, 0x00, 0x11 } },     /* 350   900      8.2   */
 812         { .icl = { 0xA, 0x47, 0x3F, 0x00, 0x00 } },     /* 500   500      0.0   */
 813         { .icl = { 0xC, 0x5F, 0x38, 0x00, 0x07 } },     /* 500   700      2.9   */
 814         { .icl = { 0x6, 0x7F, 0x2F, 0x00, 0x10 } },     /* 500   900      5.1   */
 815         { .icl = { 0xC, 0x5F, 0x3F, 0x00, 0x00 } },     /* 650   700      0.6   */
 816         { .icl = { 0x6, 0x7E, 0x36, 0x00, 0x09 } },     /* 600   900      3.5   */
 817         { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },     /* 900   900      0.0   */
 818 };
 819
 820 static const struct intel_ddi_buf_trans rkl_combo_phy_trans_dp_hbr2_hbr3 = {
 821         .entries = _rkl_combo_phy_trans_dp_hbr2_hbr3,
 822         .num_entries = ARRAY_SIZE(_rkl_combo_phy_trans_dp_hbr2_hbr3),
 823 };
 824
 825 static const union intel_ddi_buf_trans_entry _adls_combo_phy_trans_dp_hbr2_hbr3[] = {
 826                                                         /* NT mV Trans mV db    */
 827         { .icl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } },     /* 350   350      0.0   */
 828         { .icl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } },     /* 350   500      3.1   */
 829         { .icl = { 0xC, 0x63, 0x31, 0x00, 0x0E } },     /* 350   700      6.0   */
 830         { .icl = { 0x6, 0x7F, 0x2C, 0x00, 0x13 } },     /* 350   900      8.2   */
 831         { .icl = { 0xA, 0x47, 0x3F, 0x00, 0x00 } },     /* 500   500      0.0   */
 832         { .icl = { 0xC, 0x63, 0x37, 0x00, 0x08 } },     /* 500   700      2.9   */
 833         { .icl = { 0x6, 0x73, 0x32, 0x00, 0x0D } },     /* 500   900      5.1   */
 834         { .icl = { 0xC, 0x58, 0x3F, 0x00, 0x00 } },     /* 650   700      0.6   */
 835         { .icl = { 0x6, 0x7F, 0x35, 0x00, 0x0A } },     /* 600   900      3.5   */
 836         { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },     /* 900   900      0.0   */
 837 };
 838
 839 static const struct intel_ddi_buf_trans adls_combo_phy_trans_dp_hbr2_hbr3 = {
 840         .entries = _adls_combo_phy_trans_dp_hbr2_hbr3,
 841         .num_entries = ARRAY_SIZE(_adls_combo_phy_trans_dp_hbr2_hbr3),
 842 };
 843
 844 static const union intel_ddi_buf_trans_entry _adls_combo_phy_trans_edp_hbr2[] = {
 845                                                         /* NT mV Trans mV db    */
 846         { .icl = { 0x9, 0x73, 0x3D, 0x00, 0x02 } },     /* 200   200      0.0   */
 847         { .icl = { 0x9, 0x7A, 0x3C, 0x00, 0x03 } },     /* 200   250      1.9   */
 848         { .icl = { 0x9, 0x7F, 0x3B, 0x00, 0x04 } },     /* 200   300      3.5   */
 849         { .icl = { 0x4, 0x6C, 0x33, 0x00, 0x0C } },     /* 200   350      4.9   */
 850         { .icl = { 0x2, 0x73, 0x3A, 0x00, 0x05 } },     /* 250   250      0.0   */
 851         { .icl = { 0x2, 0x7C, 0x38, 0x00, 0x07 } },     /* 250   300      1.6   */
 852         { .icl = { 0x4, 0x5A, 0x36, 0x00, 0x09 } },     /* 250   350      2.9   */
 853         { .icl = { 0x4, 0x57, 0x3D, 0x00, 0x02 } },     /* 300   300      0.0   */
 854         { .icl = { 0x4, 0x65, 0x38, 0x00, 0x07 } },     /* 300   350      1.3   */
 855         { .icl = { 0x4, 0x6C, 0x3A, 0x00, 0x05 } },     /* 350   350      0.0   */
 856 };
 857
 858 static const struct intel_ddi_buf_trans adls_combo_phy_trans_edp_hbr2 = {
 859         .entries = _adls_combo_phy_trans_edp_hbr2,
 860         .num_entries = ARRAY_SIZE(_adls_combo_phy_trans_edp_hbr2),
 861 };
 862
 863 static const union intel_ddi_buf_trans_entry _adls_combo_phy_trans_edp_hbr3[] = {
 864                                                         /* NT mV Trans mV db    */
 865         { .icl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } },     /* 350   350      0.0   */
 866         { .icl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } },     /* 350   500      3.1   */
 867         { .icl = { 0xC, 0x63, 0x31, 0x00, 0x0E } },     /* 350   700      6.0   */
 868         { .icl = { 0x6, 0x7F, 0x2C, 0x00, 0x13 } },     /* 350   900      8.2   */
 869         { .icl = { 0xA, 0x47, 0x3F, 0x00, 0x00 } },     /* 500   500      0.0   */
 870         { .icl = { 0xC, 0x63, 0x37, 0x00, 0x08 } },     /* 500   700      2.9   */
 871         { .icl = { 0x6, 0x73, 0x32, 0x00, 0x0D } },     /* 500   900      5.1   */
 872         { .icl = { 0xC, 0x58, 0x3F, 0x00, 0x00 } },     /* 650   700      0.6   */
 873         { .icl = { 0x6, 0x7F, 0x35, 0x00, 0x0A } },     /* 600   900      3.5   */
 874         { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },     /* 900   900      0.0   */
 875 };
 876
 877 static const struct intel_ddi_buf_trans adls_combo_phy_trans_edp_hbr3 = {
 878         .entries = _adls_combo_phy_trans_edp_hbr3,
 879         .num_entries = ARRAY_SIZE(_adls_combo_phy_trans_edp_hbr3),
 880 };
 881
 882 static const union intel_ddi_buf_trans_entry _adlp_combo_phy_trans_dp_hbr[] = {
 883                                                         /* NT mV Trans mV db    */
 884         { .icl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } },     /* 350   350      0.0   */
 885         { .icl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } },     /* 350   500      3.1   */
 886         { .icl = { 0xC, 0x71, 0x31, 0x00, 0x0E } },     /* 350   700      6.0   */
 887         { .icl = { 0x6, 0x7F, 0x2C, 0x00, 0x13 } },     /* 350   900      8.2   */
 888         { .icl = { 0xA, 0x4C, 0x3F, 0x00, 0x00 } },     /* 500   500      0.0   */
 889         { .icl = { 0xC, 0x73, 0x34, 0x00, 0x0B } },     /* 500   700      2.9   */
 890         { .icl = { 0x6, 0x7F, 0x2F, 0x00, 0x10 } },     /* 500   900      5.1   */
 891         { .icl = { 0xC, 0x7C, 0x3C, 0x00, 0x03 } },     /* 650   700      0.6   */
 892         { .icl = { 0x6, 0x7F, 0x35, 0x00, 0x0A } },     /* 600   900      3.5   */
 893         { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },     /* 900   900      0.0   */
 894 };
 895
 896 static const struct intel_ddi_buf_trans adlp_combo_phy_trans_dp_hbr = {
 897         .entries = _adlp_combo_phy_trans_dp_hbr,
 898         .num_entries = ARRAY_SIZE(_adlp_combo_phy_trans_dp_hbr),
 899 };
 900
 901 static const union intel_ddi_buf_trans_entry _adlp_combo_phy_trans_dp_hbr2_hbr3[] = {
 902                                                         /* NT mV Trans mV db    */
 903         { .icl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } },     /* 350   350      0.0   */
 904         { .icl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } },     /* 350   500      3.1   */
 905         { .icl = { 0xC, 0x71, 0x30, 0x00, 0x0F } },     /* 350   700      6.0   */
 906         { .icl = { 0x6, 0x7F, 0x2B, 0x00, 0x14 } },     /* 350   900      8.2   */
 907         { .icl = { 0xA, 0x4C, 0x3F, 0x00, 0x00 } },     /* 500   500      0.0   */
 908         { .icl = { 0xC, 0x73, 0x34, 0x00, 0x0B } },     /* 500   700      2.9   */
 909         { .icl = { 0x6, 0x7F, 0x30, 0x00, 0x0F } },     /* 500   900      5.1   */
 910         { .icl = { 0xC, 0x63, 0x3F, 0x00, 0x00 } },     /* 650   700      0.6   */
 911         { .icl = { 0x6, 0x7F, 0x38, 0x00, 0x07 } },     /* 600   900      3.5   */
 912         { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },     /* 900   900      0.0   */
 913 };
 914
 915 static const union intel_ddi_buf_trans_entry _adlp_combo_phy_trans_edp_hbr2[] = {
 916                                                         /* NT mV Trans mV db    */
 917         { .icl = { 0x4, 0x50, 0x38, 0x00, 0x07 } },     /* 200   200      0.0   */
 918         { .icl = { 0x4, 0x58, 0x35, 0x00, 0x0A } },     /* 200   250      1.9   */
 919         { .icl = { 0x4, 0x60, 0x34, 0x00, 0x0B } },     /* 200   300      3.5   */
 920         { .icl = { 0x4, 0x6A, 0x32, 0x00, 0x0D } },     /* 200   350      4.9   */
 921         { .icl = { 0x4, 0x5E, 0x38, 0x00, 0x07 } },     /* 250   250      0.0   */
 922         { .icl = { 0x4, 0x61, 0x36, 0x00, 0x09 } },     /* 250   300      1.6   */
 923         { .icl = { 0x4, 0x6B, 0x34, 0x00, 0x0B } },     /* 250   350      2.9   */
 924         { .icl = { 0x4, 0x69, 0x39, 0x00, 0x06 } },     /* 300   300      0.0   */
 925         { .icl = { 0x4, 0x73, 0x37, 0x00, 0x08 } },     /* 300   350      1.3   */
 926         { .icl = { 0x4, 0x7A, 0x38, 0x00, 0x07 } },     /* 350   350      0.0   */
 927 };
 928
 929 static const union intel_ddi_buf_trans_entry _adlp_combo_phy_trans_dp_hbr2_edp_hbr3[] = {
 930                                                         /* NT mV Trans mV db    */
 931         { .icl = { 0xA, 0x35, 0x3F, 0x00, 0x00 } },     /* 350   350      0.0   */
 932         { .icl = { 0xA, 0x4F, 0x37, 0x00, 0x08 } },     /* 350   500      3.1   */
 933         { .icl = { 0xC, 0x71, 0x30, 0x00, 0x0f } },     /* 350   700      6.0   */
 934         { .icl = { 0x6, 0x7F, 0x2B, 0x00, 0x14 } },     /* 350   900      8.2   */
 935         { .icl = { 0xA, 0x4C, 0x3F, 0x00, 0x00 } },     /* 500   500      0.0   */
 936         { .icl = { 0xC, 0x73, 0x34, 0x00, 0x0B } },     /* 500   700      2.9   */
 937         { .icl = { 0x6, 0x7F, 0x30, 0x00, 0x0F } },     /* 500   900      5.1   */
 938         { .icl = { 0xC, 0x63, 0x3F, 0x00, 0x00 } },     /* 650   700      0.6   */
 939         { .icl = { 0x6, 0x7F, 0x38, 0x00, 0x07 } },     /* 600   900      3.5   */
 940         { .icl = { 0x6, 0x7F, 0x3F, 0x00, 0x00 } },     /* 900   900      0.0   */
 941 };
 942
 943 static const struct intel_ddi_buf_trans adlp_combo_phy_trans_dp_hbr2_hbr3 = {
 944         .entries = _adlp_combo_phy_trans_dp_hbr2_hbr3,
 945         .num_entries = ARRAY_SIZE(_adlp_combo_phy_trans_dp_hbr2_hbr3),
 946 };
 947
 948 static const struct intel_ddi_buf_trans adlp_combo_phy_trans_edp_hbr3 = {
 949         .entries = _adlp_combo_phy_trans_dp_hbr2_edp_hbr3,
 950         .num_entries = ARRAY_SIZE(_adlp_combo_phy_trans_dp_hbr2_edp_hbr3),
 951 };
 952
 953 static const struct intel_ddi_buf_trans adlp_combo_phy_trans_edp_up_to_hbr2 = {
 954         .entries = _adlp_combo_phy_trans_edp_hbr2,
 955         .num_entries = ARRAY_SIZE(_adlp_combo_phy_trans_edp_hbr2),
 956 };
 957
 958 static const union intel_ddi_buf_trans_entry _adlp_dkl_phy_trans_dp_hbr[] = {
 959                                         /* VS   pre-emp Non-trans mV    Pre-emph dB */
 960         { .dkl = { 0x7, 0x0, 0x01 } },  /* 0    0       400mV           0 dB */
 961         { .dkl = { 0x5, 0x0, 0x06 } },  /* 0    1       400mV           3.5 dB */
 962         { .dkl = { 0x2, 0x0, 0x0B } },  /* 0    2       400mV           6 dB */
 963         { .dkl = { 0x0, 0x0, 0x17 } },  /* 0    3       400mV           9.5 dB */
 964         { .dkl = { 0x5, 0x0, 0x00 } },  /* 1    0       600mV           0 dB */
 965         { .dkl = { 0x2, 0x0, 0x08 } },  /* 1    1       600mV           3.5 dB */
 966         { .dkl = { 0x0, 0x0, 0x14 } },  /* 1    2       600mV           6 dB */
 967         { .dkl = { 0x2, 0x0, 0x00 } },  /* 2    0       800mV           0 dB */
 968         { .dkl = { 0x0, 0x0, 0x0B } },  /* 2    1       800mV           3.5 dB */
 969         { .dkl = { 0x0, 0x0, 0x00 } },  /* 3    0       1200mV          0 dB */
 970 };
 971
 972 static const struct intel_ddi_buf_trans adlp_dkl_phy_trans_dp_hbr = {
 973         .entries = _adlp_dkl_phy_trans_dp_hbr,
 974         .num_entries = ARRAY_SIZE(_adlp_dkl_phy_trans_dp_hbr),
 975 };
 976
 977 static const union intel_ddi_buf_trans_entry _adlp_dkl_phy_trans_dp_hbr2_hbr3[] = {
 978                                         /* VS   pre-emp Non-trans mV    Pre-emph dB */
 979         { .dkl = { 0x7, 0x0, 0x00 } },  /* 0    0       400mV           0 dB */
 980         { .dkl = { 0x5, 0x0, 0x04 } },  /* 0    1       400mV           3.5 dB */
 981         { .dkl = { 0x2, 0x0, 0x0A } },  /* 0    2       400mV           6 dB */
 982         { .dkl = { 0x0, 0x0, 0x18 } },  /* 0    3       400mV           9.5 dB */
 983         { .dkl = { 0x5, 0x0, 0x00 } },  /* 1    0       600mV           0 dB */
 984         { .dkl = { 0x2, 0x0, 0x06 } },  /* 1    1       600mV           3.5 dB */
 985         { .dkl = { 0x0, 0x0, 0x14 } },  /* 1    2       600mV           6 dB */
 986         { .dkl = { 0x2, 0x0, 0x00 } },  /* 2    0       800mV           0 dB */
 987         { .dkl = { 0x0, 0x0, 0x09 } },  /* 2    1       800mV           3.5 dB */
 988         { .dkl = { 0x0, 0x0, 0x00 } },  /* 3    0       1200mV          0 dB */
 989 };
 990
 991 static const struct intel_ddi_buf_trans adlp_dkl_phy_trans_dp_hbr2_hbr3 = {
 992         .entries = _adlp_dkl_phy_trans_dp_hbr2_hbr3,
 993         .num_entries = ARRAY_SIZE(_adlp_dkl_phy_trans_dp_hbr2_hbr3),
 994 };
 995
 996 static const union intel_ddi_buf_trans_entry _dg2_snps_trans[] = {
 997         { .snps = { 25, 0, 0 } },       /* VS 0, pre-emph 0 */
 998         { .snps = { 32, 0, 6 } },       /* VS 0, pre-emph 1 */
 999         { .snps = { 35, 0, 10 } },      /* VS 0, pre-emph 2 */
1000         { .snps = { 43, 0, 17 } },      /* VS 0, pre-emph 3 */
1001         { .snps = { 35, 0, 0 } },       /* VS 1, pre-emph 0 */
1002         { .snps = { 45, 0, 8 } },       /* VS 1, pre-emph 1 */
1003         { .snps = { 48, 0, 14 } },      /* VS 1, pre-emph 2 */
1004         { .snps = { 47, 0, 0 } },       /* VS 2, pre-emph 0 */
1005         { .snps = { 55, 0, 7 } },       /* VS 2, pre-emph 1 */
1006         { .snps = { 62, 0, 0 } },       /* VS 3, pre-emph 0 */
1007 };
1008
1009 static const struct intel_ddi_buf_trans dg2_snps_trans = {
1010         .entries = _dg2_snps_trans,
1011         .num_entries = ARRAY_SIZE(_dg2_snps_trans),
1012         .hdmi_default_entry = ARRAY_SIZE(_dg2_snps_trans) - 1,
1013 };
1014
1015 static const union intel_ddi_buf_trans_entry _dg2_snps_trans_uhbr[] = {
1016         { .snps = { 62, 0, 0 } },       /* preset 0 */
1017         { .snps = { 55, 0, 7 } },       /* preset 1 */
1018         { .snps = { 50, 0, 12 } },      /* preset 2 */
1019         { .snps = { 44, 0, 18 } },      /* preset 3 */
1020         { .snps = { 35, 0, 21 } },      /* preset 4 */
1021         { .snps = { 59, 3, 0 } },       /* preset 5 */
1022         { .snps = { 53, 3, 6 } },       /* preset 6 */
1023         { .snps = { 48, 3, 11 } },      /* preset 7 */
1024         { .snps = { 42, 5, 15 } },      /* preset 8 */
1025         { .snps = { 37, 5, 20 } },      /* preset 9 */
1026         { .snps = { 56, 6, 0 } },       /* preset 10 */
1027         { .snps = { 48, 7, 7 } },       /* preset 11 */
1028         { .snps = { 45, 7, 10 } },      /* preset 12 */
1029         { .snps = { 39, 8, 15 } },      /* preset 13 */
1030         { .snps = { 48, 14, 0 } },      /* preset 14 */
1031         { .snps = { 45, 4, 4 } },       /* preset 15 */
1032 };
1033
1034 static const struct intel_ddi_buf_trans dg2_snps_trans_uhbr = {
1035         .entries = _dg2_snps_trans_uhbr,
1036         .num_entries = ARRAY_SIZE(_dg2_snps_trans_uhbr),
1037 };
1038
1039 static const union intel_ddi_buf_trans_entry _mtl_c10_trans_dp14[] = {
1040         { .snps = { 26, 0, 0  } },      /* preset 0 */
1041         { .snps = { 33, 0, 6  } },      /* preset 1 */
1042         { .snps = { 38, 0, 11 } },      /* preset 2 */
1043         { .snps = { 43, 0, 19 } },      /* preset 3 */
1044         { .snps = { 39, 0, 0  } },      /* preset 4 */
1045         { .snps = { 45, 0, 7  } },      /* preset 5 */
1046         { .snps = { 46, 0, 13 } },      /* preset 6 */
1047         { .snps = { 46, 0, 0  } },      /* preset 7 */
1048         { .snps = { 55, 0, 7  } },      /* preset 8 */
1049         { .snps = { 62, 0, 0  } },      /* preset 9 */
1050 };
1051
1052 static const struct intel_ddi_buf_trans mtl_cx0_trans = {
1053         .entries = _mtl_c10_trans_dp14,
1054         .num_entries = ARRAY_SIZE(_mtl_c10_trans_dp14),
1055         .hdmi_default_entry = ARRAY_SIZE(_mtl_c10_trans_dp14) - 1,
1056 };
1057
1058 /* DP2.0 */
1059 static const union intel_ddi_buf_trans_entry _mtl_c20_trans_uhbr[] = {
1060         { .snps = { 48, 0, 0 } },       /* preset 0 */
1061         { .snps = { 43, 0, 5 } },       /* preset 1 */
1062         { .snps = { 40, 0, 8 } },       /* preset 2 */
1063         { .snps = { 37, 0, 11 } },      /* preset 3 */
1064         { .snps = { 33, 0, 15 } },      /* preset 4 */
1065         { .snps = { 46, 2, 0 } },       /* preset 5 */
1066         { .snps = { 42, 2, 4 } },       /* preset 6 */
1067         { .snps = { 38, 2, 8 } },       /* preset 7 */
1068         { .snps = { 35, 2, 11 } },      /* preset 8 */
1069         { .snps = { 33, 2, 13 } },      /* preset 9 */
1070         { .snps = { 44, 4, 0 } },       /* preset 10 */
1071         { .snps = { 40, 4, 4 } },       /* preset 11 */
1072         { .snps = { 37, 4, 7 } },       /* preset 12 */
1073         { .snps = { 33, 4, 11 } },      /* preset 13 */
1074         { .snps = { 40, 8, 0 } },       /* preset 14 */
1075         { .snps = { 28, 2, 2 } },       /* preset 15 */
1076 };
1077
1078 /* HDMI2.0 */
1079 static const union intel_ddi_buf_trans_entry _mtl_c20_trans_hdmi[] = {
1080         { .snps = { 48, 0, 0 } },       /* preset 0 */
1081         { .snps = { 38, 4, 6 } },       /* preset 1 */
1082         { .snps = { 36, 4, 8 } },       /* preset 2 */
1083         { .snps = { 34, 4, 10 } },      /* preset 3 */
1084         { .snps = { 32, 4, 12 } },      /* preset 4 */
1085 };
1086
1087 static const struct intel_ddi_buf_trans mtl_c20_trans_hdmi = {
1088         .entries = _mtl_c20_trans_hdmi,
1089         .num_entries = ARRAY_SIZE(_mtl_c20_trans_hdmi),
1090         .hdmi_default_entry = 0,
1091 };
1092
1093 static const struct intel_ddi_buf_trans mtl_c20_trans_uhbr = {
1094         .entries = _mtl_c20_trans_uhbr,
1095         .num_entries = ARRAY_SIZE(_mtl_c20_trans_uhbr),
1096 };
1097
1098 bool is_hobl_buf_trans(const struct intel_ddi_buf_trans *table)
1099 {
1100         return table == &tgl_combo_phy_trans_edp_hbr2_hobl;
1101 }
1102
1103 static bool use_edp_hobl(struct intel_encoder *encoder)
1104 {
1105         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1106         struct intel_connector *connector = intel_dp->attached_connector;
1107
1108         return connector->panel.vbt.edp.hobl && !intel_dp->hobl_failed;
1109 }
1110
1111 static bool use_edp_low_vswing(struct intel_encoder *encoder)
1112 {
1113         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1114         struct intel_connector *connector = intel_dp->attached_connector;
1115
1116         return connector->panel.vbt.edp.low_vswing;
1117 }
1118
1119 static const struct intel_ddi_buf_trans *
1120 intel_get_buf_trans(const struct intel_ddi_buf_trans *trans, int *num_entries)
1121 {
1122         *num_entries = trans->num_entries;
1123         return trans;
1124 }
1125
1126 static const struct intel_ddi_buf_trans *
1127 hsw_get_buf_trans(struct intel_encoder *encoder,
1128                   const struct intel_crtc_state *crtc_state,
1129                   int *n_entries)
1130 {
1131         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
1132                 return intel_get_buf_trans(&hsw_trans_fdi, n_entries);
1133         else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1134                 return intel_get_buf_trans(&hsw_trans_hdmi, n_entries);
1135         else
1136                 return intel_get_buf_trans(&hsw_trans_dp, n_entries);
1137 }
1138
1139 static const struct intel_ddi_buf_trans *
1140 bdw_get_buf_trans(struct intel_encoder *encoder,
1141                   const struct intel_crtc_state *crtc_state,
1142                   int *n_entries)
1143 {
1144         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
1145                 return intel_get_buf_trans(&bdw_trans_fdi, n_entries);
1146         else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1147                 return intel_get_buf_trans(&bdw_trans_hdmi, n_entries);
1148         else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) &&
1149                  use_edp_low_vswing(encoder))
1150                 return intel_get_buf_trans(&bdw_trans_edp, n_entries);
1151         else
1152                 return intel_get_buf_trans(&bdw_trans_dp, n_entries);
1153 }
1154
1155 static int skl_buf_trans_num_entries(enum port port, int n_entries)
1156 {
1157         /* Only DDIA and DDIE can select the 10th register with DP */
1158         if (port == PORT_A || port == PORT_E)
1159                 return min(n_entries, 10);
1160         else
1161                 return min(n_entries, 9);
1162 }
1163
1164 static const struct intel_ddi_buf_trans *
1165 _skl_get_buf_trans_dp(struct intel_encoder *encoder,
1166                       const struct intel_ddi_buf_trans *trans,
1167                       int *n_entries)
1168 {
1169         trans = intel_get_buf_trans(trans, n_entries);
1170         *n_entries = skl_buf_trans_num_entries(encoder->port, *n_entries);
1171         return trans;
1172 }
1173
1174 static const struct intel_ddi_buf_trans *
1175 skl_y_get_buf_trans(struct intel_encoder *encoder,
1176                     const struct intel_crtc_state *crtc_state,
1177                     int *n_entries)
1178 {
1179         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1180                 return intel_get_buf_trans(&skl_y_trans_hdmi, n_entries);
1181         else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) &&
1182                  use_edp_low_vswing(encoder))
1183                 return _skl_get_buf_trans_dp(encoder, &skl_y_trans_edp, n_entries);
1184         else
1185                 return _skl_get_buf_trans_dp(encoder, &skl_y_trans_dp, n_entries);
1186 }
1187
1188 static const struct intel_ddi_buf_trans *
1189 skl_u_get_buf_trans(struct intel_encoder *encoder,
1190                     const struct intel_crtc_state *crtc_state,
1191                     int *n_entries)
1192 {
1193         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1194                 return intel_get_buf_trans(&skl_trans_hdmi, n_entries);
1195         else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) &&
1196                  use_edp_low_vswing(encoder))
1197                 return _skl_get_buf_trans_dp(encoder, &skl_u_trans_edp, n_entries);
1198         else
1199                 return _skl_get_buf_trans_dp(encoder, &skl_u_trans_dp, n_entries);
1200 }
1201
1202 static const struct intel_ddi_buf_trans *
1203 skl_get_buf_trans(struct intel_encoder *encoder,
1204                   const struct intel_crtc_state *crtc_state,
1205                   int *n_entries)
1206 {
1207         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1208                 return intel_get_buf_trans(&skl_trans_hdmi, n_entries);
1209         else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) &&
1210                  use_edp_low_vswing(encoder))
1211                 return _skl_get_buf_trans_dp(encoder, &skl_trans_edp, n_entries);
1212         else
1213                 return _skl_get_buf_trans_dp(encoder, &skl_trans_dp, n_entries);
1214 }
1215
1216 static const struct intel_ddi_buf_trans *
1217 kbl_y_get_buf_trans(struct intel_encoder *encoder,
1218                     const struct intel_crtc_state *crtc_state,
1219                     int *n_entries)
1220 {
1221         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1222                 return intel_get_buf_trans(&skl_y_trans_hdmi, n_entries);
1223         else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) &&
1224                  use_edp_low_vswing(encoder))
1225                 return _skl_get_buf_trans_dp(encoder, &skl_y_trans_edp, n_entries);
1226         else
1227                 return _skl_get_buf_trans_dp(encoder, &kbl_y_trans_dp, n_entries);
1228 }
1229
1230 static const struct intel_ddi_buf_trans *
1231 kbl_u_get_buf_trans(struct intel_encoder *encoder,
1232                     const struct intel_crtc_state *crtc_state,
1233                     int *n_entries)
1234 {
1235         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1236                 return intel_get_buf_trans(&skl_trans_hdmi, n_entries);
1237         else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) &&
1238                  use_edp_low_vswing(encoder))
1239                 return _skl_get_buf_trans_dp(encoder, &skl_u_trans_edp, n_entries);
1240         else
1241                 return _skl_get_buf_trans_dp(encoder, &kbl_u_trans_dp, n_entries);
1242 }
1243
1244 static const struct intel_ddi_buf_trans *
1245 kbl_get_buf_trans(struct intel_encoder *encoder,
1246                   const struct intel_crtc_state *crtc_state,
1247                   int *n_entries)
1248 {
1249         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1250                 return intel_get_buf_trans(&skl_trans_hdmi, n_entries);
1251         else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) &&
1252                  use_edp_low_vswing(encoder))
1253                 return _skl_get_buf_trans_dp(encoder, &skl_trans_edp, n_entries);
1254         else
1255                 return _skl_get_buf_trans_dp(encoder, &kbl_trans_dp, n_entries);
1256 }
1257
1258 static const struct intel_ddi_buf_trans *
1259 bxt_get_buf_trans(struct intel_encoder *encoder,
1260                   const struct intel_crtc_state *crtc_state,
1261                   int *n_entries)
1262 {
1263         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1264                 return intel_get_buf_trans(&bxt_trans_hdmi, n_entries);
1265         else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) &&
1266                  use_edp_low_vswing(encoder))
1267                 return intel_get_buf_trans(&bxt_trans_edp, n_entries);
1268         else
1269                 return intel_get_buf_trans(&bxt_trans_dp, n_entries);
1270 }
1271
1272 static const struct intel_ddi_buf_trans *
1273 icl_get_combo_buf_trans_dp(struct intel_encoder *encoder,
1274                            const struct intel_crtc_state *crtc_state,
1275                            int *n_entries)
1276 {
1277         return intel_get_buf_trans(&icl_combo_phy_trans_dp_hbr2_edp_hbr3,
1278                                    n_entries);
1279 }
1280
1281 static const struct intel_ddi_buf_trans *
1282 icl_get_combo_buf_trans_edp(struct intel_encoder *encoder,
1283                             const struct intel_crtc_state *crtc_state,
1284                             int *n_entries)
1285 {
1286         if (crtc_state->port_clock > 540000) {
1287                 return intel_get_buf_trans(&icl_combo_phy_trans_dp_hbr2_edp_hbr3,
1288                                            n_entries);
1289         } else if (use_edp_low_vswing(encoder)) {
1290                 return intel_get_buf_trans(&icl_combo_phy_trans_edp_hbr2,
1291                                            n_entries);
1292         }
1293
1294         return icl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
1295 }
1296
1297 static const struct intel_ddi_buf_trans *
1298 icl_get_combo_buf_trans(struct intel_encoder *encoder,
1299                         const struct intel_crtc_state *crtc_state,
1300                         int *n_entries)
1301 {
1302         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1303                 return intel_get_buf_trans(&icl_combo_phy_trans_hdmi, n_entries);
1304         else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
1305                 return icl_get_combo_buf_trans_edp(encoder, crtc_state, n_entries);
1306         else
1307                 return icl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
1308 }
1309
1310 static const struct intel_ddi_buf_trans *
1311 icl_get_mg_buf_trans_dp(struct intel_encoder *encoder,
1312                         const struct intel_crtc_state *crtc_state,
1313                         int *n_entries)
1314 {
1315         if (crtc_state->port_clock > 270000) {
1316                 return intel_get_buf_trans(&icl_mg_phy_trans_hbr2_hbr3,
1317                                            n_entries);
1318         } else {
1319                 return intel_get_buf_trans(&icl_mg_phy_trans_rbr_hbr,
1320                                            n_entries);
1321         }
1322 }
1323
1324 static const struct intel_ddi_buf_trans *
1325 icl_get_mg_buf_trans(struct intel_encoder *encoder,
1326                      const struct intel_crtc_state *crtc_state,
1327                      int *n_entries)
1328 {
1329         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1330                 return intel_get_buf_trans(&icl_mg_phy_trans_hdmi, n_entries);
1331         else
1332                 return icl_get_mg_buf_trans_dp(encoder, crtc_state, n_entries);
1333 }
1334
1335 static const struct intel_ddi_buf_trans *
1336 ehl_get_combo_buf_trans_edp(struct intel_encoder *encoder,
1337                             const struct intel_crtc_state *crtc_state,
1338                             int *n_entries)
1339 {
1340         if (crtc_state->port_clock > 270000)
1341                 return intel_get_buf_trans(&ehl_combo_phy_trans_edp_hbr2, n_entries);
1342         else
1343                 return intel_get_buf_trans(&icl_combo_phy_trans_edp_hbr2, n_entries);
1344 }
1345
1346 static const struct intel_ddi_buf_trans *
1347 ehl_get_combo_buf_trans(struct intel_encoder *encoder,
1348                         const struct intel_crtc_state *crtc_state,
1349                         int *n_entries)
1350 {
1351         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1352                 return intel_get_buf_trans(&icl_combo_phy_trans_hdmi, n_entries);
1353         else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) &&
1354                  use_edp_low_vswing(encoder))
1355                 return ehl_get_combo_buf_trans_edp(encoder, crtc_state, n_entries);
1356         else
1357                 return intel_get_buf_trans(&ehl_combo_phy_trans_dp, n_entries);
1358 }
1359
1360 static const struct intel_ddi_buf_trans *
1361 jsl_get_combo_buf_trans_edp(struct intel_encoder *encoder,
1362                             const struct intel_crtc_state *crtc_state,
1363                             int *n_entries)
1364 {
1365         if (crtc_state->port_clock > 270000)
1366                 return intel_get_buf_trans(&jsl_combo_phy_trans_edp_hbr2, n_entries);
1367         else
1368                 return intel_get_buf_trans(&jsl_combo_phy_trans_edp_hbr, n_entries);
1369 }
1370
1371 static const struct intel_ddi_buf_trans *
1372 jsl_get_combo_buf_trans(struct intel_encoder *encoder,
1373                         const struct intel_crtc_state *crtc_state,
1374                         int *n_entries)
1375 {
1376         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1377                 return intel_get_buf_trans(&icl_combo_phy_trans_hdmi, n_entries);
1378         else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP) &&
1379                  use_edp_low_vswing(encoder))
1380                 return jsl_get_combo_buf_trans_edp(encoder, crtc_state, n_entries);
1381         else
1382                 return intel_get_buf_trans(&icl_combo_phy_trans_dp_hbr2_edp_hbr3, n_entries);
1383 }
1384
1385 static const struct intel_ddi_buf_trans *
1386 tgl_get_combo_buf_trans_dp(struct intel_encoder *encoder,
1387                            const struct intel_crtc_state *crtc_state,
1388                            int *n_entries)
1389 {
1390         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1391
1392         if (crtc_state->port_clock > 270000) {
1393                 if (IS_TGL_UY(dev_priv)) {
1394                         return intel_get_buf_trans(&tgl_uy_combo_phy_trans_dp_hbr2,
1395                                                    n_entries);
1396                 } else {
1397                         return intel_get_buf_trans(&tgl_combo_phy_trans_dp_hbr2,
1398                                                    n_entries);
1399                 }
1400         } else {
1401                 return intel_get_buf_trans(&tgl_combo_phy_trans_dp_hbr,
1402                                            n_entries);
1403         }
1404 }
1405
1406 static const struct intel_ddi_buf_trans *
1407 tgl_get_combo_buf_trans_edp(struct intel_encoder *encoder,
1408                             const struct intel_crtc_state *crtc_state,
1409                             int *n_entries)
1410 {
1411         if (crtc_state->port_clock > 540000) {
1412                 return intel_get_buf_trans(&icl_combo_phy_trans_dp_hbr2_edp_hbr3,
1413                                            n_entries);
1414         } else if (use_edp_hobl(encoder)) {
1415                 return intel_get_buf_trans(&tgl_combo_phy_trans_edp_hbr2_hobl,
1416                                            n_entries);
1417         } else if (use_edp_low_vswing(encoder)) {
1418                 return intel_get_buf_trans(&icl_combo_phy_trans_edp_hbr2,
1419                                            n_entries);
1420         }
1421
1422         return tgl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
1423 }
1424
1425 static const struct intel_ddi_buf_trans *
1426 tgl_get_combo_buf_trans(struct intel_encoder *encoder,
1427                         const struct intel_crtc_state *crtc_state,
1428                         int *n_entries)
1429 {
1430         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1431                 return intel_get_buf_trans(&icl_combo_phy_trans_hdmi, n_entries);
1432         else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
1433                 return tgl_get_combo_buf_trans_edp(encoder, crtc_state, n_entries);
1434         else
1435                 return tgl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
1436 }
1437
1438 static const struct intel_ddi_buf_trans *
1439 dg1_get_combo_buf_trans_dp(struct intel_encoder *encoder,
1440                            const struct intel_crtc_state *crtc_state,
1441                            int *n_entries)
1442 {
1443         if (crtc_state->port_clock > 270000)
1444                 return intel_get_buf_trans(&dg1_combo_phy_trans_dp_hbr2_hbr3,
1445                                            n_entries);
1446         else
1447                 return intel_get_buf_trans(&dg1_combo_phy_trans_dp_rbr_hbr,
1448                                            n_entries);
1449 }
1450
1451 static const struct intel_ddi_buf_trans *
1452 dg1_get_combo_buf_trans_edp(struct intel_encoder *encoder,
1453                             const struct intel_crtc_state *crtc_state,
1454                             int *n_entries)
1455 {
1456         if (crtc_state->port_clock > 540000)
1457                 return intel_get_buf_trans(&icl_combo_phy_trans_dp_hbr2_edp_hbr3,
1458                                            n_entries);
1459         else if (use_edp_hobl(encoder))
1460                 return intel_get_buf_trans(&tgl_combo_phy_trans_edp_hbr2_hobl,
1461                                            n_entries);
1462         else if (use_edp_low_vswing(encoder))
1463                 return intel_get_buf_trans(&icl_combo_phy_trans_edp_hbr2,
1464                                            n_entries);
1465         else
1466                 return dg1_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
1467 }
1468
1469 static const struct intel_ddi_buf_trans *
1470 dg1_get_combo_buf_trans(struct intel_encoder *encoder,
1471                         const struct intel_crtc_state *crtc_state,
1472                         int *n_entries)
1473 {
1474         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1475                 return intel_get_buf_trans(&icl_combo_phy_trans_hdmi, n_entries);
1476         else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
1477                 return dg1_get_combo_buf_trans_edp(encoder, crtc_state, n_entries);
1478         else
1479                 return dg1_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
1480 }
1481
1482 static const struct intel_ddi_buf_trans *
1483 rkl_get_combo_buf_trans_dp(struct intel_encoder *encoder,
1484                            const struct intel_crtc_state *crtc_state,
1485                            int *n_entries)
1486 {
1487         if (crtc_state->port_clock > 270000)
1488                 return intel_get_buf_trans(&rkl_combo_phy_trans_dp_hbr2_hbr3, n_entries);
1489         else
1490                 return intel_get_buf_trans(&rkl_combo_phy_trans_dp_hbr, n_entries);
1491 }
1492
1493 static const struct intel_ddi_buf_trans *
1494 rkl_get_combo_buf_trans_edp(struct intel_encoder *encoder,
1495                             const struct intel_crtc_state *crtc_state,
1496                             int *n_entries)
1497 {
1498         if (crtc_state->port_clock > 540000) {
1499                 return intel_get_buf_trans(&icl_combo_phy_trans_dp_hbr2_edp_hbr3,
1500                                            n_entries);
1501         } else if (use_edp_hobl(encoder)) {
1502                 return intel_get_buf_trans(&tgl_combo_phy_trans_edp_hbr2_hobl,
1503                                            n_entries);
1504         } else if (use_edp_low_vswing(encoder)) {
1505                 return intel_get_buf_trans(&icl_combo_phy_trans_edp_hbr2,
1506                                            n_entries);
1507         }
1508
1509         return rkl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
1510 }
1511
1512 static const struct intel_ddi_buf_trans *
1513 rkl_get_combo_buf_trans(struct intel_encoder *encoder,
1514                         const struct intel_crtc_state *crtc_state,
1515                         int *n_entries)
1516 {
1517         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1518                 return intel_get_buf_trans(&icl_combo_phy_trans_hdmi, n_entries);
1519         else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
1520                 return rkl_get_combo_buf_trans_edp(encoder, crtc_state, n_entries);
1521         else
1522                 return rkl_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
1523 }
1524
1525 static const struct intel_ddi_buf_trans *
1526 adls_get_combo_buf_trans_dp(struct intel_encoder *encoder,
1527                             const struct intel_crtc_state *crtc_state,
1528                             int *n_entries)
1529 {
1530         if (crtc_state->port_clock > 270000)
1531                 return intel_get_buf_trans(&adls_combo_phy_trans_dp_hbr2_hbr3, n_entries);
1532         else
1533                 return intel_get_buf_trans(&tgl_combo_phy_trans_dp_hbr, n_entries);
1534 }
1535
1536 static const struct intel_ddi_buf_trans *
1537 adls_get_combo_buf_trans_edp(struct intel_encoder *encoder,
1538                              const struct intel_crtc_state *crtc_state,
1539                              int *n_entries)
1540 {
1541         if (crtc_state->port_clock > 540000)
1542                 return intel_get_buf_trans(&adls_combo_phy_trans_edp_hbr3, n_entries);
1543         else if (use_edp_hobl(encoder))
1544                 return intel_get_buf_trans(&tgl_combo_phy_trans_edp_hbr2_hobl, n_entries);
1545         else if (use_edp_low_vswing(encoder))
1546                 return intel_get_buf_trans(&adls_combo_phy_trans_edp_hbr2, n_entries);
1547         else
1548                 return adls_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
1549 }
1550
1551 static const struct intel_ddi_buf_trans *
1552 adls_get_combo_buf_trans(struct intel_encoder *encoder,
1553                          const struct intel_crtc_state *crtc_state,
1554                          int *n_entries)
1555 {
1556         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1557                 return intel_get_buf_trans(&icl_combo_phy_trans_hdmi, n_entries);
1558         else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
1559                 return adls_get_combo_buf_trans_edp(encoder, crtc_state, n_entries);
1560         else
1561                 return adls_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
1562 }
1563
1564 static const struct intel_ddi_buf_trans *
1565 adlp_get_combo_buf_trans_dp(struct intel_encoder *encoder,
1566                             const struct intel_crtc_state *crtc_state,
1567                             int *n_entries)
1568 {
1569         if (crtc_state->port_clock > 270000)
1570                 return intel_get_buf_trans(&adlp_combo_phy_trans_dp_hbr2_hbr3, n_entries);
1571         else
1572                 return intel_get_buf_trans(&adlp_combo_phy_trans_dp_hbr, n_entries);
1573 }
1574
1575 static const struct intel_ddi_buf_trans *
1576 adlp_get_combo_buf_trans_edp(struct intel_encoder *encoder,
1577                              const struct intel_crtc_state *crtc_state,
1578                              int *n_entries)
1579 {
1580         if (crtc_state->port_clock > 540000) {
1581                 return intel_get_buf_trans(&adlp_combo_phy_trans_edp_hbr3,
1582                                            n_entries);
1583         } else if (use_edp_hobl(encoder)) {
1584                 return intel_get_buf_trans(&tgl_combo_phy_trans_edp_hbr2_hobl,
1585                                            n_entries);
1586         } else if (use_edp_low_vswing(encoder)) {
1587                 return intel_get_buf_trans(&adlp_combo_phy_trans_edp_up_to_hbr2,
1588                                            n_entries);
1589         }
1590
1591         return adlp_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
1592 }
1593
1594 static const struct intel_ddi_buf_trans *
1595 adlp_get_combo_buf_trans(struct intel_encoder *encoder,
1596                          const struct intel_crtc_state *crtc_state,
1597                          int *n_entries)
1598 {
1599         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1600                 return intel_get_buf_trans(&icl_combo_phy_trans_hdmi, n_entries);
1601         else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
1602                 return adlp_get_combo_buf_trans_edp(encoder, crtc_state, n_entries);
1603         else
1604                 return adlp_get_combo_buf_trans_dp(encoder, crtc_state, n_entries);
1605 }
1606
1607 static const struct intel_ddi_buf_trans *
1608 tgl_get_dkl_buf_trans_dp(struct intel_encoder *encoder,
1609                          const struct intel_crtc_state *crtc_state,
1610                          int *n_entries)
1611 {
1612         if (crtc_state->port_clock > 270000) {
1613                 return intel_get_buf_trans(&tgl_dkl_phy_trans_dp_hbr2,
1614                                            n_entries);
1615         } else {
1616                 return intel_get_buf_trans(&tgl_dkl_phy_trans_dp_hbr,
1617                                            n_entries);
1618         }
1619 }
1620
1621 static const struct intel_ddi_buf_trans *
1622 tgl_get_dkl_buf_trans(struct intel_encoder *encoder,
1623                       const struct intel_crtc_state *crtc_state,
1624                       int *n_entries)
1625 {
1626         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1627                 return intel_get_buf_trans(&tgl_dkl_phy_trans_hdmi, n_entries);
1628         else
1629                 return tgl_get_dkl_buf_trans_dp(encoder, crtc_state, n_entries);
1630 }
1631
1632 static const struct intel_ddi_buf_trans *
1633 adlp_get_dkl_buf_trans_dp(struct intel_encoder *encoder,
1634                           const struct intel_crtc_state *crtc_state,
1635                           int *n_entries)
1636 {
1637         if (crtc_state->port_clock > 270000) {
1638                 return intel_get_buf_trans(&adlp_dkl_phy_trans_dp_hbr2_hbr3,
1639                                            n_entries);
1640         } else {
1641                 return intel_get_buf_trans(&adlp_dkl_phy_trans_dp_hbr,
1642                                            n_entries);
1643         }
1644 }
1645
1646 static const struct intel_ddi_buf_trans *
1647 adlp_get_dkl_buf_trans(struct intel_encoder *encoder,
1648                        const struct intel_crtc_state *crtc_state,
1649                        int *n_entries)
1650 {
1651         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1652                 return intel_get_buf_trans(&tgl_dkl_phy_trans_hdmi, n_entries);
1653         else
1654                 return adlp_get_dkl_buf_trans_dp(encoder, crtc_state, n_entries);
1655 }
1656
1657 static const struct intel_ddi_buf_trans *
1658 dg2_get_snps_buf_trans(struct intel_encoder *encoder,
1659                        const struct intel_crtc_state *crtc_state,
1660                        int *n_entries)
1661 {
1662         if (intel_crtc_has_dp_encoder(crtc_state) &&
1663             intel_dp_is_uhbr(crtc_state))
1664                 return intel_get_buf_trans(&dg2_snps_trans_uhbr, n_entries);
1665         else
1666                 return intel_get_buf_trans(&dg2_snps_trans, n_entries);
1667 }
1668
1669 static const struct intel_ddi_buf_trans *
1670 mtl_get_cx0_buf_trans(struct intel_encoder *encoder,
1671                       const struct intel_crtc_state *crtc_state,
1672                       int *n_entries)
1673 {
1674         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1675         enum phy phy = intel_port_to_phy(i915, encoder->port);
1676
1677         if (intel_crtc_has_dp_encoder(crtc_state) && crtc_state->port_clock >= 1000000)
1678                 return intel_get_buf_trans(&mtl_c20_trans_uhbr, n_entries);
1679         else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) && !(intel_is_c10phy(i915, phy)))
1680                 return intel_get_buf_trans(&mtl_c20_trans_hdmi, n_entries);
1681         else
1682                 return intel_get_buf_trans(&mtl_cx0_trans, n_entries);
1683 }
1684
1685 void intel_ddi_buf_trans_init(struct intel_encoder *encoder)
1686 {
1687         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1688         enum phy phy = intel_port_to_phy(i915, encoder->port);
1689
1690         if (DISPLAY_VER(i915) >= 14) {
1691                 encoder->get_buf_trans = mtl_get_cx0_buf_trans;
1692         } else if (IS_DG2(i915)) {
1693                 encoder->get_buf_trans = dg2_get_snps_buf_trans;
1694         } else if (IS_ALDERLAKE_P(i915)) {
1695                 if (intel_phy_is_combo(i915, phy))
1696                         encoder->get_buf_trans = adlp_get_combo_buf_trans;
1697                 else
1698                         encoder->get_buf_trans = adlp_get_dkl_buf_trans;
1699         } else if (IS_ALDERLAKE_S(i915)) {
1700                 encoder->get_buf_trans = adls_get_combo_buf_trans;
1701         } else if (IS_ROCKETLAKE(i915)) {
1702                 encoder->get_buf_trans = rkl_get_combo_buf_trans;
1703         } else if (IS_DG1(i915)) {
1704                 encoder->get_buf_trans = dg1_get_combo_buf_trans;
1705         } else if (DISPLAY_VER(i915) >= 12) {
1706                 if (intel_phy_is_combo(i915, phy))
1707                         encoder->get_buf_trans = tgl_get_combo_buf_trans;
1708                 else
1709                         encoder->get_buf_trans = tgl_get_dkl_buf_trans;
1710         } else if (DISPLAY_VER(i915) == 11) {
1711                 if (IS_PLATFORM(i915, INTEL_JASPERLAKE))
1712                         encoder->get_buf_trans = jsl_get_combo_buf_trans;
1713                 else if (IS_PLATFORM(i915, INTEL_ELKHARTLAKE))
1714                         encoder->get_buf_trans = ehl_get_combo_buf_trans;
1715                 else if (intel_phy_is_combo(i915, phy))
1716                         encoder->get_buf_trans = icl_get_combo_buf_trans;
1717                 else
1718                         encoder->get_buf_trans = icl_get_mg_buf_trans;
1719         } else if (IS_GEMINILAKE(i915) || IS_BROXTON(i915)) {
1720                 encoder->get_buf_trans = bxt_get_buf_trans;
1721         } else if (IS_CML_ULX(i915) || IS_CFL_ULX(i915) || IS_KBL_ULX(i915)) {
1722                 encoder->get_buf_trans = kbl_y_get_buf_trans;
1723         } else if (IS_CML_ULT(i915) || IS_CFL_ULT(i915) || IS_KBL_ULT(i915)) {
1724                 encoder->get_buf_trans = kbl_u_get_buf_trans;
1725         } else if (IS_COMETLAKE(i915) || IS_COFFEELAKE(i915) || IS_KABYLAKE(i915)) {
1726                 encoder->get_buf_trans = kbl_get_buf_trans;
1727         } else if (IS_SKL_ULX(i915)) {
1728                 encoder->get_buf_trans = skl_y_get_buf_trans;
1729         } else if (IS_SKL_ULT(i915)) {
1730                 encoder->get_buf_trans = skl_u_get_buf_trans;
1731         } else if (IS_SKYLAKE(i915)) {
1732                 encoder->get_buf_trans = skl_get_buf_trans;
1733         } else if (IS_BROADWELL(i915)) {
1734                 encoder->get_buf_trans = bdw_get_buf_trans;
1735         } else if (IS_HASWELL(i915)) {
1736                 encoder->get_buf_trans = hsw_get_buf_trans;
1737         } else {
1738                 MISSING_CASE(INTEL_INFO(i915)->platform);
1739         }
1740 }