drivers/gpu/drm/i915/display/intel_cdclk.c

   1 /*
   2  * Copyright © 2006-2017 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 #include <linux/time.h>
  25
  26 #include "hsw_ips.h"
  27 #include "i915_reg.h"
  28 #include "intel_atomic.h"
  29 #include "intel_atomic_plane.h"
  30 #include "intel_audio.h"
  31 #include "intel_bw.h"
  32 #include "intel_cdclk.h"
  33 #include "intel_crtc.h"
  34 #include "intel_de.h"
  35 #include "intel_display_types.h"
  36 #include "intel_mchbar_regs.h"
  37 #include "intel_pci_config.h"
  38 #include "intel_pcode.h"
  39 #include "intel_psr.h"
  40 #include "vlv_sideband.h"
  41
  42 /**
  43  * DOC: CDCLK / RAWCLK
  44  *
  45  * The display engine uses several different clocks to do its work. There
  46  * are two main clocks involved that aren't directly related to the actual
  47  * pixel clock or any symbol/bit clock of the actual output port. These
  48  * are the core display clock (CDCLK) and RAWCLK.
  49  *
  50  * CDCLK clocks most of the display pipe logic, and thus its frequency
  51  * must be high enough to support the rate at which pixels are flowing
  52  * through the pipes. Downscaling must also be accounted as that increases
  53  * the effective pixel rate.
  54  *
  55  * On several platforms the CDCLK frequency can be changed dynamically
  56  * to minimize power consumption for a given display configuration.
  57  * Typically changes to the CDCLK frequency require all the display pipes
  58  * to be shut down while the frequency is being changed.
  59  *
  60  * On SKL+ the DMC will toggle the CDCLK off/on during DC5/6 entry/exit.
  61  * DMC will not change the active CDCLK frequency however, so that part
  62  * will still be performed by the driver directly.
  63  *
  64  * RAWCLK is a fixed frequency clock, often used by various auxiliary
  65  * blocks such as AUX CH or backlight PWM. Hence the only thing we
  66  * really need to know about RAWCLK is its frequency so that various
  67  * dividers can be programmed correctly.
  68  */
  69
  70 struct intel_cdclk_funcs {
  71         void (*get_cdclk)(struct drm_i915_private *i915,
  72                           struct intel_cdclk_config *cdclk_config);
  73         void (*set_cdclk)(struct drm_i915_private *i915,
  74                           const struct intel_cdclk_config *cdclk_config,
  75                           enum pipe pipe);
  76         int (*modeset_calc_cdclk)(struct intel_cdclk_state *state);
  77         u8 (*calc_voltage_level)(int cdclk);
  78 };
  79
  80 void intel_cdclk_get_cdclk(struct drm_i915_private *dev_priv,
  81                            struct intel_cdclk_config *cdclk_config)
  82 {
  83         dev_priv->display.funcs.cdclk->get_cdclk(dev_priv, cdclk_config);
  84 }
  85
  86 static void intel_cdclk_set_cdclk(struct drm_i915_private *dev_priv,
  87                                   const struct intel_cdclk_config *cdclk_config,
  88                                   enum pipe pipe)
  89 {
  90         dev_priv->display.funcs.cdclk->set_cdclk(dev_priv, cdclk_config, pipe);
  91 }
  92
  93 static int intel_cdclk_modeset_calc_cdclk(struct drm_i915_private *dev_priv,
  94                                           struct intel_cdclk_state *cdclk_config)
  95 {
  96         return dev_priv->display.funcs.cdclk->modeset_calc_cdclk(cdclk_config);
  97 }
  98
  99 static u8 intel_cdclk_calc_voltage_level(struct drm_i915_private *dev_priv,
 100                                          int cdclk)
 101 {
 102         return dev_priv->display.funcs.cdclk->calc_voltage_level(cdclk);
 103 }
 104
 105 static void fixed_133mhz_get_cdclk(struct drm_i915_private *dev_priv,
 106                                    struct intel_cdclk_config *cdclk_config)
 107 {
 108         cdclk_config->cdclk = 133333;
 109 }
 110
 111 static void fixed_200mhz_get_cdclk(struct drm_i915_private *dev_priv,
 112                                    struct intel_cdclk_config *cdclk_config)
 113 {
 114         cdclk_config->cdclk = 200000;
 115 }
 116
 117 static void fixed_266mhz_get_cdclk(struct drm_i915_private *dev_priv,
 118                                    struct intel_cdclk_config *cdclk_config)
 119 {
 120         cdclk_config->cdclk = 266667;
 121 }
 122
 123 static void fixed_333mhz_get_cdclk(struct drm_i915_private *dev_priv,
 124                                    struct intel_cdclk_config *cdclk_config)
 125 {
 126         cdclk_config->cdclk = 333333;
 127 }
 128
 129 static void fixed_400mhz_get_cdclk(struct drm_i915_private *dev_priv,
 130                                    struct intel_cdclk_config *cdclk_config)
 131 {
 132         cdclk_config->cdclk = 400000;
 133 }
 134
 135 static void fixed_450mhz_get_cdclk(struct drm_i915_private *dev_priv,
 136                                    struct intel_cdclk_config *cdclk_config)
 137 {
 138         cdclk_config->cdclk = 450000;
 139 }
 140
 141 static void i85x_get_cdclk(struct drm_i915_private *dev_priv,
 142                            struct intel_cdclk_config *cdclk_config)
 143 {
 144         struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
 145         u16 hpllcc = 0;
 146
 147         /*
 148          * 852GM/852GMV only supports 133 MHz and the HPLLCC
 149          * encoding is different :(
 150          * FIXME is this the right way to detect 852GM/852GMV?
 151          */
 152         if (pdev->revision == 0x1) {
 153                 cdclk_config->cdclk = 133333;
 154                 return;
 155         }
 156
 157         pci_bus_read_config_word(pdev->bus,
 158                                  PCI_DEVFN(0, 3), HPLLCC, &hpllcc);
 159
 160         /* Assume that the hardware is in the high speed state.  This
 161          * should be the default.
 162          */
 163         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
 164         case GC_CLOCK_133_200:
 165         case GC_CLOCK_133_200_2:
 166         case GC_CLOCK_100_200:
 167                 cdclk_config->cdclk = 200000;
 168                 break;
 169         case GC_CLOCK_166_250:
 170                 cdclk_config->cdclk = 250000;
 171                 break;
 172         case GC_CLOCK_100_133:
 173                 cdclk_config->cdclk = 133333;
 174                 break;
 175         case GC_CLOCK_133_266:
 176         case GC_CLOCK_133_266_2:
 177         case GC_CLOCK_166_266:
 178                 cdclk_config->cdclk = 266667;
 179                 break;
 180         }
 181 }
 182
 183 static void i915gm_get_cdclk(struct drm_i915_private *dev_priv,
 184                              struct intel_cdclk_config *cdclk_config)
 185 {
 186         struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
 187         u16 gcfgc = 0;
 188
 189         pci_read_config_word(pdev, GCFGC, &gcfgc);
 190
 191         if (gcfgc & GC_LOW_FREQUENCY_ENABLE) {
 192                 cdclk_config->cdclk = 133333;
 193                 return;
 194         }
 195
 196         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
 197         case GC_DISPLAY_CLOCK_333_320_MHZ:
 198                 cdclk_config->cdclk = 333333;
 199                 break;
 200         default:
 201         case GC_DISPLAY_CLOCK_190_200_MHZ:
 202                 cdclk_config->cdclk = 190000;
 203                 break;
 204         }
 205 }
 206
 207 static void i945gm_get_cdclk(struct drm_i915_private *dev_priv,
 208                              struct intel_cdclk_config *cdclk_config)
 209 {
 210         struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
 211         u16 gcfgc = 0;
 212
 213         pci_read_config_word(pdev, GCFGC, &gcfgc);
 214
 215         if (gcfgc & GC_LOW_FREQUENCY_ENABLE) {
 216                 cdclk_config->cdclk = 133333;
 217                 return;
 218         }
 219
 220         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
 221         case GC_DISPLAY_CLOCK_333_320_MHZ:
 222                 cdclk_config->cdclk = 320000;
 223                 break;
 224         default:
 225         case GC_DISPLAY_CLOCK_190_200_MHZ:
 226                 cdclk_config->cdclk = 200000;
 227                 break;
 228         }
 229 }
 230
 231 static unsigned int intel_hpll_vco(struct drm_i915_private *dev_priv)
 232 {
 233         static const unsigned int blb_vco[8] = {
 234                 [0] = 3200000,
 235                 [1] = 4000000,
 236                 [2] = 5333333,
 237                 [3] = 4800000,
 238                 [4] = 6400000,
 239         };
 240         static const unsigned int pnv_vco[8] = {
 241                 [0] = 3200000,
 242                 [1] = 4000000,
 243                 [2] = 5333333,
 244                 [3] = 4800000,
 245                 [4] = 2666667,
 246         };
 247         static const unsigned int cl_vco[8] = {
 248                 [0] = 3200000,
 249                 [1] = 4000000,
 250                 [2] = 5333333,
 251                 [3] = 6400000,
 252                 [4] = 3333333,
 253                 [5] = 3566667,
 254                 [6] = 4266667,
 255         };
 256         static const unsigned int elk_vco[8] = {
 257                 [0] = 3200000,
 258                 [1] = 4000000,
 259                 [2] = 5333333,
 260                 [3] = 4800000,
 261         };
 262         static const unsigned int ctg_vco[8] = {
 263                 [0] = 3200000,
 264                 [1] = 4000000,
 265                 [2] = 5333333,
 266                 [3] = 6400000,
 267                 [4] = 2666667,
 268                 [5] = 4266667,
 269         };
 270         const unsigned int *vco_table;
 271         unsigned int vco;
 272         u8 tmp = 0;
 273
 274         /* FIXME other chipsets? */
 275         if (IS_GM45(dev_priv))
 276                 vco_table = ctg_vco;
 277         else if (IS_G45(dev_priv))
 278                 vco_table = elk_vco;
 279         else if (IS_I965GM(dev_priv))
 280                 vco_table = cl_vco;
 281         else if (IS_PINEVIEW(dev_priv))
 282                 vco_table = pnv_vco;
 283         else if (IS_G33(dev_priv))
 284                 vco_table = blb_vco;
 285         else
 286                 return 0;
 287
 288         tmp = intel_de_read(dev_priv,
 289                             IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv) ? HPLLVCO_MOBILE : HPLLVCO);
 290
 291         vco = vco_table[tmp & 0x7];
 292         if (vco == 0)
 293                 drm_err(&dev_priv->drm, "Bad HPLL VCO (HPLLVCO=0x%02x)\n",
 294                         tmp);
 295         else
 296                 drm_dbg_kms(&dev_priv->drm, "HPLL VCO %u kHz\n", vco);
 297
 298         return vco;
 299 }
 300
 301 static void g33_get_cdclk(struct drm_i915_private *dev_priv,
 302                           struct intel_cdclk_config *cdclk_config)
 303 {
 304         struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
 305         static const u8 div_3200[] = { 12, 10,  8,  7, 5, 16 };
 306         static const u8 div_4000[] = { 14, 12, 10,  8, 6, 20 };
 307         static const u8 div_4800[] = { 20, 14, 12, 10, 8, 24 };
 308         static const u8 div_5333[] = { 20, 16, 12, 12, 8, 28 };
 309         const u8 *div_table;
 310         unsigned int cdclk_sel;
 311         u16 tmp = 0;
 312
 313         cdclk_config->vco = intel_hpll_vco(dev_priv);
 314
 315         pci_read_config_word(pdev, GCFGC, &tmp);
 316
 317         cdclk_sel = (tmp >> 4) & 0x7;
 318
 319         if (cdclk_sel >= ARRAY_SIZE(div_3200))
 320                 goto fail;
 321
 322         switch (cdclk_config->vco) {
 323         case 3200000:
 324                 div_table = div_3200;
 325                 break;
 326         case 4000000:
 327                 div_table = div_4000;
 328                 break;
 329         case 4800000:
 330                 div_table = div_4800;
 331                 break;
 332         case 5333333:
 333                 div_table = div_5333;
 334                 break;
 335         default:
 336                 goto fail;
 337         }
 338
 339         cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco,
 340                                                 div_table[cdclk_sel]);
 341         return;
 342
 343 fail:
 344         drm_err(&dev_priv->drm,
 345                 "Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%08x\n",
 346                 cdclk_config->vco, tmp);
 347         cdclk_config->cdclk = 190476;
 348 }
 349
 350 static void pnv_get_cdclk(struct drm_i915_private *dev_priv,
 351                           struct intel_cdclk_config *cdclk_config)
 352 {
 353         struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
 354         u16 gcfgc = 0;
 355
 356         pci_read_config_word(pdev, GCFGC, &gcfgc);
 357
 358         switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
 359         case GC_DISPLAY_CLOCK_267_MHZ_PNV:
 360                 cdclk_config->cdclk = 266667;
 361                 break;
 362         case GC_DISPLAY_CLOCK_333_MHZ_PNV:
 363                 cdclk_config->cdclk = 333333;
 364                 break;
 365         case GC_DISPLAY_CLOCK_444_MHZ_PNV:
 366                 cdclk_config->cdclk = 444444;
 367                 break;
 368         case GC_DISPLAY_CLOCK_200_MHZ_PNV:
 369                 cdclk_config->cdclk = 200000;
 370                 break;
 371         default:
 372                 drm_err(&dev_priv->drm,
 373                         "Unknown pnv display core clock 0x%04x\n", gcfgc);
 374                 fallthrough;
 375         case GC_DISPLAY_CLOCK_133_MHZ_PNV:
 376                 cdclk_config->cdclk = 133333;
 377                 break;
 378         case GC_DISPLAY_CLOCK_167_MHZ_PNV:
 379                 cdclk_config->cdclk = 166667;
 380                 break;
 381         }
 382 }
 383
 384 static void i965gm_get_cdclk(struct drm_i915_private *dev_priv,
 385                              struct intel_cdclk_config *cdclk_config)
 386 {
 387         struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
 388         static const u8 div_3200[] = { 16, 10,  8 };
 389         static const u8 div_4000[] = { 20, 12, 10 };
 390         static const u8 div_5333[] = { 24, 16, 14 };
 391         const u8 *div_table;
 392         unsigned int cdclk_sel;
 393         u16 tmp = 0;
 394
 395         cdclk_config->vco = intel_hpll_vco(dev_priv);
 396
 397         pci_read_config_word(pdev, GCFGC, &tmp);
 398
 399         cdclk_sel = ((tmp >> 8) & 0x1f) - 1;
 400
 401         if (cdclk_sel >= ARRAY_SIZE(div_3200))
 402                 goto fail;
 403
 404         switch (cdclk_config->vco) {
 405         case 3200000:
 406                 div_table = div_3200;
 407                 break;
 408         case 4000000:
 409                 div_table = div_4000;
 410                 break;
 411         case 5333333:
 412                 div_table = div_5333;
 413                 break;
 414         default:
 415                 goto fail;
 416         }
 417
 418         cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco,
 419                                                 div_table[cdclk_sel]);
 420         return;
 421
 422 fail:
 423         drm_err(&dev_priv->drm,
 424                 "Unable to determine CDCLK. HPLL VCO=%u kHz, CFGC=0x%04x\n",
 425                 cdclk_config->vco, tmp);
 426         cdclk_config->cdclk = 200000;
 427 }
 428
 429 static void gm45_get_cdclk(struct drm_i915_private *dev_priv,
 430                            struct intel_cdclk_config *cdclk_config)
 431 {
 432         struct pci_dev *pdev = to_pci_dev(dev_priv->drm.dev);
 433         unsigned int cdclk_sel;
 434         u16 tmp = 0;
 435
 436         cdclk_config->vco = intel_hpll_vco(dev_priv);
 437
 438         pci_read_config_word(pdev, GCFGC, &tmp);
 439
 440         cdclk_sel = (tmp >> 12) & 0x1;
 441
 442         switch (cdclk_config->vco) {
 443         case 2666667:
 444         case 4000000:
 445         case 5333333:
 446                 cdclk_config->cdclk = cdclk_sel ? 333333 : 222222;
 447                 break;
 448         case 3200000:
 449                 cdclk_config->cdclk = cdclk_sel ? 320000 : 228571;
 450                 break;
 451         default:
 452                 drm_err(&dev_priv->drm,
 453                         "Unable to determine CDCLK. HPLL VCO=%u, CFGC=0x%04x\n",
 454                         cdclk_config->vco, tmp);
 455                 cdclk_config->cdclk = 222222;
 456                 break;
 457         }
 458 }
 459
 460 static void hsw_get_cdclk(struct drm_i915_private *dev_priv,
 461                           struct intel_cdclk_config *cdclk_config)
 462 {
 463         u32 lcpll = intel_de_read(dev_priv, LCPLL_CTL);
 464         u32 freq = lcpll & LCPLL_CLK_FREQ_MASK;
 465
 466         if (lcpll & LCPLL_CD_SOURCE_FCLK)
 467                 cdclk_config->cdclk = 800000;
 468         else if (intel_de_read(dev_priv, FUSE_STRAP) & HSW_CDCLK_LIMIT)
 469                 cdclk_config->cdclk = 450000;
 470         else if (freq == LCPLL_CLK_FREQ_450)
 471                 cdclk_config->cdclk = 450000;
 472         else if (IS_HSW_ULT(dev_priv))
 473                 cdclk_config->cdclk = 337500;
 474         else
 475                 cdclk_config->cdclk = 540000;
 476 }
 477
 478 static int vlv_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk)
 479 {
 480         int freq_320 = (dev_priv->hpll_freq <<  1) % 320000 != 0 ?
 481                 333333 : 320000;
 482
 483         /*
 484          * We seem to get an unstable or solid color picture at 200MHz.
 485          * Not sure what's wrong. For now use 200MHz only when all pipes
 486          * are off.
 487          */
 488         if (IS_VALLEYVIEW(dev_priv) && min_cdclk > freq_320)
 489                 return 400000;
 490         else if (min_cdclk > 266667)
 491                 return freq_320;
 492         else if (min_cdclk > 0)
 493                 return 266667;
 494         else
 495                 return 200000;
 496 }
 497
 498 static u8 vlv_calc_voltage_level(struct drm_i915_private *dev_priv, int cdclk)
 499 {
 500         if (IS_VALLEYVIEW(dev_priv)) {
 501                 if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
 502                         return 2;
 503                 else if (cdclk >= 266667)
 504                         return 1;
 505                 else
 506                         return 0;
 507         } else {
 508                 /*
 509                  * Specs are full of misinformation, but testing on actual
 510                  * hardware has shown that we just need to write the desired
 511                  * CCK divider into the Punit register.
 512                  */
 513                 return DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1, cdclk) - 1;
 514         }
 515 }
 516
 517 static void vlv_get_cdclk(struct drm_i915_private *dev_priv,
 518                           struct intel_cdclk_config *cdclk_config)
 519 {
 520         u32 val;
 521
 522         vlv_iosf_sb_get(dev_priv,
 523                         BIT(VLV_IOSF_SB_CCK) | BIT(VLV_IOSF_SB_PUNIT));
 524
 525         cdclk_config->vco = vlv_get_hpll_vco(dev_priv);
 526         cdclk_config->cdclk = vlv_get_cck_clock(dev_priv, "cdclk",
 527                                                 CCK_DISPLAY_CLOCK_CONTROL,
 528                                                 cdclk_config->vco);
 529
 530         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM);
 531
 532         vlv_iosf_sb_put(dev_priv,
 533                         BIT(VLV_IOSF_SB_CCK) | BIT(VLV_IOSF_SB_PUNIT));
 534
 535         if (IS_VALLEYVIEW(dev_priv))
 536                 cdclk_config->voltage_level = (val & DSPFREQGUAR_MASK) >>
 537                         DSPFREQGUAR_SHIFT;
 538         else
 539                 cdclk_config->voltage_level = (val & DSPFREQGUAR_MASK_CHV) >>
 540                         DSPFREQGUAR_SHIFT_CHV;
 541 }
 542
 543 static void vlv_program_pfi_credits(struct drm_i915_private *dev_priv)
 544 {
 545         unsigned int credits, default_credits;
 546
 547         if (IS_CHERRYVIEW(dev_priv))
 548                 default_credits = PFI_CREDIT(12);
 549         else
 550                 default_credits = PFI_CREDIT(8);
 551
 552         if (dev_priv->display.cdclk.hw.cdclk >= dev_priv->czclk_freq) {
 553                 /* CHV suggested value is 31 or 63 */
 554                 if (IS_CHERRYVIEW(dev_priv))
 555                         credits = PFI_CREDIT_63;
 556                 else
 557                         credits = PFI_CREDIT(15);
 558         } else {
 559                 credits = default_credits;
 560         }
 561
 562         /*
 563          * WA - write default credits before re-programming
 564          * FIXME: should we also set the resend bit here?
 565          */
 566         intel_de_write(dev_priv, GCI_CONTROL,
 567                        VGA_FAST_MODE_DISABLE | default_credits);
 568
 569         intel_de_write(dev_priv, GCI_CONTROL,
 570                        VGA_FAST_MODE_DISABLE | credits | PFI_CREDIT_RESEND);
 571
 572         /*
 573          * FIXME is this guaranteed to clear
 574          * immediately or should we poll for it?
 575          */
 576         drm_WARN_ON(&dev_priv->drm,
 577                     intel_de_read(dev_priv, GCI_CONTROL) & PFI_CREDIT_RESEND);
 578 }
 579
 580 static void vlv_set_cdclk(struct drm_i915_private *dev_priv,
 581                           const struct intel_cdclk_config *cdclk_config,
 582                           enum pipe pipe)
 583 {
 584         int cdclk = cdclk_config->cdclk;
 585         u32 val, cmd = cdclk_config->voltage_level;
 586         intel_wakeref_t wakeref;
 587
 588         switch (cdclk) {
 589         case 400000:
 590         case 333333:
 591         case 320000:
 592         case 266667:
 593         case 200000:
 594                 break;
 595         default:
 596                 MISSING_CASE(cdclk);
 597                 return;
 598         }
 599
 600         /* There are cases where we can end up here with power domains
 601          * off and a CDCLK frequency other than the minimum, like when
 602          * issuing a modeset without actually changing any display after
 603          * a system suspend.  So grab the display core domain, which covers
 604          * the HW blocks needed for the following programming.
 605          */
 606         wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_DISPLAY_CORE);
 607
 608         vlv_iosf_sb_get(dev_priv,
 609                         BIT(VLV_IOSF_SB_CCK) |
 610                         BIT(VLV_IOSF_SB_BUNIT) |
 611                         BIT(VLV_IOSF_SB_PUNIT));
 612
 613         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM);
 614         val &= ~DSPFREQGUAR_MASK;
 615         val |= (cmd << DSPFREQGUAR_SHIFT);
 616         vlv_punit_write(dev_priv, PUNIT_REG_DSPSSPM, val);
 617         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) &
 618                       DSPFREQSTAT_MASK) == (cmd << DSPFREQSTAT_SHIFT),
 619                      50)) {
 620                 drm_err(&dev_priv->drm,
 621                         "timed out waiting for CDclk change\n");
 622         }
 623
 624         if (cdclk == 400000) {
 625                 u32 divider;
 626
 627                 divider = DIV_ROUND_CLOSEST(dev_priv->hpll_freq << 1,
 628                                             cdclk) - 1;
 629
 630                 /* adjust cdclk divider */
 631                 val = vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL);
 632                 val &= ~CCK_FREQUENCY_VALUES;
 633                 val |= divider;
 634                 vlv_cck_write(dev_priv, CCK_DISPLAY_CLOCK_CONTROL, val);
 635
 636                 if (wait_for((vlv_cck_read(dev_priv, CCK_DISPLAY_CLOCK_CONTROL) &
 637                               CCK_FREQUENCY_STATUS) == (divider << CCK_FREQUENCY_STATUS_SHIFT),
 638                              50))
 639                         drm_err(&dev_priv->drm,
 640                                 "timed out waiting for CDclk change\n");
 641         }
 642
 643         /* adjust self-refresh exit latency value */
 644         val = vlv_bunit_read(dev_priv, BUNIT_REG_BISOC);
 645         val &= ~0x7f;
 646
 647         /*
 648          * For high bandwidth configs, we set a higher latency in the bunit
 649          * so that the core display fetch happens in time to avoid underruns.
 650          */
 651         if (cdclk == 400000)
 652                 val |= 4500 / 250; /* 4.5 usec */
 653         else
 654                 val |= 3000 / 250; /* 3.0 usec */
 655         vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
 656
 657         vlv_iosf_sb_put(dev_priv,
 658                         BIT(VLV_IOSF_SB_CCK) |
 659                         BIT(VLV_IOSF_SB_BUNIT) |
 660                         BIT(VLV_IOSF_SB_PUNIT));
 661
 662         intel_update_cdclk(dev_priv);
 663
 664         vlv_program_pfi_credits(dev_priv);
 665
 666         intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref);
 667 }
 668
 669 static void chv_set_cdclk(struct drm_i915_private *dev_priv,
 670                           const struct intel_cdclk_config *cdclk_config,
 671                           enum pipe pipe)
 672 {
 673         int cdclk = cdclk_config->cdclk;
 674         u32 val, cmd = cdclk_config->voltage_level;
 675         intel_wakeref_t wakeref;
 676
 677         switch (cdclk) {
 678         case 333333:
 679         case 320000:
 680         case 266667:
 681         case 200000:
 682                 break;
 683         default:
 684                 MISSING_CASE(cdclk);
 685                 return;
 686         }
 687
 688         /* There are cases where we can end up here with power domains
 689          * off and a CDCLK frequency other than the minimum, like when
 690          * issuing a modeset without actually changing any display after
 691          * a system suspend.  So grab the display core domain, which covers
 692          * the HW blocks needed for the following programming.
 693          */
 694         wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_DISPLAY_CORE);
 695
 696         vlv_punit_get(dev_priv);
 697         val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM);
 698         val &= ~DSPFREQGUAR_MASK_CHV;
 699         val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
 700         vlv_punit_write(dev_priv, PUNIT_REG_DSPSSPM, val);
 701         if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) &
 702                       DSPFREQSTAT_MASK_CHV) == (cmd << DSPFREQSTAT_SHIFT_CHV),
 703                      50)) {
 704                 drm_err(&dev_priv->drm,
 705                         "timed out waiting for CDclk change\n");
 706         }
 707
 708         vlv_punit_put(dev_priv);
 709
 710         intel_update_cdclk(dev_priv);
 711
 712         vlv_program_pfi_credits(dev_priv);
 713
 714         intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref);
 715 }
 716
 717 static int bdw_calc_cdclk(int min_cdclk)
 718 {
 719         if (min_cdclk > 540000)
 720                 return 675000;
 721         else if (min_cdclk > 450000)
 722                 return 540000;
 723         else if (min_cdclk > 337500)
 724                 return 450000;
 725         else
 726                 return 337500;
 727 }
 728
 729 static u8 bdw_calc_voltage_level(int cdclk)
 730 {
 731         switch (cdclk) {
 732         default:
 733         case 337500:
 734                 return 2;
 735         case 450000:
 736                 return 0;
 737         case 540000:
 738                 return 1;
 739         case 675000:
 740                 return 3;
 741         }
 742 }
 743
 744 static void bdw_get_cdclk(struct drm_i915_private *dev_priv,
 745                           struct intel_cdclk_config *cdclk_config)
 746 {
 747         u32 lcpll = intel_de_read(dev_priv, LCPLL_CTL);
 748         u32 freq = lcpll & LCPLL_CLK_FREQ_MASK;
 749
 750         if (lcpll & LCPLL_CD_SOURCE_FCLK)
 751                 cdclk_config->cdclk = 800000;
 752         else if (intel_de_read(dev_priv, FUSE_STRAP) & HSW_CDCLK_LIMIT)
 753                 cdclk_config->cdclk = 450000;
 754         else if (freq == LCPLL_CLK_FREQ_450)
 755                 cdclk_config->cdclk = 450000;
 756         else if (freq == LCPLL_CLK_FREQ_54O_BDW)
 757                 cdclk_config->cdclk = 540000;
 758         else if (freq == LCPLL_CLK_FREQ_337_5_BDW)
 759                 cdclk_config->cdclk = 337500;
 760         else
 761                 cdclk_config->cdclk = 675000;
 762
 763         /*
 764          * Can't read this out :( Let's assume it's
 765          * at least what the CDCLK frequency requires.
 766          */
 767         cdclk_config->voltage_level =
 768                 bdw_calc_voltage_level(cdclk_config->cdclk);
 769 }
 770
 771 static u32 bdw_cdclk_freq_sel(int cdclk)
 772 {
 773         switch (cdclk) {
 774         default:
 775                 MISSING_CASE(cdclk);
 776                 fallthrough;
 777         case 337500:
 778                 return LCPLL_CLK_FREQ_337_5_BDW;
 779         case 450000:
 780                 return LCPLL_CLK_FREQ_450;
 781         case 540000:
 782                 return LCPLL_CLK_FREQ_54O_BDW;
 783         case 675000:
 784                 return LCPLL_CLK_FREQ_675_BDW;
 785         }
 786 }
 787
 788 static void bdw_set_cdclk(struct drm_i915_private *dev_priv,
 789                           const struct intel_cdclk_config *cdclk_config,
 790                           enum pipe pipe)
 791 {
 792         int cdclk = cdclk_config->cdclk;
 793         int ret;
 794
 795         if (drm_WARN(&dev_priv->drm,
 796                      (intel_de_read(dev_priv, LCPLL_CTL) &
 797                       (LCPLL_PLL_DISABLE | LCPLL_PLL_LOCK |
 798                        LCPLL_CD_CLOCK_DISABLE | LCPLL_ROOT_CD_CLOCK_DISABLE |
 799                        LCPLL_CD2X_CLOCK_DISABLE | LCPLL_POWER_DOWN_ALLOW |
 800                        LCPLL_CD_SOURCE_FCLK)) != LCPLL_PLL_LOCK,
 801                      "trying to change cdclk frequency with cdclk not enabled\n"))
 802                 return;
 803
 804         ret = snb_pcode_write(&dev_priv->uncore, BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
 805         if (ret) {
 806                 drm_err(&dev_priv->drm,
 807                         "failed to inform pcode about cdclk change\n");
 808                 return;
 809         }
 810
 811         intel_de_rmw(dev_priv, LCPLL_CTL,
 812                      0, LCPLL_CD_SOURCE_FCLK);
 813
 814         /*
 815          * According to the spec, it should be enough to poll for this 1 us.
 816          * However, extensive testing shows that this can take longer.
 817          */
 818         if (wait_for_us(intel_de_read(dev_priv, LCPLL_CTL) &
 819                         LCPLL_CD_SOURCE_FCLK_DONE, 100))
 820                 drm_err(&dev_priv->drm, "Switching to FCLK failed\n");
 821
 822         intel_de_rmw(dev_priv, LCPLL_CTL,
 823                      LCPLL_CLK_FREQ_MASK, bdw_cdclk_freq_sel(cdclk));
 824
 825         intel_de_rmw(dev_priv, LCPLL_CTL,
 826                      LCPLL_CD_SOURCE_FCLK, 0);
 827
 828         if (wait_for_us((intel_de_read(dev_priv, LCPLL_CTL) &
 829                          LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
 830                 drm_err(&dev_priv->drm, "Switching back to LCPLL failed\n");
 831
 832         snb_pcode_write(&dev_priv->uncore, HSW_PCODE_DE_WRITE_FREQ_REQ,
 833                         cdclk_config->voltage_level);
 834
 835         intel_de_write(dev_priv, CDCLK_FREQ,
 836                        DIV_ROUND_CLOSEST(cdclk, 1000) - 1);
 837
 838         intel_update_cdclk(dev_priv);
 839 }
 840
 841 static int skl_calc_cdclk(int min_cdclk, int vco)
 842 {
 843         if (vco == 8640000) {
 844                 if (min_cdclk > 540000)
 845                         return 617143;
 846                 else if (min_cdclk > 432000)
 847                         return 540000;
 848                 else if (min_cdclk > 308571)
 849                         return 432000;
 850                 else
 851                         return 308571;
 852         } else {
 853                 if (min_cdclk > 540000)
 854                         return 675000;
 855                 else if (min_cdclk > 450000)
 856                         return 540000;
 857                 else if (min_cdclk > 337500)
 858                         return 450000;
 859                 else
 860                         return 337500;
 861         }
 862 }
 863
 864 static u8 skl_calc_voltage_level(int cdclk)
 865 {
 866         if (cdclk > 540000)
 867                 return 3;
 868         else if (cdclk > 450000)
 869                 return 2;
 870         else if (cdclk > 337500)
 871                 return 1;
 872         else
 873                 return 0;
 874 }
 875
 876 static void skl_dpll0_update(struct drm_i915_private *dev_priv,
 877                              struct intel_cdclk_config *cdclk_config)
 878 {
 879         u32 val;
 880
 881         cdclk_config->ref = 24000;
 882         cdclk_config->vco = 0;
 883
 884         val = intel_de_read(dev_priv, LCPLL1_CTL);
 885         if ((val & LCPLL_PLL_ENABLE) == 0)
 886                 return;
 887
 888         if (drm_WARN_ON(&dev_priv->drm, (val & LCPLL_PLL_LOCK) == 0))
 889                 return;
 890
 891         val = intel_de_read(dev_priv, DPLL_CTRL1);
 892
 893         if (drm_WARN_ON(&dev_priv->drm,
 894                         (val & (DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) |
 895                                 DPLL_CTRL1_SSC(SKL_DPLL0) |
 896                                 DPLL_CTRL1_OVERRIDE(SKL_DPLL0))) !=
 897                         DPLL_CTRL1_OVERRIDE(SKL_DPLL0)))
 898                 return;
 899
 900         switch (val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) {
 901         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0):
 902         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, SKL_DPLL0):
 903         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, SKL_DPLL0):
 904         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, SKL_DPLL0):
 905                 cdclk_config->vco = 8100000;
 906                 break;
 907         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0):
 908         case DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, SKL_DPLL0):
 909                 cdclk_config->vco = 8640000;
 910                 break;
 911         default:
 912                 MISSING_CASE(val & DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0));
 913                 break;
 914         }
 915 }
 916
 917 static void skl_get_cdclk(struct drm_i915_private *dev_priv,
 918                           struct intel_cdclk_config *cdclk_config)
 919 {
 920         u32 cdctl;
 921
 922         skl_dpll0_update(dev_priv, cdclk_config);
 923
 924         cdclk_config->cdclk = cdclk_config->bypass = cdclk_config->ref;
 925
 926         if (cdclk_config->vco == 0)
 927                 goto out;
 928
 929         cdctl = intel_de_read(dev_priv, CDCLK_CTL);
 930
 931         if (cdclk_config->vco == 8640000) {
 932                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
 933                 case CDCLK_FREQ_450_432:
 934                         cdclk_config->cdclk = 432000;
 935                         break;
 936                 case CDCLK_FREQ_337_308:
 937                         cdclk_config->cdclk = 308571;
 938                         break;
 939                 case CDCLK_FREQ_540:
 940                         cdclk_config->cdclk = 540000;
 941                         break;
 942                 case CDCLK_FREQ_675_617:
 943                         cdclk_config->cdclk = 617143;
 944                         break;
 945                 default:
 946                         MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
 947                         break;
 948                 }
 949         } else {
 950                 switch (cdctl & CDCLK_FREQ_SEL_MASK) {
 951                 case CDCLK_FREQ_450_432:
 952                         cdclk_config->cdclk = 450000;
 953                         break;
 954                 case CDCLK_FREQ_337_308:
 955                         cdclk_config->cdclk = 337500;
 956                         break;
 957                 case CDCLK_FREQ_540:
 958                         cdclk_config->cdclk = 540000;
 959                         break;
 960                 case CDCLK_FREQ_675_617:
 961                         cdclk_config->cdclk = 675000;
 962                         break;
 963                 default:
 964                         MISSING_CASE(cdctl & CDCLK_FREQ_SEL_MASK);
 965                         break;
 966                 }
 967         }
 968
 969  out:
 970         /*
 971          * Can't read this out :( Let's assume it's
 972          * at least what the CDCLK frequency requires.
 973          */
 974         cdclk_config->voltage_level =
 975                 skl_calc_voltage_level(cdclk_config->cdclk);
 976 }
 977
 978 /* convert from kHz to .1 fixpoint MHz with -1MHz offset */
 979 static int skl_cdclk_decimal(int cdclk)
 980 {
 981         return DIV_ROUND_CLOSEST(cdclk - 1000, 500);
 982 }
 983
 984 static void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv,
 985                                         int vco)
 986 {
 987         bool changed = dev_priv->skl_preferred_vco_freq != vco;
 988
 989         dev_priv->skl_preferred_vco_freq = vco;
 990
 991         if (changed)
 992                 intel_update_max_cdclk(dev_priv);
 993 }
 994
 995 static u32 skl_dpll0_link_rate(struct drm_i915_private *dev_priv, int vco)
 996 {
 997         drm_WARN_ON(&dev_priv->drm, vco != 8100000 && vco != 8640000);
 998
 999         /*
1000          * We always enable DPLL0 with the lowest link rate possible, but still
1001          * taking into account the VCO required to operate the eDP panel at the
1002          * desired frequency. The usual DP link rates operate with a VCO of
1003          * 8100 while the eDP 1.4 alternate link rates need a VCO of 8640.
1004          * The modeset code is responsible for the selection of the exact link
1005          * rate later on, with the constraint of choosing a frequency that
1006          * works with vco.
1007          */
1008         if (vco == 8640000)
1009                 return DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, SKL_DPLL0);
1010         else
1011                 return DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, SKL_DPLL0);
1012 }
1013
1014 static void skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco)
1015 {
1016         intel_de_rmw(dev_priv, DPLL_CTRL1,
1017                      DPLL_CTRL1_HDMI_MODE(SKL_DPLL0) |
1018                      DPLL_CTRL1_SSC(SKL_DPLL0) |
1019                      DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0),
1020                      DPLL_CTRL1_OVERRIDE(SKL_DPLL0) |
1021                      skl_dpll0_link_rate(dev_priv, vco));
1022         intel_de_posting_read(dev_priv, DPLL_CTRL1);
1023
1024         intel_de_rmw(dev_priv, LCPLL1_CTL,
1025                      0, LCPLL_PLL_ENABLE);
1026
1027         if (intel_de_wait_for_set(dev_priv, LCPLL1_CTL, LCPLL_PLL_LOCK, 5))
1028                 drm_err(&dev_priv->drm, "DPLL0 not locked\n");
1029
1030         dev_priv->display.cdclk.hw.vco = vco;
1031
1032         /* We'll want to keep using the current vco from now on. */
1033         skl_set_preferred_cdclk_vco(dev_priv, vco);
1034 }
1035
1036 static void skl_dpll0_disable(struct drm_i915_private *dev_priv)
1037 {
1038         intel_de_rmw(dev_priv, LCPLL1_CTL,
1039                      LCPLL_PLL_ENABLE, 0);
1040
1041         if (intel_de_wait_for_clear(dev_priv, LCPLL1_CTL, LCPLL_PLL_LOCK, 1))
1042                 drm_err(&dev_priv->drm, "Couldn't disable DPLL0\n");
1043
1044         dev_priv->display.cdclk.hw.vco = 0;
1045 }
1046
1047 static u32 skl_cdclk_freq_sel(struct drm_i915_private *dev_priv,
1048                               int cdclk, int vco)
1049 {
1050         switch (cdclk) {
1051         default:
1052                 drm_WARN_ON(&dev_priv->drm,
1053                             cdclk != dev_priv->display.cdclk.hw.bypass);
1054                 drm_WARN_ON(&dev_priv->drm, vco != 0);
1055                 fallthrough;
1056         case 308571:
1057         case 337500:
1058                 return CDCLK_FREQ_337_308;
1059         case 450000:
1060         case 432000:
1061                 return CDCLK_FREQ_450_432;
1062         case 540000:
1063                 return CDCLK_FREQ_540;
1064         case 617143:
1065         case 675000:
1066                 return CDCLK_FREQ_675_617;
1067         }
1068 }
1069
1070 static void skl_set_cdclk(struct drm_i915_private *dev_priv,
1071                           const struct intel_cdclk_config *cdclk_config,
1072                           enum pipe pipe)
1073 {
1074         int cdclk = cdclk_config->cdclk;
1075         int vco = cdclk_config->vco;
1076         u32 freq_select, cdclk_ctl;
1077         int ret;
1078
1079         /*
1080          * Based on WA#1183 CDCLK rates 308 and 617MHz CDCLK rates are
1081          * unsupported on SKL. In theory this should never happen since only
1082          * the eDP1.4 2.16 and 4.32Gbps rates require it, but eDP1.4 is not
1083          * supported on SKL either, see the above WA. WARN whenever trying to
1084          * use the corresponding VCO freq as that always leads to using the
1085          * minimum 308MHz CDCLK.
1086          */
1087         drm_WARN_ON_ONCE(&dev_priv->drm,
1088                          IS_SKYLAKE(dev_priv) && vco == 8640000);
1089
1090         ret = skl_pcode_request(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL,
1091                                 SKL_CDCLK_PREPARE_FOR_CHANGE,
1092                                 SKL_CDCLK_READY_FOR_CHANGE,
1093                                 SKL_CDCLK_READY_FOR_CHANGE, 3);
1094         if (ret) {
1095                 drm_err(&dev_priv->drm,
1096                         "Failed to inform PCU about cdclk change (%d)\n", ret);
1097                 return;
1098         }
1099
1100         freq_select = skl_cdclk_freq_sel(dev_priv, cdclk, vco);
1101
1102         if (dev_priv->display.cdclk.hw.vco != 0 &&
1103             dev_priv->display.cdclk.hw.vco != vco)
1104                 skl_dpll0_disable(dev_priv);
1105
1106         cdclk_ctl = intel_de_read(dev_priv, CDCLK_CTL);
1107
1108         if (dev_priv->display.cdclk.hw.vco != vco) {
1109                 /* Wa Display #1183: skl,kbl,cfl */
1110                 cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK);
1111                 cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk);
1112                 intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl);
1113         }
1114
1115         /* Wa Display #1183: skl,kbl,cfl */
1116         cdclk_ctl |= CDCLK_DIVMUX_CD_OVERRIDE;
1117         intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl);
1118         intel_de_posting_read(dev_priv, CDCLK_CTL);
1119
1120         if (dev_priv->display.cdclk.hw.vco != vco)
1121                 skl_dpll0_enable(dev_priv, vco);
1122
1123         /* Wa Display #1183: skl,kbl,cfl */
1124         cdclk_ctl &= ~(CDCLK_FREQ_SEL_MASK | CDCLK_FREQ_DECIMAL_MASK);
1125         intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl);
1126
1127         cdclk_ctl |= freq_select | skl_cdclk_decimal(cdclk);
1128         intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl);
1129
1130         /* Wa Display #1183: skl,kbl,cfl */
1131         cdclk_ctl &= ~CDCLK_DIVMUX_CD_OVERRIDE;
1132         intel_de_write(dev_priv, CDCLK_CTL, cdclk_ctl);
1133         intel_de_posting_read(dev_priv, CDCLK_CTL);
1134
1135         /* inform PCU of the change */
1136         snb_pcode_write(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL,
1137                         cdclk_config->voltage_level);
1138
1139         intel_update_cdclk(dev_priv);
1140 }
1141
1142 static void skl_sanitize_cdclk(struct drm_i915_private *dev_priv)
1143 {
1144         u32 cdctl, expected;
1145
1146         /*
1147          * check if the pre-os initialized the display
1148          * There is SWF18 scratchpad register defined which is set by the
1149          * pre-os which can be used by the OS drivers to check the status
1150          */
1151         if ((intel_de_read(dev_priv, SWF_ILK(0x18)) & 0x00FFFFFF) == 0)
1152                 goto sanitize;
1153
1154         intel_update_cdclk(dev_priv);
1155         intel_cdclk_dump_config(dev_priv, &dev_priv->display.cdclk.hw, "Current CDCLK");
1156
1157         /* Is PLL enabled and locked ? */
1158         if (dev_priv->display.cdclk.hw.vco == 0 ||
1159             dev_priv->display.cdclk.hw.cdclk == dev_priv->display.cdclk.hw.bypass)
1160                 goto sanitize;
1161
1162         /* DPLL okay; verify the cdclock
1163          *
1164          * Noticed in some instances that the freq selection is correct but
1165          * decimal part is programmed wrong from BIOS where pre-os does not
1166          * enable display. Verify the same as well.
1167          */
1168         cdctl = intel_de_read(dev_priv, CDCLK_CTL);
1169         expected = (cdctl & CDCLK_FREQ_SEL_MASK) |
1170                 skl_cdclk_decimal(dev_priv->display.cdclk.hw.cdclk);
1171         if (cdctl == expected)
1172                 /* All well; nothing to sanitize */
1173                 return;
1174
1175 sanitize:
1176         drm_dbg_kms(&dev_priv->drm, "Sanitizing cdclk programmed by pre-os\n");
1177
1178         /* force cdclk programming */
1179         dev_priv->display.cdclk.hw.cdclk = 0;
1180         /* force full PLL disable + enable */
1181         dev_priv->display.cdclk.hw.vco = -1;
1182 }
1183
1184 static void skl_cdclk_init_hw(struct drm_i915_private *dev_priv)
1185 {
1186         struct intel_cdclk_config cdclk_config;
1187
1188         skl_sanitize_cdclk(dev_priv);
1189
1190         if (dev_priv->display.cdclk.hw.cdclk != 0 &&
1191             dev_priv->display.cdclk.hw.vco != 0) {
1192                 /*
1193                  * Use the current vco as our initial
1194                  * guess as to what the preferred vco is.
1195                  */
1196                 if (dev_priv->skl_preferred_vco_freq == 0)
1197                         skl_set_preferred_cdclk_vco(dev_priv,
1198                                                     dev_priv->display.cdclk.hw.vco);
1199                 return;
1200         }
1201
1202         cdclk_config = dev_priv->display.cdclk.hw;
1203
1204         cdclk_config.vco = dev_priv->skl_preferred_vco_freq;
1205         if (cdclk_config.vco == 0)
1206                 cdclk_config.vco = 8100000;
1207         cdclk_config.cdclk = skl_calc_cdclk(0, cdclk_config.vco);
1208         cdclk_config.voltage_level = skl_calc_voltage_level(cdclk_config.cdclk);
1209
1210         skl_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE);
1211 }
1212
1213 static void skl_cdclk_uninit_hw(struct drm_i915_private *dev_priv)
1214 {
1215         struct intel_cdclk_config cdclk_config = dev_priv->display.cdclk.hw;
1216
1217         cdclk_config.cdclk = cdclk_config.bypass;
1218         cdclk_config.vco = 0;
1219         cdclk_config.voltage_level = skl_calc_voltage_level(cdclk_config.cdclk);
1220
1221         skl_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE);
1222 }
1223
1224 struct intel_cdclk_vals {
1225         u32 cdclk;
1226         u16 refclk;
1227         u16 waveform;
1228         u8 divider;     /* CD2X divider * 2 */
1229         u8 ratio;
1230 };
1231
1232 static const struct intel_cdclk_vals bxt_cdclk_table[] = {
1233         { .refclk = 19200, .cdclk = 144000, .divider = 8, .ratio = 60 },
1234         { .refclk = 19200, .cdclk = 288000, .divider = 4, .ratio = 60 },
1235         { .refclk = 19200, .cdclk = 384000, .divider = 3, .ratio = 60 },
1236         { .refclk = 19200, .cdclk = 576000, .divider = 2, .ratio = 60 },
1237         { .refclk = 19200, .cdclk = 624000, .divider = 2, .ratio = 65 },
1238         {}
1239 };
1240
1241 static const struct intel_cdclk_vals glk_cdclk_table[] = {
1242         { .refclk = 19200, .cdclk =  79200, .divider = 8, .ratio = 33 },
1243         { .refclk = 19200, .cdclk = 158400, .divider = 4, .ratio = 33 },
1244         { .refclk = 19200, .cdclk = 316800, .divider = 2, .ratio = 33 },
1245         {}
1246 };
1247
1248 static const struct intel_cdclk_vals icl_cdclk_table[] = {
1249         { .refclk = 19200, .cdclk = 172800, .divider = 2, .ratio = 18 },
1250         { .refclk = 19200, .cdclk = 192000, .divider = 2, .ratio = 20 },
1251         { .refclk = 19200, .cdclk = 307200, .divider = 2, .ratio = 32 },
1252         { .refclk = 19200, .cdclk = 326400, .divider = 4, .ratio = 68 },
1253         { .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 },
1254         { .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 },
1255
1256         { .refclk = 24000, .cdclk = 180000, .divider = 2, .ratio = 15 },
1257         { .refclk = 24000, .cdclk = 192000, .divider = 2, .ratio = 16 },
1258         { .refclk = 24000, .cdclk = 312000, .divider = 2, .ratio = 26 },
1259         { .refclk = 24000, .cdclk = 324000, .divider = 4, .ratio = 54 },
1260         { .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 },
1261         { .refclk = 24000, .cdclk = 648000, .divider = 2, .ratio = 54 },
1262
1263         { .refclk = 38400, .cdclk = 172800, .divider = 2, .ratio =  9 },
1264         { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 10 },
1265         { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 },
1266         { .refclk = 38400, .cdclk = 326400, .divider = 4, .ratio = 34 },
1267         { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 },
1268         { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 },
1269         {}
1270 };
1271
1272 static const struct intel_cdclk_vals rkl_cdclk_table[] = {
1273         { .refclk = 19200, .cdclk = 172800, .divider = 4, .ratio =  36 },
1274         { .refclk = 19200, .cdclk = 192000, .divider = 4, .ratio =  40 },
1275         { .refclk = 19200, .cdclk = 307200, .divider = 4, .ratio =  64 },
1276         { .refclk = 19200, .cdclk = 326400, .divider = 8, .ratio = 136 },
1277         { .refclk = 19200, .cdclk = 556800, .divider = 4, .ratio = 116 },
1278         { .refclk = 19200, .cdclk = 652800, .divider = 4, .ratio = 136 },
1279
1280         { .refclk = 24000, .cdclk = 180000, .divider = 4, .ratio =  30 },
1281         { .refclk = 24000, .cdclk = 192000, .divider = 4, .ratio =  32 },
1282         { .refclk = 24000, .cdclk = 312000, .divider = 4, .ratio =  52 },
1283         { .refclk = 24000, .cdclk = 324000, .divider = 8, .ratio = 108 },
1284         { .refclk = 24000, .cdclk = 552000, .divider = 4, .ratio =  92 },
1285         { .refclk = 24000, .cdclk = 648000, .divider = 4, .ratio = 108 },
1286
1287         { .refclk = 38400, .cdclk = 172800, .divider = 4, .ratio = 18 },
1288         { .refclk = 38400, .cdclk = 192000, .divider = 4, .ratio = 20 },
1289         { .refclk = 38400, .cdclk = 307200, .divider = 4, .ratio = 32 },
1290         { .refclk = 38400, .cdclk = 326400, .divider = 8, .ratio = 68 },
1291         { .refclk = 38400, .cdclk = 556800, .divider = 4, .ratio = 58 },
1292         { .refclk = 38400, .cdclk = 652800, .divider = 4, .ratio = 68 },
1293         {}
1294 };
1295
1296 static const struct intel_cdclk_vals adlp_a_step_cdclk_table[] = {
1297         { .refclk = 19200, .cdclk = 307200, .divider = 2, .ratio = 32 },
1298         { .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 },
1299         { .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 },
1300
1301         { .refclk = 24000, .cdclk = 312000, .divider = 2, .ratio = 26 },
1302         { .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 },
1303         { .refclk = 24400, .cdclk = 648000, .divider = 2, .ratio = 54 },
1304
1305         { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 },
1306         { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 },
1307         { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 },
1308         {}
1309 };
1310
1311 static const struct intel_cdclk_vals adlp_cdclk_table[] = {
1312         { .refclk = 19200, .cdclk = 172800, .divider = 3, .ratio = 27 },
1313         { .refclk = 19200, .cdclk = 192000, .divider = 2, .ratio = 20 },
1314         { .refclk = 19200, .cdclk = 307200, .divider = 2, .ratio = 32 },
1315         { .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 },
1316         { .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 },
1317
1318         { .refclk = 24000, .cdclk = 176000, .divider = 3, .ratio = 22 },
1319         { .refclk = 24000, .cdclk = 192000, .divider = 2, .ratio = 16 },
1320         { .refclk = 24000, .cdclk = 312000, .divider = 2, .ratio = 26 },
1321         { .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 },
1322         { .refclk = 24000, .cdclk = 648000, .divider = 2, .ratio = 54 },
1323
1324         { .refclk = 38400, .cdclk = 179200, .divider = 3, .ratio = 14 },
1325         { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 10 },
1326         { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 },
1327         { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 },
1328         { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 },
1329         {}
1330 };
1331
1332 static const struct intel_cdclk_vals rplu_cdclk_table[] = {
1333         { .refclk = 19200, .cdclk = 172800, .divider = 3, .ratio = 27 },
1334         { .refclk = 19200, .cdclk = 192000, .divider = 2, .ratio = 20 },
1335         { .refclk = 19200, .cdclk = 307200, .divider = 2, .ratio = 32 },
1336         { .refclk = 19200, .cdclk = 480000, .divider = 2, .ratio = 50 },
1337         { .refclk = 19200, .cdclk = 556800, .divider = 2, .ratio = 58 },
1338         { .refclk = 19200, .cdclk = 652800, .divider = 2, .ratio = 68 },
1339
1340         { .refclk = 24000, .cdclk = 176000, .divider = 3, .ratio = 22 },
1341         { .refclk = 24000, .cdclk = 192000, .divider = 2, .ratio = 16 },
1342         { .refclk = 24000, .cdclk = 312000, .divider = 2, .ratio = 26 },
1343         { .refclk = 24000, .cdclk = 480000, .divider = 2, .ratio = 40 },
1344         { .refclk = 24000, .cdclk = 552000, .divider = 2, .ratio = 46 },
1345         { .refclk = 24000, .cdclk = 648000, .divider = 2, .ratio = 54 },
1346
1347         { .refclk = 38400, .cdclk = 179200, .divider = 3, .ratio = 14 },
1348         { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 10 },
1349         { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16 },
1350         { .refclk = 38400, .cdclk = 480000, .divider = 2, .ratio = 25 },
1351         { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29 },
1352         { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34 },
1353         {}
1354 };
1355
1356 static const struct intel_cdclk_vals dg2_cdclk_table[] = {
1357         { .refclk = 38400, .cdclk = 163200, .divider = 2, .ratio = 34, .waveform = 0x8888 },
1358         { .refclk = 38400, .cdclk = 204000, .divider = 2, .ratio = 34, .waveform = 0x9248 },
1359         { .refclk = 38400, .cdclk = 244800, .divider = 2, .ratio = 34, .waveform = 0xa4a4 },
1360         { .refclk = 38400, .cdclk = 285600, .divider = 2, .ratio = 34, .waveform = 0xa54a },
1361         { .refclk = 38400, .cdclk = 326400, .divider = 2, .ratio = 34, .waveform = 0xaaaa },
1362         { .refclk = 38400, .cdclk = 367200, .divider = 2, .ratio = 34, .waveform = 0xad5a },
1363         { .refclk = 38400, .cdclk = 408000, .divider = 2, .ratio = 34, .waveform = 0xb6b6 },
1364         { .refclk = 38400, .cdclk = 448800, .divider = 2, .ratio = 34, .waveform = 0xdbb6 },
1365         { .refclk = 38400, .cdclk = 489600, .divider = 2, .ratio = 34, .waveform = 0xeeee },
1366         { .refclk = 38400, .cdclk = 530400, .divider = 2, .ratio = 34, .waveform = 0xf7de },
1367         { .refclk = 38400, .cdclk = 571200, .divider = 2, .ratio = 34, .waveform = 0xfefe },
1368         { .refclk = 38400, .cdclk = 612000, .divider = 2, .ratio = 34, .waveform = 0xfffe },
1369         { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34, .waveform = 0xffff },
1370         {}
1371 };
1372
1373 static const struct intel_cdclk_vals mtl_cdclk_table[] = {
1374         { .refclk = 38400, .cdclk = 172800, .divider = 2, .ratio = 16, .waveform = 0xad5a },
1375         { .refclk = 38400, .cdclk = 192000, .divider = 2, .ratio = 16, .waveform = 0xb6b6 },
1376         { .refclk = 38400, .cdclk = 307200, .divider = 2, .ratio = 16, .waveform = 0x0000 },
1377         { .refclk = 38400, .cdclk = 480000, .divider = 2, .ratio = 25, .waveform = 0x0000 },
1378         { .refclk = 38400, .cdclk = 556800, .divider = 2, .ratio = 29, .waveform = 0x0000 },
1379         { .refclk = 38400, .cdclk = 652800, .divider = 2, .ratio = 34, .waveform = 0x0000 },
1380         {}
1381 };
1382
1383 static int bxt_calc_cdclk(struct drm_i915_private *dev_priv, int min_cdclk)
1384 {
1385         const struct intel_cdclk_vals *table = dev_priv->display.cdclk.table;
1386         int i;
1387
1388         for (i = 0; table[i].refclk; i++)
1389                 if (table[i].refclk == dev_priv->display.cdclk.hw.ref &&
1390                     table[i].cdclk >= min_cdclk)
1391                         return table[i].cdclk;
1392
1393         drm_WARN(&dev_priv->drm, 1,
1394                  "Cannot satisfy minimum cdclk %d with refclk %u\n",
1395                  min_cdclk, dev_priv->display.cdclk.hw.ref);
1396         return 0;
1397 }
1398
1399 static int bxt_calc_cdclk_pll_vco(struct drm_i915_private *dev_priv, int cdclk)
1400 {
1401         const struct intel_cdclk_vals *table = dev_priv->display.cdclk.table;
1402         int i;
1403
1404         if (cdclk == dev_priv->display.cdclk.hw.bypass)
1405                 return 0;
1406
1407         for (i = 0; table[i].refclk; i++)
1408                 if (table[i].refclk == dev_priv->display.cdclk.hw.ref &&
1409                     table[i].cdclk == cdclk)
1410                         return dev_priv->display.cdclk.hw.ref * table[i].ratio;
1411
1412         drm_WARN(&dev_priv->drm, 1, "cdclk %d not valid for refclk %u\n",
1413                  cdclk, dev_priv->display.cdclk.hw.ref);
1414         return 0;
1415 }
1416
1417 static u8 bxt_calc_voltage_level(int cdclk)
1418 {
1419         return DIV_ROUND_UP(cdclk, 25000);
1420 }
1421
1422 static u8 icl_calc_voltage_level(int cdclk)
1423 {
1424         if (cdclk > 556800)
1425                 return 2;
1426         else if (cdclk > 312000)
1427                 return 1;
1428         else
1429                 return 0;
1430 }
1431
1432 static u8 ehl_calc_voltage_level(int cdclk)
1433 {
1434         if (cdclk > 326400)
1435                 return 3;
1436         else if (cdclk > 312000)
1437                 return 2;
1438         else if (cdclk > 180000)
1439                 return 1;
1440         else
1441                 return 0;
1442 }
1443
1444 static u8 tgl_calc_voltage_level(int cdclk)
1445 {
1446         if (cdclk > 556800)
1447                 return 3;
1448         else if (cdclk > 326400)
1449                 return 2;
1450         else if (cdclk > 312000)
1451                 return 1;
1452         else
1453                 return 0;
1454 }
1455
1456 static u8 rplu_calc_voltage_level(int cdclk)
1457 {
1458         if (cdclk > 556800)
1459                 return 3;
1460         else if (cdclk > 480000)
1461                 return 2;
1462         else if (cdclk > 312000)
1463                 return 1;
1464         else
1465                 return 0;
1466 }
1467
1468 static void icl_readout_refclk(struct drm_i915_private *dev_priv,
1469                                struct intel_cdclk_config *cdclk_config)
1470 {
1471         u32 dssm = intel_de_read(dev_priv, SKL_DSSM) & ICL_DSSM_CDCLK_PLL_REFCLK_MASK;
1472
1473         switch (dssm) {
1474         default:
1475                 MISSING_CASE(dssm);
1476                 fallthrough;
1477         case ICL_DSSM_CDCLK_PLL_REFCLK_24MHz:
1478                 cdclk_config->ref = 24000;
1479                 break;
1480         case ICL_DSSM_CDCLK_PLL_REFCLK_19_2MHz:
1481                 cdclk_config->ref = 19200;
1482                 break;
1483         case ICL_DSSM_CDCLK_PLL_REFCLK_38_4MHz:
1484                 cdclk_config->ref = 38400;
1485                 break;
1486         }
1487 }
1488
1489 static void bxt_de_pll_readout(struct drm_i915_private *dev_priv,
1490                                struct intel_cdclk_config *cdclk_config)
1491 {
1492         u32 val, ratio;
1493
1494         if (IS_DG2(dev_priv))
1495                 cdclk_config->ref = 38400;
1496         else if (DISPLAY_VER(dev_priv) >= 11)
1497                 icl_readout_refclk(dev_priv, cdclk_config);
1498         else
1499                 cdclk_config->ref = 19200;
1500
1501         val = intel_de_read(dev_priv, BXT_DE_PLL_ENABLE);
1502         if ((val & BXT_DE_PLL_PLL_ENABLE) == 0 ||
1503             (val & BXT_DE_PLL_LOCK) == 0) {
1504                 /*
1505                  * CDCLK PLL is disabled, the VCO/ratio doesn't matter, but
1506                  * setting it to zero is a way to signal that.
1507                  */
1508                 cdclk_config->vco = 0;
1509                 return;
1510         }
1511
1512         /*
1513          * DISPLAY_VER >= 11 have the ratio directly in the PLL enable register,
1514          * gen9lp had it in a separate PLL control register.
1515          */
1516         if (DISPLAY_VER(dev_priv) >= 11)
1517                 ratio = val & ICL_CDCLK_PLL_RATIO_MASK;
1518         else
1519                 ratio = intel_de_read(dev_priv, BXT_DE_PLL_CTL) & BXT_DE_PLL_RATIO_MASK;
1520
1521         cdclk_config->vco = ratio * cdclk_config->ref;
1522 }
1523
1524 static void bxt_get_cdclk(struct drm_i915_private *dev_priv,
1525                           struct intel_cdclk_config *cdclk_config)
1526 {
1527         u32 squash_ctl = 0;
1528         u32 divider;
1529         int div;
1530
1531         bxt_de_pll_readout(dev_priv, cdclk_config);
1532
1533         if (DISPLAY_VER(dev_priv) >= 12)
1534                 cdclk_config->bypass = cdclk_config->ref / 2;
1535         else if (DISPLAY_VER(dev_priv) >= 11)
1536                 cdclk_config->bypass = 50000;
1537         else
1538                 cdclk_config->bypass = cdclk_config->ref;
1539
1540         if (cdclk_config->vco == 0) {
1541                 cdclk_config->cdclk = cdclk_config->bypass;
1542                 goto out;
1543         }
1544
1545         divider = intel_de_read(dev_priv, CDCLK_CTL) & BXT_CDCLK_CD2X_DIV_SEL_MASK;
1546
1547         switch (divider) {
1548         case BXT_CDCLK_CD2X_DIV_SEL_1:
1549                 div = 2;
1550                 break;
1551         case BXT_CDCLK_CD2X_DIV_SEL_1_5:
1552                 div = 3;
1553                 break;
1554         case BXT_CDCLK_CD2X_DIV_SEL_2:
1555                 div = 4;
1556                 break;
1557         case BXT_CDCLK_CD2X_DIV_SEL_4:
1558                 div = 8;
1559                 break;
1560         default:
1561                 MISSING_CASE(divider);
1562                 return;
1563         }
1564
1565         if (HAS_CDCLK_SQUASH(dev_priv))
1566                 squash_ctl = intel_de_read(dev_priv, CDCLK_SQUASH_CTL);
1567
1568         if (squash_ctl & CDCLK_SQUASH_ENABLE) {
1569                 u16 waveform;
1570                 int size;
1571
1572                 size = REG_FIELD_GET(CDCLK_SQUASH_WINDOW_SIZE_MASK, squash_ctl) + 1;
1573                 waveform = REG_FIELD_GET(CDCLK_SQUASH_WAVEFORM_MASK, squash_ctl) >> (16 - size);
1574
1575                 cdclk_config->cdclk = DIV_ROUND_CLOSEST(hweight16(waveform) *
1576                                                         cdclk_config->vco, size * div);
1577         } else {
1578                 cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_config->vco, div);
1579         }
1580
1581  out:
1582         /*
1583          * Can't read this out :( Let's assume it's
1584          * at least what the CDCLK frequency requires.
1585          */
1586         cdclk_config->voltage_level =
1587                 intel_cdclk_calc_voltage_level(dev_priv, cdclk_config->cdclk);
1588 }
1589
1590 static void bxt_de_pll_disable(struct drm_i915_private *dev_priv)
1591 {
1592         intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, 0);
1593
1594         /* Timeout 200us */
1595         if (intel_de_wait_for_clear(dev_priv,
1596                                     BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1))
1597                 drm_err(&dev_priv->drm, "timeout waiting for DE PLL unlock\n");
1598
1599         dev_priv->display.cdclk.hw.vco = 0;
1600 }
1601
1602 static void bxt_de_pll_enable(struct drm_i915_private *dev_priv, int vco)
1603 {
1604         int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->display.cdclk.hw.ref);
1605
1606         intel_de_rmw(dev_priv, BXT_DE_PLL_CTL,
1607                      BXT_DE_PLL_RATIO_MASK, BXT_DE_PLL_RATIO(ratio));
1608
1609         intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, BXT_DE_PLL_PLL_ENABLE);
1610
1611         /* Timeout 200us */
1612         if (intel_de_wait_for_set(dev_priv,
1613                                   BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1))
1614                 drm_err(&dev_priv->drm, "timeout waiting for DE PLL lock\n");
1615
1616         dev_priv->display.cdclk.hw.vco = vco;
1617 }
1618
1619 static void icl_cdclk_pll_disable(struct drm_i915_private *dev_priv)
1620 {
1621         intel_de_rmw(dev_priv, BXT_DE_PLL_ENABLE,
1622                      BXT_DE_PLL_PLL_ENABLE, 0);
1623
1624         /* Timeout 200us */
1625         if (intel_de_wait_for_clear(dev_priv, BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1))
1626                 drm_err(&dev_priv->drm, "timeout waiting for CDCLK PLL unlock\n");
1627
1628         dev_priv->display.cdclk.hw.vco = 0;
1629 }
1630
1631 static void icl_cdclk_pll_enable(struct drm_i915_private *dev_priv, int vco)
1632 {
1633         int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->display.cdclk.hw.ref);
1634         u32 val;
1635
1636         val = ICL_CDCLK_PLL_RATIO(ratio);
1637         intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val);
1638
1639         val |= BXT_DE_PLL_PLL_ENABLE;
1640         intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val);
1641
1642         /* Timeout 200us */
1643         if (intel_de_wait_for_set(dev_priv, BXT_DE_PLL_ENABLE, BXT_DE_PLL_LOCK, 1))
1644                 drm_err(&dev_priv->drm, "timeout waiting for CDCLK PLL lock\n");
1645
1646         dev_priv->display.cdclk.hw.vco = vco;
1647 }
1648
1649 static void adlp_cdclk_pll_crawl(struct drm_i915_private *dev_priv, int vco)
1650 {
1651         int ratio = DIV_ROUND_CLOSEST(vco, dev_priv->display.cdclk.hw.ref);
1652         u32 val;
1653
1654         /* Write PLL ratio without disabling */
1655         val = ICL_CDCLK_PLL_RATIO(ratio) | BXT_DE_PLL_PLL_ENABLE;
1656         intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val);
1657
1658         /* Submit freq change request */
1659         val |= BXT_DE_PLL_FREQ_REQ;
1660         intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val);
1661
1662         /* Timeout 200us */
1663         if (intel_de_wait_for_set(dev_priv, BXT_DE_PLL_ENABLE,
1664                                   BXT_DE_PLL_LOCK | BXT_DE_PLL_FREQ_REQ_ACK, 1))
1665                 drm_err(&dev_priv->drm, "timeout waiting for FREQ change request ack\n");
1666
1667         val &= ~BXT_DE_PLL_FREQ_REQ;
1668         intel_de_write(dev_priv, BXT_DE_PLL_ENABLE, val);
1669
1670         dev_priv->display.cdclk.hw.vco = vco;
1671 }
1672
1673 static u32 bxt_cdclk_cd2x_pipe(struct drm_i915_private *dev_priv, enum pipe pipe)
1674 {
1675         if (DISPLAY_VER(dev_priv) >= 12) {
1676                 if (pipe == INVALID_PIPE)
1677                         return TGL_CDCLK_CD2X_PIPE_NONE;
1678                 else
1679                         return TGL_CDCLK_CD2X_PIPE(pipe);
1680         } else if (DISPLAY_VER(dev_priv) >= 11) {
1681                 if (pipe == INVALID_PIPE)
1682                         return ICL_CDCLK_CD2X_PIPE_NONE;
1683                 else
1684                         return ICL_CDCLK_CD2X_PIPE(pipe);
1685         } else {
1686                 if (pipe == INVALID_PIPE)
1687                         return BXT_CDCLK_CD2X_PIPE_NONE;
1688                 else
1689                         return BXT_CDCLK_CD2X_PIPE(pipe);
1690         }
1691 }
1692
1693 static u32 bxt_cdclk_cd2x_div_sel(struct drm_i915_private *dev_priv,
1694                                   int cdclk, int vco)
1695 {
1696         /* cdclk = vco / 2 / div{1,1.5,2,4} */
1697         switch (DIV_ROUND_CLOSEST(vco, cdclk)) {
1698         default:
1699                 drm_WARN_ON(&dev_priv->drm,
1700                             cdclk != dev_priv->display.cdclk.hw.bypass);
1701                 drm_WARN_ON(&dev_priv->drm, vco != 0);
1702                 fallthrough;
1703         case 2:
1704                 return BXT_CDCLK_CD2X_DIV_SEL_1;
1705         case 3:
1706                 return BXT_CDCLK_CD2X_DIV_SEL_1_5;
1707         case 4:
1708                 return BXT_CDCLK_CD2X_DIV_SEL_2;
1709         case 8:
1710                 return BXT_CDCLK_CD2X_DIV_SEL_4;
1711         }
1712 }
1713
1714 static u32 cdclk_squash_waveform(struct drm_i915_private *dev_priv,
1715                                  int cdclk)
1716 {
1717         const struct intel_cdclk_vals *table = dev_priv->display.cdclk.table;
1718         int i;
1719
1720         if (cdclk == dev_priv->display.cdclk.hw.bypass)
1721                 return 0;
1722
1723         for (i = 0; table[i].refclk; i++)
1724                 if (table[i].refclk == dev_priv->display.cdclk.hw.ref &&
1725                     table[i].cdclk == cdclk)
1726                         return table[i].waveform;
1727
1728         drm_WARN(&dev_priv->drm, 1, "cdclk %d not valid for refclk %u\n",
1729                  cdclk, dev_priv->display.cdclk.hw.ref);
1730
1731         return 0xffff;
1732 }
1733
1734 static void icl_cdclk_pll_update(struct drm_i915_private *i915, int vco)
1735 {
1736         if (i915->display.cdclk.hw.vco != 0 &&
1737             i915->display.cdclk.hw.vco != vco)
1738                 icl_cdclk_pll_disable(i915);
1739
1740         if (i915->display.cdclk.hw.vco != vco)
1741                 icl_cdclk_pll_enable(i915, vco);
1742 }
1743
1744 static void bxt_cdclk_pll_update(struct drm_i915_private *i915, int vco)
1745 {
1746         if (i915->display.cdclk.hw.vco != 0 &&
1747             i915->display.cdclk.hw.vco != vco)
1748                 bxt_de_pll_disable(i915);
1749
1750         if (i915->display.cdclk.hw.vco != vco)
1751                 bxt_de_pll_enable(i915, vco);
1752 }
1753
1754 static void dg2_cdclk_squash_program(struct drm_i915_private *i915,
1755                                      u16 waveform)
1756 {
1757         u32 squash_ctl = 0;
1758
1759         if (waveform)
1760                 squash_ctl = CDCLK_SQUASH_ENABLE |
1761                              CDCLK_SQUASH_WINDOW_SIZE(0xf) | waveform;
1762
1763         intel_de_write(i915, CDCLK_SQUASH_CTL, squash_ctl);
1764 }
1765
1766 static bool cdclk_pll_is_unknown(unsigned int vco)
1767 {
1768         /*
1769          * Ensure driver does not take the crawl path for the
1770          * case when the vco is set to ~0 in the
1771          * sanitize path.
1772          */
1773         return vco == ~0;
1774 }
1775
1776 static int cdclk_squash_divider(u16 waveform)
1777 {
1778         return hweight16(waveform ?: 0xffff);
1779 }
1780
1781 static bool cdclk_compute_crawl_and_squash_midpoint(struct drm_i915_private *i915,
1782                                                     const struct intel_cdclk_config *old_cdclk_config,
1783                                                     const struct intel_cdclk_config *new_cdclk_config,
1784                                                     struct intel_cdclk_config *mid_cdclk_config)
1785 {
1786         u16 old_waveform, new_waveform, mid_waveform;
1787         int size = 16;
1788         int div = 2;
1789
1790         /* Return if PLL is in an unknown state, force a complete disable and re-enable. */
1791         if (cdclk_pll_is_unknown(old_cdclk_config->vco))
1792                 return false;
1793
1794         /* Return if both Squash and Crawl are not present */
1795         if (!HAS_CDCLK_CRAWL(i915) || !HAS_CDCLK_SQUASH(i915))
1796                 return false;
1797
1798         old_waveform = cdclk_squash_waveform(i915, old_cdclk_config->cdclk);
1799         new_waveform = cdclk_squash_waveform(i915, new_cdclk_config->cdclk);
1800
1801         /* Return if Squash only or Crawl only is the desired action */
1802         if (old_cdclk_config->vco == 0 || new_cdclk_config->vco == 0 ||
1803             old_cdclk_config->vco == new_cdclk_config->vco ||
1804             old_waveform == new_waveform)
1805                 return false;
1806
1807         *mid_cdclk_config = *new_cdclk_config;
1808
1809         /*
1810          * Populate the mid_cdclk_config accordingly.
1811          * - If moving to a higher cdclk, the desired action is squashing.
1812          * The mid cdclk config should have the new (squash) waveform.
1813          * - If moving to a lower cdclk, the desired action is crawling.
1814          * The mid cdclk config should have the new vco.
1815          */
1816
1817         if (cdclk_squash_divider(new_waveform) > cdclk_squash_divider(old_waveform)) {
1818                 mid_cdclk_config->vco = old_cdclk_config->vco;
1819                 mid_waveform = new_waveform;
1820         } else {
1821                 mid_cdclk_config->vco = new_cdclk_config->vco;
1822                 mid_waveform = old_waveform;
1823         }
1824
1825         mid_cdclk_config->cdclk = DIV_ROUND_CLOSEST(cdclk_squash_divider(mid_waveform) *
1826                                                     mid_cdclk_config->vco, size * div);
1827
1828         /* make sure the mid clock came out sane */
1829
1830         drm_WARN_ON(&i915->drm, mid_cdclk_config->cdclk <
1831                     min(old_cdclk_config->cdclk, new_cdclk_config->cdclk));
1832         drm_WARN_ON(&i915->drm, mid_cdclk_config->cdclk >
1833                     i915->display.cdclk.max_cdclk_freq);
1834         drm_WARN_ON(&i915->drm, cdclk_squash_waveform(i915, mid_cdclk_config->cdclk) !=
1835                     mid_waveform);
1836
1837         return true;
1838 }
1839
1840 static bool pll_enable_wa_needed(struct drm_i915_private *dev_priv)
1841 {
1842         return ((IS_DG2(dev_priv) || IS_METEORLAKE(dev_priv)) &&
1843                 dev_priv->display.cdclk.hw.vco > 0 &&
1844                 HAS_CDCLK_SQUASH(dev_priv));
1845 }
1846
1847 static void _bxt_set_cdclk(struct drm_i915_private *dev_priv,
1848                            const struct intel_cdclk_config *cdclk_config,
1849                            enum pipe pipe)
1850 {
1851         int cdclk = cdclk_config->cdclk;
1852         int vco = cdclk_config->vco;
1853         u32 val;
1854         u16 waveform;
1855         int clock;
1856
1857         if (HAS_CDCLK_CRAWL(dev_priv) && dev_priv->display.cdclk.hw.vco > 0 && vco > 0 &&
1858             !cdclk_pll_is_unknown(dev_priv->display.cdclk.hw.vco)) {
1859                 if (dev_priv->display.cdclk.hw.vco != vco)
1860                         adlp_cdclk_pll_crawl(dev_priv, vco);
1861         } else if (DISPLAY_VER(dev_priv) >= 11) {
1862                 /* wa_15010685871: dg2, mtl */
1863                 if (pll_enable_wa_needed(dev_priv))
1864                         dg2_cdclk_squash_program(dev_priv, 0);
1865
1866                 icl_cdclk_pll_update(dev_priv, vco);
1867         } else
1868                 bxt_cdclk_pll_update(dev_priv, vco);
1869
1870         waveform = cdclk_squash_waveform(dev_priv, cdclk);
1871
1872         if (waveform)
1873                 clock = vco / 2;
1874         else
1875                 clock = cdclk;
1876
1877         if (HAS_CDCLK_SQUASH(dev_priv))
1878                 dg2_cdclk_squash_program(dev_priv, waveform);
1879
1880         val = bxt_cdclk_cd2x_div_sel(dev_priv, clock, vco) |
1881                 bxt_cdclk_cd2x_pipe(dev_priv, pipe) |
1882                 skl_cdclk_decimal(cdclk);
1883
1884         /*
1885          * Disable SSA Precharge when CD clock frequency < 500 MHz,
1886          * enable otherwise.
1887          */
1888         if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) &&
1889             cdclk >= 500000)
1890                 val |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
1891         intel_de_write(dev_priv, CDCLK_CTL, val);
1892
1893         if (pipe != INVALID_PIPE)
1894                 intel_crtc_wait_for_next_vblank(intel_crtc_for_pipe(dev_priv, pipe));
1895 }
1896
1897 static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
1898                           const struct intel_cdclk_config *cdclk_config,
1899                           enum pipe pipe)
1900 {
1901         struct intel_cdclk_config mid_cdclk_config;
1902         int cdclk = cdclk_config->cdclk;
1903         int ret = 0;
1904
1905         /*
1906          * Inform power controller of upcoming frequency change.
1907          * Display versions 14 and beyond do not follow the PUnit
1908          * mailbox communication, skip
1909          * this step.
1910          */
1911         if (DISPLAY_VER(dev_priv) >= 14 || IS_DG2(dev_priv))
1912                 /* NOOP */;
1913         else if (DISPLAY_VER(dev_priv) >= 11)
1914                 ret = skl_pcode_request(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL,
1915                                         SKL_CDCLK_PREPARE_FOR_CHANGE,
1916                                         SKL_CDCLK_READY_FOR_CHANGE,
1917                                         SKL_CDCLK_READY_FOR_CHANGE, 3);
1918         else
1919                 /*
1920                  * BSpec requires us to wait up to 150usec, but that leads to
1921                  * timeouts; the 2ms used here is based on experiment.
1922                  */
1923                 ret = snb_pcode_write_timeout(&dev_priv->uncore,
1924                                               HSW_PCODE_DE_WRITE_FREQ_REQ,
1925                                               0x80000000, 150, 2);
1926
1927         if (ret) {
1928                 drm_err(&dev_priv->drm,
1929                         "Failed to inform PCU about cdclk change (err %d, freq %d)\n",
1930                         ret, cdclk);
1931                 return;
1932         }
1933
1934         if (cdclk_compute_crawl_and_squash_midpoint(dev_priv, &dev_priv->display.cdclk.hw,
1935                                                     cdclk_config, &mid_cdclk_config)) {
1936                 _bxt_set_cdclk(dev_priv, &mid_cdclk_config, pipe);
1937                 _bxt_set_cdclk(dev_priv, cdclk_config, pipe);
1938         } else {
1939                 _bxt_set_cdclk(dev_priv, cdclk_config, pipe);
1940         }
1941
1942         if (DISPLAY_VER(dev_priv) >= 14)
1943                 /*
1944                  * NOOP - No Pcode communication needed for
1945                  * Display versions 14 and beyond
1946                  */;
1947         else if (DISPLAY_VER(dev_priv) >= 11 && !IS_DG2(dev_priv))
1948                 ret = snb_pcode_write(&dev_priv->uncore, SKL_PCODE_CDCLK_CONTROL,
1949                                       cdclk_config->voltage_level);
1950         if (DISPLAY_VER(dev_priv) < 11) {
1951                 /*
1952                  * The timeout isn't specified, the 2ms used here is based on
1953                  * experiment.
1954                  * FIXME: Waiting for the request completion could be delayed
1955                  * until the next PCODE request based on BSpec.
1956                  */
1957                 ret = snb_pcode_write_timeout(&dev_priv->uncore,
1958                                               HSW_PCODE_DE_WRITE_FREQ_REQ,
1959                                               cdclk_config->voltage_level,
1960                                               150, 2);
1961         }
1962         if (ret) {
1963                 drm_err(&dev_priv->drm,
1964                         "PCode CDCLK freq set failed, (err %d, freq %d)\n",
1965                         ret, cdclk);
1966                 return;
1967         }
1968
1969         intel_update_cdclk(dev_priv);
1970
1971         if (DISPLAY_VER(dev_priv) >= 11)
1972                 /*
1973                  * Can't read out the voltage level :(
1974                  * Let's just assume everything is as expected.
1975                  */
1976                 dev_priv->display.cdclk.hw.voltage_level = cdclk_config->voltage_level;
1977 }
1978
1979 static void bxt_sanitize_cdclk(struct drm_i915_private *dev_priv)
1980 {
1981         u32 cdctl, expected;
1982         int cdclk, clock, vco;
1983
1984         intel_update_cdclk(dev_priv);
1985         intel_cdclk_dump_config(dev_priv, &dev_priv->display.cdclk.hw, "Current CDCLK");
1986
1987         if (dev_priv->display.cdclk.hw.vco == 0 ||
1988             dev_priv->display.cdclk.hw.cdclk == dev_priv->display.cdclk.hw.bypass)
1989                 goto sanitize;
1990
1991         /* DPLL okay; verify the cdclock
1992          *
1993          * Some BIOS versions leave an incorrect decimal frequency value and
1994          * set reserved MBZ bits in CDCLK_CTL at least during exiting from S4,
1995          * so sanitize this register.
1996          */
1997         cdctl = intel_de_read(dev_priv, CDCLK_CTL);
1998         /*
1999          * Let's ignore the pipe field, since BIOS could have configured the
2000          * dividers both synching to an active pipe, or asynchronously
2001          * (PIPE_NONE).
2002          */
2003         cdctl &= ~bxt_cdclk_cd2x_pipe(dev_priv, INVALID_PIPE);
2004
2005         /* Make sure this is a legal cdclk value for the platform */
2006         cdclk = bxt_calc_cdclk(dev_priv, dev_priv->display.cdclk.hw.cdclk);
2007         if (cdclk != dev_priv->display.cdclk.hw.cdclk)
2008                 goto sanitize;
2009
2010         /* Make sure the VCO is correct for the cdclk */
2011         vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk);
2012         if (vco != dev_priv->display.cdclk.hw.vco)
2013                 goto sanitize;
2014
2015         expected = skl_cdclk_decimal(cdclk);
2016
2017         /* Figure out what CD2X divider we should be using for this cdclk */
2018         if (HAS_CDCLK_SQUASH(dev_priv))
2019                 clock = dev_priv->display.cdclk.hw.vco / 2;
2020         else
2021                 clock = dev_priv->display.cdclk.hw.cdclk;
2022
2023         expected |= bxt_cdclk_cd2x_div_sel(dev_priv, clock,
2024                                            dev_priv->display.cdclk.hw.vco);
2025
2026         /*
2027          * Disable SSA Precharge when CD clock frequency < 500 MHz,
2028          * enable otherwise.
2029          */
2030         if ((IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) &&
2031             dev_priv->display.cdclk.hw.cdclk >= 500000)
2032                 expected |= BXT_CDCLK_SSA_PRECHARGE_ENABLE;
2033
2034         if (cdctl == expected)
2035                 /* All well; nothing to sanitize */
2036                 return;
2037
2038 sanitize:
2039         drm_dbg_kms(&dev_priv->drm, "Sanitizing cdclk programmed by pre-os\n");
2040
2041         /* force cdclk programming */
2042         dev_priv->display.cdclk.hw.cdclk = 0;
2043
2044         /* force full PLL disable + enable */
2045         dev_priv->display.cdclk.hw.vco = -1;
2046 }
2047
2048 static void bxt_cdclk_init_hw(struct drm_i915_private *dev_priv)
2049 {
2050         struct intel_cdclk_config cdclk_config;
2051
2052         bxt_sanitize_cdclk(dev_priv);
2053
2054         if (dev_priv->display.cdclk.hw.cdclk != 0 &&
2055             dev_priv->display.cdclk.hw.vco != 0)
2056                 return;
2057
2058         cdclk_config = dev_priv->display.cdclk.hw;
2059
2060         /*
2061          * FIXME:
2062          * - The initial CDCLK needs to be read from VBT.
2063          *   Need to make this change after VBT has changes for BXT.
2064          */
2065         cdclk_config.cdclk = bxt_calc_cdclk(dev_priv, 0);
2066         cdclk_config.vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk_config.cdclk);
2067         cdclk_config.voltage_level =
2068                 intel_cdclk_calc_voltage_level(dev_priv, cdclk_config.cdclk);
2069
2070         bxt_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE);
2071 }
2072
2073 static void bxt_cdclk_uninit_hw(struct drm_i915_private *dev_priv)
2074 {
2075         struct intel_cdclk_config cdclk_config = dev_priv->display.cdclk.hw;
2076
2077         cdclk_config.cdclk = cdclk_config.bypass;
2078         cdclk_config.vco = 0;
2079         cdclk_config.voltage_level =
2080                 intel_cdclk_calc_voltage_level(dev_priv, cdclk_config.cdclk);
2081
2082         bxt_set_cdclk(dev_priv, &cdclk_config, INVALID_PIPE);
2083 }
2084
2085 /**
2086  * intel_cdclk_init_hw - Initialize CDCLK hardware
2087  * @i915: i915 device
2088  *
2089  * Initialize CDCLK. This consists mainly of initializing dev_priv->display.cdclk.hw and
2090  * sanitizing the state of the hardware if needed. This is generally done only
2091  * during the display core initialization sequence, after which the DMC will
2092  * take care of turning CDCLK off/on as needed.
2093  */
2094 void intel_cdclk_init_hw(struct drm_i915_private *i915)
2095 {
2096         if (DISPLAY_VER(i915) >= 10 || IS_BROXTON(i915))
2097                 bxt_cdclk_init_hw(i915);
2098         else if (DISPLAY_VER(i915) == 9)
2099                 skl_cdclk_init_hw(i915);
2100 }
2101
2102 /**
2103  * intel_cdclk_uninit_hw - Uninitialize CDCLK hardware
2104  * @i915: i915 device
2105  *
2106  * Uninitialize CDCLK. This is done only during the display core
2107  * uninitialization sequence.
2108  */
2109 void intel_cdclk_uninit_hw(struct drm_i915_private *i915)
2110 {
2111         if (DISPLAY_VER(i915) >= 10 || IS_BROXTON(i915))
2112                 bxt_cdclk_uninit_hw(i915);
2113         else if (DISPLAY_VER(i915) == 9)
2114                 skl_cdclk_uninit_hw(i915);
2115 }
2116
2117 static bool intel_cdclk_can_crawl_and_squash(struct drm_i915_private *i915,
2118                                              const struct intel_cdclk_config *a,
2119                                              const struct intel_cdclk_config *b)
2120 {
2121         u16 old_waveform;
2122         u16 new_waveform;
2123
2124         drm_WARN_ON(&i915->drm, cdclk_pll_is_unknown(a->vco));
2125
2126         if (a->vco == 0 || b->vco == 0)
2127                 return false;
2128
2129         if (!HAS_CDCLK_CRAWL(i915) || !HAS_CDCLK_SQUASH(i915))
2130                 return false;
2131
2132         old_waveform = cdclk_squash_waveform(i915, a->cdclk);
2133         new_waveform = cdclk_squash_waveform(i915, b->cdclk);
2134
2135         return a->vco != b->vco &&
2136                old_waveform != new_waveform;
2137 }
2138
2139 static bool intel_cdclk_can_crawl(struct drm_i915_private *dev_priv,
2140                                   const struct intel_cdclk_config *a,
2141                                   const struct intel_cdclk_config *b)
2142 {
2143         int a_div, b_div;
2144
2145         if (!HAS_CDCLK_CRAWL(dev_priv))
2146                 return false;
2147
2148         /*
2149          * The vco and cd2x divider will change independently
2150          * from each, so we disallow cd2x change when crawling.
2151          */
2152         a_div = DIV_ROUND_CLOSEST(a->vco, a->cdclk);
2153         b_div = DIV_ROUND_CLOSEST(b->vco, b->cdclk);
2154
2155         return a->vco != 0 && b->vco != 0 &&
2156                 a->vco != b->vco &&
2157                 a_div == b_div &&
2158                 a->ref == b->ref;
2159 }
2160
2161 static bool intel_cdclk_can_squash(struct drm_i915_private *dev_priv,
2162                                    const struct intel_cdclk_config *a,
2163                                    const struct intel_cdclk_config *b)
2164 {
2165         /*
2166          * FIXME should store a bit more state in intel_cdclk_config
2167          * to differentiate squasher vs. cd2x divider properly. For
2168          * the moment all platforms with squasher use a fixed cd2x
2169          * divider.
2170          */
2171         if (!HAS_CDCLK_SQUASH(dev_priv))
2172                 return false;
2173
2174         return a->cdclk != b->cdclk &&
2175                 a->vco != 0 &&
2176                 a->vco == b->vco &&
2177                 a->ref == b->ref;
2178 }
2179
2180 /**
2181  * intel_cdclk_needs_modeset - Determine if changong between the CDCLK
2182  *                             configurations requires a modeset on all pipes
2183  * @a: first CDCLK configuration
2184  * @b: second CDCLK configuration
2185  *
2186  * Returns:
2187  * True if changing between the two CDCLK configurations
2188  * requires all pipes to be off, false if not.
2189  */
2190 bool intel_cdclk_needs_modeset(const struct intel_cdclk_config *a,
2191                                const struct intel_cdclk_config *b)
2192 {
2193         return a->cdclk != b->cdclk ||
2194                 a->vco != b->vco ||
2195                 a->ref != b->ref;
2196 }
2197
2198 /**
2199  * intel_cdclk_can_cd2x_update - Determine if changing between the two CDCLK
2200  *                               configurations requires only a cd2x divider update
2201  * @dev_priv: i915 device
2202  * @a: first CDCLK configuration
2203  * @b: second CDCLK configuration
2204  *
2205  * Returns:
2206  * True if changing between the two CDCLK configurations
2207  * can be done with just a cd2x divider update, false if not.
2208  */
2209 static bool intel_cdclk_can_cd2x_update(struct drm_i915_private *dev_priv,
2210                                         const struct intel_cdclk_config *a,
2211                                         const struct intel_cdclk_config *b)
2212 {
2213         /* Older hw doesn't have the capability */
2214         if (DISPLAY_VER(dev_priv) < 10 && !IS_BROXTON(dev_priv))
2215                 return false;
2216
2217         /*
2218          * FIXME should store a bit more state in intel_cdclk_config
2219          * to differentiate squasher vs. cd2x divider properly. For
2220          * the moment all platforms with squasher use a fixed cd2x
2221          * divider.
2222          */
2223         if (HAS_CDCLK_SQUASH(dev_priv))
2224                 return false;
2225
2226         return a->cdclk != b->cdclk &&
2227                 a->vco != 0 &&
2228                 a->vco == b->vco &&
2229                 a->ref == b->ref;
2230 }
2231
2232 /**
2233  * intel_cdclk_changed - Determine if two CDCLK configurations are different
2234  * @a: first CDCLK configuration
2235  * @b: second CDCLK configuration
2236  *
2237  * Returns:
2238  * True if the CDCLK configurations don't match, false if they do.
2239  */
2240 static bool intel_cdclk_changed(const struct intel_cdclk_config *a,
2241                                 const struct intel_cdclk_config *b)
2242 {
2243         return intel_cdclk_needs_modeset(a, b) ||
2244                 a->voltage_level != b->voltage_level;
2245 }
2246
2247 void intel_cdclk_dump_config(struct drm_i915_private *i915,
2248                              const struct intel_cdclk_config *cdclk_config,
2249                              const char *context)
2250 {
2251         drm_dbg_kms(&i915->drm, "%s %d kHz, VCO %d kHz, ref %d kHz, bypass %d kHz, voltage level %d\n",
2252                     context, cdclk_config->cdclk, cdclk_config->vco,
2253                     cdclk_config->ref, cdclk_config->bypass,
2254                     cdclk_config->voltage_level);
2255 }
2256
2257 static void intel_pcode_notify(struct drm_i915_private *i915,
2258                                u8 voltage_level,
2259                                u8 active_pipe_count,
2260                                u16 cdclk,
2261                                bool cdclk_update_valid,
2262                                bool pipe_count_update_valid)
2263 {
2264         int ret;
2265         u32 update_mask = 0;
2266
2267         if (!IS_DG2(i915))
2268                 return;
2269
2270         update_mask = DISPLAY_TO_PCODE_UPDATE_MASK(cdclk, active_pipe_count, voltage_level);
2271
2272         if (cdclk_update_valid)
2273                 update_mask |= DISPLAY_TO_PCODE_CDCLK_VALID;
2274
2275         if (pipe_count_update_valid)
2276                 update_mask |= DISPLAY_TO_PCODE_PIPE_COUNT_VALID;
2277
2278         ret = skl_pcode_request(&i915->uncore, SKL_PCODE_CDCLK_CONTROL,
2279                                 SKL_CDCLK_PREPARE_FOR_CHANGE |
2280                                 update_mask,
2281                                 SKL_CDCLK_READY_FOR_CHANGE,
2282                                 SKL_CDCLK_READY_FOR_CHANGE, 3);
2283         if (ret)
2284                 drm_err(&i915->drm,
2285                         "Failed to inform PCU about display config (err %d)\n",
2286                         ret);
2287 }
2288
2289 /**
2290  * intel_set_cdclk - Push the CDCLK configuration to the hardware
2291  * @dev_priv: i915 device
2292  * @cdclk_config: new CDCLK configuration
2293  * @pipe: pipe with which to synchronize the update
2294  *
2295  * Program the hardware based on the passed in CDCLK state,
2296  * if necessary.
2297  */
2298 static void intel_set_cdclk(struct drm_i915_private *dev_priv,
2299                             const struct intel_cdclk_config *cdclk_config,
2300                             enum pipe pipe)
2301 {
2302         struct intel_encoder *encoder;
2303
2304         if (!intel_cdclk_changed(&dev_priv->display.cdclk.hw, cdclk_config))
2305                 return;
2306
2307         if (drm_WARN_ON_ONCE(&dev_priv->drm, !dev_priv->display.funcs.cdclk->set_cdclk))
2308                 return;
2309
2310         intel_cdclk_dump_config(dev_priv, cdclk_config, "Changing CDCLK to");
2311
2312         for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {
2313                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2314
2315                 intel_psr_pause(intel_dp);
2316         }
2317
2318         intel_audio_cdclk_change_pre(dev_priv);
2319
2320         /*
2321          * Lock aux/gmbus while we change cdclk in case those
2322          * functions use cdclk. Not all platforms/ports do,
2323          * but we'll lock them all for simplicity.
2324          */
2325         mutex_lock(&dev_priv->display.gmbus.mutex);
2326         for_each_intel_dp(&dev_priv->drm, encoder) {
2327                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2328
2329                 mutex_lock_nest_lock(&intel_dp->aux.hw_mutex,
2330                                      &dev_priv->display.gmbus.mutex);
2331         }
2332
2333         intel_cdclk_set_cdclk(dev_priv, cdclk_config, pipe);
2334
2335         for_each_intel_dp(&dev_priv->drm, encoder) {
2336                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2337
2338                 mutex_unlock(&intel_dp->aux.hw_mutex);
2339         }
2340         mutex_unlock(&dev_priv->display.gmbus.mutex);
2341
2342         for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) {
2343                 struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
2344
2345                 intel_psr_resume(intel_dp);
2346         }
2347
2348         intel_audio_cdclk_change_post(dev_priv);
2349
2350         if (drm_WARN(&dev_priv->drm,
2351                      intel_cdclk_changed(&dev_priv->display.cdclk.hw, cdclk_config),
2352                      "cdclk state doesn't match!\n")) {
2353                 intel_cdclk_dump_config(dev_priv, &dev_priv->display.cdclk.hw, "[hw state]");
2354                 intel_cdclk_dump_config(dev_priv, cdclk_config, "[sw state]");
2355         }
2356 }
2357
2358 static void intel_cdclk_pcode_pre_notify(struct intel_atomic_state *state)
2359 {
2360         struct drm_i915_private *i915 = to_i915(state->base.dev);
2361         const struct intel_cdclk_state *old_cdclk_state =
2362                 intel_atomic_get_old_cdclk_state(state);
2363         const struct intel_cdclk_state *new_cdclk_state =
2364                 intel_atomic_get_new_cdclk_state(state);
2365         unsigned int cdclk = 0; u8 voltage_level, num_active_pipes = 0;
2366         bool change_cdclk, update_pipe_count;
2367
2368         if (!intel_cdclk_changed(&old_cdclk_state->actual,
2369                                  &new_cdclk_state->actual) &&
2370                                  new_cdclk_state->active_pipes ==
2371                                  old_cdclk_state->active_pipes)
2372                 return;
2373
2374         /* According to "Sequence Before Frequency Change", voltage level set to 0x3 */
2375         voltage_level = DISPLAY_TO_PCODE_VOLTAGE_MAX;
2376
2377         change_cdclk = new_cdclk_state->actual.cdclk != old_cdclk_state->actual.cdclk;
2378         update_pipe_count = hweight8(new_cdclk_state->active_pipes) >
2379                             hweight8(old_cdclk_state->active_pipes);
2380
2381         /*
2382          * According to "Sequence Before Frequency Change",
2383          * if CDCLK is increasing, set bits 25:16 to upcoming CDCLK,
2384          * if CDCLK is decreasing or not changing, set bits 25:16 to current CDCLK,
2385          * which basically means we choose the maximum of old and new CDCLK, if we know both
2386          */
2387         if (change_cdclk)
2388                 cdclk = max(new_cdclk_state->actual.cdclk, old_cdclk_state->actual.cdclk);
2389
2390         /*
2391          * According to "Sequence For Pipe Count Change",
2392          * if pipe count is increasing, set bits 25:16 to upcoming pipe count
2393          * (power well is enabled)
2394          * no action if it is decreasing, before the change
2395          */
2396         if (update_pipe_count)
2397                 num_active_pipes = hweight8(new_cdclk_state->active_pipes);
2398
2399         intel_pcode_notify(i915, voltage_level, num_active_pipes, cdclk,
2400                            change_cdclk, update_pipe_count);
2401 }
2402
2403 static void intel_cdclk_pcode_post_notify(struct intel_atomic_state *state)
2404 {
2405         struct drm_i915_private *i915 = to_i915(state->base.dev);
2406         const struct intel_cdclk_state *new_cdclk_state =
2407                 intel_atomic_get_new_cdclk_state(state);
2408         const struct intel_cdclk_state *old_cdclk_state =
2409                 intel_atomic_get_old_cdclk_state(state);
2410         unsigned int cdclk = 0; u8 voltage_level, num_active_pipes = 0;
2411         bool update_cdclk, update_pipe_count;
2412
2413         /* According to "Sequence After Frequency Change", set voltage to used level */
2414         voltage_level = new_cdclk_state->actual.voltage_level;
2415
2416         update_cdclk = new_cdclk_state->actual.cdclk != old_cdclk_state->actual.cdclk;
2417         update_pipe_count = hweight8(new_cdclk_state->active_pipes) <
2418                             hweight8(old_cdclk_state->active_pipes);
2419
2420         /*
2421          * According to "Sequence After Frequency Change",
2422          * set bits 25:16 to current CDCLK
2423          */
2424         if (update_cdclk)
2425                 cdclk = new_cdclk_state->actual.cdclk;
2426
2427         /*
2428          * According to "Sequence For Pipe Count Change",
2429          * if pipe count is decreasing, set bits 25:16 to current pipe count,
2430          * after the change(power well is disabled)
2431          * no action if it is increasing, after the change
2432          */
2433         if (update_pipe_count)
2434                 num_active_pipes = hweight8(new_cdclk_state->active_pipes);
2435
2436         intel_pcode_notify(i915, voltage_level, num_active_pipes, cdclk,
2437                            update_cdclk, update_pipe_count);
2438 }
2439
2440 /**
2441  * intel_set_cdclk_pre_plane_update - Push the CDCLK state to the hardware
2442  * @state: intel atomic state
2443  *
2444  * Program the hardware before updating the HW plane state based on the
2445  * new CDCLK state, if necessary.
2446  */
2447 void
2448 intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state)
2449 {
2450         struct drm_i915_private *i915 = to_i915(state->base.dev);
2451         const struct intel_cdclk_state *old_cdclk_state =
2452                 intel_atomic_get_old_cdclk_state(state);
2453         const struct intel_cdclk_state *new_cdclk_state =
2454                 intel_atomic_get_new_cdclk_state(state);
2455         enum pipe pipe = new_cdclk_state->pipe;
2456
2457         if (!intel_cdclk_changed(&old_cdclk_state->actual,
2458                                  &new_cdclk_state->actual))
2459                 return;
2460
2461         if (IS_DG2(i915))
2462                 intel_cdclk_pcode_pre_notify(state);
2463
2464         if (pipe == INVALID_PIPE ||
2465             old_cdclk_state->actual.cdclk <= new_cdclk_state->actual.cdclk) {
2466                 drm_WARN_ON(&i915->drm, !new_cdclk_state->base.changed);
2467
2468                 intel_set_cdclk(i915, &new_cdclk_state->actual, pipe);
2469         }
2470 }
2471
2472 /**
2473  * intel_set_cdclk_post_plane_update - Push the CDCLK state to the hardware
2474  * @state: intel atomic state
2475  *
2476  * Program the hardware after updating the HW plane state based on the
2477  * new CDCLK state, if necessary.
2478  */
2479 void
2480 intel_set_cdclk_post_plane_update(struct intel_atomic_state *state)
2481 {
2482         struct drm_i915_private *i915 = to_i915(state->base.dev);
2483         const struct intel_cdclk_state *old_cdclk_state =
2484                 intel_atomic_get_old_cdclk_state(state);
2485         const struct intel_cdclk_state *new_cdclk_state =
2486                 intel_atomic_get_new_cdclk_state(state);
2487         enum pipe pipe = new_cdclk_state->pipe;
2488
2489         if (!intel_cdclk_changed(&old_cdclk_state->actual,
2490                                  &new_cdclk_state->actual))
2491                 return;
2492
2493         if (IS_DG2(i915))
2494                 intel_cdclk_pcode_post_notify(state);
2495
2496         if (pipe != INVALID_PIPE &&
2497             old_cdclk_state->actual.cdclk > new_cdclk_state->actual.cdclk) {
2498                 drm_WARN_ON(&i915->drm, !new_cdclk_state->base.changed);
2499
2500                 intel_set_cdclk(i915, &new_cdclk_state->actual, pipe);
2501         }
2502 }
2503
2504 static int intel_pixel_rate_to_cdclk(const struct intel_crtc_state *crtc_state)
2505 {
2506         struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
2507         int pixel_rate = crtc_state->pixel_rate;
2508
2509         if (DISPLAY_VER(dev_priv) >= 10)
2510                 return DIV_ROUND_UP(pixel_rate, 2);
2511         else if (DISPLAY_VER(dev_priv) == 9 ||
2512                  IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
2513                 return pixel_rate;
2514         else if (IS_CHERRYVIEW(dev_priv))
2515                 return DIV_ROUND_UP(pixel_rate * 100, 95);
2516         else if (crtc_state->double_wide)
2517                 return DIV_ROUND_UP(pixel_rate * 100, 90 * 2);
2518         else
2519                 return DIV_ROUND_UP(pixel_rate * 100, 90);
2520 }
2521
2522 static int intel_planes_min_cdclk(const struct intel_crtc_state *crtc_state)
2523 {
2524         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
2525         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2526         struct intel_plane *plane;
2527         int min_cdclk = 0;
2528
2529         for_each_intel_plane_on_crtc(&dev_priv->drm, crtc, plane)
2530                 min_cdclk = max(crtc_state->min_cdclk[plane->id], min_cdclk);
2531
2532         return min_cdclk;
2533 }
2534
2535 int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
2536 {
2537         struct drm_i915_private *dev_priv =
2538                 to_i915(crtc_state->uapi.crtc->dev);
2539         int min_cdclk;
2540
2541         if (!crtc_state->hw.enable)
2542                 return 0;
2543
2544         min_cdclk = intel_pixel_rate_to_cdclk(crtc_state);
2545
2546         /* pixel rate mustn't exceed 95% of cdclk with IPS on BDW */
2547         if (IS_BROADWELL(dev_priv) && hsw_crtc_state_ips_capable(crtc_state))
2548                 min_cdclk = DIV_ROUND_UP(min_cdclk * 100, 95);
2549
2550         /* BSpec says "Do not use DisplayPort with CDCLK less than 432 MHz,
2551          * audio enabled, port width x4, and link rate HBR2 (5.4 GHz), or else
2552          * there may be audio corruption or screen corruption." This cdclk
2553          * restriction for GLK is 316.8 MHz.
2554          */
2555         if (intel_crtc_has_dp_encoder(crtc_state) &&
2556             crtc_state->has_audio &&
2557             crtc_state->port_clock >= 540000 &&
2558             crtc_state->lane_count == 4) {
2559                 if (DISPLAY_VER(dev_priv) == 10) {
2560                         /* Display WA #1145: glk */
2561                         min_cdclk = max(316800, min_cdclk);
2562                 } else if (DISPLAY_VER(dev_priv) == 9 || IS_BROADWELL(dev_priv)) {
2563                         /* Display WA #1144: skl,bxt */
2564                         min_cdclk = max(432000, min_cdclk);
2565                 }
2566         }
2567
2568         /*
2569          * According to BSpec, "The CD clock frequency must be at least twice
2570          * the frequency of the Azalia BCLK." and BCLK is 96 MHz by default.
2571          */
2572         if (crtc_state->has_audio && DISPLAY_VER(dev_priv) >= 9)
2573                 min_cdclk = max(2 * 96000, min_cdclk);
2574
2575         /*
2576          * "For DP audio configuration, cdclk frequency shall be set to
2577          *  meet the following requirements:
2578          *  DP Link Frequency(MHz) | Cdclk frequency(MHz)
2579          *  270                    | 320 or higher
2580          *  162                    | 200 or higher"
2581          */
2582         if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
2583             intel_crtc_has_dp_encoder(crtc_state) && crtc_state->has_audio)
2584                 min_cdclk = max(crtc_state->port_clock, min_cdclk);
2585
2586         /*
2587          * On Valleyview some DSI panels lose (v|h)sync when the clock is lower
2588          * than 320000KHz.
2589          */
2590         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) &&
2591             IS_VALLEYVIEW(dev_priv))
2592                 min_cdclk = max(320000, min_cdclk);
2593
2594         /*
2595          * On Geminilake once the CDCLK gets as low as 79200
2596          * picture gets unstable, despite that values are
2597          * correct for DSI PLL and DE PLL.
2598          */
2599         if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) &&
2600             IS_GEMINILAKE(dev_priv))
2601                 min_cdclk = max(158400, min_cdclk);
2602
2603         /* Account for additional needs from the planes */
2604         min_cdclk = max(intel_planes_min_cdclk(crtc_state), min_cdclk);
2605
2606         /*
2607          * When we decide to use only one VDSC engine, since
2608          * each VDSC operates with 1 ppc throughput, pixel clock
2609          * cannot be higher than the VDSC clock (cdclk)
2610          */
2611         if (crtc_state->dsc.compression_enable && !crtc_state->dsc.dsc_split)
2612                 min_cdclk = max(min_cdclk, (int)crtc_state->pixel_rate);
2613
2614         /*
2615          * HACK. Currently for TGL/DG2 platforms we calculate
2616          * min_cdclk initially based on pixel_rate divided
2617          * by 2, accounting for also plane requirements,
2618          * however in some cases the lowest possible CDCLK
2619          * doesn't work and causing the underruns.
2620          * Explicitly stating here that this seems to be currently
2621          * rather a Hack, than final solution.
2622          */
2623         if (IS_TIGERLAKE(dev_priv) || IS_DG2(dev_priv)) {
2624                 /*
2625                  * Clamp to max_cdclk_freq in case pixel rate is higher,
2626                  * in order not to break an 8K, but still leave W/A at place.
2627                  */
2628                 min_cdclk = max_t(int, min_cdclk,
2629                                   min_t(int, crtc_state->pixel_rate,
2630                                         dev_priv->display.cdclk.max_cdclk_freq));
2631         }
2632
2633         return min_cdclk;
2634 }
2635
2636 static int intel_compute_min_cdclk(struct intel_cdclk_state *cdclk_state)
2637 {
2638         struct intel_atomic_state *state = cdclk_state->base.state;
2639         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
2640         const struct intel_bw_state *bw_state;
2641         struct intel_crtc *crtc;
2642         struct intel_crtc_state *crtc_state;
2643         int min_cdclk, i;
2644         enum pipe pipe;
2645
2646         for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
2647                 int ret;
2648
2649                 min_cdclk = intel_crtc_compute_min_cdclk(crtc_state);
2650                 if (min_cdclk < 0)
2651                         return min_cdclk;
2652
2653                 if (cdclk_state->min_cdclk[crtc->pipe] == min_cdclk)
2654                         continue;
2655
2656                 cdclk_state->min_cdclk[crtc->pipe] = min_cdclk;
2657
2658                 ret = intel_atomic_lock_global_state(&cdclk_state->base);
2659                 if (ret)
2660                         return ret;
2661         }
2662
2663         bw_state = intel_atomic_get_new_bw_state(state);
2664         if (bw_state) {
2665                 min_cdclk = intel_bw_min_cdclk(dev_priv, bw_state);
2666
2667                 if (cdclk_state->bw_min_cdclk != min_cdclk) {
2668                         int ret;
2669
2670                         cdclk_state->bw_min_cdclk = min_cdclk;
2671
2672                         ret = intel_atomic_lock_global_state(&cdclk_state->base);
2673                         if (ret)
2674                                 return ret;
2675                 }
2676         }
2677
2678         min_cdclk = max(cdclk_state->force_min_cdclk,
2679                         cdclk_state->bw_min_cdclk);
2680         for_each_pipe(dev_priv, pipe)
2681                 min_cdclk = max(cdclk_state->min_cdclk[pipe], min_cdclk);
2682
2683         if (min_cdclk > dev_priv->display.cdclk.max_cdclk_freq) {
2684                 drm_dbg_kms(&dev_priv->drm,
2685                             "required cdclk (%d kHz) exceeds max (%d kHz)\n",
2686                             min_cdclk, dev_priv->display.cdclk.max_cdclk_freq);
2687                 return -EINVAL;
2688         }
2689
2690         return min_cdclk;
2691 }
2692
2693 /*
2694  * Account for port clock min voltage level requirements.
2695  * This only really does something on DISPLA_VER >= 11 but can be
2696  * called on earlier platforms as well.
2697  *
2698  * Note that this functions assumes that 0 is
2699  * the lowest voltage value, and higher values
2700  * correspond to increasingly higher voltages.
2701  *
2702  * Should that relationship no longer hold on
2703  * future platforms this code will need to be
2704  * adjusted.
2705  */
2706 static int bxt_compute_min_voltage_level(struct intel_cdclk_state *cdclk_state)
2707 {
2708         struct intel_atomic_state *state = cdclk_state->base.state;
2709         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
2710         struct intel_crtc *crtc;
2711         struct intel_crtc_state *crtc_state;
2712         u8 min_voltage_level;
2713         int i;
2714         enum pipe pipe;
2715
2716         for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
2717                 int ret;
2718
2719                 if (crtc_state->hw.enable)
2720                         min_voltage_level = crtc_state->min_voltage_level;
2721                 else
2722                         min_voltage_level = 0;
2723
2724                 if (cdclk_state->min_voltage_level[crtc->pipe] == min_voltage_level)
2725                         continue;
2726
2727                 cdclk_state->min_voltage_level[crtc->pipe] = min_voltage_level;
2728
2729                 ret = intel_atomic_lock_global_state(&cdclk_state->base);
2730                 if (ret)
2731                         return ret;
2732         }
2733
2734         min_voltage_level = 0;
2735         for_each_pipe(dev_priv, pipe)
2736                 min_voltage_level = max(cdclk_state->min_voltage_level[pipe],
2737                                         min_voltage_level);
2738
2739         return min_voltage_level;
2740 }
2741
2742 static int vlv_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state)
2743 {
2744         struct intel_atomic_state *state = cdclk_state->base.state;
2745         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
2746         int min_cdclk, cdclk;
2747
2748         min_cdclk = intel_compute_min_cdclk(cdclk_state);
2749         if (min_cdclk < 0)
2750                 return min_cdclk;
2751
2752         cdclk = vlv_calc_cdclk(dev_priv, min_cdclk);
2753
2754         cdclk_state->logical.cdclk = cdclk;
2755         cdclk_state->logical.voltage_level =
2756                 vlv_calc_voltage_level(dev_priv, cdclk);
2757
2758         if (!cdclk_state->active_pipes) {
2759                 cdclk = vlv_calc_cdclk(dev_priv, cdclk_state->force_min_cdclk);
2760
2761                 cdclk_state->actual.cdclk = cdclk;
2762                 cdclk_state->actual.voltage_level =
2763                         vlv_calc_voltage_level(dev_priv, cdclk);
2764         } else {
2765                 cdclk_state->actual = cdclk_state->logical;
2766         }
2767
2768         return 0;
2769 }
2770
2771 static int bdw_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state)
2772 {
2773         int min_cdclk, cdclk;
2774
2775         min_cdclk = intel_compute_min_cdclk(cdclk_state);
2776         if (min_cdclk < 0)
2777                 return min_cdclk;
2778
2779         cdclk = bdw_calc_cdclk(min_cdclk);
2780
2781         cdclk_state->logical.cdclk = cdclk;
2782         cdclk_state->logical.voltage_level =
2783                 bdw_calc_voltage_level(cdclk);
2784
2785         if (!cdclk_state->active_pipes) {
2786                 cdclk = bdw_calc_cdclk(cdclk_state->force_min_cdclk);
2787
2788                 cdclk_state->actual.cdclk = cdclk;
2789                 cdclk_state->actual.voltage_level =
2790                         bdw_calc_voltage_level(cdclk);
2791         } else {
2792                 cdclk_state->actual = cdclk_state->logical;
2793         }
2794
2795         return 0;
2796 }
2797
2798 static int skl_dpll0_vco(struct intel_cdclk_state *cdclk_state)
2799 {
2800         struct intel_atomic_state *state = cdclk_state->base.state;
2801         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
2802         struct intel_crtc *crtc;
2803         struct intel_crtc_state *crtc_state;
2804         int vco, i;
2805
2806         vco = cdclk_state->logical.vco;
2807         if (!vco)
2808                 vco = dev_priv->skl_preferred_vco_freq;
2809
2810         for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
2811                 if (!crtc_state->hw.enable)
2812                         continue;
2813
2814                 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
2815                         continue;
2816
2817                 /*
2818                  * DPLL0 VCO may need to be adjusted to get the correct
2819                  * clock for eDP. This will affect cdclk as well.
2820                  */
2821                 switch (crtc_state->port_clock / 2) {
2822                 case 108000:
2823                 case 216000:
2824                         vco = 8640000;
2825                         break;
2826                 default:
2827                         vco = 8100000;
2828                         break;
2829                 }
2830         }
2831
2832         return vco;
2833 }
2834
2835 static int skl_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state)
2836 {
2837         int min_cdclk, cdclk, vco;
2838
2839         min_cdclk = intel_compute_min_cdclk(cdclk_state);
2840         if (min_cdclk < 0)
2841                 return min_cdclk;
2842
2843         vco = skl_dpll0_vco(cdclk_state);
2844
2845         cdclk = skl_calc_cdclk(min_cdclk, vco);
2846
2847         cdclk_state->logical.vco = vco;
2848         cdclk_state->logical.cdclk = cdclk;
2849         cdclk_state->logical.voltage_level =
2850                 skl_calc_voltage_level(cdclk);
2851
2852         if (!cdclk_state->active_pipes) {
2853                 cdclk = skl_calc_cdclk(cdclk_state->force_min_cdclk, vco);
2854
2855                 cdclk_state->actual.vco = vco;
2856                 cdclk_state->actual.cdclk = cdclk;
2857                 cdclk_state->actual.voltage_level =
2858                         skl_calc_voltage_level(cdclk);
2859         } else {
2860                 cdclk_state->actual = cdclk_state->logical;
2861         }
2862
2863         return 0;
2864 }
2865
2866 static int bxt_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state)
2867 {
2868         struct intel_atomic_state *state = cdclk_state->base.state;
2869         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
2870         int min_cdclk, min_voltage_level, cdclk, vco;
2871
2872         min_cdclk = intel_compute_min_cdclk(cdclk_state);
2873         if (min_cdclk < 0)
2874                 return min_cdclk;
2875
2876         min_voltage_level = bxt_compute_min_voltage_level(cdclk_state);
2877         if (min_voltage_level < 0)
2878                 return min_voltage_level;
2879
2880         cdclk = bxt_calc_cdclk(dev_priv, min_cdclk);
2881         vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk);
2882
2883         cdclk_state->logical.vco = vco;
2884         cdclk_state->logical.cdclk = cdclk;
2885         cdclk_state->logical.voltage_level =
2886                 max_t(int, min_voltage_level,
2887                       intel_cdclk_calc_voltage_level(dev_priv, cdclk));
2888
2889         if (!cdclk_state->active_pipes) {
2890                 cdclk = bxt_calc_cdclk(dev_priv, cdclk_state->force_min_cdclk);
2891                 vco = bxt_calc_cdclk_pll_vco(dev_priv, cdclk);
2892
2893                 cdclk_state->actual.vco = vco;
2894                 cdclk_state->actual.cdclk = cdclk;
2895                 cdclk_state->actual.voltage_level =
2896                         intel_cdclk_calc_voltage_level(dev_priv, cdclk);
2897         } else {
2898                 cdclk_state->actual = cdclk_state->logical;
2899         }
2900
2901         return 0;
2902 }
2903
2904 static int fixed_modeset_calc_cdclk(struct intel_cdclk_state *cdclk_state)
2905 {
2906         int min_cdclk;
2907
2908         /*
2909          * We can't change the cdclk frequency, but we still want to
2910          * check that the required minimum frequency doesn't exceed
2911          * the actual cdclk frequency.
2912          */
2913         min_cdclk = intel_compute_min_cdclk(cdclk_state);
2914         if (min_cdclk < 0)
2915                 return min_cdclk;
2916
2917         return 0;
2918 }
2919
2920 static struct intel_global_state *intel_cdclk_duplicate_state(struct intel_global_obj *obj)
2921 {
2922         struct intel_cdclk_state *cdclk_state;
2923
2924         cdclk_state = kmemdup(obj->state, sizeof(*cdclk_state), GFP_KERNEL);
2925         if (!cdclk_state)
2926                 return NULL;
2927
2928         cdclk_state->pipe = INVALID_PIPE;
2929
2930         return &cdclk_state->base;
2931 }
2932
2933 static void intel_cdclk_destroy_state(struct intel_global_obj *obj,
2934                                       struct intel_global_state *state)
2935 {
2936         kfree(state);
2937 }
2938
2939 static const struct intel_global_state_funcs intel_cdclk_funcs = {
2940         .atomic_duplicate_state = intel_cdclk_duplicate_state,
2941         .atomic_destroy_state = intel_cdclk_destroy_state,
2942 };
2943
2944 struct intel_cdclk_state *
2945 intel_atomic_get_cdclk_state(struct intel_atomic_state *state)
2946 {
2947         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
2948         struct intel_global_state *cdclk_state;
2949
2950         cdclk_state = intel_atomic_get_global_obj_state(state, &dev_priv->display.cdclk.obj);
2951         if (IS_ERR(cdclk_state))
2952                 return ERR_CAST(cdclk_state);
2953
2954         return to_intel_cdclk_state(cdclk_state);
2955 }
2956
2957 int intel_cdclk_atomic_check(struct intel_atomic_state *state,
2958                              bool *need_cdclk_calc)
2959 {
2960         const struct intel_cdclk_state *old_cdclk_state;
2961         const struct intel_cdclk_state *new_cdclk_state;
2962         struct intel_plane_state *plane_state;
2963         struct intel_plane *plane;
2964         int ret;
2965         int i;
2966
2967         /*
2968          * active_planes bitmask has been updated, and potentially affected
2969          * planes are part of the state. We can now compute the minimum cdclk
2970          * for each plane.
2971          */
2972         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
2973                 ret = intel_plane_calc_min_cdclk(state, plane, need_cdclk_calc);
2974                 if (ret)
2975                         return ret;
2976         }
2977
2978         ret = intel_bw_calc_min_cdclk(state, need_cdclk_calc);
2979         if (ret)
2980                 return ret;
2981
2982         old_cdclk_state = intel_atomic_get_old_cdclk_state(state);
2983         new_cdclk_state = intel_atomic_get_new_cdclk_state(state);
2984
2985         if (new_cdclk_state &&
2986             old_cdclk_state->force_min_cdclk != new_cdclk_state->force_min_cdclk)
2987                 *need_cdclk_calc = true;
2988
2989         return 0;
2990 }
2991
2992 int intel_cdclk_init(struct drm_i915_private *dev_priv)
2993 {
2994         struct intel_cdclk_state *cdclk_state;
2995
2996         cdclk_state = kzalloc(sizeof(*cdclk_state), GFP_KERNEL);
2997         if (!cdclk_state)
2998                 return -ENOMEM;
2999
3000         intel_atomic_global_obj_init(dev_priv, &dev_priv->display.cdclk.obj,
3001                                      &cdclk_state->base, &intel_cdclk_funcs);
3002
3003         return 0;
3004 }
3005
3006 static bool intel_cdclk_need_serialize(struct drm_i915_private *i915,
3007                                        const struct intel_cdclk_state *old_cdclk_state,
3008                                        const struct intel_cdclk_state *new_cdclk_state)
3009 {
3010         bool power_well_cnt_changed = hweight8(old_cdclk_state->active_pipes) !=
3011                                       hweight8(new_cdclk_state->active_pipes);
3012         bool cdclk_changed = intel_cdclk_changed(&old_cdclk_state->actual,
3013                                                  &new_cdclk_state->actual);
3014         /*
3015          * We need to poke hw for gen >= 12, because we notify PCode if
3016          * pipe power well count changes.
3017          */
3018         return cdclk_changed || (IS_DG2(i915) && power_well_cnt_changed);
3019 }
3020
3021 int intel_modeset_calc_cdclk(struct intel_atomic_state *state)
3022 {
3023         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
3024         const struct intel_cdclk_state *old_cdclk_state;
3025         struct intel_cdclk_state *new_cdclk_state;
3026         enum pipe pipe = INVALID_PIPE;
3027         int ret;
3028
3029         new_cdclk_state = intel_atomic_get_cdclk_state(state);
3030         if (IS_ERR(new_cdclk_state))
3031                 return PTR_ERR(new_cdclk_state);
3032
3033         old_cdclk_state = intel_atomic_get_old_cdclk_state(state);
3034
3035         new_cdclk_state->active_pipes =
3036                 intel_calc_active_pipes(state, old_cdclk_state->active_pipes);
3037
3038         ret = intel_cdclk_modeset_calc_cdclk(dev_priv, new_cdclk_state);
3039         if (ret)
3040                 return ret;
3041
3042         if (intel_cdclk_need_serialize(dev_priv, old_cdclk_state, new_cdclk_state)) {
3043                 /*
3044                  * Also serialize commits across all crtcs
3045                  * if the actual hw needs to be poked.
3046                  */
3047                 ret = intel_atomic_serialize_global_state(&new_cdclk_state->base);
3048                 if (ret)
3049                         return ret;
3050         } else if (old_cdclk_state->active_pipes != new_cdclk_state->active_pipes ||
3051                    old_cdclk_state->force_min_cdclk != new_cdclk_state->force_min_cdclk ||
3052                    intel_cdclk_changed(&old_cdclk_state->logical,
3053                                        &new_cdclk_state->logical)) {
3054                 ret = intel_atomic_lock_global_state(&new_cdclk_state->base);
3055                 if (ret)
3056                         return ret;
3057         } else {
3058                 return 0;
3059         }
3060
3061         if (is_power_of_2(new_cdclk_state->active_pipes) &&
3062             intel_cdclk_can_cd2x_update(dev_priv,
3063                                         &old_cdclk_state->actual,
3064                                         &new_cdclk_state->actual)) {
3065                 struct intel_crtc *crtc;
3066                 struct intel_crtc_state *crtc_state;
3067
3068                 pipe = ilog2(new_cdclk_state->active_pipes);
3069                 crtc = intel_crtc_for_pipe(dev_priv, pipe);
3070
3071                 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
3072                 if (IS_ERR(crtc_state))
3073                         return PTR_ERR(crtc_state);
3074
3075                 if (intel_crtc_needs_modeset(crtc_state))
3076                         pipe = INVALID_PIPE;
3077         }
3078
3079         if (intel_cdclk_can_crawl_and_squash(dev_priv,
3080                                              &old_cdclk_state->actual,
3081                                              &new_cdclk_state->actual)) {
3082                 drm_dbg_kms(&dev_priv->drm,
3083                             "Can change cdclk via crawling and squashing\n");
3084         } else if (intel_cdclk_can_squash(dev_priv,
3085                                         &old_cdclk_state->actual,
3086                                         &new_cdclk_state->actual)) {
3087                 drm_dbg_kms(&dev_priv->drm,
3088                             "Can change cdclk via squashing\n");
3089         } else if (intel_cdclk_can_crawl(dev_priv,
3090                                          &old_cdclk_state->actual,
3091                                          &new_cdclk_state->actual)) {
3092                 drm_dbg_kms(&dev_priv->drm,
3093                             "Can change cdclk via crawling\n");
3094         } else if (pipe != INVALID_PIPE) {
3095                 new_cdclk_state->pipe = pipe;
3096
3097                 drm_dbg_kms(&dev_priv->drm,
3098                             "Can change cdclk cd2x divider with pipe %c active\n",
3099                             pipe_name(pipe));
3100         } else if (intel_cdclk_needs_modeset(&old_cdclk_state->actual,
3101                                              &new_cdclk_state->actual)) {
3102                 /* All pipes must be switched off while we change the cdclk. */
3103                 ret = intel_modeset_all_pipes(state, "CDCLK change");
3104                 if (ret)
3105                         return ret;
3106
3107                 drm_dbg_kms(&dev_priv->drm,
3108                             "Modeset required for cdclk change\n");
3109         }
3110
3111         drm_dbg_kms(&dev_priv->drm,
3112                     "New cdclk calculated to be logical %u kHz, actual %u kHz\n",
3113                     new_cdclk_state->logical.cdclk,
3114                     new_cdclk_state->actual.cdclk);
3115         drm_dbg_kms(&dev_priv->drm,
3116                     "New voltage level calculated to be logical %u, actual %u\n",
3117                     new_cdclk_state->logical.voltage_level,
3118                     new_cdclk_state->actual.voltage_level);
3119
3120         return 0;
3121 }
3122
3123 static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv)
3124 {
3125         int max_cdclk_freq = dev_priv->display.cdclk.max_cdclk_freq;
3126
3127         if (DISPLAY_VER(dev_priv) >= 10)
3128                 return 2 * max_cdclk_freq;
3129         else if (DISPLAY_VER(dev_priv) == 9 ||
3130                  IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv))
3131                 return max_cdclk_freq;
3132         else if (IS_CHERRYVIEW(dev_priv))
3133                 return max_cdclk_freq*95/100;
3134         else if (DISPLAY_VER(dev_priv) < 4)
3135                 return 2*max_cdclk_freq*90/100;
3136         else
3137                 return max_cdclk_freq*90/100;
3138 }
3139
3140 /**
3141  * intel_update_max_cdclk - Determine the maximum support CDCLK frequency
3142  * @dev_priv: i915 device
3143  *
3144  * Determine the maximum CDCLK frequency the platform supports, and also
3145  * derive the maximum dot clock frequency the maximum CDCLK frequency
3146  * allows.
3147  */
3148 void intel_update_max_cdclk(struct drm_i915_private *dev_priv)
3149 {
3150         if (IS_JSL_EHL(dev_priv)) {
3151                 if (dev_priv->display.cdclk.hw.ref == 24000)
3152                         dev_priv->display.cdclk.max_cdclk_freq = 552000;
3153                 else
3154                         dev_priv->display.cdclk.max_cdclk_freq = 556800;
3155         } else if (DISPLAY_VER(dev_priv) >= 11) {
3156                 if (dev_priv->display.cdclk.hw.ref == 24000)
3157                         dev_priv->display.cdclk.max_cdclk_freq = 648000;
3158                 else
3159                         dev_priv->display.cdclk.max_cdclk_freq = 652800;
3160         } else if (IS_GEMINILAKE(dev_priv)) {
3161                 dev_priv->display.cdclk.max_cdclk_freq = 316800;
3162         } else if (IS_BROXTON(dev_priv)) {
3163                 dev_priv->display.cdclk.max_cdclk_freq = 624000;
3164         } else if (DISPLAY_VER(dev_priv) == 9) {
3165                 u32 limit = intel_de_read(dev_priv, SKL_DFSM) & SKL_DFSM_CDCLK_LIMIT_MASK;
3166                 int max_cdclk, vco;
3167
3168                 vco = dev_priv->skl_preferred_vco_freq;
3169                 drm_WARN_ON(&dev_priv->drm, vco != 8100000 && vco != 8640000);
3170
3171                 /*
3172                  * Use the lower (vco 8640) cdclk values as a
3173                  * first guess. skl_calc_cdclk() will correct it
3174                  * if the preferred vco is 8100 instead.
3175                  */
3176                 if (limit == SKL_DFSM_CDCLK_LIMIT_675)
3177                         max_cdclk = 617143;
3178                 else if (limit == SKL_DFSM_CDCLK_LIMIT_540)
3179                         max_cdclk = 540000;
3180                 else if (limit == SKL_DFSM_CDCLK_LIMIT_450)
3181                         max_cdclk = 432000;
3182                 else
3183                         max_cdclk = 308571;
3184
3185                 dev_priv->display.cdclk.max_cdclk_freq = skl_calc_cdclk(max_cdclk, vco);
3186         } else if (IS_BROADWELL(dev_priv))  {
3187                 /*
3188                  * FIXME with extra cooling we can allow
3189                  * 540 MHz for ULX and 675 Mhz for ULT.
3190                  * How can we know if extra cooling is
3191                  * available? PCI ID, VTB, something else?
3192                  */
3193                 if (intel_de_read(dev_priv, FUSE_STRAP) & HSW_CDCLK_LIMIT)
3194                         dev_priv->display.cdclk.max_cdclk_freq = 450000;
3195                 else if (IS_BDW_ULX(dev_priv))
3196                         dev_priv->display.cdclk.max_cdclk_freq = 450000;
3197                 else if (IS_BDW_ULT(dev_priv))
3198                         dev_priv->display.cdclk.max_cdclk_freq = 540000;
3199                 else
3200                         dev_priv->display.cdclk.max_cdclk_freq = 675000;
3201         } else if (IS_CHERRYVIEW(dev_priv)) {
3202                 dev_priv->display.cdclk.max_cdclk_freq = 320000;
3203         } else if (IS_VALLEYVIEW(dev_priv)) {
3204                 dev_priv->display.cdclk.max_cdclk_freq = 400000;
3205         } else {
3206                 /* otherwise assume cdclk is fixed */
3207                 dev_priv->display.cdclk.max_cdclk_freq = dev_priv->display.cdclk.hw.cdclk;
3208         }
3209
3210         dev_priv->max_dotclk_freq = intel_compute_max_dotclk(dev_priv);
3211
3212         drm_dbg(&dev_priv->drm, "Max CD clock rate: %d kHz\n",
3213                 dev_priv->display.cdclk.max_cdclk_freq);
3214
3215         drm_dbg(&dev_priv->drm, "Max dotclock rate: %d kHz\n",
3216                 dev_priv->max_dotclk_freq);
3217 }
3218
3219 /**
3220  * intel_update_cdclk - Determine the current CDCLK frequency
3221  * @dev_priv: i915 device
3222  *
3223  * Determine the current CDCLK frequency.
3224  */
3225 void intel_update_cdclk(struct drm_i915_private *dev_priv)
3226 {
3227         intel_cdclk_get_cdclk(dev_priv, &dev_priv->display.cdclk.hw);
3228
3229         /*
3230          * 9:0 CMBUS [sic] CDCLK frequency (cdfreq):
3231          * Programmng [sic] note: bit[9:2] should be programmed to the number
3232          * of cdclk that generates 4MHz reference clock freq which is used to
3233          * generate GMBus clock. This will vary with the cdclk freq.
3234          */
3235         if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
3236                 intel_de_write(dev_priv, GMBUSFREQ_VLV,
3237                                DIV_ROUND_UP(dev_priv->display.cdclk.hw.cdclk, 1000));
3238 }
3239
3240 static int dg1_rawclk(struct drm_i915_private *dev_priv)
3241 {
3242         /*
3243          * DG1 always uses a 38.4 MHz rawclk.  The bspec tells us
3244          * "Program Numerator=2, Denominator=4, Divider=37 decimal."
3245          */
3246         intel_de_write(dev_priv, PCH_RAWCLK_FREQ,
3247                        CNP_RAWCLK_DEN(4) | CNP_RAWCLK_DIV(37) | ICP_RAWCLK_NUM(2));
3248
3249         return 38400;
3250 }
3251
3252 static int cnp_rawclk(struct drm_i915_private *dev_priv)
3253 {
3254         u32 rawclk;
3255         int divider, fraction;
3256
3257         if (intel_de_read(dev_priv, SFUSE_STRAP) & SFUSE_STRAP_RAW_FREQUENCY) {
3258                 /* 24 MHz */
3259                 divider = 24000;
3260                 fraction = 0;
3261         } else {
3262                 /* 19.2 MHz */
3263                 divider = 19000;
3264                 fraction = 200;
3265         }
3266
3267         rawclk = CNP_RAWCLK_DIV(divider / 1000);
3268         if (fraction) {
3269                 int numerator = 1;
3270
3271                 rawclk |= CNP_RAWCLK_DEN(DIV_ROUND_CLOSEST(numerator * 1000,
3272                                                            fraction) - 1);
3273                 if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
3274                         rawclk |= ICP_RAWCLK_NUM(numerator);
3275         }
3276
3277         intel_de_write(dev_priv, PCH_RAWCLK_FREQ, rawclk);
3278         return divider + fraction;
3279 }
3280
3281 static int pch_rawclk(struct drm_i915_private *dev_priv)
3282 {
3283         return (intel_de_read(dev_priv, PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK) * 1000;
3284 }
3285
3286 static int vlv_hrawclk(struct drm_i915_private *dev_priv)
3287 {
3288         /* RAWCLK_FREQ_VLV register updated from power well code */
3289         return vlv_get_cck_clock_hpll(dev_priv, "hrawclk",
3290                                       CCK_DISPLAY_REF_CLOCK_CONTROL);
3291 }
3292
3293 static int i9xx_hrawclk(struct drm_i915_private *dev_priv)
3294 {
3295         u32 clkcfg;
3296
3297         /*
3298          * hrawclock is 1/4 the FSB frequency
3299          *
3300          * Note that this only reads the state of the FSB
3301          * straps, not the actual FSB frequency. Some BIOSen
3302          * let you configure each independently. Ideally we'd
3303          * read out the actual FSB frequency but sadly we
3304          * don't know which registers have that information,
3305          * and all the relevant docs have gone to bit heaven :(
3306          */
3307         clkcfg = intel_de_read(dev_priv, CLKCFG) & CLKCFG_FSB_MASK;
3308
3309         if (IS_MOBILE(dev_priv)) {
3310                 switch (clkcfg) {
3311                 case CLKCFG_FSB_400:
3312                         return 100000;
3313                 case CLKCFG_FSB_533:
3314                         return 133333;
3315                 case CLKCFG_FSB_667:
3316                         return 166667;
3317                 case CLKCFG_FSB_800:
3318                         return 200000;
3319                 case CLKCFG_FSB_1067:
3320                         return 266667;
3321                 case CLKCFG_FSB_1333:
3322                         return 333333;
3323                 default:
3324                         MISSING_CASE(clkcfg);
3325                         return 133333;
3326                 }
3327         } else {
3328                 switch (clkcfg) {
3329                 case CLKCFG_FSB_400_ALT:
3330                         return 100000;
3331                 case CLKCFG_FSB_533:
3332                         return 133333;
3333                 case CLKCFG_FSB_667:
3334                         return 166667;
3335                 case CLKCFG_FSB_800:
3336                         return 200000;
3337                 case CLKCFG_FSB_1067_ALT:
3338                         return 266667;
3339                 case CLKCFG_FSB_1333_ALT:
3340                         return 333333;
3341                 case CLKCFG_FSB_1600_ALT:
3342                         return 400000;
3343                 default:
3344                         return 133333;
3345                 }
3346         }
3347 }
3348
3349 /**
3350  * intel_read_rawclk - Determine the current RAWCLK frequency
3351  * @dev_priv: i915 device
3352  *
3353  * Determine the current RAWCLK frequency. RAWCLK is a fixed
3354  * frequency clock so this needs to done only once.
3355  */
3356 u32 intel_read_rawclk(struct drm_i915_private *dev_priv)
3357 {
3358         u32 freq;
3359
3360         if (INTEL_PCH_TYPE(dev_priv) >= PCH_DG1)
3361                 freq = dg1_rawclk(dev_priv);
3362         else if (INTEL_PCH_TYPE(dev_priv) >= PCH_MTP)
3363                 /*
3364                  * MTL always uses a 38.4 MHz rawclk.  The bspec tells us
3365                  * "RAWCLK_FREQ defaults to the values for 38.4 and does
3366                  * not need to be programmed."
3367                  */
3368                 freq = 38400;
3369         else if (INTEL_PCH_TYPE(dev_priv) >= PCH_CNP)
3370                 freq = cnp_rawclk(dev_priv);
3371         else if (HAS_PCH_SPLIT(dev_priv))
3372                 freq = pch_rawclk(dev_priv);
3373         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
3374                 freq = vlv_hrawclk(dev_priv);
3375         else if (DISPLAY_VER(dev_priv) >= 3)
3376                 freq = i9xx_hrawclk(dev_priv);
3377         else
3378                 /* no rawclk on other platforms, or no need to know it */
3379                 return 0;
3380
3381         return freq;
3382 }
3383
3384 static int i915_cdclk_info_show(struct seq_file *m, void *unused)
3385 {
3386         struct drm_i915_private *i915 = m->private;
3387
3388         seq_printf(m, "Current CD clock frequency: %d kHz\n", i915->display.cdclk.hw.cdclk);
3389         seq_printf(m, "Max CD clock frequency: %d kHz\n", i915->display.cdclk.max_cdclk_freq);
3390         seq_printf(m, "Max pixel clock frequency: %d kHz\n", i915->max_dotclk_freq);
3391
3392         return 0;
3393 }
3394
3395 DEFINE_SHOW_ATTRIBUTE(i915_cdclk_info);
3396
3397 void intel_cdclk_debugfs_register(struct drm_i915_private *i915)
3398 {
3399         struct drm_minor *minor = i915->drm.primary;
3400
3401         debugfs_create_file("i915_cdclk_info", 0444, minor->debugfs_root,
3402                             i915, &i915_cdclk_info_fops);
3403 }
3404
3405 static const struct intel_cdclk_funcs mtl_cdclk_funcs = {
3406         .get_cdclk = bxt_get_cdclk,
3407         .set_cdclk = bxt_set_cdclk,
3408         .modeset_calc_cdclk = bxt_modeset_calc_cdclk,
3409         .calc_voltage_level = tgl_calc_voltage_level,
3410 };
3411
3412 static const struct intel_cdclk_funcs rplu_cdclk_funcs = {
3413         .get_cdclk = bxt_get_cdclk,
3414         .set_cdclk = bxt_set_cdclk,
3415         .modeset_calc_cdclk = bxt_modeset_calc_cdclk,
3416         .calc_voltage_level = rplu_calc_voltage_level,
3417 };
3418
3419 static const struct intel_cdclk_funcs tgl_cdclk_funcs = {
3420         .get_cdclk = bxt_get_cdclk,
3421         .set_cdclk = bxt_set_cdclk,
3422         .modeset_calc_cdclk = bxt_modeset_calc_cdclk,
3423         .calc_voltage_level = tgl_calc_voltage_level,
3424 };
3425
3426 static const struct intel_cdclk_funcs ehl_cdclk_funcs = {
3427         .get_cdclk = bxt_get_cdclk,
3428         .set_cdclk = bxt_set_cdclk,
3429         .modeset_calc_cdclk = bxt_modeset_calc_cdclk,
3430         .calc_voltage_level = ehl_calc_voltage_level,
3431 };
3432
3433 static const struct intel_cdclk_funcs icl_cdclk_funcs = {
3434         .get_cdclk = bxt_get_cdclk,
3435         .set_cdclk = bxt_set_cdclk,
3436         .modeset_calc_cdclk = bxt_modeset_calc_cdclk,
3437         .calc_voltage_level = icl_calc_voltage_level,
3438 };
3439
3440 static const struct intel_cdclk_funcs bxt_cdclk_funcs = {
3441         .get_cdclk = bxt_get_cdclk,
3442         .set_cdclk = bxt_set_cdclk,
3443         .modeset_calc_cdclk = bxt_modeset_calc_cdclk,
3444         .calc_voltage_level = bxt_calc_voltage_level,
3445 };
3446
3447 static const struct intel_cdclk_funcs skl_cdclk_funcs = {
3448         .get_cdclk = skl_get_cdclk,
3449         .set_cdclk = skl_set_cdclk,
3450         .modeset_calc_cdclk = skl_modeset_calc_cdclk,
3451 };
3452
3453 static const struct intel_cdclk_funcs bdw_cdclk_funcs = {
3454         .get_cdclk = bdw_get_cdclk,
3455         .set_cdclk = bdw_set_cdclk,
3456         .modeset_calc_cdclk = bdw_modeset_calc_cdclk,
3457 };
3458
3459 static const struct intel_cdclk_funcs chv_cdclk_funcs = {
3460         .get_cdclk = vlv_get_cdclk,
3461         .set_cdclk = chv_set_cdclk,
3462         .modeset_calc_cdclk = vlv_modeset_calc_cdclk,
3463 };
3464
3465 static const struct intel_cdclk_funcs vlv_cdclk_funcs = {
3466         .get_cdclk = vlv_get_cdclk,
3467         .set_cdclk = vlv_set_cdclk,
3468         .modeset_calc_cdclk = vlv_modeset_calc_cdclk,
3469 };
3470
3471 static const struct intel_cdclk_funcs hsw_cdclk_funcs = {
3472         .get_cdclk = hsw_get_cdclk,
3473         .modeset_calc_cdclk = fixed_modeset_calc_cdclk,
3474 };
3475
3476 /* SNB, IVB, 965G, 945G */
3477 static const struct intel_cdclk_funcs fixed_400mhz_cdclk_funcs = {
3478         .get_cdclk = fixed_400mhz_get_cdclk,
3479         .modeset_calc_cdclk = fixed_modeset_calc_cdclk,
3480 };
3481
3482 static const struct intel_cdclk_funcs ilk_cdclk_funcs = {
3483         .get_cdclk = fixed_450mhz_get_cdclk,
3484         .modeset_calc_cdclk = fixed_modeset_calc_cdclk,
3485 };
3486
3487 static const struct intel_cdclk_funcs gm45_cdclk_funcs = {
3488         .get_cdclk = gm45_get_cdclk,
3489         .modeset_calc_cdclk = fixed_modeset_calc_cdclk,
3490 };
3491
3492 /* G45 uses G33 */
3493
3494 static const struct intel_cdclk_funcs i965gm_cdclk_funcs = {
3495         .get_cdclk = i965gm_get_cdclk,
3496         .modeset_calc_cdclk = fixed_modeset_calc_cdclk,
3497 };
3498
3499 /* i965G uses fixed 400 */
3500
3501 static const struct intel_cdclk_funcs pnv_cdclk_funcs = {
3502         .get_cdclk = pnv_get_cdclk,
3503         .modeset_calc_cdclk = fixed_modeset_calc_cdclk,
3504 };
3505
3506 static const struct intel_cdclk_funcs g33_cdclk_funcs = {
3507         .get_cdclk = g33_get_cdclk,
3508         .modeset_calc_cdclk = fixed_modeset_calc_cdclk,
3509 };
3510
3511 static const struct intel_cdclk_funcs i945gm_cdclk_funcs = {
3512         .get_cdclk = i945gm_get_cdclk,
3513         .modeset_calc_cdclk = fixed_modeset_calc_cdclk,
3514 };
3515
3516 /* i945G uses fixed 400 */
3517
3518 static const struct intel_cdclk_funcs i915gm_cdclk_funcs = {
3519         .get_cdclk = i915gm_get_cdclk,
3520         .modeset_calc_cdclk = fixed_modeset_calc_cdclk,
3521 };
3522
3523 static const struct intel_cdclk_funcs i915g_cdclk_funcs = {
3524         .get_cdclk = fixed_333mhz_get_cdclk,
3525         .modeset_calc_cdclk = fixed_modeset_calc_cdclk,
3526 };
3527
3528 static const struct intel_cdclk_funcs i865g_cdclk_funcs = {
3529         .get_cdclk = fixed_266mhz_get_cdclk,
3530         .modeset_calc_cdclk = fixed_modeset_calc_cdclk,
3531 };
3532
3533 static const struct intel_cdclk_funcs i85x_cdclk_funcs = {
3534         .get_cdclk = i85x_get_cdclk,
3535         .modeset_calc_cdclk = fixed_modeset_calc_cdclk,
3536 };
3537
3538 static const struct intel_cdclk_funcs i845g_cdclk_funcs = {
3539         .get_cdclk = fixed_200mhz_get_cdclk,
3540         .modeset_calc_cdclk = fixed_modeset_calc_cdclk,
3541 };
3542
3543 static const struct intel_cdclk_funcs i830_cdclk_funcs = {
3544         .get_cdclk = fixed_133mhz_get_cdclk,
3545         .modeset_calc_cdclk = fixed_modeset_calc_cdclk,
3546 };
3547
3548 /**
3549  * intel_init_cdclk_hooks - Initialize CDCLK related modesetting hooks
3550  * @dev_priv: i915 device
3551  */
3552 void intel_init_cdclk_hooks(struct drm_i915_private *dev_priv)
3553 {
3554         if (IS_METEORLAKE(dev_priv)) {
3555                 dev_priv->display.funcs.cdclk = &mtl_cdclk_funcs;
3556                 dev_priv->display.cdclk.table = mtl_cdclk_table;
3557         } else if (IS_DG2(dev_priv)) {
3558                 dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
3559                 dev_priv->display.cdclk.table = dg2_cdclk_table;
3560         } else if (IS_ALDERLAKE_P(dev_priv)) {
3561                 /* Wa_22011320316:adl-p[a0] */
3562                 if (IS_ADLP_DISPLAY_STEP(dev_priv, STEP_A0, STEP_B0)) {
3563                         dev_priv->display.cdclk.table = adlp_a_step_cdclk_table;
3564                         dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
3565                 } else if (IS_ADLP_RPLU(dev_priv)) {
3566                         dev_priv->display.cdclk.table = rplu_cdclk_table;
3567                         dev_priv->display.funcs.cdclk = &rplu_cdclk_funcs;
3568                 } else {
3569                         dev_priv->display.cdclk.table = adlp_cdclk_table;
3570                         dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
3571                 }
3572         } else if (IS_ROCKETLAKE(dev_priv)) {
3573                 dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
3574                 dev_priv->display.cdclk.table = rkl_cdclk_table;
3575         } else if (DISPLAY_VER(dev_priv) >= 12) {
3576                 dev_priv->display.funcs.cdclk = &tgl_cdclk_funcs;
3577                 dev_priv->display.cdclk.table = icl_cdclk_table;
3578         } else if (IS_JSL_EHL(dev_priv)) {
3579                 dev_priv->display.funcs.cdclk = &ehl_cdclk_funcs;
3580                 dev_priv->display.cdclk.table = icl_cdclk_table;
3581         } else if (DISPLAY_VER(dev_priv) >= 11) {
3582                 dev_priv->display.funcs.cdclk = &icl_cdclk_funcs;
3583                 dev_priv->display.cdclk.table = icl_cdclk_table;
3584         } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) {
3585                 dev_priv->display.funcs.cdclk = &bxt_cdclk_funcs;
3586                 if (IS_GEMINILAKE(dev_priv))
3587                         dev_priv->display.cdclk.table = glk_cdclk_table;
3588                 else
3589                         dev_priv->display.cdclk.table = bxt_cdclk_table;
3590         } else if (DISPLAY_VER(dev_priv) == 9) {
3591                 dev_priv->display.funcs.cdclk = &skl_cdclk_funcs;
3592         } else if (IS_BROADWELL(dev_priv)) {
3593                 dev_priv->display.funcs.cdclk = &bdw_cdclk_funcs;
3594         } else if (IS_HASWELL(dev_priv)) {
3595                 dev_priv->display.funcs.cdclk = &hsw_cdclk_funcs;
3596         } else if (IS_CHERRYVIEW(dev_priv)) {
3597                 dev_priv->display.funcs.cdclk = &chv_cdclk_funcs;
3598         } else if (IS_VALLEYVIEW(dev_priv)) {
3599                 dev_priv->display.funcs.cdclk = &vlv_cdclk_funcs;
3600         } else if (IS_SANDYBRIDGE(dev_priv) || IS_IVYBRIDGE(dev_priv)) {
3601                 dev_priv->display.funcs.cdclk = &fixed_400mhz_cdclk_funcs;
3602         } else if (IS_IRONLAKE(dev_priv)) {
3603                 dev_priv->display.funcs.cdclk = &ilk_cdclk_funcs;
3604         } else if (IS_GM45(dev_priv)) {
3605                 dev_priv->display.funcs.cdclk = &gm45_cdclk_funcs;
3606         } else if (IS_G45(dev_priv)) {
3607                 dev_priv->display.funcs.cdclk = &g33_cdclk_funcs;
3608         } else if (IS_I965GM(dev_priv)) {
3609                 dev_priv->display.funcs.cdclk = &i965gm_cdclk_funcs;
3610         } else if (IS_I965G(dev_priv)) {
3611                 dev_priv->display.funcs.cdclk = &fixed_400mhz_cdclk_funcs;
3612         } else if (IS_PINEVIEW(dev_priv)) {
3613                 dev_priv->display.funcs.cdclk = &pnv_cdclk_funcs;
3614         } else if (IS_G33(dev_priv)) {
3615                 dev_priv->display.funcs.cdclk = &g33_cdclk_funcs;
3616         } else if (IS_I945GM(dev_priv)) {
3617                 dev_priv->display.funcs.cdclk = &i945gm_cdclk_funcs;
3618         } else if (IS_I945G(dev_priv)) {
3619                 dev_priv->display.funcs.cdclk = &fixed_400mhz_cdclk_funcs;
3620         } else if (IS_I915GM(dev_priv)) {
3621                 dev_priv->display.funcs.cdclk = &i915gm_cdclk_funcs;
3622         } else if (IS_I915G(dev_priv)) {
3623                 dev_priv->display.funcs.cdclk = &i915g_cdclk_funcs;
3624         } else if (IS_I865G(dev_priv)) {
3625                 dev_priv->display.funcs.cdclk = &i865g_cdclk_funcs;
3626         } else if (IS_I85X(dev_priv)) {
3627                 dev_priv->display.funcs.cdclk = &i85x_cdclk_funcs;
3628         } else if (IS_I845G(dev_priv)) {
3629                 dev_priv->display.funcs.cdclk = &i845g_cdclk_funcs;
3630         } else if (IS_I830(dev_priv)) {
3631                 dev_priv->display.funcs.cdclk = &i830_cdclk_funcs;
3632         }
3633
3634         if (drm_WARN(&dev_priv->drm, !dev_priv->display.funcs.cdclk,
3635                      "Unknown platform. Assuming i830\n"))
3636                 dev_priv->display.funcs.cdclk = &i830_cdclk_funcs;
3637 }