drivers/gpu/drm/i915/display/intel_bw.c

   1 // SPDX-License-Identifier: MIT
   2 /*
   3  * Copyright © 2019 Intel Corporation
   4  */
   5
   6 #include <drm/drm_atomic_state_helper.h>
   7
   8 #include "i915_drv.h"
   9 #include "i915_reg.h"
  10 #include "i915_utils.h"
  11 #include "intel_atomic.h"
  12 #include "intel_bw.h"
  13 #include "intel_cdclk.h"
  14 #include "intel_display_core.h"
  15 #include "intel_display_types.h"
  16 #include "skl_watermark.h"
  17 #include "intel_mchbar_regs.h"
  18 #include "intel_pcode.h"
  19
  20 /* Parameters for Qclk Geyserville (QGV) */
  21 struct intel_qgv_point {
  22         u16 dclk, t_rp, t_rdpre, t_rc, t_ras, t_rcd;
  23 };
  24
  25 struct intel_psf_gv_point {
  26         u8 clk; /* clock in multiples of 16.6666 MHz */
  27 };
  28
  29 struct intel_qgv_info {
  30         struct intel_qgv_point points[I915_NUM_QGV_POINTS];
  31         struct intel_psf_gv_point psf_points[I915_NUM_PSF_GV_POINTS];
  32         u8 num_points;
  33         u8 num_psf_points;
  34         u8 t_bl;
  35         u8 max_numchannels;
  36         u8 channel_width;
  37         u8 deinterleave;
  38 };
  39
  40 static int dg1_mchbar_read_qgv_point_info(struct drm_i915_private *dev_priv,
  41                                           struct intel_qgv_point *sp,
  42                                           int point)
  43 {
  44         u32 dclk_ratio, dclk_reference;
  45         u32 val;
  46
  47         val = intel_uncore_read(&dev_priv->uncore, SA_PERF_STATUS_0_0_0_MCHBAR_PC);
  48         dclk_ratio = REG_FIELD_GET(DG1_QCLK_RATIO_MASK, val);
  49         if (val & DG1_QCLK_REFERENCE)
  50                 dclk_reference = 6; /* 6 * 16.666 MHz = 100 MHz */
  51         else
  52                 dclk_reference = 8; /* 8 * 16.666 MHz = 133 MHz */
  53         sp->dclk = DIV_ROUND_UP((16667 * dclk_ratio * dclk_reference) + 500, 1000);
  54
  55         val = intel_uncore_read(&dev_priv->uncore, SKL_MC_BIOS_DATA_0_0_0_MCHBAR_PCU);
  56         if (val & DG1_GEAR_TYPE)
  57                 sp->dclk *= 2;
  58
  59         if (sp->dclk == 0)
  60                 return -EINVAL;
  61
  62         val = intel_uncore_read(&dev_priv->uncore, MCHBAR_CH0_CR_TC_PRE_0_0_0_MCHBAR);
  63         sp->t_rp = REG_FIELD_GET(DG1_DRAM_T_RP_MASK, val);
  64         sp->t_rdpre = REG_FIELD_GET(DG1_DRAM_T_RDPRE_MASK, val);
  65
  66         val = intel_uncore_read(&dev_priv->uncore, MCHBAR_CH0_CR_TC_PRE_0_0_0_MCHBAR_HIGH);
  67         sp->t_rcd = REG_FIELD_GET(DG1_DRAM_T_RCD_MASK, val);
  68         sp->t_ras = REG_FIELD_GET(DG1_DRAM_T_RAS_MASK, val);
  69
  70         sp->t_rc = sp->t_rp + sp->t_ras;
  71
  72         return 0;
  73 }
  74
  75 static int icl_pcode_read_qgv_point_info(struct drm_i915_private *dev_priv,
  76                                          struct intel_qgv_point *sp,
  77                                          int point)
  78 {
  79         u32 val = 0, val2 = 0;
  80         u16 dclk;
  81         int ret;
  82
  83         ret = snb_pcode_read(&dev_priv->uncore, ICL_PCODE_MEM_SUBSYSYSTEM_INFO |
  84                              ICL_PCODE_MEM_SS_READ_QGV_POINT_INFO(point),
  85                              &val, &val2);
  86         if (ret)
  87                 return ret;
  88
  89         dclk = val & 0xffff;
  90         sp->dclk = DIV_ROUND_UP((16667 * dclk) + (DISPLAY_VER(dev_priv) > 11 ? 500 : 0), 1000);
  91         sp->t_rp = (val & 0xff0000) >> 16;
  92         sp->t_rcd = (val & 0xff000000) >> 24;
  93
  94         sp->t_rdpre = val2 & 0xff;
  95         sp->t_ras = (val2 & 0xff00) >> 8;
  96
  97         sp->t_rc = sp->t_rp + sp->t_ras;
  98
  99         return 0;
 100 }
 101
 102 static int adls_pcode_read_psf_gv_point_info(struct drm_i915_private *dev_priv,
 103                                             struct intel_psf_gv_point *points)
 104 {
 105         u32 val = 0;
 106         int ret;
 107         int i;
 108
 109         ret = snb_pcode_read(&dev_priv->uncore, ICL_PCODE_MEM_SUBSYSYSTEM_INFO |
 110                              ADL_PCODE_MEM_SS_READ_PSF_GV_INFO, &val, NULL);
 111         if (ret)
 112                 return ret;
 113
 114         for (i = 0; i < I915_NUM_PSF_GV_POINTS; i++) {
 115                 points[i].clk = val & 0xff;
 116                 val >>= 8;
 117         }
 118
 119         return 0;
 120 }
 121
 122 static u16 icl_qgv_points_mask(struct drm_i915_private *i915)
 123 {
 124         unsigned int num_psf_gv_points = i915->display.bw.max[0].num_psf_gv_points;
 125         unsigned int num_qgv_points = i915->display.bw.max[0].num_qgv_points;
 126         u16 qgv_points = 0, psf_points = 0;
 127
 128         /*
 129          * We can _not_ use the whole ADLS_QGV_PT_MASK here, as PCode rejects
 130          * it with failure if we try masking any unadvertised points.
 131          * So need to operate only with those returned from PCode.
 132          */
 133         if (num_qgv_points > 0)
 134                 qgv_points = GENMASK(num_qgv_points - 1, 0);
 135
 136         if (num_psf_gv_points > 0)
 137                 psf_points = GENMASK(num_psf_gv_points - 1, 0);
 138
 139         return ICL_PCODE_REQ_QGV_PT(qgv_points) | ADLS_PCODE_REQ_PSF_PT(psf_points);
 140 }
 141
 142 static bool is_sagv_enabled(struct drm_i915_private *i915, u16 points_mask)
 143 {
 144         return !is_power_of_2(~points_mask & icl_qgv_points_mask(i915) &
 145                               ICL_PCODE_REQ_QGV_PT_MASK);
 146 }
 147
 148 int icl_pcode_restrict_qgv_points(struct drm_i915_private *dev_priv,
 149                                   u32 points_mask)
 150 {
 151         int ret;
 152
 153         if (DISPLAY_VER(dev_priv) >= 14)
 154                 return 0;
 155
 156         /* bspec says to keep retrying for at least 1 ms */
 157         ret = skl_pcode_request(&dev_priv->uncore, ICL_PCODE_SAGV_DE_MEM_SS_CONFIG,
 158                                 points_mask,
 159                                 ICL_PCODE_REP_QGV_MASK | ADLS_PCODE_REP_PSF_MASK,
 160                                 ICL_PCODE_REP_QGV_SAFE | ADLS_PCODE_REP_PSF_SAFE,
 161                                 1);
 162
 163         if (ret < 0) {
 164                 drm_err(&dev_priv->drm, "Failed to disable qgv points (%d) points: 0x%x\n", ret, points_mask);
 165                 return ret;
 166         }
 167
 168         dev_priv->display.sagv.status = is_sagv_enabled(dev_priv, points_mask) ?
 169                 I915_SAGV_ENABLED : I915_SAGV_DISABLED;
 170
 171         return 0;
 172 }
 173
 174 static int mtl_read_qgv_point_info(struct drm_i915_private *dev_priv,
 175                                    struct intel_qgv_point *sp, int point)
 176 {
 177         u32 val, val2;
 178         u16 dclk;
 179
 180         val = intel_uncore_read(&dev_priv->uncore,
 181                                 MTL_MEM_SS_INFO_QGV_POINT_LOW(point));
 182         val2 = intel_uncore_read(&dev_priv->uncore,
 183                                  MTL_MEM_SS_INFO_QGV_POINT_HIGH(point));
 184         dclk = REG_FIELD_GET(MTL_DCLK_MASK, val);
 185         sp->dclk = DIV_ROUND_UP((16667 * dclk), 1000);
 186         sp->t_rp = REG_FIELD_GET(MTL_TRP_MASK, val);
 187         sp->t_rcd = REG_FIELD_GET(MTL_TRCD_MASK, val);
 188
 189         sp->t_rdpre = REG_FIELD_GET(MTL_TRDPRE_MASK, val2);
 190         sp->t_ras = REG_FIELD_GET(MTL_TRAS_MASK, val2);
 191
 192         sp->t_rc = sp->t_rp + sp->t_ras;
 193
 194         return 0;
 195 }
 196
 197 static int
 198 intel_read_qgv_point_info(struct drm_i915_private *dev_priv,
 199                           struct intel_qgv_point *sp,
 200                           int point)
 201 {
 202         if (DISPLAY_VER(dev_priv) >= 14)
 203                 return mtl_read_qgv_point_info(dev_priv, sp, point);
 204         else if (IS_DG1(dev_priv))
 205                 return dg1_mchbar_read_qgv_point_info(dev_priv, sp, point);
 206         else
 207                 return icl_pcode_read_qgv_point_info(dev_priv, sp, point);
 208 }
 209
 210 static int icl_get_qgv_points(struct drm_i915_private *dev_priv,
 211                               struct intel_qgv_info *qi,
 212                               bool is_y_tile)
 213 {
 214         const struct dram_info *dram_info = &dev_priv->dram_info;
 215         int i, ret;
 216
 217         qi->num_points = dram_info->num_qgv_points;
 218         qi->num_psf_points = dram_info->num_psf_gv_points;
 219
 220         if (DISPLAY_VER(dev_priv) >= 14) {
 221                 switch (dram_info->type) {
 222                 case INTEL_DRAM_DDR4:
 223                         qi->t_bl = 4;
 224                         qi->max_numchannels = 2;
 225                         qi->channel_width = 64;
 226                         qi->deinterleave = 2;
 227                         break;
 228                 case INTEL_DRAM_DDR5:
 229                         qi->t_bl = 8;
 230                         qi->max_numchannels = 4;
 231                         qi->channel_width = 32;
 232                         qi->deinterleave = 2;
 233                         break;
 234                 case INTEL_DRAM_LPDDR4:
 235                 case INTEL_DRAM_LPDDR5:
 236                         qi->t_bl = 16;
 237                         qi->max_numchannels = 8;
 238                         qi->channel_width = 16;
 239                         qi->deinterleave = 4;
 240                         break;
 241                 default:
 242                         MISSING_CASE(dram_info->type);
 243                         return -EINVAL;
 244                 }
 245         } else if (DISPLAY_VER(dev_priv) >= 12) {
 246                 switch (dram_info->type) {
 247                 case INTEL_DRAM_DDR4:
 248                         qi->t_bl = is_y_tile ? 8 : 4;
 249                         qi->max_numchannels = 2;
 250                         qi->channel_width = 64;
 251                         qi->deinterleave = is_y_tile ? 1 : 2;
 252                         break;
 253                 case INTEL_DRAM_DDR5:
 254                         qi->t_bl = is_y_tile ? 16 : 8;
 255                         qi->max_numchannels = 4;
 256                         qi->channel_width = 32;
 257                         qi->deinterleave = is_y_tile ? 1 : 2;
 258                         break;
 259                 case INTEL_DRAM_LPDDR4:
 260                         if (IS_ROCKETLAKE(dev_priv)) {
 261                                 qi->t_bl = 8;
 262                                 qi->max_numchannels = 4;
 263                                 qi->channel_width = 32;
 264                                 qi->deinterleave = 2;
 265                                 break;
 266                         }
 267                         fallthrough;
 268                 case INTEL_DRAM_LPDDR5:
 269                         qi->t_bl = 16;
 270                         qi->max_numchannels = 8;
 271                         qi->channel_width = 16;
 272                         qi->deinterleave = is_y_tile ? 2 : 4;
 273                         break;
 274                 default:
 275                         qi->t_bl = 16;
 276                         qi->max_numchannels = 1;
 277                         break;
 278                 }
 279         } else if (DISPLAY_VER(dev_priv) == 11) {
 280                 qi->t_bl = dev_priv->dram_info.type == INTEL_DRAM_DDR4 ? 4 : 8;
 281                 qi->max_numchannels = 1;
 282         }
 283
 284         if (drm_WARN_ON(&dev_priv->drm,
 285                         qi->num_points > ARRAY_SIZE(qi->points)))
 286                 qi->num_points = ARRAY_SIZE(qi->points);
 287
 288         for (i = 0; i < qi->num_points; i++) {
 289                 struct intel_qgv_point *sp = &qi->points[i];
 290
 291                 ret = intel_read_qgv_point_info(dev_priv, sp, i);
 292                 if (ret)
 293                         return ret;
 294
 295                 drm_dbg_kms(&dev_priv->drm,
 296                             "QGV %d: DCLK=%d tRP=%d tRDPRE=%d tRAS=%d tRCD=%d tRC=%d\n",
 297                             i, sp->dclk, sp->t_rp, sp->t_rdpre, sp->t_ras,
 298                             sp->t_rcd, sp->t_rc);
 299         }
 300
 301         if (qi->num_psf_points > 0) {
 302                 ret = adls_pcode_read_psf_gv_point_info(dev_priv, qi->psf_points);
 303                 if (ret) {
 304                         drm_err(&dev_priv->drm, "Failed to read PSF point data; PSF points will not be considered in bandwidth calculations.\n");
 305                         qi->num_psf_points = 0;
 306                 }
 307
 308                 for (i = 0; i < qi->num_psf_points; i++)
 309                         drm_dbg_kms(&dev_priv->drm,
 310                                     "PSF GV %d: CLK=%d \n",
 311                                     i, qi->psf_points[i].clk);
 312         }
 313
 314         return 0;
 315 }
 316
 317 static int adl_calc_psf_bw(int clk)
 318 {
 319         /*
 320          * clk is multiples of 16.666MHz (100/6)
 321          * According to BSpec PSF GV bandwidth is
 322          * calculated as BW = 64 * clk * 16.666Mhz
 323          */
 324         return DIV_ROUND_CLOSEST(64 * clk * 100, 6);
 325 }
 326
 327 static int icl_sagv_max_dclk(const struct intel_qgv_info *qi)
 328 {
 329         u16 dclk = 0;
 330         int i;
 331
 332         for (i = 0; i < qi->num_points; i++)
 333                 dclk = max(dclk, qi->points[i].dclk);
 334
 335         return dclk;
 336 }
 337
 338 struct intel_sa_info {
 339         u16 displayrtids;
 340         u8 deburst, deprogbwlimit, derating;
 341 };
 342
 343 static const struct intel_sa_info icl_sa_info = {
 344         .deburst = 8,
 345         .deprogbwlimit = 25, /* GB/s */
 346         .displayrtids = 128,
 347         .derating = 10,
 348 };
 349
 350 static const struct intel_sa_info tgl_sa_info = {
 351         .deburst = 16,
 352         .deprogbwlimit = 34, /* GB/s */
 353         .displayrtids = 256,
 354         .derating = 10,
 355 };
 356
 357 static const struct intel_sa_info rkl_sa_info = {
 358         .deburst = 8,
 359         .deprogbwlimit = 20, /* GB/s */
 360         .displayrtids = 128,
 361         .derating = 10,
 362 };
 363
 364 static const struct intel_sa_info adls_sa_info = {
 365         .deburst = 16,
 366         .deprogbwlimit = 38, /* GB/s */
 367         .displayrtids = 256,
 368         .derating = 10,
 369 };
 370
 371 static const struct intel_sa_info adlp_sa_info = {
 372         .deburst = 16,
 373         .deprogbwlimit = 38, /* GB/s */
 374         .displayrtids = 256,
 375         .derating = 20,
 376 };
 377
 378 static const struct intel_sa_info mtl_sa_info = {
 379         .deburst = 32,
 380         .deprogbwlimit = 38, /* GB/s */
 381         .displayrtids = 256,
 382         .derating = 20,
 383 };
 384
 385 static int icl_get_bw_info(struct drm_i915_private *dev_priv, const struct intel_sa_info *sa)
 386 {
 387         struct intel_qgv_info qi = {};
 388         bool is_y_tile = true; /* assume y tile may be used */
 389         int num_channels = max_t(u8, 1, dev_priv->dram_info.num_channels);
 390         int ipqdepth, ipqdepthpch = 16;
 391         int dclk_max;
 392         int maxdebw;
 393         int num_groups = ARRAY_SIZE(dev_priv->display.bw.max);
 394         int i, ret;
 395
 396         ret = icl_get_qgv_points(dev_priv, &qi, is_y_tile);
 397         if (ret) {
 398                 drm_dbg_kms(&dev_priv->drm,
 399                             "Failed to get memory subsystem information, ignoring bandwidth limits");
 400                 return ret;
 401         }
 402
 403         dclk_max = icl_sagv_max_dclk(&qi);
 404         maxdebw = min(sa->deprogbwlimit * 1000, dclk_max * 16 * 6 / 10);
 405         ipqdepth = min(ipqdepthpch, sa->displayrtids / num_channels);
 406         qi.deinterleave = DIV_ROUND_UP(num_channels, is_y_tile ? 4 : 2);
 407
 408         for (i = 0; i < num_groups; i++) {
 409                 struct intel_bw_info *bi = &dev_priv->display.bw.max[i];
 410                 int clpchgroup;
 411                 int j;
 412
 413                 clpchgroup = (sa->deburst * qi.deinterleave / num_channels) << i;
 414                 bi->num_planes = (ipqdepth - clpchgroup) / clpchgroup + 1;
 415
 416                 bi->num_qgv_points = qi.num_points;
 417                 bi->num_psf_gv_points = qi.num_psf_points;
 418
 419                 for (j = 0; j < qi.num_points; j++) {
 420                         const struct intel_qgv_point *sp = &qi.points[j];
 421                         int ct, bw;
 422
 423                         /*
 424                          * Max row cycle time
 425                          *
 426                          * FIXME what is the logic behind the
 427                          * assumed burst length?
 428                          */
 429                         ct = max_t(int, sp->t_rc, sp->t_rp + sp->t_rcd +
 430                                    (clpchgroup - 1) * qi.t_bl + sp->t_rdpre);
 431                         bw = DIV_ROUND_UP(sp->dclk * clpchgroup * 32 * num_channels, ct);
 432
 433                         bi->deratedbw[j] = min(maxdebw,
 434                                                bw * (100 - sa->derating) / 100);
 435
 436                         drm_dbg_kms(&dev_priv->drm,
 437                                     "BW%d / QGV %d: num_planes=%d deratedbw=%u\n",
 438                                     i, j, bi->num_planes, bi->deratedbw[j]);
 439                 }
 440         }
 441         /*
 442          * In case if SAGV is disabled in BIOS, we always get 1
 443          * SAGV point, but we can't send PCode commands to restrict it
 444          * as it will fail and pointless anyway.
 445          */
 446         if (qi.num_points == 1)
 447                 dev_priv->display.sagv.status = I915_SAGV_NOT_CONTROLLED;
 448         else
 449                 dev_priv->display.sagv.status = I915_SAGV_ENABLED;
 450
 451         return 0;
 452 }
 453
 454 static int tgl_get_bw_info(struct drm_i915_private *dev_priv, const struct intel_sa_info *sa)
 455 {
 456         struct intel_qgv_info qi = {};
 457         const struct dram_info *dram_info = &dev_priv->dram_info;
 458         bool is_y_tile = true; /* assume y tile may be used */
 459         int num_channels = max_t(u8, 1, dev_priv->dram_info.num_channels);
 460         int ipqdepth, ipqdepthpch = 16;
 461         int dclk_max;
 462         int maxdebw, peakbw;
 463         int clperchgroup;
 464         int num_groups = ARRAY_SIZE(dev_priv->display.bw.max);
 465         int i, ret;
 466
 467         ret = icl_get_qgv_points(dev_priv, &qi, is_y_tile);
 468         if (ret) {
 469                 drm_dbg_kms(&dev_priv->drm,
 470                             "Failed to get memory subsystem information, ignoring bandwidth limits");
 471                 return ret;
 472         }
 473
 474         if (DISPLAY_VER(dev_priv) < 14 &&
 475             (dram_info->type == INTEL_DRAM_LPDDR4 || dram_info->type == INTEL_DRAM_LPDDR5))
 476                 num_channels *= 2;
 477
 478         qi.deinterleave = qi.deinterleave ? : DIV_ROUND_UP(num_channels, is_y_tile ? 4 : 2);
 479
 480         if (num_channels < qi.max_numchannels && DISPLAY_VER(dev_priv) >= 12)
 481                 qi.deinterleave = max(DIV_ROUND_UP(qi.deinterleave, 2), 1);
 482
 483         if (DISPLAY_VER(dev_priv) > 11 && num_channels > qi.max_numchannels)
 484                 drm_warn(&dev_priv->drm, "Number of channels exceeds max number of channels.");
 485         if (qi.max_numchannels != 0)
 486                 num_channels = min_t(u8, num_channels, qi.max_numchannels);
 487
 488         dclk_max = icl_sagv_max_dclk(&qi);
 489
 490         peakbw = num_channels * DIV_ROUND_UP(qi.channel_width, 8) * dclk_max;
 491         maxdebw = min(sa->deprogbwlimit * 1000, peakbw * 6 / 10); /* 60% */
 492
 493         ipqdepth = min(ipqdepthpch, sa->displayrtids / num_channels);
 494         /*
 495          * clperchgroup = 4kpagespermempage * clperchperblock,
 496          * clperchperblock = 8 / num_channels * interleave
 497          */
 498         clperchgroup = 4 * DIV_ROUND_UP(8, num_channels) * qi.deinterleave;
 499
 500         for (i = 0; i < num_groups; i++) {
 501                 struct intel_bw_info *bi = &dev_priv->display.bw.max[i];
 502                 struct intel_bw_info *bi_next;
 503                 int clpchgroup;
 504                 int j;
 505
 506                 clpchgroup = (sa->deburst * qi.deinterleave / num_channels) << i;
 507
 508                 if (i < num_groups - 1) {
 509                         bi_next = &dev_priv->display.bw.max[i + 1];
 510
 511                         if (clpchgroup < clperchgroup)
 512                                 bi_next->num_planes = (ipqdepth - clpchgroup) /
 513                                                        clpchgroup + 1;
 514                         else
 515                                 bi_next->num_planes = 0;
 516                 }
 517
 518                 bi->num_qgv_points = qi.num_points;
 519                 bi->num_psf_gv_points = qi.num_psf_points;
 520
 521                 for (j = 0; j < qi.num_points; j++) {
 522                         const struct intel_qgv_point *sp = &qi.points[j];
 523                         int ct, bw;
 524
 525                         /*
 526                          * Max row cycle time
 527                          *
 528                          * FIXME what is the logic behind the
 529                          * assumed burst length?
 530                          */
 531                         ct = max_t(int, sp->t_rc, sp->t_rp + sp->t_rcd +
 532                                    (clpchgroup - 1) * qi.t_bl + sp->t_rdpre);
 533                         bw = DIV_ROUND_UP(sp->dclk * clpchgroup * 32 * num_channels, ct);
 534
 535                         bi->deratedbw[j] = min(maxdebw,
 536                                                bw * (100 - sa->derating) / 100);
 537
 538                         drm_dbg_kms(&dev_priv->drm,
 539                                     "BW%d / QGV %d: num_planes=%d deratedbw=%u\n",
 540                                     i, j, bi->num_planes, bi->deratedbw[j]);
 541                 }
 542
 543                 for (j = 0; j < qi.num_psf_points; j++) {
 544                         const struct intel_psf_gv_point *sp = &qi.psf_points[j];
 545
 546                         bi->psf_bw[j] = adl_calc_psf_bw(sp->clk);
 547
 548                         drm_dbg_kms(&dev_priv->drm,
 549                                     "BW%d / PSF GV %d: num_planes=%d bw=%u\n",
 550                                     i, j, bi->num_planes, bi->psf_bw[j]);
 551                 }
 552         }
 553
 554         /*
 555          * In case if SAGV is disabled in BIOS, we always get 1
 556          * SAGV point, but we can't send PCode commands to restrict it
 557          * as it will fail and pointless anyway.
 558          */
 559         if (qi.num_points == 1)
 560                 dev_priv->display.sagv.status = I915_SAGV_NOT_CONTROLLED;
 561         else
 562                 dev_priv->display.sagv.status = I915_SAGV_ENABLED;
 563
 564         return 0;
 565 }
 566
 567 static void dg2_get_bw_info(struct drm_i915_private *i915)
 568 {
 569         unsigned int deratedbw = IS_DG2_G11(i915) ? 38000 : 50000;
 570         int num_groups = ARRAY_SIZE(i915->display.bw.max);
 571         int i;
 572
 573         /*
 574          * DG2 doesn't have SAGV or QGV points, just a constant max bandwidth
 575          * that doesn't depend on the number of planes enabled. So fill all the
 576          * plane group with constant bw information for uniformity with other
 577          * platforms. DG2-G10 platforms have a constant 50 GB/s bandwidth,
 578          * whereas DG2-G11 platforms have 38 GB/s.
 579          */
 580         for (i = 0; i < num_groups; i++) {
 581                 struct intel_bw_info *bi = &i915->display.bw.max[i];
 582
 583                 bi->num_planes = 1;
 584                 /* Need only one dummy QGV point per group */
 585                 bi->num_qgv_points = 1;
 586                 bi->deratedbw[0] = deratedbw;
 587         }
 588
 589         i915->display.sagv.status = I915_SAGV_NOT_CONTROLLED;
 590 }
 591
 592 static unsigned int icl_max_bw(struct drm_i915_private *dev_priv,
 593                                int num_planes, int qgv_point)
 594 {
 595         int i;
 596
 597         /*
 598          * Let's return max bw for 0 planes
 599          */
 600         num_planes = max(1, num_planes);
 601
 602         for (i = 0; i < ARRAY_SIZE(dev_priv->display.bw.max); i++) {
 603                 const struct intel_bw_info *bi =
 604                         &dev_priv->display.bw.max[i];
 605
 606                 /*
 607                  * Pcode will not expose all QGV points when
 608                  * SAGV is forced to off/min/med/max.
 609                  */
 610                 if (qgv_point >= bi->num_qgv_points)
 611                         return UINT_MAX;
 612
 613                 if (num_planes >= bi->num_planes)
 614                         return bi->deratedbw[qgv_point];
 615         }
 616
 617         return 0;
 618 }
 619
 620 static unsigned int tgl_max_bw(struct drm_i915_private *dev_priv,
 621                                int num_planes, int qgv_point)
 622 {
 623         int i;
 624
 625         /*
 626          * Let's return max bw for 0 planes
 627          */
 628         num_planes = max(1, num_planes);
 629
 630         for (i = ARRAY_SIZE(dev_priv->display.bw.max) - 1; i >= 0; i--) {
 631                 const struct intel_bw_info *bi =
 632                         &dev_priv->display.bw.max[i];
 633
 634                 /*
 635                  * Pcode will not expose all QGV points when
 636                  * SAGV is forced to off/min/med/max.
 637                  */
 638                 if (qgv_point >= bi->num_qgv_points)
 639                         return UINT_MAX;
 640
 641                 if (num_planes <= bi->num_planes)
 642                         return bi->deratedbw[qgv_point];
 643         }
 644
 645         return dev_priv->display.bw.max[0].deratedbw[qgv_point];
 646 }
 647
 648 static unsigned int adl_psf_bw(struct drm_i915_private *dev_priv,
 649                                int psf_gv_point)
 650 {
 651         const struct intel_bw_info *bi =
 652                         &dev_priv->display.bw.max[0];
 653
 654         return bi->psf_bw[psf_gv_point];
 655 }
 656
 657 void intel_bw_init_hw(struct drm_i915_private *dev_priv)
 658 {
 659         if (!HAS_DISPLAY(dev_priv))
 660                 return;
 661
 662         if (DISPLAY_VER(dev_priv) >= 14)
 663                 tgl_get_bw_info(dev_priv, &mtl_sa_info);
 664         else if (IS_DG2(dev_priv))
 665                 dg2_get_bw_info(dev_priv);
 666         else if (IS_ALDERLAKE_P(dev_priv))
 667                 tgl_get_bw_info(dev_priv, &adlp_sa_info);
 668         else if (IS_ALDERLAKE_S(dev_priv))
 669                 tgl_get_bw_info(dev_priv, &adls_sa_info);
 670         else if (IS_ROCKETLAKE(dev_priv))
 671                 tgl_get_bw_info(dev_priv, &rkl_sa_info);
 672         else if (DISPLAY_VER(dev_priv) == 12)
 673                 tgl_get_bw_info(dev_priv, &tgl_sa_info);
 674         else if (DISPLAY_VER(dev_priv) == 11)
 675                 icl_get_bw_info(dev_priv, &icl_sa_info);
 676 }
 677
 678 static unsigned int intel_bw_crtc_num_active_planes(const struct intel_crtc_state *crtc_state)
 679 {
 680         /*
 681          * We assume cursors are small enough
 682          * to not not cause bandwidth problems.
 683          */
 684         return hweight8(crtc_state->active_planes & ~BIT(PLANE_CURSOR));
 685 }
 686
 687 static unsigned int intel_bw_crtc_data_rate(const struct intel_crtc_state *crtc_state)
 688 {
 689         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 690         struct drm_i915_private *i915 = to_i915(crtc->base.dev);
 691         unsigned int data_rate = 0;
 692         enum plane_id plane_id;
 693
 694         for_each_plane_id_on_crtc(crtc, plane_id) {
 695                 /*
 696                  * We assume cursors are small enough
 697                  * to not not cause bandwidth problems.
 698                  */
 699                 if (plane_id == PLANE_CURSOR)
 700                         continue;
 701
 702                 data_rate += crtc_state->data_rate[plane_id];
 703
 704                 if (DISPLAY_VER(i915) < 11)
 705                         data_rate += crtc_state->data_rate_y[plane_id];
 706         }
 707
 708         return data_rate;
 709 }
 710
 711 /* "Maximum Pipe Read Bandwidth" */
 712 static int intel_bw_crtc_min_cdclk(const struct intel_crtc_state *crtc_state)
 713 {
 714         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 715         struct drm_i915_private *i915 = to_i915(crtc->base.dev);
 716
 717         if (DISPLAY_VER(i915) < 12)
 718                 return 0;
 719
 720         return DIV_ROUND_UP_ULL(mul_u32_u32(intel_bw_crtc_data_rate(crtc_state), 10), 512);
 721 }
 722
 723 void intel_bw_crtc_update(struct intel_bw_state *bw_state,
 724                           const struct intel_crtc_state *crtc_state)
 725 {
 726         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 727         struct drm_i915_private *i915 = to_i915(crtc->base.dev);
 728
 729         bw_state->data_rate[crtc->pipe] =
 730                 intel_bw_crtc_data_rate(crtc_state);
 731         bw_state->num_active_planes[crtc->pipe] =
 732                 intel_bw_crtc_num_active_planes(crtc_state);
 733
 734         drm_dbg_kms(&i915->drm, "pipe %c data rate %u num active planes %u\n",
 735                     pipe_name(crtc->pipe),
 736                     bw_state->data_rate[crtc->pipe],
 737                     bw_state->num_active_planes[crtc->pipe]);
 738 }
 739
 740 static unsigned int intel_bw_num_active_planes(struct drm_i915_private *dev_priv,
 741                                                const struct intel_bw_state *bw_state)
 742 {
 743         unsigned int num_active_planes = 0;
 744         enum pipe pipe;
 745
 746         for_each_pipe(dev_priv, pipe)
 747                 num_active_planes += bw_state->num_active_planes[pipe];
 748
 749         return num_active_planes;
 750 }
 751
 752 static unsigned int intel_bw_data_rate(struct drm_i915_private *dev_priv,
 753                                        const struct intel_bw_state *bw_state)
 754 {
 755         unsigned int data_rate = 0;
 756         enum pipe pipe;
 757
 758         for_each_pipe(dev_priv, pipe)
 759                 data_rate += bw_state->data_rate[pipe];
 760
 761         if (DISPLAY_VER(dev_priv) >= 13 && i915_vtd_active(dev_priv))
 762                 data_rate = DIV_ROUND_UP(data_rate * 105, 100);
 763
 764         return data_rate;
 765 }
 766
 767 struct intel_bw_state *
 768 intel_atomic_get_old_bw_state(struct intel_atomic_state *state)
 769 {
 770         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
 771         struct intel_global_state *bw_state;
 772
 773         bw_state = intel_atomic_get_old_global_obj_state(state, &dev_priv->display.bw.obj);
 774
 775         return to_intel_bw_state(bw_state);
 776 }
 777
 778 struct intel_bw_state *
 779 intel_atomic_get_new_bw_state(struct intel_atomic_state *state)
 780 {
 781         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
 782         struct intel_global_state *bw_state;
 783
 784         bw_state = intel_atomic_get_new_global_obj_state(state, &dev_priv->display.bw.obj);
 785
 786         return to_intel_bw_state(bw_state);
 787 }
 788
 789 struct intel_bw_state *
 790 intel_atomic_get_bw_state(struct intel_atomic_state *state)
 791 {
 792         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
 793         struct intel_global_state *bw_state;
 794
 795         bw_state = intel_atomic_get_global_obj_state(state, &dev_priv->display.bw.obj);
 796         if (IS_ERR(bw_state))
 797                 return ERR_CAST(bw_state);
 798
 799         return to_intel_bw_state(bw_state);
 800 }
 801
 802 static bool intel_bw_state_changed(struct drm_i915_private *i915,
 803                                    const struct intel_bw_state *old_bw_state,
 804                                    const struct intel_bw_state *new_bw_state)
 805 {
 806         enum pipe pipe;
 807
 808         for_each_pipe(i915, pipe) {
 809                 const struct intel_dbuf_bw *old_crtc_bw =
 810                         &old_bw_state->dbuf_bw[pipe];
 811                 const struct intel_dbuf_bw *new_crtc_bw =
 812                         &new_bw_state->dbuf_bw[pipe];
 813                 enum dbuf_slice slice;
 814
 815                 for_each_dbuf_slice(i915, slice) {
 816                         if (old_crtc_bw->max_bw[slice] != new_crtc_bw->max_bw[slice] ||
 817                             old_crtc_bw->active_planes[slice] != new_crtc_bw->active_planes[slice])
 818                                 return true;
 819                 }
 820
 821                 if (old_bw_state->min_cdclk[pipe] != new_bw_state->min_cdclk[pipe])
 822                         return true;
 823         }
 824
 825         return false;
 826 }
 827
 828 static void skl_plane_calc_dbuf_bw(struct intel_bw_state *bw_state,
 829                                    struct intel_crtc *crtc,
 830                                    enum plane_id plane_id,
 831                                    const struct skl_ddb_entry *ddb,
 832                                    unsigned int data_rate)
 833 {
 834         struct drm_i915_private *i915 = to_i915(crtc->base.dev);
 835         struct intel_dbuf_bw *crtc_bw = &bw_state->dbuf_bw[crtc->pipe];
 836         unsigned int dbuf_mask = skl_ddb_dbuf_slice_mask(i915, ddb);
 837         enum dbuf_slice slice;
 838
 839         /*
 840          * The arbiter can only really guarantee an
 841          * equal share of the total bw to each plane.
 842          */
 843         for_each_dbuf_slice_in_mask(i915, slice, dbuf_mask) {
 844                 crtc_bw->max_bw[slice] = max(crtc_bw->max_bw[slice], data_rate);
 845                 crtc_bw->active_planes[slice] |= BIT(plane_id);
 846         }
 847 }
 848
 849 static void skl_crtc_calc_dbuf_bw(struct intel_bw_state *bw_state,
 850                                   const struct intel_crtc_state *crtc_state)
 851 {
 852         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 853         struct drm_i915_private *i915 = to_i915(crtc->base.dev);
 854         struct intel_dbuf_bw *crtc_bw = &bw_state->dbuf_bw[crtc->pipe];
 855         enum plane_id plane_id;
 856
 857         memset(crtc_bw, 0, sizeof(*crtc_bw));
 858
 859         if (!crtc_state->hw.active)
 860                 return;
 861
 862         for_each_plane_id_on_crtc(crtc, plane_id) {
 863                 /*
 864                  * We assume cursors are small enough
 865                  * to not cause bandwidth problems.
 866                  */
 867                 if (plane_id == PLANE_CURSOR)
 868                         continue;
 869
 870                 skl_plane_calc_dbuf_bw(bw_state, crtc, plane_id,
 871                                        &crtc_state->wm.skl.plane_ddb[plane_id],
 872                                        crtc_state->data_rate[plane_id]);
 873
 874                 if (DISPLAY_VER(i915) < 11)
 875                         skl_plane_calc_dbuf_bw(bw_state, crtc, plane_id,
 876                                                &crtc_state->wm.skl.plane_ddb_y[plane_id],
 877                                                crtc_state->data_rate[plane_id]);
 878         }
 879 }
 880
 881 /* "Maximum Data Buffer Bandwidth" */
 882 static int
 883 intel_bw_dbuf_min_cdclk(struct drm_i915_private *i915,
 884                         const struct intel_bw_state *bw_state)
 885 {
 886         unsigned int total_max_bw = 0;
 887         enum dbuf_slice slice;
 888
 889         for_each_dbuf_slice(i915, slice) {
 890                 int num_active_planes = 0;
 891                 unsigned int max_bw = 0;
 892                 enum pipe pipe;
 893
 894                 /*
 895                  * The arbiter can only really guarantee an
 896                  * equal share of the total bw to each plane.
 897                  */
 898                 for_each_pipe(i915, pipe) {
 899                         const struct intel_dbuf_bw *crtc_bw = &bw_state->dbuf_bw[pipe];
 900
 901                         max_bw = max(crtc_bw->max_bw[slice], max_bw);
 902                         num_active_planes += hweight8(crtc_bw->active_planes[slice]);
 903                 }
 904                 max_bw *= num_active_planes;
 905
 906                 total_max_bw = max(total_max_bw, max_bw);
 907         }
 908
 909         return DIV_ROUND_UP(total_max_bw, 64);
 910 }
 911
 912 int intel_bw_min_cdclk(struct drm_i915_private *i915,
 913                        const struct intel_bw_state *bw_state)
 914 {
 915         enum pipe pipe;
 916         int min_cdclk;
 917
 918         min_cdclk = intel_bw_dbuf_min_cdclk(i915, bw_state);
 919
 920         for_each_pipe(i915, pipe)
 921                 min_cdclk = max(bw_state->min_cdclk[pipe], min_cdclk);
 922
 923         return min_cdclk;
 924 }
 925
 926 int intel_bw_calc_min_cdclk(struct intel_atomic_state *state,
 927                             bool *need_cdclk_calc)
 928 {
 929         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
 930         struct intel_bw_state *new_bw_state = NULL;
 931         const struct intel_bw_state *old_bw_state = NULL;
 932         const struct intel_cdclk_state *cdclk_state;
 933         const struct intel_crtc_state *crtc_state;
 934         int old_min_cdclk, new_min_cdclk;
 935         struct intel_crtc *crtc;
 936         int i;
 937
 938         if (DISPLAY_VER(dev_priv) < 9)
 939                 return 0;
 940
 941         for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
 942                 new_bw_state = intel_atomic_get_bw_state(state);
 943                 if (IS_ERR(new_bw_state))
 944                         return PTR_ERR(new_bw_state);
 945
 946                 old_bw_state = intel_atomic_get_old_bw_state(state);
 947
 948                 skl_crtc_calc_dbuf_bw(new_bw_state, crtc_state);
 949
 950                 new_bw_state->min_cdclk[crtc->pipe] =
 951                         intel_bw_crtc_min_cdclk(crtc_state);
 952         }
 953
 954         if (!old_bw_state)
 955                 return 0;
 956
 957         if (intel_bw_state_changed(dev_priv, old_bw_state, new_bw_state)) {
 958                 int ret = intel_atomic_lock_global_state(&new_bw_state->base);
 959                 if (ret)
 960                         return ret;
 961         }
 962
 963         old_min_cdclk = intel_bw_min_cdclk(dev_priv, old_bw_state);
 964         new_min_cdclk = intel_bw_min_cdclk(dev_priv, new_bw_state);
 965
 966         /*
 967          * No need to check against the cdclk state if
 968          * the min cdclk doesn't increase.
 969          *
 970          * Ie. we only ever increase the cdclk due to bandwidth
 971          * requirements. This can reduce back and forth
 972          * display blinking due to constant cdclk changes.
 973          */
 974         if (new_min_cdclk <= old_min_cdclk)
 975                 return 0;
 976
 977         cdclk_state = intel_atomic_get_cdclk_state(state);
 978         if (IS_ERR(cdclk_state))
 979                 return PTR_ERR(cdclk_state);
 980
 981         /*
 982          * No need to recalculate the cdclk state if
 983          * the min cdclk doesn't increase.
 984          *
 985          * Ie. we only ever increase the cdclk due to bandwidth
 986          * requirements. This can reduce back and forth
 987          * display blinking due to constant cdclk changes.
 988          */
 989         if (new_min_cdclk <= cdclk_state->bw_min_cdclk)
 990                 return 0;
 991
 992         drm_dbg_kms(&dev_priv->drm,
 993                     "new bandwidth min cdclk (%d kHz) > old min cdclk (%d kHz)\n",
 994                     new_min_cdclk, cdclk_state->bw_min_cdclk);
 995         *need_cdclk_calc = true;
 996
 997         return 0;
 998 }
 999
1000 static int intel_bw_check_data_rate(struct intel_atomic_state *state, bool *changed)
1001 {
1002         struct drm_i915_private *i915 = to_i915(state->base.dev);
1003         const struct intel_crtc_state *new_crtc_state, *old_crtc_state;
1004         struct intel_crtc *crtc;
1005         int i;
1006
1007         for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
1008                                             new_crtc_state, i) {
1009                 unsigned int old_data_rate =
1010                         intel_bw_crtc_data_rate(old_crtc_state);
1011                 unsigned int new_data_rate =
1012                         intel_bw_crtc_data_rate(new_crtc_state);
1013                 unsigned int old_active_planes =
1014                         intel_bw_crtc_num_active_planes(old_crtc_state);
1015                 unsigned int new_active_planes =
1016                         intel_bw_crtc_num_active_planes(new_crtc_state);
1017                 struct intel_bw_state *new_bw_state;
1018
1019                 /*
1020                  * Avoid locking the bw state when
1021                  * nothing significant has changed.
1022                  */
1023                 if (old_data_rate == new_data_rate &&
1024                     old_active_planes == new_active_planes)
1025                         continue;
1026
1027                 new_bw_state = intel_atomic_get_bw_state(state);
1028                 if (IS_ERR(new_bw_state))
1029                         return PTR_ERR(new_bw_state);
1030
1031                 new_bw_state->data_rate[crtc->pipe] = new_data_rate;
1032                 new_bw_state->num_active_planes[crtc->pipe] = new_active_planes;
1033
1034                 *changed = true;
1035
1036                 drm_dbg_kms(&i915->drm,
1037                             "[CRTC:%d:%s] data rate %u num active planes %u\n",
1038                             crtc->base.base.id, crtc->base.name,
1039                             new_bw_state->data_rate[crtc->pipe],
1040                             new_bw_state->num_active_planes[crtc->pipe]);
1041         }
1042
1043         return 0;
1044 }
1045
1046 int intel_bw_atomic_check(struct intel_atomic_state *state)
1047 {
1048         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
1049         const struct intel_bw_state *old_bw_state;
1050         struct intel_bw_state *new_bw_state;
1051         unsigned int data_rate;
1052         unsigned int num_active_planes;
1053         int i, ret;
1054         u16 qgv_points = 0, psf_points = 0;
1055         unsigned int max_bw_point = 0, max_bw = 0;
1056         unsigned int num_qgv_points = dev_priv->display.bw.max[0].num_qgv_points;
1057         unsigned int num_psf_gv_points = dev_priv->display.bw.max[0].num_psf_gv_points;
1058         bool changed = false;
1059
1060         /* FIXME earlier gens need some checks too */
1061         if (DISPLAY_VER(dev_priv) < 11)
1062                 return 0;
1063
1064         ret = intel_bw_check_data_rate(state, &changed);
1065         if (ret)
1066                 return ret;
1067
1068         old_bw_state = intel_atomic_get_old_bw_state(state);
1069         new_bw_state = intel_atomic_get_new_bw_state(state);
1070
1071         if (new_bw_state &&
1072             intel_can_enable_sagv(dev_priv, old_bw_state) !=
1073             intel_can_enable_sagv(dev_priv, new_bw_state))
1074                 changed = true;
1075
1076         /*
1077          * If none of our inputs (data rates, number of active
1078          * planes, SAGV yes/no) changed then nothing to do here.
1079          */
1080         if (!changed)
1081                 return 0;
1082
1083         ret = intel_atomic_lock_global_state(&new_bw_state->base);
1084         if (ret)
1085                 return ret;
1086
1087         data_rate = intel_bw_data_rate(dev_priv, new_bw_state);
1088         data_rate = DIV_ROUND_UP(data_rate, 1000);
1089
1090         num_active_planes = intel_bw_num_active_planes(dev_priv, new_bw_state);
1091
1092         for (i = 0; i < num_qgv_points; i++) {
1093                 unsigned int max_data_rate;
1094
1095                 if (DISPLAY_VER(dev_priv) > 11)
1096                         max_data_rate = tgl_max_bw(dev_priv, num_active_planes, i);
1097                 else
1098                         max_data_rate = icl_max_bw(dev_priv, num_active_planes, i);
1099                 /*
1100                  * We need to know which qgv point gives us
1101                  * maximum bandwidth in order to disable SAGV
1102                  * if we find that we exceed SAGV block time
1103                  * with watermarks. By that moment we already
1104                  * have those, as it is calculated earlier in
1105                  * intel_atomic_check,
1106                  */
1107                 if (max_data_rate > max_bw) {
1108                         max_bw_point = i;
1109                         max_bw = max_data_rate;
1110                 }
1111                 if (max_data_rate >= data_rate)
1112                         qgv_points |= BIT(i);
1113
1114                 drm_dbg_kms(&dev_priv->drm, "QGV point %d: max bw %d required %d\n",
1115                             i, max_data_rate, data_rate);
1116         }
1117
1118         for (i = 0; i < num_psf_gv_points; i++) {
1119                 unsigned int max_data_rate = adl_psf_bw(dev_priv, i);
1120
1121                 if (max_data_rate >= data_rate)
1122                         psf_points |= BIT(i);
1123
1124                 drm_dbg_kms(&dev_priv->drm, "PSF GV point %d: max bw %d"
1125                             " required %d\n",
1126                             i, max_data_rate, data_rate);
1127         }
1128
1129         /*
1130          * BSpec states that we always should have at least one allowed point
1131          * left, so if we couldn't - simply reject the configuration for obvious
1132          * reasons.
1133          */
1134         if (qgv_points == 0) {
1135                 drm_dbg_kms(&dev_priv->drm, "No QGV points provide sufficient memory"
1136                             " bandwidth %d for display configuration(%d active planes).\n",
1137                             data_rate, num_active_planes);
1138                 return -EINVAL;
1139         }
1140
1141         if (num_psf_gv_points > 0 && psf_points == 0) {
1142                 drm_dbg_kms(&dev_priv->drm, "No PSF GV points provide sufficient memory"
1143                             " bandwidth %d for display configuration(%d active planes).\n",
1144                             data_rate, num_active_planes);
1145                 return -EINVAL;
1146         }
1147
1148         /*
1149          * Leave only single point with highest bandwidth, if
1150          * we can't enable SAGV due to the increased memory latency it may
1151          * cause.
1152          */
1153         if (!intel_can_enable_sagv(dev_priv, new_bw_state)) {
1154                 qgv_points = BIT(max_bw_point);
1155                 drm_dbg_kms(&dev_priv->drm, "No SAGV, using single QGV point %d\n",
1156                             max_bw_point);
1157         }
1158
1159         /*
1160          * We store the ones which need to be masked as that is what PCode
1161          * actually accepts as a parameter.
1162          */
1163         new_bw_state->qgv_points_mask =
1164                 ~(ICL_PCODE_REQ_QGV_PT(qgv_points) |
1165                   ADLS_PCODE_REQ_PSF_PT(psf_points)) &
1166                 icl_qgv_points_mask(dev_priv);
1167
1168         /*
1169          * If the actual mask had changed we need to make sure that
1170          * the commits are serialized(in case this is a nomodeset, nonblocking)
1171          */
1172         if (new_bw_state->qgv_points_mask != old_bw_state->qgv_points_mask) {
1173                 ret = intel_atomic_serialize_global_state(&new_bw_state->base);
1174                 if (ret)
1175                         return ret;
1176         }
1177
1178         return 0;
1179 }
1180
1181 static struct intel_global_state *
1182 intel_bw_duplicate_state(struct intel_global_obj *obj)
1183 {
1184         struct intel_bw_state *state;
1185
1186         state = kmemdup(obj->state, sizeof(*state), GFP_KERNEL);
1187         if (!state)
1188                 return NULL;
1189
1190         return &state->base;
1191 }
1192
1193 static void intel_bw_destroy_state(struct intel_global_obj *obj,
1194                                    struct intel_global_state *state)
1195 {
1196         kfree(state);
1197 }
1198
1199 static const struct intel_global_state_funcs intel_bw_funcs = {
1200         .atomic_duplicate_state = intel_bw_duplicate_state,
1201         .atomic_destroy_state = intel_bw_destroy_state,
1202 };
1203
1204 int intel_bw_init(struct drm_i915_private *dev_priv)
1205 {
1206         struct intel_bw_state *state;
1207
1208         state = kzalloc(sizeof(*state), GFP_KERNEL);
1209         if (!state)
1210                 return -ENOMEM;
1211
1212         intel_atomic_global_obj_init(dev_priv, &dev_priv->display.bw.obj,
1213                                      &state->base, &intel_bw_funcs);
1214
1215         return 0;
1216 }