drivers/gpu/drm/i915/display/intel_atomic_plane.c

   1 /*
   2  * Copyright © 2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  */
  23
  24 /**
  25  * DOC: atomic plane helpers
  26  *
  27  * The functions here are used by the atomic plane helper functions to
  28  * implement legacy plane updates (i.e., drm_plane->update_plane() and
  29  * drm_plane->disable_plane()).  This allows plane updates to use the
  30  * atomic state infrastructure and perform plane updates as separate
  31  * prepare/check/commit/cleanup steps.
  32  */
  33
  34 #include <drm/drm_atomic_helper.h>
  35 #include <drm/drm_blend.h>
  36 #include <drm/drm_fourcc.h>
  37
  38 #include "i915_config.h"
  39 #include "i915_reg.h"
  40 #include "intel_atomic_plane.h"
  41 #include "intel_cdclk.h"
  42 #include "intel_display_rps.h"
  43 #include "intel_display_trace.h"
  44 #include "intel_display_types.h"
  45 #include "intel_fb.h"
  46 #include "intel_fb_pin.h"
  47 #include "skl_scaler.h"
  48 #include "skl_watermark.h"
  49
  50 static void intel_plane_state_reset(struct intel_plane_state *plane_state,
  51                                     struct intel_plane *plane)
  52 {
  53         memset(plane_state, 0, sizeof(*plane_state));
  54
  55         __drm_atomic_helper_plane_state_reset(&plane_state->uapi, &plane->base);
  56
  57         plane_state->scaler_id = -1;
  58 }
  59
  60 struct intel_plane *intel_plane_alloc(void)
  61 {
  62         struct intel_plane_state *plane_state;
  63         struct intel_plane *plane;
  64
  65         plane = kzalloc(sizeof(*plane), GFP_KERNEL);
  66         if (!plane)
  67                 return ERR_PTR(-ENOMEM);
  68
  69         plane_state = kzalloc(sizeof(*plane_state), GFP_KERNEL);
  70         if (!plane_state) {
  71                 kfree(plane);
  72                 return ERR_PTR(-ENOMEM);
  73         }
  74
  75         intel_plane_state_reset(plane_state, plane);
  76
  77         plane->base.state = &plane_state->uapi;
  78
  79         return plane;
  80 }
  81
  82 void intel_plane_free(struct intel_plane *plane)
  83 {
  84         intel_plane_destroy_state(&plane->base, plane->base.state);
  85         kfree(plane);
  86 }
  87
  88 /**
  89  * intel_plane_duplicate_state - duplicate plane state
  90  * @plane: drm plane
  91  *
  92  * Allocates and returns a copy of the plane state (both common and
  93  * Intel-specific) for the specified plane.
  94  *
  95  * Returns: The newly allocated plane state, or NULL on failure.
  96  */
  97 struct drm_plane_state *
  98 intel_plane_duplicate_state(struct drm_plane *plane)
  99 {
 100         struct intel_plane_state *intel_state;
 101
 102         intel_state = to_intel_plane_state(plane->state);
 103         intel_state = kmemdup(intel_state, sizeof(*intel_state), GFP_KERNEL);
 104
 105         if (!intel_state)
 106                 return NULL;
 107
 108         __drm_atomic_helper_plane_duplicate_state(plane, &intel_state->uapi);
 109
 110         intel_state->ggtt_vma = NULL;
 111         intel_state->dpt_vma = NULL;
 112         intel_state->flags = 0;
 113
 114         /* add reference to fb */
 115         if (intel_state->hw.fb)
 116                 drm_framebuffer_get(intel_state->hw.fb);
 117
 118         return &intel_state->uapi;
 119 }
 120
 121 /**
 122  * intel_plane_destroy_state - destroy plane state
 123  * @plane: drm plane
 124  * @state: state object to destroy
 125  *
 126  * Destroys the plane state (both common and Intel-specific) for the
 127  * specified plane.
 128  */
 129 void
 130 intel_plane_destroy_state(struct drm_plane *plane,
 131                           struct drm_plane_state *state)
 132 {
 133         struct intel_plane_state *plane_state = to_intel_plane_state(state);
 134
 135         drm_WARN_ON(plane->dev, plane_state->ggtt_vma);
 136         drm_WARN_ON(plane->dev, plane_state->dpt_vma);
 137
 138         __drm_atomic_helper_plane_destroy_state(&plane_state->uapi);
 139         if (plane_state->hw.fb)
 140                 drm_framebuffer_put(plane_state->hw.fb);
 141         kfree(plane_state);
 142 }
 143
 144 unsigned int intel_adjusted_rate(const struct drm_rect *src,
 145                                  const struct drm_rect *dst,
 146                                  unsigned int rate)
 147 {
 148         unsigned int src_w, src_h, dst_w, dst_h;
 149
 150         src_w = drm_rect_width(src) >> 16;
 151         src_h = drm_rect_height(src) >> 16;
 152         dst_w = drm_rect_width(dst);
 153         dst_h = drm_rect_height(dst);
 154
 155         /* Downscaling limits the maximum pixel rate */
 156         dst_w = min(src_w, dst_w);
 157         dst_h = min(src_h, dst_h);
 158
 159         return DIV_ROUND_UP_ULL(mul_u32_u32(rate, src_w * src_h),
 160                                 dst_w * dst_h);
 161 }
 162
 163 unsigned int intel_plane_pixel_rate(const struct intel_crtc_state *crtc_state,
 164                                     const struct intel_plane_state *plane_state)
 165 {
 166         /*
 167          * Note we don't check for plane visibility here as
 168          * we want to use this when calculating the cursor
 169          * watermarks even if the cursor is fully offscreen.
 170          * That depends on the src/dst rectangles being
 171          * correctly populated whenever the watermark code
 172          * considers the cursor to be visible, whether or not
 173          * it is actually visible.
 174          *
 175          * See: intel_wm_plane_visible() and intel_check_cursor()
 176          */
 177
 178         return intel_adjusted_rate(&plane_state->uapi.src,
 179                                    &plane_state->uapi.dst,
 180                                    crtc_state->pixel_rate);
 181 }
 182
 183 unsigned int intel_plane_data_rate(const struct intel_crtc_state *crtc_state,
 184                                    const struct intel_plane_state *plane_state,
 185                                    int color_plane)
 186 {
 187         const struct drm_framebuffer *fb = plane_state->hw.fb;
 188
 189         if (!plane_state->uapi.visible)
 190                 return 0;
 191
 192         return intel_plane_pixel_rate(crtc_state, plane_state) *
 193                 fb->format->cpp[color_plane];
 194 }
 195
 196 static bool
 197 use_min_ddb(const struct intel_crtc_state *crtc_state,
 198             struct intel_plane *plane)
 199 {
 200         struct drm_i915_private *i915 = to_i915(plane->base.dev);
 201
 202         return DISPLAY_VER(i915) >= 13 &&
 203                crtc_state->uapi.async_flip &&
 204                plane->async_flip;
 205 }
 206
 207 static unsigned int
 208 intel_plane_relative_data_rate(const struct intel_crtc_state *crtc_state,
 209                                const struct intel_plane_state *plane_state,
 210                                int color_plane)
 211 {
 212         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
 213         const struct drm_framebuffer *fb = plane_state->hw.fb;
 214         int width, height;
 215
 216         if (plane->id == PLANE_CURSOR)
 217                 return 0;
 218
 219         if (!plane_state->uapi.visible)
 220                 return 0;
 221
 222         /*
 223          * We calculate extra ddb based on ratio plane rate/total data rate
 224          * in case, in some cases we should not allocate extra ddb for the plane,
 225          * so do not count its data rate, if this is the case.
 226          */
 227         if (use_min_ddb(crtc_state, plane))
 228                 return 0;
 229
 230         /*
 231          * Src coordinates are already rotated by 270 degrees for
 232          * the 90/270 degree plane rotation cases (to match the
 233          * GTT mapping), hence no need to account for rotation here.
 234          */
 235         width = drm_rect_width(&plane_state->uapi.src) >> 16;
 236         height = drm_rect_height(&plane_state->uapi.src) >> 16;
 237
 238         /* UV plane does 1/2 pixel sub-sampling */
 239         if (color_plane == 1) {
 240                 width /= 2;
 241                 height /= 2;
 242         }
 243
 244         return width * height * fb->format->cpp[color_plane];
 245 }
 246
 247 int intel_plane_calc_min_cdclk(struct intel_atomic_state *state,
 248                                struct intel_plane *plane,
 249                                bool *need_cdclk_calc)
 250 {
 251         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 252         const struct intel_plane_state *plane_state =
 253                 intel_atomic_get_new_plane_state(state, plane);
 254         struct intel_crtc *crtc = to_intel_crtc(plane_state->hw.crtc);
 255         const struct intel_cdclk_state *cdclk_state;
 256         const struct intel_crtc_state *old_crtc_state;
 257         struct intel_crtc_state *new_crtc_state;
 258
 259         if (!plane_state->uapi.visible || !plane->min_cdclk)
 260                 return 0;
 261
 262         old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc);
 263         new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
 264
 265         new_crtc_state->min_cdclk[plane->id] =
 266                 plane->min_cdclk(new_crtc_state, plane_state);
 267
 268         /*
 269          * No need to check against the cdclk state if
 270          * the min cdclk for the plane doesn't increase.
 271          *
 272          * Ie. we only ever increase the cdclk due to plane
 273          * requirements. This can reduce back and forth
 274          * display blinking due to constant cdclk changes.
 275          */
 276         if (new_crtc_state->min_cdclk[plane->id] <=
 277             old_crtc_state->min_cdclk[plane->id])
 278                 return 0;
 279
 280         cdclk_state = intel_atomic_get_cdclk_state(state);
 281         if (IS_ERR(cdclk_state))
 282                 return PTR_ERR(cdclk_state);
 283
 284         /*
 285          * No need to recalculate the cdclk state if
 286          * the min cdclk for the pipe doesn't increase.
 287          *
 288          * Ie. we only ever increase the cdclk due to plane
 289          * requirements. This can reduce back and forth
 290          * display blinking due to constant cdclk changes.
 291          */
 292         if (new_crtc_state->min_cdclk[plane->id] <=
 293             cdclk_state->min_cdclk[crtc->pipe])
 294                 return 0;
 295
 296         drm_dbg_kms(&dev_priv->drm,
 297                     "[PLANE:%d:%s] min cdclk (%d kHz) > [CRTC:%d:%s] min cdclk (%d kHz)\n",
 298                     plane->base.base.id, plane->base.name,
 299                     new_crtc_state->min_cdclk[plane->id],
 300                     crtc->base.base.id, crtc->base.name,
 301                     cdclk_state->min_cdclk[crtc->pipe]);
 302         *need_cdclk_calc = true;
 303
 304         return 0;
 305 }
 306
 307 static void intel_plane_clear_hw_state(struct intel_plane_state *plane_state)
 308 {
 309         if (plane_state->hw.fb)
 310                 drm_framebuffer_put(plane_state->hw.fb);
 311
 312         memset(&plane_state->hw, 0, sizeof(plane_state->hw));
 313 }
 314
 315 void intel_plane_copy_uapi_to_hw_state(struct intel_plane_state *plane_state,
 316                                        const struct intel_plane_state *from_plane_state,
 317                                        struct intel_crtc *crtc)
 318 {
 319         intel_plane_clear_hw_state(plane_state);
 320
 321         /*
 322          * For the bigjoiner slave uapi.crtc will point at
 323          * the master crtc. So we explicitly assign the right
 324          * slave crtc to hw.crtc. uapi.crtc!=NULL simply indicates
 325          * the plane is logically enabled on the uapi level.
 326          */
 327         plane_state->hw.crtc = from_plane_state->uapi.crtc ? &crtc->base : NULL;
 328
 329         plane_state->hw.fb = from_plane_state->uapi.fb;
 330         if (plane_state->hw.fb)
 331                 drm_framebuffer_get(plane_state->hw.fb);
 332
 333         plane_state->hw.alpha = from_plane_state->uapi.alpha;
 334         plane_state->hw.pixel_blend_mode =
 335                 from_plane_state->uapi.pixel_blend_mode;
 336         plane_state->hw.rotation = from_plane_state->uapi.rotation;
 337         plane_state->hw.color_encoding = from_plane_state->uapi.color_encoding;
 338         plane_state->hw.color_range = from_plane_state->uapi.color_range;
 339         plane_state->hw.scaling_filter = from_plane_state->uapi.scaling_filter;
 340
 341         plane_state->uapi.src = drm_plane_state_src(&from_plane_state->uapi);
 342         plane_state->uapi.dst = drm_plane_state_dest(&from_plane_state->uapi);
 343 }
 344
 345 void intel_plane_copy_hw_state(struct intel_plane_state *plane_state,
 346                                const struct intel_plane_state *from_plane_state)
 347 {
 348         intel_plane_clear_hw_state(plane_state);
 349
 350         memcpy(&plane_state->hw, &from_plane_state->hw,
 351                sizeof(plane_state->hw));
 352
 353         if (plane_state->hw.fb)
 354                 drm_framebuffer_get(plane_state->hw.fb);
 355 }
 356
 357 void intel_plane_set_invisible(struct intel_crtc_state *crtc_state,
 358                                struct intel_plane_state *plane_state)
 359 {
 360         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
 361
 362         crtc_state->active_planes &= ~BIT(plane->id);
 363         crtc_state->scaled_planes &= ~BIT(plane->id);
 364         crtc_state->nv12_planes &= ~BIT(plane->id);
 365         crtc_state->c8_planes &= ~BIT(plane->id);
 366         crtc_state->async_flip_planes &= ~BIT(plane->id);
 367         crtc_state->data_rate[plane->id] = 0;
 368         crtc_state->data_rate_y[plane->id] = 0;
 369         crtc_state->rel_data_rate[plane->id] = 0;
 370         crtc_state->rel_data_rate_y[plane->id] = 0;
 371         crtc_state->min_cdclk[plane->id] = 0;
 372
 373         plane_state->uapi.visible = false;
 374 }
 375
 376 /* FIXME nuke when all wm code is atomic */
 377 static bool intel_wm_need_update(const struct intel_plane_state *cur,
 378                                  struct intel_plane_state *new)
 379 {
 380         /* Update watermarks on tiling or size changes. */
 381         if (new->uapi.visible != cur->uapi.visible)
 382                 return true;
 383
 384         if (!cur->hw.fb || !new->hw.fb)
 385                 return false;
 386
 387         if (cur->hw.fb->modifier != new->hw.fb->modifier ||
 388             cur->hw.rotation != new->hw.rotation ||
 389             drm_rect_width(&new->uapi.src) != drm_rect_width(&cur->uapi.src) ||
 390             drm_rect_height(&new->uapi.src) != drm_rect_height(&cur->uapi.src) ||
 391             drm_rect_width(&new->uapi.dst) != drm_rect_width(&cur->uapi.dst) ||
 392             drm_rect_height(&new->uapi.dst) != drm_rect_height(&cur->uapi.dst))
 393                 return true;
 394
 395         return false;
 396 }
 397
 398 static bool intel_plane_is_scaled(const struct intel_plane_state *plane_state)
 399 {
 400         int src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
 401         int src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
 402         int dst_w = drm_rect_width(&plane_state->uapi.dst);
 403         int dst_h = drm_rect_height(&plane_state->uapi.dst);
 404
 405         return src_w != dst_w || src_h != dst_h;
 406 }
 407
 408 static bool intel_plane_do_async_flip(struct intel_plane *plane,
 409                                       const struct intel_crtc_state *old_crtc_state,
 410                                       const struct intel_crtc_state *new_crtc_state)
 411 {
 412         struct drm_i915_private *i915 = to_i915(plane->base.dev);
 413
 414         if (!plane->async_flip)
 415                 return false;
 416
 417         if (!new_crtc_state->uapi.async_flip)
 418                 return false;
 419
 420         /*
 421          * In platforms after DISPLAY13, we might need to override
 422          * first async flip in order to change watermark levels
 423          * as part of optimization.
 424          * So for those, we are checking if this is a first async flip.
 425          * For platforms earlier than DISPLAY13 we always do async flip.
 426          */
 427         return DISPLAY_VER(i915) < 13 || old_crtc_state->uapi.async_flip;
 428 }
 429
 430 static bool i9xx_must_disable_cxsr(const struct intel_crtc_state *new_crtc_state,
 431                                    const struct intel_plane_state *old_plane_state,
 432                                    const struct intel_plane_state *new_plane_state)
 433 {
 434         struct intel_plane *plane = to_intel_plane(new_plane_state->uapi.plane);
 435         bool old_visible = old_plane_state->uapi.visible;
 436         bool new_visible = new_plane_state->uapi.visible;
 437         u32 old_ctl = old_plane_state->ctl;
 438         u32 new_ctl = new_plane_state->ctl;
 439         bool modeset, turn_on, turn_off;
 440
 441         if (plane->id == PLANE_CURSOR)
 442                 return false;
 443
 444         modeset = intel_crtc_needs_modeset(new_crtc_state);
 445         turn_off = old_visible && (!new_visible || modeset);
 446         turn_on = new_visible && (!old_visible || modeset);
 447
 448         /* Must disable CxSR around plane enable/disable */
 449         if (turn_on || turn_off)
 450                 return true;
 451
 452         if (!old_visible || !new_visible)
 453                 return false;
 454
 455         /*
 456          * Most plane control register updates are blocked while in CxSR.
 457          *
 458          * Tiling mode is one exception where the primary plane can
 459          * apparently handle it, whereas the sprites can not (the
 460          * sprite issue being only relevant on VLV/CHV where CxSR
 461          * is actually possible with a sprite enabled).
 462          */
 463         if (plane->id == PLANE_PRIMARY) {
 464                 old_ctl &= ~DISP_TILED;
 465                 new_ctl &= ~DISP_TILED;
 466         }
 467
 468         return old_ctl != new_ctl;
 469 }
 470
 471 static int intel_plane_atomic_calc_changes(const struct intel_crtc_state *old_crtc_state,
 472                                            struct intel_crtc_state *new_crtc_state,
 473                                            const struct intel_plane_state *old_plane_state,
 474                                            struct intel_plane_state *new_plane_state)
 475 {
 476         struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->uapi.crtc);
 477         struct intel_plane *plane = to_intel_plane(new_plane_state->uapi.plane);
 478         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 479         bool mode_changed = intel_crtc_needs_modeset(new_crtc_state);
 480         bool was_crtc_enabled = old_crtc_state->hw.active;
 481         bool is_crtc_enabled = new_crtc_state->hw.active;
 482         bool turn_off, turn_on, visible, was_visible;
 483         int ret;
 484
 485         if (DISPLAY_VER(dev_priv) >= 9 && plane->id != PLANE_CURSOR) {
 486                 ret = skl_update_scaler_plane(new_crtc_state, new_plane_state);
 487                 if (ret)
 488                         return ret;
 489         }
 490
 491         was_visible = old_plane_state->uapi.visible;
 492         visible = new_plane_state->uapi.visible;
 493
 494         if (!was_crtc_enabled && drm_WARN_ON(&dev_priv->drm, was_visible))
 495                 was_visible = false;
 496
 497         /*
 498          * Visibility is calculated as if the crtc was on, but
 499          * after scaler setup everything depends on it being off
 500          * when the crtc isn't active.
 501          *
 502          * FIXME this is wrong for watermarks. Watermarks should also
 503          * be computed as if the pipe would be active. Perhaps move
 504          * per-plane wm computation to the .check_plane() hook, and
 505          * only combine the results from all planes in the current place?
 506          */
 507         if (!is_crtc_enabled) {
 508                 intel_plane_set_invisible(new_crtc_state, new_plane_state);
 509                 visible = false;
 510         }
 511
 512         if (!was_visible && !visible)
 513                 return 0;
 514
 515         turn_off = was_visible && (!visible || mode_changed);
 516         turn_on = visible && (!was_visible || mode_changed);
 517
 518         drm_dbg_atomic(&dev_priv->drm,
 519                        "[CRTC:%d:%s] with [PLANE:%d:%s] visible %i -> %i, off %i, on %i, ms %i\n",
 520                        crtc->base.base.id, crtc->base.name,
 521                        plane->base.base.id, plane->base.name,
 522                        was_visible, visible,
 523                        turn_off, turn_on, mode_changed);
 524
 525         if (turn_on) {
 526                 if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv))
 527                         new_crtc_state->update_wm_pre = true;
 528         } else if (turn_off) {
 529                 if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv))
 530                         new_crtc_state->update_wm_post = true;
 531         } else if (intel_wm_need_update(old_plane_state, new_plane_state)) {
 532                 if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv)) {
 533                         /* FIXME bollocks */
 534                         new_crtc_state->update_wm_pre = true;
 535                         new_crtc_state->update_wm_post = true;
 536                 }
 537         }
 538
 539         if (visible || was_visible)
 540                 new_crtc_state->fb_bits |= plane->frontbuffer_bit;
 541
 542         if (HAS_GMCH(dev_priv) &&
 543             i9xx_must_disable_cxsr(new_crtc_state, old_plane_state, new_plane_state))
 544                 new_crtc_state->disable_cxsr = true;
 545
 546         /*
 547          * ILK/SNB DVSACNTR/Sprite Enable
 548          * IVB SPR_CTL/Sprite Enable
 549          * "When in Self Refresh Big FIFO mode, a write to enable the
 550          *  plane will be internally buffered and delayed while Big FIFO
 551          *  mode is exiting."
 552          *
 553          * Which means that enabling the sprite can take an extra frame
 554          * when we start in big FIFO mode (LP1+). Thus we need to drop
 555          * down to LP0 and wait for vblank in order to make sure the
 556          * sprite gets enabled on the next vblank after the register write.
 557          * Doing otherwise would risk enabling the sprite one frame after
 558          * we've already signalled flip completion. We can resume LP1+
 559          * once the sprite has been enabled.
 560          *
 561          *
 562          * WaCxSRDisabledForSpriteScaling:ivb
 563          * IVB SPR_SCALE/Scaling Enable
 564          * "Low Power watermarks must be disabled for at least one
 565          *  frame before enabling sprite scaling, and kept disabled
 566          *  until sprite scaling is disabled."
 567          *
 568          * ILK/SNB DVSASCALE/Scaling Enable
 569          * "When in Self Refresh Big FIFO mode, scaling enable will be
 570          *  masked off while Big FIFO mode is exiting."
 571          *
 572          * Despite the w/a only being listed for IVB we assume that
 573          * the ILK/SNB note has similar ramifications, hence we apply
 574          * the w/a on all three platforms.
 575          *
 576          * With experimental results seems this is needed also for primary
 577          * plane, not only sprite plane.
 578          */
 579         if (plane->id != PLANE_CURSOR &&
 580             (IS_IRONLAKE(dev_priv) || IS_SANDYBRIDGE(dev_priv) ||
 581              IS_IVYBRIDGE(dev_priv)) &&
 582             (turn_on || (!intel_plane_is_scaled(old_plane_state) &&
 583                          intel_plane_is_scaled(new_plane_state))))
 584                 new_crtc_state->disable_lp_wm = true;
 585
 586         if (intel_plane_do_async_flip(plane, old_crtc_state, new_crtc_state)) {
 587                 new_crtc_state->do_async_flip = true;
 588                 new_crtc_state->async_flip_planes |= BIT(plane->id);
 589         }
 590
 591         return 0;
 592 }
 593
 594 int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_state,
 595                                         struct intel_crtc_state *new_crtc_state,
 596                                         const struct intel_plane_state *old_plane_state,
 597                                         struct intel_plane_state *new_plane_state)
 598 {
 599         struct intel_plane *plane = to_intel_plane(new_plane_state->uapi.plane);
 600         const struct drm_framebuffer *fb = new_plane_state->hw.fb;
 601         int ret;
 602
 603         intel_plane_set_invisible(new_crtc_state, new_plane_state);
 604         new_crtc_state->enabled_planes &= ~BIT(plane->id);
 605
 606         if (!new_plane_state->hw.crtc && !old_plane_state->hw.crtc)
 607                 return 0;
 608
 609         ret = plane->check_plane(new_crtc_state, new_plane_state);
 610         if (ret)
 611                 return ret;
 612
 613         if (fb)
 614                 new_crtc_state->enabled_planes |= BIT(plane->id);
 615
 616         /* FIXME pre-g4x don't work like this */
 617         if (new_plane_state->uapi.visible)
 618                 new_crtc_state->active_planes |= BIT(plane->id);
 619
 620         if (new_plane_state->uapi.visible &&
 621             intel_plane_is_scaled(new_plane_state))
 622                 new_crtc_state->scaled_planes |= BIT(plane->id);
 623
 624         if (new_plane_state->uapi.visible &&
 625             intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier))
 626                 new_crtc_state->nv12_planes |= BIT(plane->id);
 627
 628         if (new_plane_state->uapi.visible &&
 629             fb->format->format == DRM_FORMAT_C8)
 630                 new_crtc_state->c8_planes |= BIT(plane->id);
 631
 632         if (new_plane_state->uapi.visible || old_plane_state->uapi.visible)
 633                 new_crtc_state->update_planes |= BIT(plane->id);
 634
 635         if (new_plane_state->uapi.visible &&
 636             intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier)) {
 637                 new_crtc_state->data_rate_y[plane->id] =
 638                         intel_plane_data_rate(new_crtc_state, new_plane_state, 0);
 639                 new_crtc_state->data_rate[plane->id] =
 640                         intel_plane_data_rate(new_crtc_state, new_plane_state, 1);
 641
 642                 new_crtc_state->rel_data_rate_y[plane->id] =
 643                         intel_plane_relative_data_rate(new_crtc_state,
 644                                                        new_plane_state, 0);
 645                 new_crtc_state->rel_data_rate[plane->id] =
 646                         intel_plane_relative_data_rate(new_crtc_state,
 647                                                        new_plane_state, 1);
 648         } else if (new_plane_state->uapi.visible) {
 649                 new_crtc_state->data_rate[plane->id] =
 650                         intel_plane_data_rate(new_crtc_state, new_plane_state, 0);
 651
 652                 new_crtc_state->rel_data_rate[plane->id] =
 653                         intel_plane_relative_data_rate(new_crtc_state,
 654                                                        new_plane_state, 0);
 655         }
 656
 657         return intel_plane_atomic_calc_changes(old_crtc_state, new_crtc_state,
 658                                                old_plane_state, new_plane_state);
 659 }
 660
 661 static struct intel_plane *
 662 intel_crtc_get_plane(struct intel_crtc *crtc, enum plane_id plane_id)
 663 {
 664         struct drm_i915_private *i915 = to_i915(crtc->base.dev);
 665         struct intel_plane *plane;
 666
 667         for_each_intel_plane_on_crtc(&i915->drm, crtc, plane) {
 668                 if (plane->id == plane_id)
 669                         return plane;
 670         }
 671
 672         return NULL;
 673 }
 674
 675 int intel_plane_atomic_check(struct intel_atomic_state *state,
 676                              struct intel_plane *plane)
 677 {
 678         struct drm_i915_private *i915 = to_i915(state->base.dev);
 679         struct intel_plane_state *new_plane_state =
 680                 intel_atomic_get_new_plane_state(state, plane);
 681         const struct intel_plane_state *old_plane_state =
 682                 intel_atomic_get_old_plane_state(state, plane);
 683         const struct intel_plane_state *new_master_plane_state;
 684         struct intel_crtc *crtc = intel_crtc_for_pipe(i915, plane->pipe);
 685         const struct intel_crtc_state *old_crtc_state =
 686                 intel_atomic_get_old_crtc_state(state, crtc);
 687         struct intel_crtc_state *new_crtc_state =
 688                 intel_atomic_get_new_crtc_state(state, crtc);
 689
 690         if (new_crtc_state && intel_crtc_is_bigjoiner_slave(new_crtc_state)) {
 691                 struct intel_crtc *master_crtc =
 692                         intel_master_crtc(new_crtc_state);
 693                 struct intel_plane *master_plane =
 694                         intel_crtc_get_plane(master_crtc, plane->id);
 695
 696                 new_master_plane_state =
 697                         intel_atomic_get_new_plane_state(state, master_plane);
 698         } else {
 699                 new_master_plane_state = new_plane_state;
 700         }
 701
 702         intel_plane_copy_uapi_to_hw_state(new_plane_state,
 703                                           new_master_plane_state,
 704                                           crtc);
 705
 706         new_plane_state->uapi.visible = false;
 707         if (!new_crtc_state)
 708                 return 0;
 709
 710         return intel_plane_atomic_check_with_state(old_crtc_state,
 711                                                    new_crtc_state,
 712                                                    old_plane_state,
 713                                                    new_plane_state);
 714 }
 715
 716 static struct intel_plane *
 717 skl_next_plane_to_commit(struct intel_atomic_state *state,
 718                          struct intel_crtc *crtc,
 719                          struct skl_ddb_entry ddb[I915_MAX_PLANES],
 720                          struct skl_ddb_entry ddb_y[I915_MAX_PLANES],
 721                          unsigned int *update_mask)
 722 {
 723         struct intel_crtc_state *crtc_state =
 724                 intel_atomic_get_new_crtc_state(state, crtc);
 725         struct intel_plane_state *plane_state;
 726         struct intel_plane *plane;
 727         int i;
 728
 729         if (*update_mask == 0)
 730                 return NULL;
 731
 732         for_each_new_intel_plane_in_state(state, plane, plane_state, i) {
 733                 enum plane_id plane_id = plane->id;
 734
 735                 if (crtc->pipe != plane->pipe ||
 736                     !(*update_mask & BIT(plane_id)))
 737                         continue;
 738
 739                 if (skl_ddb_allocation_overlaps(&crtc_state->wm.skl.plane_ddb[plane_id],
 740                                                 ddb, I915_MAX_PLANES, plane_id) ||
 741                     skl_ddb_allocation_overlaps(&crtc_state->wm.skl.plane_ddb_y[plane_id],
 742                                                 ddb_y, I915_MAX_PLANES, plane_id))
 743                         continue;
 744
 745                 *update_mask &= ~BIT(plane_id);
 746                 ddb[plane_id] = crtc_state->wm.skl.plane_ddb[plane_id];
 747                 ddb_y[plane_id] = crtc_state->wm.skl.plane_ddb_y[plane_id];
 748
 749                 return plane;
 750         }
 751
 752         /* should never happen */
 753         drm_WARN_ON(state->base.dev, 1);
 754
 755         return NULL;
 756 }
 757
 758 void intel_plane_update_noarm(struct intel_plane *plane,
 759                               const struct intel_crtc_state *crtc_state,
 760                               const struct intel_plane_state *plane_state)
 761 {
 762         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 763
 764         trace_intel_plane_update_noarm(plane, crtc);
 765
 766         if (plane->update_noarm)
 767                 plane->update_noarm(plane, crtc_state, plane_state);
 768 }
 769
 770 void intel_plane_update_arm(struct intel_plane *plane,
 771                             const struct intel_crtc_state *crtc_state,
 772                             const struct intel_plane_state *plane_state)
 773 {
 774         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 775
 776         trace_intel_plane_update_arm(plane, crtc);
 777
 778         if (crtc_state->do_async_flip && plane->async_flip)
 779                 plane->async_flip(plane, crtc_state, plane_state, true);
 780         else
 781                 plane->update_arm(plane, crtc_state, plane_state);
 782 }
 783
 784 void intel_plane_disable_arm(struct intel_plane *plane,
 785                              const struct intel_crtc_state *crtc_state)
 786 {
 787         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 788
 789         trace_intel_plane_disable_arm(plane, crtc);
 790         plane->disable_arm(plane, crtc_state);
 791 }
 792
 793 void intel_crtc_planes_update_noarm(struct intel_atomic_state *state,
 794                                     struct intel_crtc *crtc)
 795 {
 796         struct intel_crtc_state *new_crtc_state =
 797                 intel_atomic_get_new_crtc_state(state, crtc);
 798         u32 update_mask = new_crtc_state->update_planes;
 799         struct intel_plane_state *new_plane_state;
 800         struct intel_plane *plane;
 801         int i;
 802
 803         if (new_crtc_state->do_async_flip)
 804                 return;
 805
 806         /*
 807          * Since we only write non-arming registers here,
 808          * the order does not matter even for skl+.
 809          */
 810         for_each_new_intel_plane_in_state(state, plane, new_plane_state, i) {
 811                 if (crtc->pipe != plane->pipe ||
 812                     !(update_mask & BIT(plane->id)))
 813                         continue;
 814
 815                 /* TODO: for mailbox updates this should be skipped */
 816                 if (new_plane_state->uapi.visible ||
 817                     new_plane_state->planar_slave)
 818                         intel_plane_update_noarm(plane, new_crtc_state, new_plane_state);
 819         }
 820 }
 821
 822 static void skl_crtc_planes_update_arm(struct intel_atomic_state *state,
 823                                        struct intel_crtc *crtc)
 824 {
 825         struct intel_crtc_state *old_crtc_state =
 826                 intel_atomic_get_old_crtc_state(state, crtc);
 827         struct intel_crtc_state *new_crtc_state =
 828                 intel_atomic_get_new_crtc_state(state, crtc);
 829         struct skl_ddb_entry ddb[I915_MAX_PLANES];
 830         struct skl_ddb_entry ddb_y[I915_MAX_PLANES];
 831         u32 update_mask = new_crtc_state->update_planes;
 832         struct intel_plane *plane;
 833
 834         memcpy(ddb, old_crtc_state->wm.skl.plane_ddb,
 835                sizeof(old_crtc_state->wm.skl.plane_ddb));
 836         memcpy(ddb_y, old_crtc_state->wm.skl.plane_ddb_y,
 837                sizeof(old_crtc_state->wm.skl.plane_ddb_y));
 838
 839         while ((plane = skl_next_plane_to_commit(state, crtc, ddb, ddb_y, &update_mask))) {
 840                 struct intel_plane_state *new_plane_state =
 841                         intel_atomic_get_new_plane_state(state, plane);
 842
 843                 /*
 844                  * TODO: for mailbox updates intel_plane_update_noarm()
 845                  * would have to be called here as well.
 846                  */
 847                 if (new_plane_state->uapi.visible ||
 848                     new_plane_state->planar_slave)
 849                         intel_plane_update_arm(plane, new_crtc_state, new_plane_state);
 850                 else
 851                         intel_plane_disable_arm(plane, new_crtc_state);
 852         }
 853 }
 854
 855 static void i9xx_crtc_planes_update_arm(struct intel_atomic_state *state,
 856                                         struct intel_crtc *crtc)
 857 {
 858         struct intel_crtc_state *new_crtc_state =
 859                 intel_atomic_get_new_crtc_state(state, crtc);
 860         u32 update_mask = new_crtc_state->update_planes;
 861         struct intel_plane_state *new_plane_state;
 862         struct intel_plane *plane;
 863         int i;
 864
 865         for_each_new_intel_plane_in_state(state, plane, new_plane_state, i) {
 866                 if (crtc->pipe != plane->pipe ||
 867                     !(update_mask & BIT(plane->id)))
 868                         continue;
 869
 870                 /*
 871                  * TODO: for mailbox updates intel_plane_update_noarm()
 872                  * would have to be called here as well.
 873                  */
 874                 if (new_plane_state->uapi.visible)
 875                         intel_plane_update_arm(plane, new_crtc_state, new_plane_state);
 876                 else
 877                         intel_plane_disable_arm(plane, new_crtc_state);
 878         }
 879 }
 880
 881 void intel_crtc_planes_update_arm(struct intel_atomic_state *state,
 882                                   struct intel_crtc *crtc)
 883 {
 884         struct drm_i915_private *i915 = to_i915(state->base.dev);
 885
 886         if (DISPLAY_VER(i915) >= 9)
 887                 skl_crtc_planes_update_arm(state, crtc);
 888         else
 889                 i9xx_crtc_planes_update_arm(state, crtc);
 890 }
 891
 892 int intel_atomic_plane_check_clipping(struct intel_plane_state *plane_state,
 893                                       struct intel_crtc_state *crtc_state,
 894                                       int min_scale, int max_scale,
 895                                       bool can_position)
 896 {
 897         struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
 898         struct drm_framebuffer *fb = plane_state->hw.fb;
 899         struct drm_rect *src = &plane_state->uapi.src;
 900         struct drm_rect *dst = &plane_state->uapi.dst;
 901         const struct drm_rect *clip = &crtc_state->pipe_src;
 902         unsigned int rotation = plane_state->hw.rotation;
 903         int hscale, vscale;
 904
 905         if (!fb) {
 906                 plane_state->uapi.visible = false;
 907                 return 0;
 908         }
 909
 910         drm_rect_rotate(src, fb->width << 16, fb->height << 16, rotation);
 911
 912         /* Check scaling */
 913         hscale = drm_rect_calc_hscale(src, dst, min_scale, max_scale);
 914         vscale = drm_rect_calc_vscale(src, dst, min_scale, max_scale);
 915         if (hscale < 0 || vscale < 0) {
 916                 drm_dbg_kms(&i915->drm, "Invalid scaling of plane\n");
 917                 drm_rect_debug_print("src: ", src, true);
 918                 drm_rect_debug_print("dst: ", dst, false);
 919                 return -ERANGE;
 920         }
 921
 922         /*
 923          * FIXME: This might need further adjustment for seamless scaling
 924          * with phase information, for the 2p2 and 2p1 scenarios.
 925          */
 926         plane_state->uapi.visible = drm_rect_clip_scaled(src, dst, clip);
 927
 928         drm_rect_rotate_inv(src, fb->width << 16, fb->height << 16, rotation);
 929
 930         if (!can_position && plane_state->uapi.visible &&
 931             !drm_rect_equals(dst, clip)) {
 932                 drm_dbg_kms(&i915->drm, "Plane must cover entire CRTC\n");
 933                 drm_rect_debug_print("dst: ", dst, false);
 934                 drm_rect_debug_print("clip: ", clip, false);
 935                 return -EINVAL;
 936         }
 937
 938         /* final plane coordinates will be relative to the plane's pipe */
 939         drm_rect_translate(dst, -clip->x1, -clip->y1);
 940
 941         return 0;
 942 }
 943
 944 int intel_plane_check_src_coordinates(struct intel_plane_state *plane_state)
 945 {
 946         struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
 947         const struct drm_framebuffer *fb = plane_state->hw.fb;
 948         struct drm_rect *src = &plane_state->uapi.src;
 949         u32 src_x, src_y, src_w, src_h, hsub, vsub;
 950         bool rotated = drm_rotation_90_or_270(plane_state->hw.rotation);
 951
 952         /*
 953          * FIXME hsub/vsub vs. block size is a mess. Pre-tgl CCS
 954          * abuses hsub/vsub so we can't use them here. But as they
 955          * are limited to 32bpp RGB formats we don't actually need
 956          * to check anything.
 957          */
 958         if (fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
 959             fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS)
 960                 return 0;
 961
 962         /*
 963          * Hardware doesn't handle subpixel coordinates.
 964          * Adjust to (macro)pixel boundary, but be careful not to
 965          * increase the source viewport size, because that could
 966          * push the downscaling factor out of bounds.
 967          */
 968         src_x = src->x1 >> 16;
 969         src_w = drm_rect_width(src) >> 16;
 970         src_y = src->y1 >> 16;
 971         src_h = drm_rect_height(src) >> 16;
 972
 973         drm_rect_init(src, src_x << 16, src_y << 16,
 974                       src_w << 16, src_h << 16);
 975
 976         if (fb->format->format == DRM_FORMAT_RGB565 && rotated) {
 977                 hsub = 2;
 978                 vsub = 2;
 979         } else {
 980                 hsub = fb->format->hsub;
 981                 vsub = fb->format->vsub;
 982         }
 983
 984         if (rotated)
 985                 hsub = vsub = max(hsub, vsub);
 986
 987         if (src_x % hsub || src_w % hsub) {
 988                 drm_dbg_kms(&i915->drm, "src x/w (%u, %u) must be a multiple of %u (rotated: %s)\n",
 989                             src_x, src_w, hsub, str_yes_no(rotated));
 990                 return -EINVAL;
 991         }
 992
 993         if (src_y % vsub || src_h % vsub) {
 994                 drm_dbg_kms(&i915->drm, "src y/h (%u, %u) must be a multiple of %u (rotated: %s)\n",
 995                             src_y, src_h, vsub, str_yes_no(rotated));
 996                 return -EINVAL;
 997         }
 998
 999         return 0;
1000 }
1001
1002 /**
1003  * intel_prepare_plane_fb - Prepare fb for usage on plane
1004  * @_plane: drm plane to prepare for
1005  * @_new_plane_state: the plane state being prepared
1006  *
1007  * Prepares a framebuffer for usage on a display plane.  Generally this
1008  * involves pinning the underlying object and updating the frontbuffer tracking
1009  * bits.  Some older platforms need special physical address handling for
1010  * cursor planes.
1011  *
1012  * Returns 0 on success, negative error code on failure.
1013  */
1014 static int
1015 intel_prepare_plane_fb(struct drm_plane *_plane,
1016                        struct drm_plane_state *_new_plane_state)
1017 {
1018         struct i915_sched_attr attr = { .priority = I915_PRIORITY_DISPLAY };
1019         struct intel_plane *plane = to_intel_plane(_plane);
1020         struct intel_plane_state *new_plane_state =
1021                 to_intel_plane_state(_new_plane_state);
1022         struct intel_atomic_state *state =
1023                 to_intel_atomic_state(new_plane_state->uapi.state);
1024         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
1025         const struct intel_plane_state *old_plane_state =
1026                 intel_atomic_get_old_plane_state(state, plane);
1027         struct drm_i915_gem_object *obj = intel_fb_obj(new_plane_state->hw.fb);
1028         struct drm_i915_gem_object *old_obj = intel_fb_obj(old_plane_state->hw.fb);
1029         int ret;
1030
1031         if (old_obj) {
1032                 const struct intel_crtc_state *new_crtc_state =
1033                         intel_atomic_get_new_crtc_state(state,
1034                                                         to_intel_crtc(old_plane_state->hw.crtc));
1035
1036                 /* Big Hammer, we also need to ensure that any pending
1037                  * MI_WAIT_FOR_EVENT inside a user batch buffer on the
1038                  * current scanout is retired before unpinning the old
1039                  * framebuffer. Note that we rely on userspace rendering
1040                  * into the buffer attached to the pipe they are waiting
1041                  * on. If not, userspace generates a GPU hang with IPEHR
1042                  * point to the MI_WAIT_FOR_EVENT.
1043                  *
1044                  * This should only fail upon a hung GPU, in which case we
1045                  * can safely continue.
1046                  */
1047                 if (new_crtc_state && intel_crtc_needs_modeset(new_crtc_state)) {
1048                         ret = i915_sw_fence_await_reservation(&state->commit_ready,
1049                                                               old_obj->base.resv,
1050                                                               false, 0,
1051                                                               GFP_KERNEL);
1052                         if (ret < 0)
1053                                 return ret;
1054                 }
1055         }
1056
1057         if (new_plane_state->uapi.fence) { /* explicit fencing */
1058                 i915_gem_fence_wait_priority(new_plane_state->uapi.fence,
1059                                              &attr);
1060                 ret = i915_sw_fence_await_dma_fence(&state->commit_ready,
1061                                                     new_plane_state->uapi.fence,
1062                                                     i915_fence_timeout(dev_priv),
1063                                                     GFP_KERNEL);
1064                 if (ret < 0)
1065                         return ret;
1066         }
1067
1068         if (!obj)
1069                 return 0;
1070
1071
1072         ret = intel_plane_pin_fb(new_plane_state);
1073         if (ret)
1074                 return ret;
1075
1076         i915_gem_object_wait_priority(obj, 0, &attr);
1077
1078         if (!new_plane_state->uapi.fence) { /* implicit fencing */
1079                 struct dma_resv_iter cursor;
1080                 struct dma_fence *fence;
1081
1082                 ret = i915_sw_fence_await_reservation(&state->commit_ready,
1083                                                       obj->base.resv, false,
1084                                                       i915_fence_timeout(dev_priv),
1085                                                       GFP_KERNEL);
1086                 if (ret < 0)
1087                         goto unpin_fb;
1088
1089                 dma_resv_iter_begin(&cursor, obj->base.resv,
1090                                     DMA_RESV_USAGE_WRITE);
1091                 dma_resv_for_each_fence_unlocked(&cursor, fence) {
1092                         intel_display_rps_boost_after_vblank(new_plane_state->hw.crtc,
1093                                                              fence);
1094                 }
1095                 dma_resv_iter_end(&cursor);
1096         } else {
1097                 intel_display_rps_boost_after_vblank(new_plane_state->hw.crtc,
1098                                                      new_plane_state->uapi.fence);
1099         }
1100
1101         /*
1102          * We declare pageflips to be interactive and so merit a small bias
1103          * towards upclocking to deliver the frame on time. By only changing
1104          * the RPS thresholds to sample more regularly and aim for higher
1105          * clocks we can hopefully deliver low power workloads (like kodi)
1106          * that are not quite steady state without resorting to forcing
1107          * maximum clocks following a vblank miss (see do_rps_boost()).
1108          */
1109         intel_display_rps_mark_interactive(dev_priv, state, true);
1110
1111         return 0;
1112
1113 unpin_fb:
1114         intel_plane_unpin_fb(new_plane_state);
1115
1116         return ret;
1117 }
1118
1119 /**
1120  * intel_cleanup_plane_fb - Cleans up an fb after plane use
1121  * @plane: drm plane to clean up for
1122  * @_old_plane_state: the state from the previous modeset
1123  *
1124  * Cleans up a framebuffer that has just been removed from a plane.
1125  */
1126 static void
1127 intel_cleanup_plane_fb(struct drm_plane *plane,
1128                        struct drm_plane_state *_old_plane_state)
1129 {
1130         struct intel_plane_state *old_plane_state =
1131                 to_intel_plane_state(_old_plane_state);
1132         struct intel_atomic_state *state =
1133                 to_intel_atomic_state(old_plane_state->uapi.state);
1134         struct drm_i915_private *dev_priv = to_i915(plane->dev);
1135         struct drm_i915_gem_object *obj = intel_fb_obj(old_plane_state->hw.fb);
1136
1137         if (!obj)
1138                 return;
1139
1140         intel_display_rps_mark_interactive(dev_priv, state, false);
1141
1142         /* Should only be called after a successful intel_prepare_plane_fb()! */
1143         intel_plane_unpin_fb(old_plane_state);
1144 }
1145
1146 static const struct drm_plane_helper_funcs intel_plane_helper_funcs = {
1147         .prepare_fb = intel_prepare_plane_fb,
1148         .cleanup_fb = intel_cleanup_plane_fb,
1149 };
1150
1151 void intel_plane_helper_add(struct intel_plane *plane)
1152 {
1153         drm_plane_helper_add(&plane->base, &intel_plane_helper_funcs);
1154 }