drivers/gpu/drm/i915/display/icl_dsi.c

   1 /*
   2  * Copyright © 2018 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *   Madhav Chauhan <[email protected]>
  25  *   Jani Nikula <[email protected]>
  26  */
  27
  28 #include <drm/display/drm_dsc_helper.h>
  29 #include <drm/drm_atomic_helper.h>
  30 #include <drm/drm_mipi_dsi.h>
  31
  32 #include "i915_reg.h"
  33 #include "icl_dsi.h"
  34 #include "icl_dsi_regs.h"
  35 #include "intel_atomic.h"
  36 #include "intel_backlight.h"
  37 #include "intel_backlight_regs.h"
  38 #include "intel_combo_phy.h"
  39 #include "intel_combo_phy_regs.h"
  40 #include "intel_connector.h"
  41 #include "intel_crtc.h"
  42 #include "intel_ddi.h"
  43 #include "intel_de.h"
  44 #include "intel_dsi.h"
  45 #include "intel_dsi_vbt.h"
  46 #include "intel_panel.h"
  47 #include "intel_vdsc.h"
  48 #include "intel_vdsc_regs.h"
  49 #include "skl_scaler.h"
  50 #include "skl_universal_plane.h"
  51
  52 static int header_credits_available(struct drm_i915_private *dev_priv,
  53                                     enum transcoder dsi_trans)
  54 {
  55         return (intel_de_read(dev_priv, DSI_CMD_TXCTL(dsi_trans)) & FREE_HEADER_CREDIT_MASK)
  56                 >> FREE_HEADER_CREDIT_SHIFT;
  57 }
  58
  59 static int payload_credits_available(struct drm_i915_private *dev_priv,
  60                                      enum transcoder dsi_trans)
  61 {
  62         return (intel_de_read(dev_priv, DSI_CMD_TXCTL(dsi_trans)) & FREE_PLOAD_CREDIT_MASK)
  63                 >> FREE_PLOAD_CREDIT_SHIFT;
  64 }
  65
  66 static bool wait_for_header_credits(struct drm_i915_private *dev_priv,
  67                                     enum transcoder dsi_trans, int hdr_credit)
  68 {
  69         if (wait_for_us(header_credits_available(dev_priv, dsi_trans) >=
  70                         hdr_credit, 100)) {
  71                 drm_err(&dev_priv->drm, "DSI header credits not released\n");
  72                 return false;
  73         }
  74
  75         return true;
  76 }
  77
  78 static bool wait_for_payload_credits(struct drm_i915_private *dev_priv,
  79                                      enum transcoder dsi_trans, int payld_credit)
  80 {
  81         if (wait_for_us(payload_credits_available(dev_priv, dsi_trans) >=
  82                         payld_credit, 100)) {
  83                 drm_err(&dev_priv->drm, "DSI payload credits not released\n");
  84                 return false;
  85         }
  86
  87         return true;
  88 }
  89
  90 static enum transcoder dsi_port_to_transcoder(enum port port)
  91 {
  92         if (port == PORT_A)
  93                 return TRANSCODER_DSI_0;
  94         else
  95                 return TRANSCODER_DSI_1;
  96 }
  97
  98 static void wait_for_cmds_dispatched_to_panel(struct intel_encoder *encoder)
  99 {
 100         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 101         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 102         struct mipi_dsi_device *dsi;
 103         enum port port;
 104         enum transcoder dsi_trans;
 105         int ret;
 106
 107         /* wait for header/payload credits to be released */
 108         for_each_dsi_port(port, intel_dsi->ports) {
 109                 dsi_trans = dsi_port_to_transcoder(port);
 110                 wait_for_header_credits(dev_priv, dsi_trans, MAX_HEADER_CREDIT);
 111                 wait_for_payload_credits(dev_priv, dsi_trans, MAX_PLOAD_CREDIT);
 112         }
 113
 114         /* send nop DCS command */
 115         for_each_dsi_port(port, intel_dsi->ports) {
 116                 dsi = intel_dsi->dsi_hosts[port]->device;
 117                 dsi->mode_flags |= MIPI_DSI_MODE_LPM;
 118                 dsi->channel = 0;
 119                 ret = mipi_dsi_dcs_nop(dsi);
 120                 if (ret < 0)
 121                         drm_err(&dev_priv->drm,
 122                                 "error sending DCS NOP command\n");
 123         }
 124
 125         /* wait for header credits to be released */
 126         for_each_dsi_port(port, intel_dsi->ports) {
 127                 dsi_trans = dsi_port_to_transcoder(port);
 128                 wait_for_header_credits(dev_priv, dsi_trans, MAX_HEADER_CREDIT);
 129         }
 130
 131         /* wait for LP TX in progress bit to be cleared */
 132         for_each_dsi_port(port, intel_dsi->ports) {
 133                 dsi_trans = dsi_port_to_transcoder(port);
 134                 if (wait_for_us(!(intel_de_read(dev_priv, DSI_LP_MSG(dsi_trans)) &
 135                                   LPTX_IN_PROGRESS), 20))
 136                         drm_err(&dev_priv->drm, "LPTX bit not cleared\n");
 137         }
 138 }
 139
 140 static int dsi_send_pkt_payld(struct intel_dsi_host *host,
 141                               const struct mipi_dsi_packet *packet)
 142 {
 143         struct intel_dsi *intel_dsi = host->intel_dsi;
 144         struct drm_i915_private *i915 = to_i915(intel_dsi->base.base.dev);
 145         enum transcoder dsi_trans = dsi_port_to_transcoder(host->port);
 146         const u8 *data = packet->payload;
 147         u32 len = packet->payload_length;
 148         int i, j;
 149
 150         /* payload queue can accept *256 bytes*, check limit */
 151         if (len > MAX_PLOAD_CREDIT * 4) {
 152                 drm_err(&i915->drm, "payload size exceeds max queue limit\n");
 153                 return -EINVAL;
 154         }
 155
 156         for (i = 0; i < len; i += 4) {
 157                 u32 tmp = 0;
 158
 159                 if (!wait_for_payload_credits(i915, dsi_trans, 1))
 160                         return -EBUSY;
 161
 162                 for (j = 0; j < min_t(u32, len - i, 4); j++)
 163                         tmp |= *data++ << 8 * j;
 164
 165                 intel_de_write(i915, DSI_CMD_TXPYLD(dsi_trans), tmp);
 166         }
 167
 168         return 0;
 169 }
 170
 171 static int dsi_send_pkt_hdr(struct intel_dsi_host *host,
 172                             const struct mipi_dsi_packet *packet,
 173                             bool enable_lpdt)
 174 {
 175         struct intel_dsi *intel_dsi = host->intel_dsi;
 176         struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev);
 177         enum transcoder dsi_trans = dsi_port_to_transcoder(host->port);
 178         u32 tmp;
 179
 180         if (!wait_for_header_credits(dev_priv, dsi_trans, 1))
 181                 return -EBUSY;
 182
 183         tmp = intel_de_read(dev_priv, DSI_CMD_TXHDR(dsi_trans));
 184
 185         if (packet->payload)
 186                 tmp |= PAYLOAD_PRESENT;
 187         else
 188                 tmp &= ~PAYLOAD_PRESENT;
 189
 190         tmp &= ~VBLANK_FENCE;
 191
 192         if (enable_lpdt)
 193                 tmp |= LP_DATA_TRANSFER;
 194         else
 195                 tmp &= ~LP_DATA_TRANSFER;
 196
 197         tmp &= ~(PARAM_WC_MASK | VC_MASK | DT_MASK);
 198         tmp |= ((packet->header[0] & VC_MASK) << VC_SHIFT);
 199         tmp |= ((packet->header[0] & DT_MASK) << DT_SHIFT);
 200         tmp |= (packet->header[1] << PARAM_WC_LOWER_SHIFT);
 201         tmp |= (packet->header[2] << PARAM_WC_UPPER_SHIFT);
 202         intel_de_write(dev_priv, DSI_CMD_TXHDR(dsi_trans), tmp);
 203
 204         return 0;
 205 }
 206
 207 void icl_dsi_frame_update(struct intel_crtc_state *crtc_state)
 208 {
 209         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 210         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 211         u32 mode_flags;
 212         enum port port;
 213
 214         mode_flags = crtc_state->mode_flags;
 215
 216         /*
 217          * case 1 also covers dual link
 218          * In case of dual link, frame update should be set on
 219          * DSI_0
 220          */
 221         if (mode_flags & I915_MODE_FLAG_DSI_USE_TE0)
 222                 port = PORT_A;
 223         else if (mode_flags & I915_MODE_FLAG_DSI_USE_TE1)
 224                 port = PORT_B;
 225         else
 226                 return;
 227
 228         intel_de_rmw(dev_priv, DSI_CMD_FRMCTL(port), 0, DSI_FRAME_UPDATE_REQUEST);
 229 }
 230
 231 static void dsi_program_swing_and_deemphasis(struct intel_encoder *encoder)
 232 {
 233         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 234         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 235         enum phy phy;
 236         u32 tmp, mask, val;
 237         int lane;
 238
 239         for_each_dsi_phy(phy, intel_dsi->phys) {
 240                 /*
 241                  * Program voltage swing and pre-emphasis level values as per
 242                  * table in BSPEC under DDI buffer programing
 243                  */
 244                 mask = SCALING_MODE_SEL_MASK | RTERM_SELECT_MASK;
 245                 val = SCALING_MODE_SEL(0x2) | TAP2_DISABLE | TAP3_DISABLE |
 246                       RTERM_SELECT(0x6);
 247                 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy));
 248                 tmp &= ~mask;
 249                 tmp |= val;
 250                 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), tmp);
 251                 intel_de_rmw(dev_priv, ICL_PORT_TX_DW5_AUX(phy), mask, val);
 252
 253                 mask = SWING_SEL_LOWER_MASK | SWING_SEL_UPPER_MASK |
 254                        RCOMP_SCALAR_MASK;
 255                 val = SWING_SEL_UPPER(0x2) | SWING_SEL_LOWER(0x2) |
 256                       RCOMP_SCALAR(0x98);
 257                 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN(0, phy));
 258                 tmp &= ~mask;
 259                 tmp |= val;
 260                 intel_de_write(dev_priv, ICL_PORT_TX_DW2_GRP(phy), tmp);
 261                 intel_de_rmw(dev_priv, ICL_PORT_TX_DW2_AUX(phy), mask, val);
 262
 263                 mask = POST_CURSOR_1_MASK | POST_CURSOR_2_MASK |
 264                        CURSOR_COEFF_MASK;
 265                 val = POST_CURSOR_1(0x0) | POST_CURSOR_2(0x0) |
 266                       CURSOR_COEFF(0x3f);
 267                 intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_AUX(phy), mask, val);
 268
 269                 /* Bspec: must not use GRP register for write */
 270                 for (lane = 0; lane <= 3; lane++)
 271                         intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_LN(lane, phy),
 272                                      mask, val);
 273         }
 274 }
 275
 276 static void configure_dual_link_mode(struct intel_encoder *encoder,
 277                                      const struct intel_crtc_state *pipe_config)
 278 {
 279         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 280         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 281         i915_reg_t dss_ctl1_reg, dss_ctl2_reg;
 282         u32 dss_ctl1;
 283
 284         /* FIXME: Move all DSS handling to intel_vdsc.c */
 285         if (DISPLAY_VER(dev_priv) >= 12) {
 286                 struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
 287
 288                 dss_ctl1_reg = ICL_PIPE_DSS_CTL1(crtc->pipe);
 289                 dss_ctl2_reg = ICL_PIPE_DSS_CTL2(crtc->pipe);
 290         } else {
 291                 dss_ctl1_reg = DSS_CTL1;
 292                 dss_ctl2_reg = DSS_CTL2;
 293         }
 294
 295         dss_ctl1 = intel_de_read(dev_priv, dss_ctl1_reg);
 296         dss_ctl1 |= SPLITTER_ENABLE;
 297         dss_ctl1 &= ~OVERLAP_PIXELS_MASK;
 298         dss_ctl1 |= OVERLAP_PIXELS(intel_dsi->pixel_overlap);
 299
 300         if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
 301                 const struct drm_display_mode *adjusted_mode =
 302                                         &pipe_config->hw.adjusted_mode;
 303                 u16 hactive = adjusted_mode->crtc_hdisplay;
 304                 u16 dl_buffer_depth;
 305
 306                 dss_ctl1 &= ~DUAL_LINK_MODE_INTERLEAVE;
 307                 dl_buffer_depth = hactive / 2 + intel_dsi->pixel_overlap;
 308
 309                 if (dl_buffer_depth > MAX_DL_BUFFER_TARGET_DEPTH)
 310                         drm_err(&dev_priv->drm,
 311                                 "DL buffer depth exceed max value\n");
 312
 313                 dss_ctl1 &= ~LEFT_DL_BUF_TARGET_DEPTH_MASK;
 314                 dss_ctl1 |= LEFT_DL_BUF_TARGET_DEPTH(dl_buffer_depth);
 315                 intel_de_rmw(dev_priv, dss_ctl2_reg, RIGHT_DL_BUF_TARGET_DEPTH_MASK,
 316                              RIGHT_DL_BUF_TARGET_DEPTH(dl_buffer_depth));
 317         } else {
 318                 /* Interleave */
 319                 dss_ctl1 |= DUAL_LINK_MODE_INTERLEAVE;
 320         }
 321
 322         intel_de_write(dev_priv, dss_ctl1_reg, dss_ctl1);
 323 }
 324
 325 /* aka DSI 8X clock */
 326 static int afe_clk(struct intel_encoder *encoder,
 327                    const struct intel_crtc_state *crtc_state)
 328 {
 329         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 330         int bpp;
 331
 332         if (crtc_state->dsc.compression_enable)
 333                 bpp = crtc_state->dsc.compressed_bpp;
 334         else
 335                 bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
 336
 337         return DIV_ROUND_CLOSEST(intel_dsi->pclk * bpp, intel_dsi->lane_count);
 338 }
 339
 340 static void gen11_dsi_program_esc_clk_div(struct intel_encoder *encoder,
 341                                           const struct intel_crtc_state *crtc_state)
 342 {
 343         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 344         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 345         enum port port;
 346         int afe_clk_khz;
 347         int theo_word_clk, act_word_clk;
 348         u32 esc_clk_div_m, esc_clk_div_m_phy;
 349
 350         afe_clk_khz = afe_clk(encoder, crtc_state);
 351
 352         if (IS_ALDERLAKE_S(dev_priv) || IS_ALDERLAKE_P(dev_priv)) {
 353                 theo_word_clk = DIV_ROUND_UP(afe_clk_khz, 8 * DSI_MAX_ESC_CLK);
 354                 act_word_clk = max(3, theo_word_clk + (theo_word_clk + 1) % 2);
 355                 esc_clk_div_m = act_word_clk * 8;
 356                 esc_clk_div_m_phy = (act_word_clk - 1) / 2;
 357         } else {
 358                 esc_clk_div_m = DIV_ROUND_UP(afe_clk_khz, DSI_MAX_ESC_CLK);
 359         }
 360
 361         for_each_dsi_port(port, intel_dsi->ports) {
 362                 intel_de_write(dev_priv, ICL_DSI_ESC_CLK_DIV(port),
 363                                esc_clk_div_m & ICL_ESC_CLK_DIV_MASK);
 364                 intel_de_posting_read(dev_priv, ICL_DSI_ESC_CLK_DIV(port));
 365         }
 366
 367         for_each_dsi_port(port, intel_dsi->ports) {
 368                 intel_de_write(dev_priv, ICL_DPHY_ESC_CLK_DIV(port),
 369                                esc_clk_div_m & ICL_ESC_CLK_DIV_MASK);
 370                 intel_de_posting_read(dev_priv, ICL_DPHY_ESC_CLK_DIV(port));
 371         }
 372
 373         if (IS_ALDERLAKE_S(dev_priv) || IS_ALDERLAKE_P(dev_priv)) {
 374                 for_each_dsi_port(port, intel_dsi->ports) {
 375                         intel_de_write(dev_priv, ADL_MIPIO_DW(port, 8),
 376                                        esc_clk_div_m_phy & TX_ESC_CLK_DIV_PHY);
 377                         intel_de_posting_read(dev_priv, ADL_MIPIO_DW(port, 8));
 378                 }
 379         }
 380 }
 381
 382 static void get_dsi_io_power_domains(struct drm_i915_private *dev_priv,
 383                                      struct intel_dsi *intel_dsi)
 384 {
 385         enum port port;
 386
 387         for_each_dsi_port(port, intel_dsi->ports) {
 388                 drm_WARN_ON(&dev_priv->drm, intel_dsi->io_wakeref[port]);
 389                 intel_dsi->io_wakeref[port] =
 390                         intel_display_power_get(dev_priv,
 391                                                 port == PORT_A ?
 392                                                 POWER_DOMAIN_PORT_DDI_IO_A :
 393                                                 POWER_DOMAIN_PORT_DDI_IO_B);
 394         }
 395 }
 396
 397 static void gen11_dsi_enable_io_power(struct intel_encoder *encoder)
 398 {
 399         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 400         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 401         enum port port;
 402
 403         for_each_dsi_port(port, intel_dsi->ports)
 404                 intel_de_rmw(dev_priv, ICL_DSI_IO_MODECTL(port),
 405                              0, COMBO_PHY_MODE_DSI);
 406
 407         get_dsi_io_power_domains(dev_priv, intel_dsi);
 408 }
 409
 410 static void gen11_dsi_power_up_lanes(struct intel_encoder *encoder)
 411 {
 412         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 413         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 414         enum phy phy;
 415
 416         for_each_dsi_phy(phy, intel_dsi->phys)
 417                 intel_combo_phy_power_up_lanes(dev_priv, phy, true,
 418                                                intel_dsi->lane_count, false);
 419 }
 420
 421 static void gen11_dsi_config_phy_lanes_sequence(struct intel_encoder *encoder)
 422 {
 423         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 424         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 425         enum phy phy;
 426         u32 tmp;
 427         int lane;
 428
 429         /* Step 4b(i) set loadgen select for transmit and aux lanes */
 430         for_each_dsi_phy(phy, intel_dsi->phys) {
 431                 intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_AUX(phy), LOADGEN_SELECT, 0);
 432                 for (lane = 0; lane <= 3; lane++)
 433                         intel_de_rmw(dev_priv, ICL_PORT_TX_DW4_LN(lane, phy),
 434                                      LOADGEN_SELECT, lane != 2 ? LOADGEN_SELECT : 0);
 435         }
 436
 437         /* Step 4b(ii) set latency optimization for transmit and aux lanes */
 438         for_each_dsi_phy(phy, intel_dsi->phys) {
 439                 intel_de_rmw(dev_priv, ICL_PORT_TX_DW2_AUX(phy),
 440                              FRC_LATENCY_OPTIM_MASK, FRC_LATENCY_OPTIM_VAL(0x5));
 441                 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW2_LN(0, phy));
 442                 tmp &= ~FRC_LATENCY_OPTIM_MASK;
 443                 tmp |= FRC_LATENCY_OPTIM_VAL(0x5);
 444                 intel_de_write(dev_priv, ICL_PORT_TX_DW2_GRP(phy), tmp);
 445
 446                 /* For EHL, TGL, set latency optimization for PCS_DW1 lanes */
 447                 if (IS_JSL_EHL(dev_priv) || (DISPLAY_VER(dev_priv) >= 12)) {
 448                         intel_de_rmw(dev_priv, ICL_PORT_PCS_DW1_AUX(phy),
 449                                      LATENCY_OPTIM_MASK, LATENCY_OPTIM_VAL(0));
 450
 451                         tmp = intel_de_read(dev_priv,
 452                                             ICL_PORT_PCS_DW1_LN(0, phy));
 453                         tmp &= ~LATENCY_OPTIM_MASK;
 454                         tmp |= LATENCY_OPTIM_VAL(0x1);
 455                         intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy),
 456                                        tmp);
 457                 }
 458         }
 459
 460 }
 461
 462 static void gen11_dsi_voltage_swing_program_seq(struct intel_encoder *encoder)
 463 {
 464         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 465         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 466         u32 tmp;
 467         enum phy phy;
 468
 469         /* clear common keeper enable bit */
 470         for_each_dsi_phy(phy, intel_dsi->phys) {
 471                 tmp = intel_de_read(dev_priv, ICL_PORT_PCS_DW1_LN(0, phy));
 472                 tmp &= ~COMMON_KEEPER_EN;
 473                 intel_de_write(dev_priv, ICL_PORT_PCS_DW1_GRP(phy), tmp);
 474                 intel_de_rmw(dev_priv, ICL_PORT_PCS_DW1_AUX(phy), COMMON_KEEPER_EN, 0);
 475         }
 476
 477         /*
 478          * Set SUS Clock Config bitfield to 11b
 479          * Note: loadgen select program is done
 480          * as part of lane phy sequence configuration
 481          */
 482         for_each_dsi_phy(phy, intel_dsi->phys)
 483                 intel_de_rmw(dev_priv, ICL_PORT_CL_DW5(phy), 0, SUS_CLOCK_CONFIG);
 484
 485         /* Clear training enable to change swing values */
 486         for_each_dsi_phy(phy, intel_dsi->phys) {
 487                 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy));
 488                 tmp &= ~TX_TRAINING_EN;
 489                 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), tmp);
 490                 intel_de_rmw(dev_priv, ICL_PORT_TX_DW5_AUX(phy), TX_TRAINING_EN, 0);
 491         }
 492
 493         /* Program swing and de-emphasis */
 494         dsi_program_swing_and_deemphasis(encoder);
 495
 496         /* Set training enable to trigger update */
 497         for_each_dsi_phy(phy, intel_dsi->phys) {
 498                 tmp = intel_de_read(dev_priv, ICL_PORT_TX_DW5_LN(0, phy));
 499                 tmp |= TX_TRAINING_EN;
 500                 intel_de_write(dev_priv, ICL_PORT_TX_DW5_GRP(phy), tmp);
 501                 intel_de_rmw(dev_priv, ICL_PORT_TX_DW5_AUX(phy), 0, TX_TRAINING_EN);
 502         }
 503 }
 504
 505 static void gen11_dsi_enable_ddi_buffer(struct intel_encoder *encoder)
 506 {
 507         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 508         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 509         enum port port;
 510
 511         for_each_dsi_port(port, intel_dsi->ports) {
 512                 intel_de_rmw(dev_priv, DDI_BUF_CTL(port), 0, DDI_BUF_CTL_ENABLE);
 513
 514                 if (wait_for_us(!(intel_de_read(dev_priv, DDI_BUF_CTL(port)) &
 515                                   DDI_BUF_IS_IDLE),
 516                                   500))
 517                         drm_err(&dev_priv->drm, "DDI port:%c buffer idle\n",
 518                                 port_name(port));
 519         }
 520 }
 521
 522 static void
 523 gen11_dsi_setup_dphy_timings(struct intel_encoder *encoder,
 524                              const struct intel_crtc_state *crtc_state)
 525 {
 526         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 527         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 528         enum port port;
 529         enum phy phy;
 530
 531         /* Program T-INIT master registers */
 532         for_each_dsi_port(port, intel_dsi->ports)
 533                 intel_de_rmw(dev_priv, ICL_DSI_T_INIT_MASTER(port),
 534                              DSI_T_INIT_MASTER_MASK, intel_dsi->init_count);
 535
 536         /* Program DPHY clock lanes timings */
 537         for_each_dsi_port(port, intel_dsi->ports) {
 538                 intel_de_write(dev_priv, DPHY_CLK_TIMING_PARAM(port),
 539                                intel_dsi->dphy_reg);
 540
 541                 /* shadow register inside display core */
 542                 intel_de_write(dev_priv, DSI_CLK_TIMING_PARAM(port),
 543                                intel_dsi->dphy_reg);
 544         }
 545
 546         /* Program DPHY data lanes timings */
 547         for_each_dsi_port(port, intel_dsi->ports) {
 548                 intel_de_write(dev_priv, DPHY_DATA_TIMING_PARAM(port),
 549                                intel_dsi->dphy_data_lane_reg);
 550
 551                 /* shadow register inside display core */
 552                 intel_de_write(dev_priv, DSI_DATA_TIMING_PARAM(port),
 553                                intel_dsi->dphy_data_lane_reg);
 554         }
 555
 556         /*
 557          * If DSI link operating at or below an 800 MHz,
 558          * TA_SURE should be override and programmed to
 559          * a value '0' inside TA_PARAM_REGISTERS otherwise
 560          * leave all fields at HW default values.
 561          */
 562         if (DISPLAY_VER(dev_priv) == 11) {
 563                 if (afe_clk(encoder, crtc_state) <= 800000) {
 564                         for_each_dsi_port(port, intel_dsi->ports) {
 565                                 intel_de_rmw(dev_priv, DPHY_TA_TIMING_PARAM(port),
 566                                              TA_SURE_MASK,
 567                                              TA_SURE_OVERRIDE | TA_SURE(0));
 568
 569                                 /* shadow register inside display core */
 570                                 intel_de_rmw(dev_priv, DSI_TA_TIMING_PARAM(port),
 571                                              TA_SURE_MASK,
 572                                              TA_SURE_OVERRIDE | TA_SURE(0));
 573                         }
 574                 }
 575         }
 576
 577         if (IS_JSL_EHL(dev_priv)) {
 578                 for_each_dsi_phy(phy, intel_dsi->phys)
 579                         intel_de_rmw(dev_priv, ICL_DPHY_CHKN(phy),
 580                                      0, ICL_DPHY_CHKN_AFE_OVER_PPI_STRAP);
 581         }
 582 }
 583
 584 static void gen11_dsi_gate_clocks(struct intel_encoder *encoder)
 585 {
 586         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 587         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 588         u32 tmp;
 589         enum phy phy;
 590
 591         mutex_lock(&dev_priv->display.dpll.lock);
 592         tmp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);
 593         for_each_dsi_phy(phy, intel_dsi->phys)
 594                 tmp |= ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
 595
 596         intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, tmp);
 597         mutex_unlock(&dev_priv->display.dpll.lock);
 598 }
 599
 600 static void gen11_dsi_ungate_clocks(struct intel_encoder *encoder)
 601 {
 602         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 603         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 604         u32 tmp;
 605         enum phy phy;
 606
 607         mutex_lock(&dev_priv->display.dpll.lock);
 608         tmp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);
 609         for_each_dsi_phy(phy, intel_dsi->phys)
 610                 tmp &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
 611
 612         intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, tmp);
 613         mutex_unlock(&dev_priv->display.dpll.lock);
 614 }
 615
 616 static bool gen11_dsi_is_clock_enabled(struct intel_encoder *encoder)
 617 {
 618         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 619         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 620         bool clock_enabled = false;
 621         enum phy phy;
 622         u32 tmp;
 623
 624         tmp = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);
 625
 626         for_each_dsi_phy(phy, intel_dsi->phys) {
 627                 if (!(tmp & ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy)))
 628                         clock_enabled = true;
 629         }
 630
 631         return clock_enabled;
 632 }
 633
 634 static void gen11_dsi_map_pll(struct intel_encoder *encoder,
 635                               const struct intel_crtc_state *crtc_state)
 636 {
 637         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 638         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 639         struct intel_shared_dpll *pll = crtc_state->shared_dpll;
 640         enum phy phy;
 641         u32 val;
 642
 643         mutex_lock(&dev_priv->display.dpll.lock);
 644
 645         val = intel_de_read(dev_priv, ICL_DPCLKA_CFGCR0);
 646         for_each_dsi_phy(phy, intel_dsi->phys) {
 647                 val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_SEL_MASK(phy);
 648                 val |= ICL_DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, phy);
 649         }
 650         intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val);
 651
 652         for_each_dsi_phy(phy, intel_dsi->phys) {
 653                 val &= ~ICL_DPCLKA_CFGCR0_DDI_CLK_OFF(phy);
 654         }
 655         intel_de_write(dev_priv, ICL_DPCLKA_CFGCR0, val);
 656
 657         intel_de_posting_read(dev_priv, ICL_DPCLKA_CFGCR0);
 658
 659         mutex_unlock(&dev_priv->display.dpll.lock);
 660 }
 661
 662 static void
 663 gen11_dsi_configure_transcoder(struct intel_encoder *encoder,
 664                                const struct intel_crtc_state *pipe_config)
 665 {
 666         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 667         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 668         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
 669         enum pipe pipe = crtc->pipe;
 670         u32 tmp;
 671         enum port port;
 672         enum transcoder dsi_trans;
 673
 674         for_each_dsi_port(port, intel_dsi->ports) {
 675                 dsi_trans = dsi_port_to_transcoder(port);
 676                 tmp = intel_de_read(dev_priv, DSI_TRANS_FUNC_CONF(dsi_trans));
 677
 678                 if (intel_dsi->eotp_pkt)
 679                         tmp &= ~EOTP_DISABLED;
 680                 else
 681                         tmp |= EOTP_DISABLED;
 682
 683                 /* enable link calibration if freq > 1.5Gbps */
 684                 if (afe_clk(encoder, pipe_config) >= 1500 * 1000) {
 685                         tmp &= ~LINK_CALIBRATION_MASK;
 686                         tmp |= CALIBRATION_ENABLED_INITIAL_ONLY;
 687                 }
 688
 689                 /* configure continuous clock */
 690                 tmp &= ~CONTINUOUS_CLK_MASK;
 691                 if (intel_dsi->clock_stop)
 692                         tmp |= CLK_ENTER_LP_AFTER_DATA;
 693                 else
 694                         tmp |= CLK_HS_CONTINUOUS;
 695
 696                 /* configure buffer threshold limit to minimum */
 697                 tmp &= ~PIX_BUF_THRESHOLD_MASK;
 698                 tmp |= PIX_BUF_THRESHOLD_1_4;
 699
 700                 /* set virtual channel to '0' */
 701                 tmp &= ~PIX_VIRT_CHAN_MASK;
 702                 tmp |= PIX_VIRT_CHAN(0);
 703
 704                 /* program BGR transmission */
 705                 if (intel_dsi->bgr_enabled)
 706                         tmp |= BGR_TRANSMISSION;
 707
 708                 /* select pixel format */
 709                 tmp &= ~PIX_FMT_MASK;
 710                 if (pipe_config->dsc.compression_enable) {
 711                         tmp |= PIX_FMT_COMPRESSED;
 712                 } else {
 713                         switch (intel_dsi->pixel_format) {
 714                         default:
 715                                 MISSING_CASE(intel_dsi->pixel_format);
 716                                 fallthrough;
 717                         case MIPI_DSI_FMT_RGB565:
 718                                 tmp |= PIX_FMT_RGB565;
 719                                 break;
 720                         case MIPI_DSI_FMT_RGB666_PACKED:
 721                                 tmp |= PIX_FMT_RGB666_PACKED;
 722                                 break;
 723                         case MIPI_DSI_FMT_RGB666:
 724                                 tmp |= PIX_FMT_RGB666_LOOSE;
 725                                 break;
 726                         case MIPI_DSI_FMT_RGB888:
 727                                 tmp |= PIX_FMT_RGB888;
 728                                 break;
 729                         }
 730                 }
 731
 732                 if (DISPLAY_VER(dev_priv) >= 12) {
 733                         if (is_vid_mode(intel_dsi))
 734                                 tmp |= BLANKING_PACKET_ENABLE;
 735                 }
 736
 737                 /* program DSI operation mode */
 738                 if (is_vid_mode(intel_dsi)) {
 739                         tmp &= ~OP_MODE_MASK;
 740                         switch (intel_dsi->video_mode) {
 741                         default:
 742                                 MISSING_CASE(intel_dsi->video_mode);
 743                                 fallthrough;
 744                         case NON_BURST_SYNC_EVENTS:
 745                                 tmp |= VIDEO_MODE_SYNC_EVENT;
 746                                 break;
 747                         case NON_BURST_SYNC_PULSE:
 748                                 tmp |= VIDEO_MODE_SYNC_PULSE;
 749                                 break;
 750                         }
 751                 } else {
 752                         /*
 753                          * FIXME: Retrieve this info from VBT.
 754                          * As per the spec when dsi transcoder is operating
 755                          * in TE GATE mode, TE comes from GPIO
 756                          * which is UTIL PIN for DSI 0.
 757                          * Also this GPIO would not be used for other
 758                          * purposes is an assumption.
 759                          */
 760                         tmp &= ~OP_MODE_MASK;
 761                         tmp |= CMD_MODE_TE_GATE;
 762                         tmp |= TE_SOURCE_GPIO;
 763                 }
 764
 765                 intel_de_write(dev_priv, DSI_TRANS_FUNC_CONF(dsi_trans), tmp);
 766         }
 767
 768         /* enable port sync mode if dual link */
 769         if (intel_dsi->dual_link) {
 770                 for_each_dsi_port(port, intel_dsi->ports) {
 771                         dsi_trans = dsi_port_to_transcoder(port);
 772                         intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL2(dsi_trans),
 773                                      0, PORT_SYNC_MODE_ENABLE);
 774                 }
 775
 776                 /* configure stream splitting */
 777                 configure_dual_link_mode(encoder, pipe_config);
 778         }
 779
 780         for_each_dsi_port(port, intel_dsi->ports) {
 781                 dsi_trans = dsi_port_to_transcoder(port);
 782
 783                 /* select data lane width */
 784                 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(dsi_trans));
 785                 tmp &= ~DDI_PORT_WIDTH_MASK;
 786                 tmp |= DDI_PORT_WIDTH(intel_dsi->lane_count);
 787
 788                 /* select input pipe */
 789                 tmp &= ~TRANS_DDI_EDP_INPUT_MASK;
 790                 switch (pipe) {
 791                 default:
 792                         MISSING_CASE(pipe);
 793                         fallthrough;
 794                 case PIPE_A:
 795                         tmp |= TRANS_DDI_EDP_INPUT_A_ON;
 796                         break;
 797                 case PIPE_B:
 798                         tmp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
 799                         break;
 800                 case PIPE_C:
 801                         tmp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
 802                         break;
 803                 case PIPE_D:
 804                         tmp |= TRANS_DDI_EDP_INPUT_D_ONOFF;
 805                         break;
 806                 }
 807
 808                 /* enable DDI buffer */
 809                 tmp |= TRANS_DDI_FUNC_ENABLE;
 810                 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(dsi_trans), tmp);
 811         }
 812
 813         /* wait for link ready */
 814         for_each_dsi_port(port, intel_dsi->ports) {
 815                 dsi_trans = dsi_port_to_transcoder(port);
 816                 if (wait_for_us((intel_de_read(dev_priv, DSI_TRANS_FUNC_CONF(dsi_trans)) &
 817                                  LINK_READY), 2500))
 818                         drm_err(&dev_priv->drm, "DSI link not ready\n");
 819         }
 820 }
 821
 822 static void
 823 gen11_dsi_set_transcoder_timings(struct intel_encoder *encoder,
 824                                  const struct intel_crtc_state *crtc_state)
 825 {
 826         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 827         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 828         const struct drm_display_mode *adjusted_mode =
 829                 &crtc_state->hw.adjusted_mode;
 830         enum port port;
 831         enum transcoder dsi_trans;
 832         /* horizontal timings */
 833         u16 htotal, hactive, hsync_start, hsync_end, hsync_size;
 834         u16 hback_porch;
 835         /* vertical timings */
 836         u16 vtotal, vactive, vsync_start, vsync_end, vsync_shift;
 837         int mul = 1, div = 1;
 838
 839         /*
 840          * Adjust horizontal timings (htotal, hsync_start, hsync_end) to account
 841          * for slower link speed if DSC is enabled.
 842          *
 843          * The compression frequency ratio is the ratio between compressed and
 844          * non-compressed link speeds, and simplifies down to the ratio between
 845          * compressed and non-compressed bpp.
 846          */
 847         if (crtc_state->dsc.compression_enable) {
 848                 mul = crtc_state->dsc.compressed_bpp;
 849                 div = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
 850         }
 851
 852         hactive = adjusted_mode->crtc_hdisplay;
 853
 854         if (is_vid_mode(intel_dsi))
 855                 htotal = DIV_ROUND_UP(adjusted_mode->crtc_htotal * mul, div);
 856         else
 857                 htotal = DIV_ROUND_UP((hactive + 160) * mul, div);
 858
 859         hsync_start = DIV_ROUND_UP(adjusted_mode->crtc_hsync_start * mul, div);
 860         hsync_end = DIV_ROUND_UP(adjusted_mode->crtc_hsync_end * mul, div);
 861         hsync_size  = hsync_end - hsync_start;
 862         hback_porch = (adjusted_mode->crtc_htotal -
 863                        adjusted_mode->crtc_hsync_end);
 864         vactive = adjusted_mode->crtc_vdisplay;
 865
 866         if (is_vid_mode(intel_dsi)) {
 867                 vtotal = adjusted_mode->crtc_vtotal;
 868         } else {
 869                 int bpp, line_time_us, byte_clk_period_ns;
 870
 871                 if (crtc_state->dsc.compression_enable)
 872                         bpp = crtc_state->dsc.compressed_bpp;
 873                 else
 874                         bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
 875
 876                 byte_clk_period_ns = 1000000 / afe_clk(encoder, crtc_state);
 877                 line_time_us = (htotal * (bpp / 8) * byte_clk_period_ns) / (1000 * intel_dsi->lane_count);
 878                 vtotal = vactive + DIV_ROUND_UP(400, line_time_us);
 879         }
 880         vsync_start = adjusted_mode->crtc_vsync_start;
 881         vsync_end = adjusted_mode->crtc_vsync_end;
 882         vsync_shift = hsync_start - htotal / 2;
 883
 884         if (intel_dsi->dual_link) {
 885                 hactive /= 2;
 886                 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
 887                         hactive += intel_dsi->pixel_overlap;
 888                 htotal /= 2;
 889         }
 890
 891         /* minimum hactive as per bspec: 256 pixels */
 892         if (adjusted_mode->crtc_hdisplay < 256)
 893                 drm_err(&dev_priv->drm, "hactive is less then 256 pixels\n");
 894
 895         /* if RGB666 format, then hactive must be multiple of 4 pixels */
 896         if (intel_dsi->pixel_format == MIPI_DSI_FMT_RGB666 && hactive % 4 != 0)
 897                 drm_err(&dev_priv->drm,
 898                         "hactive pixels are not multiple of 4\n");
 899
 900         /* program TRANS_HTOTAL register */
 901         for_each_dsi_port(port, intel_dsi->ports) {
 902                 dsi_trans = dsi_port_to_transcoder(port);
 903                 intel_de_write(dev_priv, TRANS_HTOTAL(dsi_trans),
 904                                HACTIVE(hactive - 1) | HTOTAL(htotal - 1));
 905         }
 906
 907         /* TRANS_HSYNC register to be programmed only for video mode */
 908         if (is_vid_mode(intel_dsi)) {
 909                 if (intel_dsi->video_mode == NON_BURST_SYNC_PULSE) {
 910                         /* BSPEC: hsync size should be atleast 16 pixels */
 911                         if (hsync_size < 16)
 912                                 drm_err(&dev_priv->drm,
 913                                         "hsync size < 16 pixels\n");
 914                 }
 915
 916                 if (hback_porch < 16)
 917                         drm_err(&dev_priv->drm, "hback porch < 16 pixels\n");
 918
 919                 if (intel_dsi->dual_link) {
 920                         hsync_start /= 2;
 921                         hsync_end /= 2;
 922                 }
 923
 924                 for_each_dsi_port(port, intel_dsi->ports) {
 925                         dsi_trans = dsi_port_to_transcoder(port);
 926                         intel_de_write(dev_priv, TRANS_HSYNC(dsi_trans),
 927                                        HSYNC_START(hsync_start - 1) | HSYNC_END(hsync_end - 1));
 928                 }
 929         }
 930
 931         /* program TRANS_VTOTAL register */
 932         for_each_dsi_port(port, intel_dsi->ports) {
 933                 dsi_trans = dsi_port_to_transcoder(port);
 934                 /*
 935                  * FIXME: Programing this by assuming progressive mode, since
 936                  * non-interlaced info from VBT is not saved inside
 937                  * struct drm_display_mode.
 938                  * For interlace mode: program required pixel minus 2
 939                  */
 940                 intel_de_write(dev_priv, TRANS_VTOTAL(dsi_trans),
 941                                VACTIVE(vactive - 1) | VTOTAL(vtotal - 1));
 942         }
 943
 944         if (vsync_end < vsync_start || vsync_end > vtotal)
 945                 drm_err(&dev_priv->drm, "Invalid vsync_end value\n");
 946
 947         if (vsync_start < vactive)
 948                 drm_err(&dev_priv->drm, "vsync_start less than vactive\n");
 949
 950         /* program TRANS_VSYNC register for video mode only */
 951         if (is_vid_mode(intel_dsi)) {
 952                 for_each_dsi_port(port, intel_dsi->ports) {
 953                         dsi_trans = dsi_port_to_transcoder(port);
 954                         intel_de_write(dev_priv, TRANS_VSYNC(dsi_trans),
 955                                        VSYNC_START(vsync_start - 1) | VSYNC_END(vsync_end - 1));
 956                 }
 957         }
 958
 959         /*
 960          * FIXME: It has to be programmed only for video modes and interlaced
 961          * modes. Put the check condition here once interlaced
 962          * info available as described above.
 963          * program TRANS_VSYNCSHIFT register
 964          */
 965         if (is_vid_mode(intel_dsi)) {
 966                 for_each_dsi_port(port, intel_dsi->ports) {
 967                         dsi_trans = dsi_port_to_transcoder(port);
 968                         intel_de_write(dev_priv, TRANS_VSYNCSHIFT(dsi_trans),
 969                                        vsync_shift);
 970                 }
 971         }
 972
 973         /*
 974          * program TRANS_VBLANK register, should be same as vtotal programmed
 975          *
 976          * FIXME get rid of these local hacks and do it right,
 977          * this will not handle eg. delayed vblank correctly.
 978          */
 979         if (DISPLAY_VER(dev_priv) >= 12) {
 980                 for_each_dsi_port(port, intel_dsi->ports) {
 981                         dsi_trans = dsi_port_to_transcoder(port);
 982                         intel_de_write(dev_priv, TRANS_VBLANK(dsi_trans),
 983                                        VBLANK_START(vactive - 1) | VBLANK_END(vtotal - 1));
 984                 }
 985         }
 986 }
 987
 988 static void gen11_dsi_enable_transcoder(struct intel_encoder *encoder)
 989 {
 990         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 991         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
 992         enum port port;
 993         enum transcoder dsi_trans;
 994
 995         for_each_dsi_port(port, intel_dsi->ports) {
 996                 dsi_trans = dsi_port_to_transcoder(port);
 997                 intel_de_rmw(dev_priv, TRANSCONF(dsi_trans), 0, TRANSCONF_ENABLE);
 998
 999                 /* wait for transcoder to be enabled */
1000                 if (intel_de_wait_for_set(dev_priv, TRANSCONF(dsi_trans),
1001                                           TRANSCONF_STATE_ENABLE, 10))
1002                         drm_err(&dev_priv->drm,
1003                                 "DSI transcoder not enabled\n");
1004         }
1005 }
1006
1007 static void gen11_dsi_setup_timeouts(struct intel_encoder *encoder,
1008                                      const struct intel_crtc_state *crtc_state)
1009 {
1010         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1011         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1012         enum port port;
1013         enum transcoder dsi_trans;
1014         u32 hs_tx_timeout, lp_rx_timeout, ta_timeout, divisor, mul;
1015
1016         /*
1017          * escape clock count calculation:
1018          * BYTE_CLK_COUNT = TIME_NS/(8 * UI)
1019          * UI (nsec) = (10^6)/Bitrate
1020          * TIME_NS = (BYTE_CLK_COUNT * 8 * 10^6)/ Bitrate
1021          * ESCAPE_CLK_COUNT  = TIME_NS/ESC_CLK_NS
1022          */
1023         divisor = intel_dsi_tlpx_ns(intel_dsi) * afe_clk(encoder, crtc_state) * 1000;
1024         mul = 8 * 1000000;
1025         hs_tx_timeout = DIV_ROUND_UP(intel_dsi->hs_tx_timeout * mul,
1026                                      divisor);
1027         lp_rx_timeout = DIV_ROUND_UP(intel_dsi->lp_rx_timeout * mul, divisor);
1028         ta_timeout = DIV_ROUND_UP(intel_dsi->turn_arnd_val * mul, divisor);
1029
1030         for_each_dsi_port(port, intel_dsi->ports) {
1031                 dsi_trans = dsi_port_to_transcoder(port);
1032
1033                 /* program hst_tx_timeout */
1034                 intel_de_rmw(dev_priv, DSI_HSTX_TO(dsi_trans),
1035                              HSTX_TIMEOUT_VALUE_MASK,
1036                              HSTX_TIMEOUT_VALUE(hs_tx_timeout));
1037
1038                 /* FIXME: DSI_CALIB_TO */
1039
1040                 /* program lp_rx_host timeout */
1041                 intel_de_rmw(dev_priv, DSI_LPRX_HOST_TO(dsi_trans),
1042                              LPRX_TIMEOUT_VALUE_MASK,
1043                              LPRX_TIMEOUT_VALUE(lp_rx_timeout));
1044
1045                 /* FIXME: DSI_PWAIT_TO */
1046
1047                 /* program turn around timeout */
1048                 intel_de_rmw(dev_priv, DSI_TA_TO(dsi_trans),
1049                              TA_TIMEOUT_VALUE_MASK,
1050                              TA_TIMEOUT_VALUE(ta_timeout));
1051         }
1052 }
1053
1054 static void gen11_dsi_config_util_pin(struct intel_encoder *encoder,
1055                                       bool enable)
1056 {
1057         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1058         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1059         u32 tmp;
1060
1061         /*
1062          * used as TE i/p for DSI0,
1063          * for dual link/DSI1 TE is from slave DSI1
1064          * through GPIO.
1065          */
1066         if (is_vid_mode(intel_dsi) || (intel_dsi->ports & BIT(PORT_B)))
1067                 return;
1068
1069         tmp = intel_de_read(dev_priv, UTIL_PIN_CTL);
1070
1071         if (enable) {
1072                 tmp |= UTIL_PIN_DIRECTION_INPUT;
1073                 tmp |= UTIL_PIN_ENABLE;
1074         } else {
1075                 tmp &= ~UTIL_PIN_ENABLE;
1076         }
1077         intel_de_write(dev_priv, UTIL_PIN_CTL, tmp);
1078 }
1079
1080 static void
1081 gen11_dsi_enable_port_and_phy(struct intel_encoder *encoder,
1082                               const struct intel_crtc_state *crtc_state)
1083 {
1084         /* step 4a: power up all lanes of the DDI used by DSI */
1085         gen11_dsi_power_up_lanes(encoder);
1086
1087         /* step 4b: configure lane sequencing of the Combo-PHY transmitters */
1088         gen11_dsi_config_phy_lanes_sequence(encoder);
1089
1090         /* step 4c: configure voltage swing and skew */
1091         gen11_dsi_voltage_swing_program_seq(encoder);
1092
1093         /* enable DDI buffer */
1094         gen11_dsi_enable_ddi_buffer(encoder);
1095
1096         /* setup D-PHY timings */
1097         gen11_dsi_setup_dphy_timings(encoder, crtc_state);
1098
1099         /* Since transcoder is configured to take events from GPIO */
1100         gen11_dsi_config_util_pin(encoder, true);
1101
1102         /* step 4h: setup DSI protocol timeouts */
1103         gen11_dsi_setup_timeouts(encoder, crtc_state);
1104
1105         /* Step (4h, 4i, 4j, 4k): Configure transcoder */
1106         gen11_dsi_configure_transcoder(encoder, crtc_state);
1107
1108         /* Step 4l: Gate DDI clocks */
1109         gen11_dsi_gate_clocks(encoder);
1110 }
1111
1112 static void gen11_dsi_powerup_panel(struct intel_encoder *encoder)
1113 {
1114         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1115         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1116         struct mipi_dsi_device *dsi;
1117         enum port port;
1118         enum transcoder dsi_trans;
1119         u32 tmp;
1120         int ret;
1121
1122         /* set maximum return packet size */
1123         for_each_dsi_port(port, intel_dsi->ports) {
1124                 dsi_trans = dsi_port_to_transcoder(port);
1125
1126                 /*
1127                  * FIXME: This uses the number of DW's currently in the payload
1128                  * receive queue. This is probably not what we want here.
1129                  */
1130                 tmp = intel_de_read(dev_priv, DSI_CMD_RXCTL(dsi_trans));
1131                 tmp &= NUMBER_RX_PLOAD_DW_MASK;
1132                 /* multiply "Number Rx Payload DW" by 4 to get max value */
1133                 tmp = tmp * 4;
1134                 dsi = intel_dsi->dsi_hosts[port]->device;
1135                 ret = mipi_dsi_set_maximum_return_packet_size(dsi, tmp);
1136                 if (ret < 0)
1137                         drm_err(&dev_priv->drm,
1138                                 "error setting max return pkt size%d\n", tmp);
1139         }
1140
1141         /* panel power on related mipi dsi vbt sequences */
1142         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_ON);
1143         msleep(intel_dsi->panel_on_delay);
1144         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DEASSERT_RESET);
1145         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_INIT_OTP);
1146         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_ON);
1147
1148         /* ensure all panel commands dispatched before enabling transcoder */
1149         wait_for_cmds_dispatched_to_panel(encoder);
1150 }
1151
1152 static void gen11_dsi_pre_pll_enable(struct intel_atomic_state *state,
1153                                      struct intel_encoder *encoder,
1154                                      const struct intel_crtc_state *crtc_state,
1155                                      const struct drm_connector_state *conn_state)
1156 {
1157         /* step2: enable IO power */
1158         gen11_dsi_enable_io_power(encoder);
1159
1160         /* step3: enable DSI PLL */
1161         gen11_dsi_program_esc_clk_div(encoder, crtc_state);
1162 }
1163
1164 static void gen11_dsi_pre_enable(struct intel_atomic_state *state,
1165                                  struct intel_encoder *encoder,
1166                                  const struct intel_crtc_state *pipe_config,
1167                                  const struct drm_connector_state *conn_state)
1168 {
1169         /* step3b */
1170         gen11_dsi_map_pll(encoder, pipe_config);
1171
1172         /* step4: enable DSI port and DPHY */
1173         gen11_dsi_enable_port_and_phy(encoder, pipe_config);
1174
1175         /* step5: program and powerup panel */
1176         gen11_dsi_powerup_panel(encoder);
1177
1178         intel_dsc_dsi_pps_write(encoder, pipe_config);
1179
1180         /* step6c: configure transcoder timings */
1181         gen11_dsi_set_transcoder_timings(encoder, pipe_config);
1182 }
1183
1184 /*
1185  * Wa_1409054076:icl,jsl,ehl
1186  * When pipe A is disabled and MIPI DSI is enabled on pipe B,
1187  * the AMT KVMR feature will incorrectly see pipe A as enabled.
1188  * Set 0x42080 bit 23=1 before enabling DSI on pipe B and leave
1189  * it set while DSI is enabled on pipe B
1190  */
1191 static void icl_apply_kvmr_pipe_a_wa(struct intel_encoder *encoder,
1192                                      enum pipe pipe, bool enable)
1193 {
1194         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1195
1196         if (DISPLAY_VER(dev_priv) == 11 && pipe == PIPE_B)
1197                 intel_de_rmw(dev_priv, CHICKEN_PAR1_1,
1198                              IGNORE_KVMR_PIPE_A,
1199                              enable ? IGNORE_KVMR_PIPE_A : 0);
1200 }
1201
1202 /*
1203  * Wa_16012360555:adl-p
1204  * SW will have to program the "LP to HS Wakeup Guardband"
1205  * to account for the repeaters on the HS Request/Ready
1206  * PPI signaling between the Display engine and the DPHY.
1207  */
1208 static void adlp_set_lp_hs_wakeup_gb(struct intel_encoder *encoder)
1209 {
1210         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1211         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1212         enum port port;
1213
1214         if (DISPLAY_VER(i915) == 13) {
1215                 for_each_dsi_port(port, intel_dsi->ports)
1216                         intel_de_rmw(i915, TGL_DSI_CHKN_REG(port),
1217                                      TGL_DSI_CHKN_LSHS_GB_MASK,
1218                                      TGL_DSI_CHKN_LSHS_GB(4));
1219         }
1220 }
1221
1222 static void gen11_dsi_enable(struct intel_atomic_state *state,
1223                              struct intel_encoder *encoder,
1224                              const struct intel_crtc_state *crtc_state,
1225                              const struct drm_connector_state *conn_state)
1226 {
1227         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1228         struct intel_crtc *crtc = to_intel_crtc(conn_state->crtc);
1229
1230         drm_WARN_ON(state->base.dev, crtc_state->has_pch_encoder);
1231
1232         /* Wa_1409054076:icl,jsl,ehl */
1233         icl_apply_kvmr_pipe_a_wa(encoder, crtc->pipe, true);
1234
1235         /* Wa_16012360555:adl-p */
1236         adlp_set_lp_hs_wakeup_gb(encoder);
1237
1238         /* step6d: enable dsi transcoder */
1239         gen11_dsi_enable_transcoder(encoder);
1240
1241         /* step7: enable backlight */
1242         intel_backlight_enable(crtc_state, conn_state);
1243         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_ON);
1244
1245         intel_crtc_vblank_on(crtc_state);
1246 }
1247
1248 static void gen11_dsi_disable_transcoder(struct intel_encoder *encoder)
1249 {
1250         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1251         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1252         enum port port;
1253         enum transcoder dsi_trans;
1254
1255         for_each_dsi_port(port, intel_dsi->ports) {
1256                 dsi_trans = dsi_port_to_transcoder(port);
1257
1258                 /* disable transcoder */
1259                 intel_de_rmw(dev_priv, TRANSCONF(dsi_trans), TRANSCONF_ENABLE, 0);
1260
1261                 /* wait for transcoder to be disabled */
1262                 if (intel_de_wait_for_clear(dev_priv, TRANSCONF(dsi_trans),
1263                                             TRANSCONF_STATE_ENABLE, 50))
1264                         drm_err(&dev_priv->drm,
1265                                 "DSI trancoder not disabled\n");
1266         }
1267 }
1268
1269 static void gen11_dsi_powerdown_panel(struct intel_encoder *encoder)
1270 {
1271         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1272
1273         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_DISPLAY_OFF);
1274         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_ASSERT_RESET);
1275         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_POWER_OFF);
1276
1277         /* ensure cmds dispatched to panel */
1278         wait_for_cmds_dispatched_to_panel(encoder);
1279 }
1280
1281 static void gen11_dsi_deconfigure_trancoder(struct intel_encoder *encoder)
1282 {
1283         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1284         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1285         enum port port;
1286         enum transcoder dsi_trans;
1287         u32 tmp;
1288
1289         /* disable periodic update mode */
1290         if (is_cmd_mode(intel_dsi)) {
1291                 for_each_dsi_port(port, intel_dsi->ports)
1292                         intel_de_rmw(dev_priv, DSI_CMD_FRMCTL(port),
1293                                      DSI_PERIODIC_FRAME_UPDATE_ENABLE, 0);
1294         }
1295
1296         /* put dsi link in ULPS */
1297         for_each_dsi_port(port, intel_dsi->ports) {
1298                 dsi_trans = dsi_port_to_transcoder(port);
1299                 tmp = intel_de_read(dev_priv, DSI_LP_MSG(dsi_trans));
1300                 tmp |= LINK_ENTER_ULPS;
1301                 tmp &= ~LINK_ULPS_TYPE_LP11;
1302                 intel_de_write(dev_priv, DSI_LP_MSG(dsi_trans), tmp);
1303
1304                 if (wait_for_us((intel_de_read(dev_priv, DSI_LP_MSG(dsi_trans)) &
1305                                  LINK_IN_ULPS),
1306                                 10))
1307                         drm_err(&dev_priv->drm, "DSI link not in ULPS\n");
1308         }
1309
1310         /* disable ddi function */
1311         for_each_dsi_port(port, intel_dsi->ports) {
1312                 dsi_trans = dsi_port_to_transcoder(port);
1313                 intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL(dsi_trans),
1314                              TRANS_DDI_FUNC_ENABLE, 0);
1315         }
1316
1317         /* disable port sync mode if dual link */
1318         if (intel_dsi->dual_link) {
1319                 for_each_dsi_port(port, intel_dsi->ports) {
1320                         dsi_trans = dsi_port_to_transcoder(port);
1321                         intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL2(dsi_trans),
1322                                      PORT_SYNC_MODE_ENABLE, 0);
1323                 }
1324         }
1325 }
1326
1327 static void gen11_dsi_disable_port(struct intel_encoder *encoder)
1328 {
1329         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1330         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1331         enum port port;
1332
1333         gen11_dsi_ungate_clocks(encoder);
1334         for_each_dsi_port(port, intel_dsi->ports) {
1335                 intel_de_rmw(dev_priv, DDI_BUF_CTL(port), DDI_BUF_CTL_ENABLE, 0);
1336
1337                 if (wait_for_us((intel_de_read(dev_priv, DDI_BUF_CTL(port)) &
1338                                  DDI_BUF_IS_IDLE),
1339                                  8))
1340                         drm_err(&dev_priv->drm,
1341                                 "DDI port:%c buffer not idle\n",
1342                                 port_name(port));
1343         }
1344         gen11_dsi_gate_clocks(encoder);
1345 }
1346
1347 static void gen11_dsi_disable_io_power(struct intel_encoder *encoder)
1348 {
1349         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1350         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1351         enum port port;
1352
1353         for_each_dsi_port(port, intel_dsi->ports) {
1354                 intel_wakeref_t wakeref;
1355
1356                 wakeref = fetch_and_zero(&intel_dsi->io_wakeref[port]);
1357                 intel_display_power_put(dev_priv,
1358                                         port == PORT_A ?
1359                                         POWER_DOMAIN_PORT_DDI_IO_A :
1360                                         POWER_DOMAIN_PORT_DDI_IO_B,
1361                                         wakeref);
1362         }
1363
1364         /* set mode to DDI */
1365         for_each_dsi_port(port, intel_dsi->ports)
1366                 intel_de_rmw(dev_priv, ICL_DSI_IO_MODECTL(port),
1367                              COMBO_PHY_MODE_DSI, 0);
1368 }
1369
1370 static void gen11_dsi_disable(struct intel_atomic_state *state,
1371                               struct intel_encoder *encoder,
1372                               const struct intel_crtc_state *old_crtc_state,
1373                               const struct drm_connector_state *old_conn_state)
1374 {
1375         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1376         struct intel_crtc *crtc = to_intel_crtc(old_conn_state->crtc);
1377
1378         /* step1: turn off backlight */
1379         intel_dsi_vbt_exec_sequence(intel_dsi, MIPI_SEQ_BACKLIGHT_OFF);
1380         intel_backlight_disable(old_conn_state);
1381
1382         /* step2d,e: disable transcoder and wait */
1383         gen11_dsi_disable_transcoder(encoder);
1384
1385         /* Wa_1409054076:icl,jsl,ehl */
1386         icl_apply_kvmr_pipe_a_wa(encoder, crtc->pipe, false);
1387
1388         /* step2f,g: powerdown panel */
1389         gen11_dsi_powerdown_panel(encoder);
1390
1391         /* step2h,i,j: deconfig trancoder */
1392         gen11_dsi_deconfigure_trancoder(encoder);
1393
1394         /* step3: disable port */
1395         gen11_dsi_disable_port(encoder);
1396
1397         gen11_dsi_config_util_pin(encoder, false);
1398
1399         /* step4: disable IO power */
1400         gen11_dsi_disable_io_power(encoder);
1401 }
1402
1403 static void gen11_dsi_post_disable(struct intel_atomic_state *state,
1404                                    struct intel_encoder *encoder,
1405                                    const struct intel_crtc_state *old_crtc_state,
1406                                    const struct drm_connector_state *old_conn_state)
1407 {
1408         intel_crtc_vblank_off(old_crtc_state);
1409
1410         intel_dsc_disable(old_crtc_state);
1411
1412         skl_scaler_disable(old_crtc_state);
1413 }
1414
1415 static enum drm_mode_status gen11_dsi_mode_valid(struct drm_connector *connector,
1416                                                  struct drm_display_mode *mode)
1417 {
1418         /* FIXME: DSC? */
1419         return intel_dsi_mode_valid(connector, mode);
1420 }
1421
1422 static void gen11_dsi_get_timings(struct intel_encoder *encoder,
1423                                   struct intel_crtc_state *pipe_config)
1424 {
1425         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1426         struct drm_display_mode *adjusted_mode =
1427                                         &pipe_config->hw.adjusted_mode;
1428
1429         if (pipe_config->dsc.compressed_bpp) {
1430                 int div = pipe_config->dsc.compressed_bpp;
1431                 int mul = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
1432
1433                 adjusted_mode->crtc_htotal =
1434                         DIV_ROUND_UP(adjusted_mode->crtc_htotal * mul, div);
1435                 adjusted_mode->crtc_hsync_start =
1436                         DIV_ROUND_UP(adjusted_mode->crtc_hsync_start * mul, div);
1437                 adjusted_mode->crtc_hsync_end =
1438                         DIV_ROUND_UP(adjusted_mode->crtc_hsync_end * mul, div);
1439         }
1440
1441         if (intel_dsi->dual_link) {
1442                 adjusted_mode->crtc_hdisplay *= 2;
1443                 if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK)
1444                         adjusted_mode->crtc_hdisplay -=
1445                                                 intel_dsi->pixel_overlap;
1446                 adjusted_mode->crtc_htotal *= 2;
1447         }
1448         adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hdisplay;
1449         adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_htotal;
1450
1451         if (intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE) {
1452                 if (intel_dsi->dual_link) {
1453                         adjusted_mode->crtc_hsync_start *= 2;
1454                         adjusted_mode->crtc_hsync_end *= 2;
1455                 }
1456         }
1457         adjusted_mode->crtc_vblank_start = adjusted_mode->crtc_vdisplay;
1458         adjusted_mode->crtc_vblank_end = adjusted_mode->crtc_vtotal;
1459 }
1460
1461 static bool gen11_dsi_is_periodic_cmd_mode(struct intel_dsi *intel_dsi)
1462 {
1463         struct drm_device *dev = intel_dsi->base.base.dev;
1464         struct drm_i915_private *dev_priv = to_i915(dev);
1465         enum transcoder dsi_trans;
1466         u32 val;
1467
1468         if (intel_dsi->ports == BIT(PORT_B))
1469                 dsi_trans = TRANSCODER_DSI_1;
1470         else
1471                 dsi_trans = TRANSCODER_DSI_0;
1472
1473         val = intel_de_read(dev_priv, DSI_TRANS_FUNC_CONF(dsi_trans));
1474         return (val & DSI_PERIODIC_FRAME_UPDATE_ENABLE);
1475 }
1476
1477 static void gen11_dsi_get_cmd_mode_config(struct intel_dsi *intel_dsi,
1478                                           struct intel_crtc_state *pipe_config)
1479 {
1480         if (intel_dsi->ports == (BIT(PORT_B) | BIT(PORT_A)))
1481                 pipe_config->mode_flags |= I915_MODE_FLAG_DSI_USE_TE1 |
1482                                             I915_MODE_FLAG_DSI_USE_TE0;
1483         else if (intel_dsi->ports == BIT(PORT_B))
1484                 pipe_config->mode_flags |= I915_MODE_FLAG_DSI_USE_TE1;
1485         else
1486                 pipe_config->mode_flags |= I915_MODE_FLAG_DSI_USE_TE0;
1487 }
1488
1489 static void gen11_dsi_get_config(struct intel_encoder *encoder,
1490                                  struct intel_crtc_state *pipe_config)
1491 {
1492         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
1493         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1494
1495         intel_ddi_get_clock(encoder, pipe_config, icl_ddi_combo_get_pll(encoder));
1496
1497         pipe_config->hw.adjusted_mode.crtc_clock = intel_dsi->pclk;
1498         if (intel_dsi->dual_link)
1499                 pipe_config->hw.adjusted_mode.crtc_clock *= 2;
1500
1501         gen11_dsi_get_timings(encoder, pipe_config);
1502         pipe_config->output_types |= BIT(INTEL_OUTPUT_DSI);
1503         pipe_config->pipe_bpp = bdw_get_pipe_misc_bpp(crtc);
1504
1505         /* Get the details on which TE should be enabled */
1506         if (is_cmd_mode(intel_dsi))
1507                 gen11_dsi_get_cmd_mode_config(intel_dsi, pipe_config);
1508
1509         if (gen11_dsi_is_periodic_cmd_mode(intel_dsi))
1510                 pipe_config->mode_flags |= I915_MODE_FLAG_DSI_PERIODIC_CMD_MODE;
1511 }
1512
1513 static void gen11_dsi_sync_state(struct intel_encoder *encoder,
1514                                  const struct intel_crtc_state *crtc_state)
1515 {
1516         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1517         struct intel_crtc *intel_crtc;
1518         enum pipe pipe;
1519
1520         if (!crtc_state)
1521                 return;
1522
1523         intel_crtc = to_intel_crtc(crtc_state->uapi.crtc);
1524         pipe = intel_crtc->pipe;
1525
1526         /* wa verify 1409054076:icl,jsl,ehl */
1527         if (DISPLAY_VER(dev_priv) == 11 && pipe == PIPE_B &&
1528             !(intel_de_read(dev_priv, CHICKEN_PAR1_1) & IGNORE_KVMR_PIPE_A))
1529                 drm_dbg_kms(&dev_priv->drm,
1530                             "[ENCODER:%d:%s] BIOS left IGNORE_KVMR_PIPE_A cleared with pipe B enabled\n",
1531                             encoder->base.base.id,
1532                             encoder->base.name);
1533 }
1534
1535 static int gen11_dsi_dsc_compute_config(struct intel_encoder *encoder,
1536                                         struct intel_crtc_state *crtc_state)
1537 {
1538         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1539         struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
1540         int dsc_max_bpc = DISPLAY_VER(dev_priv) >= 12 ? 12 : 10;
1541         bool use_dsc;
1542         int ret;
1543
1544         use_dsc = intel_bios_get_dsc_params(encoder, crtc_state, dsc_max_bpc);
1545         if (!use_dsc)
1546                 return 0;
1547
1548         if (crtc_state->pipe_bpp < 8 * 3)
1549                 return -EINVAL;
1550
1551         /* FIXME: split only when necessary */
1552         if (crtc_state->dsc.slice_count > 1)
1553                 crtc_state->dsc.dsc_split = true;
1554
1555         /* FIXME: initialize from VBT */
1556         vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST;
1557
1558         vdsc_cfg->pic_height = crtc_state->hw.adjusted_mode.crtc_vdisplay;
1559
1560         ret = intel_dsc_compute_params(crtc_state);
1561         if (ret)
1562                 return ret;
1563
1564         /* DSI specific sanity checks on the common code */
1565         drm_WARN_ON(&dev_priv->drm, vdsc_cfg->vbr_enable);
1566         drm_WARN_ON(&dev_priv->drm, vdsc_cfg->simple_422);
1567         drm_WARN_ON(&dev_priv->drm,
1568                     vdsc_cfg->pic_width % vdsc_cfg->slice_width);
1569         drm_WARN_ON(&dev_priv->drm, vdsc_cfg->slice_height < 8);
1570         drm_WARN_ON(&dev_priv->drm,
1571                     vdsc_cfg->pic_height % vdsc_cfg->slice_height);
1572
1573         ret = drm_dsc_compute_rc_parameters(vdsc_cfg);
1574         if (ret)
1575                 return ret;
1576
1577         crtc_state->dsc.compression_enable = true;
1578
1579         return 0;
1580 }
1581
1582 static int gen11_dsi_compute_config(struct intel_encoder *encoder,
1583                                     struct intel_crtc_state *pipe_config,
1584                                     struct drm_connector_state *conn_state)
1585 {
1586         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1587         struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi,
1588                                                    base);
1589         struct intel_connector *intel_connector = intel_dsi->attached_connector;
1590         struct drm_display_mode *adjusted_mode =
1591                 &pipe_config->hw.adjusted_mode;
1592         int ret;
1593
1594         pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB;
1595         pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
1596
1597         ret = intel_panel_compute_config(intel_connector, adjusted_mode);
1598         if (ret)
1599                 return ret;
1600
1601         ret = intel_panel_fitting(pipe_config, conn_state);
1602         if (ret)
1603                 return ret;
1604
1605         adjusted_mode->flags = 0;
1606
1607         /* Dual link goes to trancoder DSI'0' */
1608         if (intel_dsi->ports == BIT(PORT_B))
1609                 pipe_config->cpu_transcoder = TRANSCODER_DSI_1;
1610         else
1611                 pipe_config->cpu_transcoder = TRANSCODER_DSI_0;
1612
1613         if (intel_dsi->pixel_format == MIPI_DSI_FMT_RGB888)
1614                 pipe_config->pipe_bpp = 24;
1615         else
1616                 pipe_config->pipe_bpp = 18;
1617
1618         pipe_config->clock_set = true;
1619
1620         if (gen11_dsi_dsc_compute_config(encoder, pipe_config))
1621                 drm_dbg_kms(&i915->drm, "Attempting to use DSC failed\n");
1622
1623         pipe_config->port_clock = afe_clk(encoder, pipe_config) / 5;
1624
1625         /*
1626          * In case of TE GATE cmd mode, we
1627          * receive TE from the slave if
1628          * dual link is enabled
1629          */
1630         if (is_cmd_mode(intel_dsi))
1631                 gen11_dsi_get_cmd_mode_config(intel_dsi, pipe_config);
1632
1633         return 0;
1634 }
1635
1636 static void gen11_dsi_get_power_domains(struct intel_encoder *encoder,
1637                                         struct intel_crtc_state *crtc_state)
1638 {
1639         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
1640
1641         get_dsi_io_power_domains(i915,
1642                                  enc_to_intel_dsi(encoder));
1643 }
1644
1645 static bool gen11_dsi_get_hw_state(struct intel_encoder *encoder,
1646                                    enum pipe *pipe)
1647 {
1648         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1649         struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
1650         enum transcoder dsi_trans;
1651         intel_wakeref_t wakeref;
1652         enum port port;
1653         bool ret = false;
1654         u32 tmp;
1655
1656         wakeref = intel_display_power_get_if_enabled(dev_priv,
1657                                                      encoder->power_domain);
1658         if (!wakeref)
1659                 return false;
1660
1661         for_each_dsi_port(port, intel_dsi->ports) {
1662                 dsi_trans = dsi_port_to_transcoder(port);
1663                 tmp = intel_de_read(dev_priv, TRANS_DDI_FUNC_CTL(dsi_trans));
1664                 switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
1665                 case TRANS_DDI_EDP_INPUT_A_ON:
1666                         *pipe = PIPE_A;
1667                         break;
1668                 case TRANS_DDI_EDP_INPUT_B_ONOFF:
1669                         *pipe = PIPE_B;
1670                         break;
1671                 case TRANS_DDI_EDP_INPUT_C_ONOFF:
1672                         *pipe = PIPE_C;
1673                         break;
1674                 case TRANS_DDI_EDP_INPUT_D_ONOFF:
1675                         *pipe = PIPE_D;
1676                         break;
1677                 default:
1678                         drm_err(&dev_priv->drm, "Invalid PIPE input\n");
1679                         goto out;
1680                 }
1681
1682                 tmp = intel_de_read(dev_priv, TRANSCONF(dsi_trans));
1683                 ret = tmp & TRANSCONF_ENABLE;
1684         }
1685 out:
1686         intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
1687         return ret;
1688 }
1689
1690 static bool gen11_dsi_initial_fastset_check(struct intel_encoder *encoder,
1691                                             struct intel_crtc_state *crtc_state)
1692 {
1693         if (crtc_state->dsc.compression_enable) {
1694                 drm_dbg_kms(encoder->base.dev, "Forcing full modeset due to DSC being enabled\n");
1695                 crtc_state->uapi.mode_changed = true;
1696
1697                 return false;
1698         }
1699
1700         return true;
1701 }
1702
1703 static void gen11_dsi_encoder_destroy(struct drm_encoder *encoder)
1704 {
1705         intel_encoder_destroy(encoder);
1706 }
1707
1708 static const struct drm_encoder_funcs gen11_dsi_encoder_funcs = {
1709         .destroy = gen11_dsi_encoder_destroy,
1710 };
1711
1712 static const struct drm_connector_funcs gen11_dsi_connector_funcs = {
1713         .detect = intel_panel_detect,
1714         .late_register = intel_connector_register,
1715         .early_unregister = intel_connector_unregister,
1716         .destroy = intel_connector_destroy,
1717         .fill_modes = drm_helper_probe_single_connector_modes,
1718         .atomic_get_property = intel_digital_connector_atomic_get_property,
1719         .atomic_set_property = intel_digital_connector_atomic_set_property,
1720         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1721         .atomic_duplicate_state = intel_digital_connector_duplicate_state,
1722 };
1723
1724 static const struct drm_connector_helper_funcs gen11_dsi_connector_helper_funcs = {
1725         .get_modes = intel_dsi_get_modes,
1726         .mode_valid = gen11_dsi_mode_valid,
1727         .atomic_check = intel_digital_connector_atomic_check,
1728 };
1729
1730 static int gen11_dsi_host_attach(struct mipi_dsi_host *host,
1731                                  struct mipi_dsi_device *dsi)
1732 {
1733         return 0;
1734 }
1735
1736 static int gen11_dsi_host_detach(struct mipi_dsi_host *host,
1737                                  struct mipi_dsi_device *dsi)
1738 {
1739         return 0;
1740 }
1741
1742 static ssize_t gen11_dsi_host_transfer(struct mipi_dsi_host *host,
1743                                        const struct mipi_dsi_msg *msg)
1744 {
1745         struct intel_dsi_host *intel_dsi_host = to_intel_dsi_host(host);
1746         struct mipi_dsi_packet dsi_pkt;
1747         ssize_t ret;
1748         bool enable_lpdt = false;
1749
1750         ret = mipi_dsi_create_packet(&dsi_pkt, msg);
1751         if (ret < 0)
1752                 return ret;
1753
1754         if (msg->flags & MIPI_DSI_MSG_USE_LPM)
1755                 enable_lpdt = true;
1756
1757         /* only long packet contains payload */
1758         if (mipi_dsi_packet_format_is_long(msg->type)) {
1759                 ret = dsi_send_pkt_payld(intel_dsi_host, &dsi_pkt);
1760                 if (ret < 0)
1761                         return ret;
1762         }
1763
1764         /* send packet header */
1765         ret  = dsi_send_pkt_hdr(intel_dsi_host, &dsi_pkt, enable_lpdt);
1766         if (ret < 0)
1767                 return ret;
1768
1769         //TODO: add payload receive code if needed
1770
1771         ret = sizeof(dsi_pkt.header) + dsi_pkt.payload_length;
1772
1773         return ret;
1774 }
1775
1776 static const struct mipi_dsi_host_ops gen11_dsi_host_ops = {
1777         .attach = gen11_dsi_host_attach,
1778         .detach = gen11_dsi_host_detach,
1779         .transfer = gen11_dsi_host_transfer,
1780 };
1781
1782 #define ICL_PREPARE_CNT_MAX     0x7
1783 #define ICL_CLK_ZERO_CNT_MAX    0xf
1784 #define ICL_TRAIL_CNT_MAX       0x7
1785 #define ICL_TCLK_PRE_CNT_MAX    0x3
1786 #define ICL_TCLK_POST_CNT_MAX   0x7
1787 #define ICL_HS_ZERO_CNT_MAX     0xf
1788 #define ICL_EXIT_ZERO_CNT_MAX   0x7
1789
1790 static void icl_dphy_param_init(struct intel_dsi *intel_dsi)
1791 {
1792         struct drm_device *dev = intel_dsi->base.base.dev;
1793         struct drm_i915_private *dev_priv = to_i915(dev);
1794         struct intel_connector *connector = intel_dsi->attached_connector;
1795         struct mipi_config *mipi_config = connector->panel.vbt.dsi.config;
1796         u32 tlpx_ns;
1797         u32 prepare_cnt, exit_zero_cnt, clk_zero_cnt, trail_cnt;
1798         u32 ths_prepare_ns, tclk_trail_ns;
1799         u32 hs_zero_cnt;
1800         u32 tclk_pre_cnt, tclk_post_cnt;
1801
1802         tlpx_ns = intel_dsi_tlpx_ns(intel_dsi);
1803
1804         tclk_trail_ns = max(mipi_config->tclk_trail, mipi_config->ths_trail);
1805         ths_prepare_ns = max(mipi_config->ths_prepare,
1806                              mipi_config->tclk_prepare);
1807
1808         /*
1809          * prepare cnt in escape clocks
1810          * this field represents a hexadecimal value with a precision
1811          * of 1.2 – i.e. the most significant bit is the integer
1812          * and the least significant 2 bits are fraction bits.
1813          * so, the field can represent a range of 0.25 to 1.75
1814          */
1815         prepare_cnt = DIV_ROUND_UP(ths_prepare_ns * 4, tlpx_ns);
1816         if (prepare_cnt > ICL_PREPARE_CNT_MAX) {
1817                 drm_dbg_kms(&dev_priv->drm, "prepare_cnt out of range (%d)\n",
1818                             prepare_cnt);
1819                 prepare_cnt = ICL_PREPARE_CNT_MAX;
1820         }
1821
1822         /* clk zero count in escape clocks */
1823         clk_zero_cnt = DIV_ROUND_UP(mipi_config->tclk_prepare_clkzero -
1824                                     ths_prepare_ns, tlpx_ns);
1825         if (clk_zero_cnt > ICL_CLK_ZERO_CNT_MAX) {
1826                 drm_dbg_kms(&dev_priv->drm,
1827                             "clk_zero_cnt out of range (%d)\n", clk_zero_cnt);
1828                 clk_zero_cnt = ICL_CLK_ZERO_CNT_MAX;
1829         }
1830
1831         /* trail cnt in escape clocks*/
1832         trail_cnt = DIV_ROUND_UP(tclk_trail_ns, tlpx_ns);
1833         if (trail_cnt > ICL_TRAIL_CNT_MAX) {
1834                 drm_dbg_kms(&dev_priv->drm, "trail_cnt out of range (%d)\n",
1835                             trail_cnt);
1836                 trail_cnt = ICL_TRAIL_CNT_MAX;
1837         }
1838
1839         /* tclk pre count in escape clocks */
1840         tclk_pre_cnt = DIV_ROUND_UP(mipi_config->tclk_pre, tlpx_ns);
1841         if (tclk_pre_cnt > ICL_TCLK_PRE_CNT_MAX) {
1842                 drm_dbg_kms(&dev_priv->drm,
1843                             "tclk_pre_cnt out of range (%d)\n", tclk_pre_cnt);
1844                 tclk_pre_cnt = ICL_TCLK_PRE_CNT_MAX;
1845         }
1846
1847         /* tclk post count in escape clocks */
1848         tclk_post_cnt = DIV_ROUND_UP(mipi_config->tclk_post, tlpx_ns);
1849         if (tclk_post_cnt > ICL_TCLK_POST_CNT_MAX) {
1850                 drm_dbg_kms(&dev_priv->drm,
1851                             "tclk_post_cnt out of range (%d)\n",
1852                             tclk_post_cnt);
1853                 tclk_post_cnt = ICL_TCLK_POST_CNT_MAX;
1854         }
1855
1856         /* hs zero cnt in escape clocks */
1857         hs_zero_cnt = DIV_ROUND_UP(mipi_config->ths_prepare_hszero -
1858                                    ths_prepare_ns, tlpx_ns);
1859         if (hs_zero_cnt > ICL_HS_ZERO_CNT_MAX) {
1860                 drm_dbg_kms(&dev_priv->drm, "hs_zero_cnt out of range (%d)\n",
1861                             hs_zero_cnt);
1862                 hs_zero_cnt = ICL_HS_ZERO_CNT_MAX;
1863         }
1864
1865         /* hs exit zero cnt in escape clocks */
1866         exit_zero_cnt = DIV_ROUND_UP(mipi_config->ths_exit, tlpx_ns);
1867         if (exit_zero_cnt > ICL_EXIT_ZERO_CNT_MAX) {
1868                 drm_dbg_kms(&dev_priv->drm,
1869                             "exit_zero_cnt out of range (%d)\n",
1870                             exit_zero_cnt);
1871                 exit_zero_cnt = ICL_EXIT_ZERO_CNT_MAX;
1872         }
1873
1874         /* clock lane dphy timings */
1875         intel_dsi->dphy_reg = (CLK_PREPARE_OVERRIDE |
1876                                CLK_PREPARE(prepare_cnt) |
1877                                CLK_ZERO_OVERRIDE |
1878                                CLK_ZERO(clk_zero_cnt) |
1879                                CLK_PRE_OVERRIDE |
1880                                CLK_PRE(tclk_pre_cnt) |
1881                                CLK_POST_OVERRIDE |
1882                                CLK_POST(tclk_post_cnt) |
1883                                CLK_TRAIL_OVERRIDE |
1884                                CLK_TRAIL(trail_cnt));
1885
1886         /* data lanes dphy timings */
1887         intel_dsi->dphy_data_lane_reg = (HS_PREPARE_OVERRIDE |
1888                                          HS_PREPARE(prepare_cnt) |
1889                                          HS_ZERO_OVERRIDE |
1890                                          HS_ZERO(hs_zero_cnt) |
1891                                          HS_TRAIL_OVERRIDE |
1892                                          HS_TRAIL(trail_cnt) |
1893                                          HS_EXIT_OVERRIDE |
1894                                          HS_EXIT(exit_zero_cnt));
1895
1896         intel_dsi_log_params(intel_dsi);
1897 }
1898
1899 static void icl_dsi_add_properties(struct intel_connector *connector)
1900 {
1901         const struct drm_display_mode *fixed_mode =
1902                 intel_panel_preferred_fixed_mode(connector);
1903
1904         intel_attach_scaling_mode_property(&connector->base);
1905
1906         drm_connector_set_panel_orientation_with_quirk(&connector->base,
1907                                                        intel_dsi_get_panel_orientation(connector),
1908                                                        fixed_mode->hdisplay,
1909                                                        fixed_mode->vdisplay);
1910 }
1911
1912 void icl_dsi_init(struct drm_i915_private *dev_priv)
1913 {
1914         struct intel_dsi *intel_dsi;
1915         struct intel_encoder *encoder;
1916         struct intel_connector *intel_connector;
1917         struct drm_connector *connector;
1918         enum port port;
1919
1920         if (!intel_bios_is_dsi_present(dev_priv, &port))
1921                 return;
1922
1923         intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL);
1924         if (!intel_dsi)
1925                 return;
1926
1927         intel_connector = intel_connector_alloc();
1928         if (!intel_connector) {
1929                 kfree(intel_dsi);
1930                 return;
1931         }
1932
1933         encoder = &intel_dsi->base;
1934         intel_dsi->attached_connector = intel_connector;
1935         connector = &intel_connector->base;
1936
1937         /* register DSI encoder with DRM subsystem */
1938         drm_encoder_init(&dev_priv->drm, &encoder->base, &gen11_dsi_encoder_funcs,
1939                          DRM_MODE_ENCODER_DSI, "DSI %c", port_name(port));
1940
1941         encoder->pre_pll_enable = gen11_dsi_pre_pll_enable;
1942         encoder->pre_enable = gen11_dsi_pre_enable;
1943         encoder->enable = gen11_dsi_enable;
1944         encoder->disable = gen11_dsi_disable;
1945         encoder->post_disable = gen11_dsi_post_disable;
1946         encoder->port = port;
1947         encoder->get_config = gen11_dsi_get_config;
1948         encoder->sync_state = gen11_dsi_sync_state;
1949         encoder->update_pipe = intel_backlight_update;
1950         encoder->compute_config = gen11_dsi_compute_config;
1951         encoder->get_hw_state = gen11_dsi_get_hw_state;
1952         encoder->initial_fastset_check = gen11_dsi_initial_fastset_check;
1953         encoder->type = INTEL_OUTPUT_DSI;
1954         encoder->cloneable = 0;
1955         encoder->pipe_mask = ~0;
1956         encoder->power_domain = POWER_DOMAIN_PORT_DSI;
1957         encoder->get_power_domains = gen11_dsi_get_power_domains;
1958         encoder->disable_clock = gen11_dsi_gate_clocks;
1959         encoder->is_clock_enabled = gen11_dsi_is_clock_enabled;
1960
1961         /* register DSI connector with DRM subsystem */
1962         drm_connector_init(&dev_priv->drm, connector, &gen11_dsi_connector_funcs,
1963                            DRM_MODE_CONNECTOR_DSI);
1964         drm_connector_helper_add(connector, &gen11_dsi_connector_helper_funcs);
1965         connector->display_info.subpixel_order = SubPixelHorizontalRGB;
1966         intel_connector->get_hw_state = intel_connector_get_hw_state;
1967
1968         /* attach connector to encoder */
1969         intel_connector_attach_encoder(intel_connector, encoder);
1970
1971         encoder->devdata = intel_bios_encoder_data_lookup(dev_priv, port);
1972         intel_bios_init_panel_late(dev_priv, &intel_connector->panel, encoder->devdata, NULL);
1973
1974         mutex_lock(&dev_priv->drm.mode_config.mutex);
1975         intel_panel_add_vbt_lfp_fixed_mode(intel_connector);
1976         mutex_unlock(&dev_priv->drm.mode_config.mutex);
1977
1978         if (!intel_panel_preferred_fixed_mode(intel_connector)) {
1979                 drm_err(&dev_priv->drm, "DSI fixed mode info missing\n");
1980                 goto err;
1981         }
1982
1983         intel_panel_init(intel_connector, NULL);
1984
1985         intel_backlight_setup(intel_connector, INVALID_PIPE);
1986
1987         if (intel_connector->panel.vbt.dsi.config->dual_link)
1988                 intel_dsi->ports = BIT(PORT_A) | BIT(PORT_B);
1989         else
1990                 intel_dsi->ports = BIT(port);
1991
1992         if (drm_WARN_ON(&dev_priv->drm, intel_connector->panel.vbt.dsi.bl_ports & ~intel_dsi->ports))
1993                 intel_connector->panel.vbt.dsi.bl_ports &= intel_dsi->ports;
1994
1995         if (drm_WARN_ON(&dev_priv->drm, intel_connector->panel.vbt.dsi.cabc_ports & ~intel_dsi->ports))
1996                 intel_connector->panel.vbt.dsi.cabc_ports &= intel_dsi->ports;
1997
1998         for_each_dsi_port(port, intel_dsi->ports) {
1999                 struct intel_dsi_host *host;
2000
2001                 host = intel_dsi_host_init(intel_dsi, &gen11_dsi_host_ops, port);
2002                 if (!host)
2003                         goto err;
2004
2005                 intel_dsi->dsi_hosts[port] = host;
2006         }
2007
2008         if (!intel_dsi_vbt_init(intel_dsi, MIPI_DSI_GENERIC_PANEL_ID)) {
2009                 drm_dbg_kms(&dev_priv->drm, "no device found\n");
2010                 goto err;
2011         }
2012
2013         icl_dphy_param_init(intel_dsi);
2014
2015         icl_dsi_add_properties(intel_connector);
2016         return;
2017
2018 err:
2019         drm_connector_cleanup(connector);
2020         drm_encoder_cleanup(&encoder->base);
2021         kfree(intel_dsi);
2022         kfree(intel_connector);
2023 }