drivers/gpu/drm/bridge/ti-sn65dsi86.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2018, The Linux Foundation. All rights reserved.
   4  * datasheet: https://www.ti.com/lit/ds/symlink/sn65dsi86.pdf
   5  */
   6
   7 #include <linux/atomic.h>
   8 #include <linux/auxiliary_bus.h>
   9 #include <linux/bitfield.h>
  10 #include <linux/bits.h>
  11 #include <linux/clk.h>
  12 #include <linux/debugfs.h>
  13 #include <linux/gpio/consumer.h>
  14 #include <linux/gpio/driver.h>
  15 #include <linux/i2c.h>
  16 #include <linux/iopoll.h>
  17 #include <linux/module.h>
  18 #include <linux/of_graph.h>
  19 #include <linux/pm_runtime.h>
  20 #include <linux/pwm.h>
  21 #include <linux/regmap.h>
  22 #include <linux/regulator/consumer.h>
  23
  24 #include <asm/unaligned.h>
  25
  26 #include <drm/display/drm_dp_aux_bus.h>
  27 #include <drm/display/drm_dp_helper.h>
  28 #include <drm/drm_atomic.h>
  29 #include <drm/drm_atomic_helper.h>
  30 #include <drm/drm_bridge.h>
  31 #include <drm/drm_bridge_connector.h>
  32 #include <drm/drm_edid.h>
  33 #include <drm/drm_mipi_dsi.h>
  34 #include <drm/drm_of.h>
  35 #include <drm/drm_panel.h>
  36 #include <drm/drm_print.h>
  37 #include <drm/drm_probe_helper.h>
  38
  39 #define SN_DEVICE_REV_REG                       0x08
  40 #define SN_DPPLL_SRC_REG                        0x0A
  41 #define  DPPLL_CLK_SRC_DSICLK                   BIT(0)
  42 #define  REFCLK_FREQ_MASK                       GENMASK(3, 1)
  43 #define  REFCLK_FREQ(x)                         ((x) << 1)
  44 #define  DPPLL_SRC_DP_PLL_LOCK                  BIT(7)
  45 #define SN_PLL_ENABLE_REG                       0x0D
  46 #define SN_DSI_LANES_REG                        0x10
  47 #define  CHA_DSI_LANES_MASK                     GENMASK(4, 3)
  48 #define  CHA_DSI_LANES(x)                       ((x) << 3)
  49 #define SN_DSIA_CLK_FREQ_REG                    0x12
  50 #define SN_CHA_ACTIVE_LINE_LENGTH_LOW_REG       0x20
  51 #define SN_CHA_VERTICAL_DISPLAY_SIZE_LOW_REG    0x24
  52 #define SN_CHA_HSYNC_PULSE_WIDTH_LOW_REG        0x2C
  53 #define SN_CHA_HSYNC_PULSE_WIDTH_HIGH_REG       0x2D
  54 #define  CHA_HSYNC_POLARITY                     BIT(7)
  55 #define SN_CHA_VSYNC_PULSE_WIDTH_LOW_REG        0x30
  56 #define SN_CHA_VSYNC_PULSE_WIDTH_HIGH_REG       0x31
  57 #define  CHA_VSYNC_POLARITY                     BIT(7)
  58 #define SN_CHA_HORIZONTAL_BACK_PORCH_REG        0x34
  59 #define SN_CHA_VERTICAL_BACK_PORCH_REG          0x36
  60 #define SN_CHA_HORIZONTAL_FRONT_PORCH_REG       0x38
  61 #define SN_CHA_VERTICAL_FRONT_PORCH_REG         0x3A
  62 #define SN_LN_ASSIGN_REG                        0x59
  63 #define  LN_ASSIGN_WIDTH                        2
  64 #define SN_ENH_FRAME_REG                        0x5A
  65 #define  VSTREAM_ENABLE                         BIT(3)
  66 #define  LN_POLRS_OFFSET                        4
  67 #define  LN_POLRS_MASK                          0xf0
  68 #define SN_DATA_FORMAT_REG                      0x5B
  69 #define  BPP_18_RGB                             BIT(0)
  70 #define SN_HPD_DISABLE_REG                      0x5C
  71 #define  HPD_DISABLE                            BIT(0)
  72 #define  HPD_DEBOUNCED_STATE                    BIT(4)
  73 #define SN_GPIO_IO_REG                          0x5E
  74 #define  SN_GPIO_INPUT_SHIFT                    4
  75 #define  SN_GPIO_OUTPUT_SHIFT                   0
  76 #define SN_GPIO_CTRL_REG                        0x5F
  77 #define  SN_GPIO_MUX_INPUT                      0
  78 #define  SN_GPIO_MUX_OUTPUT                     1
  79 #define  SN_GPIO_MUX_SPECIAL                    2
  80 #define  SN_GPIO_MUX_MASK                       0x3
  81 #define SN_AUX_WDATA_REG(x)                     (0x64 + (x))
  82 #define SN_AUX_ADDR_19_16_REG                   0x74
  83 #define SN_AUX_ADDR_15_8_REG                    0x75
  84 #define SN_AUX_ADDR_7_0_REG                     0x76
  85 #define SN_AUX_ADDR_MASK                        GENMASK(19, 0)
  86 #define SN_AUX_LENGTH_REG                       0x77
  87 #define SN_AUX_CMD_REG                          0x78
  88 #define  AUX_CMD_SEND                           BIT(0)
  89 #define  AUX_CMD_REQ(x)                         ((x) << 4)
  90 #define SN_AUX_RDATA_REG(x)                     (0x79 + (x))
  91 #define SN_SSC_CONFIG_REG                       0x93
  92 #define  DP_NUM_LANES_MASK                      GENMASK(5, 4)
  93 #define  DP_NUM_LANES(x)                        ((x) << 4)
  94 #define SN_DATARATE_CONFIG_REG                  0x94
  95 #define  DP_DATARATE_MASK                       GENMASK(7, 5)
  96 #define  DP_DATARATE(x)                         ((x) << 5)
  97 #define SN_TRAINING_SETTING_REG                 0x95
  98 #define  SCRAMBLE_DISABLE                       BIT(4)
  99 #define SN_ML_TX_MODE_REG                       0x96
 100 #define  ML_TX_MAIN_LINK_OFF                    0
 101 #define  ML_TX_NORMAL_MODE                      BIT(0)
 102 #define SN_PWM_PRE_DIV_REG                      0xA0
 103 #define SN_BACKLIGHT_SCALE_REG                  0xA1
 104 #define  BACKLIGHT_SCALE_MAX                    0xFFFF
 105 #define SN_BACKLIGHT_REG                        0xA3
 106 #define SN_PWM_EN_INV_REG                       0xA5
 107 #define  SN_PWM_INV_MASK                        BIT(0)
 108 #define  SN_PWM_EN_MASK                         BIT(1)
 109 #define SN_AUX_CMD_STATUS_REG                   0xF4
 110 #define  AUX_IRQ_STATUS_AUX_RPLY_TOUT           BIT(3)
 111 #define  AUX_IRQ_STATUS_AUX_SHORT               BIT(5)
 112 #define  AUX_IRQ_STATUS_NAT_I2C_FAIL            BIT(6)
 113
 114 #define MIN_DSI_CLK_FREQ_MHZ    40
 115
 116 /* fudge factor required to account for 8b/10b encoding */
 117 #define DP_CLK_FUDGE_NUM        10
 118 #define DP_CLK_FUDGE_DEN        8
 119
 120 /* Matches DP_AUX_MAX_PAYLOAD_BYTES (for now) */
 121 #define SN_AUX_MAX_PAYLOAD_BYTES        16
 122
 123 #define SN_REGULATOR_SUPPLY_NUM         4
 124
 125 #define SN_MAX_DP_LANES                 4
 126 #define SN_NUM_GPIOS                    4
 127 #define SN_GPIO_PHYSICAL_OFFSET         1
 128
 129 #define SN_LINK_TRAINING_TRIES          10
 130
 131 #define SN_PWM_GPIO_IDX                 3 /* 4th GPIO */
 132
 133 /**
 134  * struct ti_sn65dsi86 - Platform data for ti-sn65dsi86 driver.
 135  * @bridge_aux:   AUX-bus sub device for MIPI-to-eDP bridge functionality.
 136  * @gpio_aux:     AUX-bus sub device for GPIO controller functionality.
 137  * @aux_aux:      AUX-bus sub device for eDP AUX channel functionality.
 138  * @pwm_aux:      AUX-bus sub device for PWM controller functionality.
 139  *
 140  * @dev:          Pointer to the top level (i2c) device.
 141  * @regmap:       Regmap for accessing i2c.
 142  * @aux:          Our aux channel.
 143  * @bridge:       Our bridge.
 144  * @connector:    Our connector.
 145  * @host_node:    Remote DSI node.
 146  * @dsi:          Our MIPI DSI source.
 147  * @refclk:       Our reference clock.
 148  * @next_bridge:  The bridge on the eDP side.
 149  * @enable_gpio:  The GPIO we toggle to enable the bridge.
 150  * @supplies:     Data for bulk enabling/disabling our regulators.
 151  * @dp_lanes:     Count of dp_lanes we're using.
 152  * @ln_assign:    Value to program to the LN_ASSIGN register.
 153  * @ln_polrs:     Value for the 4-bit LN_POLRS field of SN_ENH_FRAME_REG.
 154  * @comms_enabled: If true then communication over the aux channel is enabled.
 155  * @comms_mutex:   Protects modification of comms_enabled.
 156  *
 157  * @gchip:        If we expose our GPIOs, this is used.
 158  * @gchip_output: A cache of whether we've set GPIOs to output.  This
 159  *                serves double-duty of keeping track of the direction and
 160  *                also keeping track of whether we've incremented the
 161  *                pm_runtime reference count for this pin, which we do
 162  *                whenever a pin is configured as an output.  This is a
 163  *                bitmap so we can do atomic ops on it without an extra
 164  *                lock so concurrent users of our 4 GPIOs don't stomp on
 165  *                each other's read-modify-write.
 166  *
 167  * @pchip:        pwm_chip if the PWM is exposed.
 168  * @pwm_enabled:  Used to track if the PWM signal is currently enabled.
 169  * @pwm_pin_busy: Track if GPIO4 is currently requested for GPIO or PWM.
 170  * @pwm_refclk_freq: Cache for the reference clock input to the PWM.
 171  */
 172 struct ti_sn65dsi86 {
 173         struct auxiliary_device         bridge_aux;
 174         struct auxiliary_device         gpio_aux;
 175         struct auxiliary_device         aux_aux;
 176         struct auxiliary_device         pwm_aux;
 177
 178         struct device                   *dev;
 179         struct regmap                   *regmap;
 180         struct drm_dp_aux               aux;
 181         struct drm_bridge               bridge;
 182         struct drm_connector            *connector;
 183         struct device_node              *host_node;
 184         struct mipi_dsi_device          *dsi;
 185         struct clk                      *refclk;
 186         struct drm_bridge               *next_bridge;
 187         struct gpio_desc                *enable_gpio;
 188         struct regulator_bulk_data      supplies[SN_REGULATOR_SUPPLY_NUM];
 189         int                             dp_lanes;
 190         u8                              ln_assign;
 191         u8                              ln_polrs;
 192         bool                            comms_enabled;
 193         struct mutex                    comms_mutex;
 194
 195 #if defined(CONFIG_OF_GPIO)
 196         struct gpio_chip                gchip;
 197         DECLARE_BITMAP(gchip_output, SN_NUM_GPIOS);
 198 #endif
 199 #if defined(CONFIG_PWM)
 200         struct pwm_chip                 pchip;
 201         bool                            pwm_enabled;
 202         atomic_t                        pwm_pin_busy;
 203 #endif
 204         unsigned int                    pwm_refclk_freq;
 205 };
 206
 207 static const struct regmap_range ti_sn65dsi86_volatile_ranges[] = {
 208         { .range_min = 0, .range_max = 0xFF },
 209 };
 210
 211 static const struct regmap_access_table ti_sn_bridge_volatile_table = {
 212         .yes_ranges = ti_sn65dsi86_volatile_ranges,
 213         .n_yes_ranges = ARRAY_SIZE(ti_sn65dsi86_volatile_ranges),
 214 };
 215
 216 static const struct regmap_config ti_sn65dsi86_regmap_config = {
 217         .reg_bits = 8,
 218         .val_bits = 8,
 219         .volatile_table = &ti_sn_bridge_volatile_table,
 220         .cache_type = REGCACHE_NONE,
 221         .max_register = 0xFF,
 222 };
 223
 224 static int __maybe_unused ti_sn65dsi86_read_u16(struct ti_sn65dsi86 *pdata,
 225                                                 unsigned int reg, u16 *val)
 226 {
 227         u8 buf[2];
 228         int ret;
 229
 230         ret = regmap_bulk_read(pdata->regmap, reg, buf, ARRAY_SIZE(buf));
 231         if (ret)
 232                 return ret;
 233
 234         *val = buf[0] | (buf[1] << 8);
 235
 236         return 0;
 237 }
 238
 239 static void ti_sn65dsi86_write_u16(struct ti_sn65dsi86 *pdata,
 240                                    unsigned int reg, u16 val)
 241 {
 242         u8 buf[2] = { val & 0xff, val >> 8 };
 243
 244         regmap_bulk_write(pdata->regmap, reg, buf, ARRAY_SIZE(buf));
 245 }
 246
 247 static u32 ti_sn_bridge_get_dsi_freq(struct ti_sn65dsi86 *pdata)
 248 {
 249         u32 bit_rate_khz, clk_freq_khz;
 250         struct drm_display_mode *mode =
 251                 &pdata->bridge.encoder->crtc->state->adjusted_mode;
 252
 253         bit_rate_khz = mode->clock *
 254                         mipi_dsi_pixel_format_to_bpp(pdata->dsi->format);
 255         clk_freq_khz = bit_rate_khz / (pdata->dsi->lanes * 2);
 256
 257         return clk_freq_khz;
 258 }
 259
 260 /* clk frequencies supported by bridge in Hz in case derived from REFCLK pin */
 261 static const u32 ti_sn_bridge_refclk_lut[] = {
 262         12000000,
 263         19200000,
 264         26000000,
 265         27000000,
 266         38400000,
 267 };
 268
 269 /* clk frequencies supported by bridge in Hz in case derived from DACP/N pin */
 270 static const u32 ti_sn_bridge_dsiclk_lut[] = {
 271         468000000,
 272         384000000,
 273         416000000,
 274         486000000,
 275         460800000,
 276 };
 277
 278 static void ti_sn_bridge_set_refclk_freq(struct ti_sn65dsi86 *pdata)
 279 {
 280         int i;
 281         u32 refclk_rate;
 282         const u32 *refclk_lut;
 283         size_t refclk_lut_size;
 284
 285         if (pdata->refclk) {
 286                 refclk_rate = clk_get_rate(pdata->refclk);
 287                 refclk_lut = ti_sn_bridge_refclk_lut;
 288                 refclk_lut_size = ARRAY_SIZE(ti_sn_bridge_refclk_lut);
 289                 clk_prepare_enable(pdata->refclk);
 290         } else {
 291                 refclk_rate = ti_sn_bridge_get_dsi_freq(pdata) * 1000;
 292                 refclk_lut = ti_sn_bridge_dsiclk_lut;
 293                 refclk_lut_size = ARRAY_SIZE(ti_sn_bridge_dsiclk_lut);
 294         }
 295
 296         /* for i equals to refclk_lut_size means default frequency */
 297         for (i = 0; i < refclk_lut_size; i++)
 298                 if (refclk_lut[i] == refclk_rate)
 299                         break;
 300
 301         regmap_update_bits(pdata->regmap, SN_DPPLL_SRC_REG, REFCLK_FREQ_MASK,
 302                            REFCLK_FREQ(i));
 303
 304         /*
 305          * The PWM refclk is based on the value written to SN_DPPLL_SRC_REG,
 306          * regardless of its actual sourcing.
 307          */
 308         pdata->pwm_refclk_freq = ti_sn_bridge_refclk_lut[i];
 309 }
 310
 311 static void ti_sn65dsi86_enable_comms(struct ti_sn65dsi86 *pdata)
 312 {
 313         mutex_lock(&pdata->comms_mutex);
 314
 315         /* configure bridge ref_clk */
 316         ti_sn_bridge_set_refclk_freq(pdata);
 317
 318         /*
 319          * HPD on this bridge chip is a bit useless.  This is an eDP bridge
 320          * so the HPD is an internal signal that's only there to signal that
 321          * the panel is done powering up.  ...but the bridge chip debounces
 322          * this signal by between 100 ms and 400 ms (depending on process,
 323          * voltage, and temperate--I measured it at about 200 ms).  One
 324          * particular panel asserted HPD 84 ms after it was powered on meaning
 325          * that we saw HPD 284 ms after power on.  ...but the same panel said
 326          * that instead of looking at HPD you could just hardcode a delay of
 327          * 200 ms.  We'll assume that the panel driver will have the hardcoded
 328          * delay in its prepare and always disable HPD.
 329          *
 330          * If HPD somehow makes sense on some future panel we'll have to
 331          * change this to be conditional on someone specifying that HPD should
 332          * be used.
 333          */
 334         regmap_update_bits(pdata->regmap, SN_HPD_DISABLE_REG, HPD_DISABLE,
 335                            HPD_DISABLE);
 336
 337         pdata->comms_enabled = true;
 338
 339         mutex_unlock(&pdata->comms_mutex);
 340 }
 341
 342 static void ti_sn65dsi86_disable_comms(struct ti_sn65dsi86 *pdata)
 343 {
 344         mutex_lock(&pdata->comms_mutex);
 345
 346         pdata->comms_enabled = false;
 347         clk_disable_unprepare(pdata->refclk);
 348
 349         mutex_unlock(&pdata->comms_mutex);
 350 }
 351
 352 static int __maybe_unused ti_sn65dsi86_resume(struct device *dev)
 353 {
 354         struct ti_sn65dsi86 *pdata = dev_get_drvdata(dev);
 355         int ret;
 356
 357         ret = regulator_bulk_enable(SN_REGULATOR_SUPPLY_NUM, pdata->supplies);
 358         if (ret) {
 359                 DRM_ERROR("failed to enable supplies %d\n", ret);
 360                 return ret;
 361         }
 362
 363         /* td2: min 100 us after regulators before enabling the GPIO */
 364         usleep_range(100, 110);
 365
 366         gpiod_set_value_cansleep(pdata->enable_gpio, 1);
 367
 368         /*
 369          * If we have a reference clock we can enable communication w/ the
 370          * panel (including the aux channel) w/out any need for an input clock
 371          * so we can do it in resume which lets us read the EDID before
 372          * pre_enable(). Without a reference clock we need the MIPI reference
 373          * clock so reading early doesn't work.
 374          */
 375         if (pdata->refclk)
 376                 ti_sn65dsi86_enable_comms(pdata);
 377
 378         return ret;
 379 }
 380
 381 static int __maybe_unused ti_sn65dsi86_suspend(struct device *dev)
 382 {
 383         struct ti_sn65dsi86 *pdata = dev_get_drvdata(dev);
 384         int ret;
 385
 386         if (pdata->refclk)
 387                 ti_sn65dsi86_disable_comms(pdata);
 388
 389         gpiod_set_value_cansleep(pdata->enable_gpio, 0);
 390
 391         ret = regulator_bulk_disable(SN_REGULATOR_SUPPLY_NUM, pdata->supplies);
 392         if (ret)
 393                 DRM_ERROR("failed to disable supplies %d\n", ret);
 394
 395         return ret;
 396 }
 397
 398 static const struct dev_pm_ops ti_sn65dsi86_pm_ops = {
 399         SET_RUNTIME_PM_OPS(ti_sn65dsi86_suspend, ti_sn65dsi86_resume, NULL)
 400         SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
 401                                 pm_runtime_force_resume)
 402 };
 403
 404 static int status_show(struct seq_file *s, void *data)
 405 {
 406         struct ti_sn65dsi86 *pdata = s->private;
 407         unsigned int reg, val;
 408
 409         seq_puts(s, "STATUS REGISTERS:\n");
 410
 411         pm_runtime_get_sync(pdata->dev);
 412
 413         /* IRQ Status Registers, see Table 31 in datasheet */
 414         for (reg = 0xf0; reg <= 0xf8; reg++) {
 415                 regmap_read(pdata->regmap, reg, &val);
 416                 seq_printf(s, "[0x%02x] = 0x%08x\n", reg, val);
 417         }
 418
 419         pm_runtime_put_autosuspend(pdata->dev);
 420
 421         return 0;
 422 }
 423
 424 DEFINE_SHOW_ATTRIBUTE(status);
 425
 426 static void ti_sn65dsi86_debugfs_remove(void *data)
 427 {
 428         debugfs_remove_recursive(data);
 429 }
 430
 431 static void ti_sn65dsi86_debugfs_init(struct ti_sn65dsi86 *pdata)
 432 {
 433         struct device *dev = pdata->dev;
 434         struct dentry *debugfs;
 435         int ret;
 436
 437         debugfs = debugfs_create_dir(dev_name(dev), NULL);
 438
 439         /*
 440          * We might get an error back if debugfs wasn't enabled in the kernel
 441          * so let's just silently return upon failure.
 442          */
 443         if (IS_ERR_OR_NULL(debugfs))
 444                 return;
 445
 446         ret = devm_add_action_or_reset(dev, ti_sn65dsi86_debugfs_remove, debugfs);
 447         if (ret)
 448                 return;
 449
 450         debugfs_create_file("status", 0600, debugfs, pdata, &status_fops);
 451 }
 452
 453 /* -----------------------------------------------------------------------------
 454  * Auxiliary Devices (*not* AUX)
 455  */
 456
 457 static void ti_sn65dsi86_uninit_aux(void *data)
 458 {
 459         auxiliary_device_uninit(data);
 460 }
 461
 462 static void ti_sn65dsi86_delete_aux(void *data)
 463 {
 464         auxiliary_device_delete(data);
 465 }
 466
 467 /*
 468  * AUX bus docs say that a non-NULL release is mandatory, but it makes no
 469  * sense for the model used here where all of the aux devices are allocated
 470  * in the single shared structure. We'll use this noop as a workaround.
 471  */
 472 static void ti_sn65dsi86_noop(struct device *dev) {}
 473
 474 static int ti_sn65dsi86_add_aux_device(struct ti_sn65dsi86 *pdata,
 475                                        struct auxiliary_device *aux,
 476                                        const char *name)
 477 {
 478         struct device *dev = pdata->dev;
 479         int ret;
 480
 481         aux->name = name;
 482         aux->dev.parent = dev;
 483         aux->dev.release = ti_sn65dsi86_noop;
 484         device_set_of_node_from_dev(&aux->dev, dev);
 485         ret = auxiliary_device_init(aux);
 486         if (ret)
 487                 return ret;
 488         ret = devm_add_action_or_reset(dev, ti_sn65dsi86_uninit_aux, aux);
 489         if (ret)
 490                 return ret;
 491
 492         ret = auxiliary_device_add(aux);
 493         if (ret)
 494                 return ret;
 495         ret = devm_add_action_or_reset(dev, ti_sn65dsi86_delete_aux, aux);
 496
 497         return ret;
 498 }
 499
 500 /* -----------------------------------------------------------------------------
 501  * AUX Adapter
 502  */
 503
 504 static struct ti_sn65dsi86 *aux_to_ti_sn65dsi86(struct drm_dp_aux *aux)
 505 {
 506         return container_of(aux, struct ti_sn65dsi86, aux);
 507 }
 508
 509 static ssize_t ti_sn_aux_transfer(struct drm_dp_aux *aux,
 510                                   struct drm_dp_aux_msg *msg)
 511 {
 512         struct ti_sn65dsi86 *pdata = aux_to_ti_sn65dsi86(aux);
 513         u32 request = msg->request & ~(DP_AUX_I2C_MOT | DP_AUX_I2C_WRITE_STATUS_UPDATE);
 514         u32 request_val = AUX_CMD_REQ(msg->request);
 515         u8 *buf = msg->buffer;
 516         unsigned int len = msg->size;
 517         unsigned int val;
 518         int ret;
 519         u8 addr_len[SN_AUX_LENGTH_REG + 1 - SN_AUX_ADDR_19_16_REG];
 520
 521         if (len > SN_AUX_MAX_PAYLOAD_BYTES)
 522                 return -EINVAL;
 523
 524         pm_runtime_get_sync(pdata->dev);
 525         mutex_lock(&pdata->comms_mutex);
 526
 527         /*
 528          * If someone tries to do a DDC over AUX transaction before pre_enable()
 529          * on a device without a dedicated reference clock then we just can't
 530          * do it. Fail right away. This prevents non-refclk users from reading
 531          * the EDID before enabling the panel but such is life.
 532          */
 533         if (!pdata->comms_enabled) {
 534                 ret = -EIO;
 535                 goto exit;
 536         }
 537
 538         switch (request) {
 539         case DP_AUX_NATIVE_WRITE:
 540         case DP_AUX_I2C_WRITE:
 541         case DP_AUX_NATIVE_READ:
 542         case DP_AUX_I2C_READ:
 543                 regmap_write(pdata->regmap, SN_AUX_CMD_REG, request_val);
 544                 /* Assume it's good */
 545                 msg->reply = 0;
 546                 break;
 547         default:
 548                 ret = -EINVAL;
 549                 goto exit;
 550         }
 551
 552         BUILD_BUG_ON(sizeof(addr_len) != sizeof(__be32));
 553         put_unaligned_be32((msg->address & SN_AUX_ADDR_MASK) << 8 | len,
 554                            addr_len);
 555         regmap_bulk_write(pdata->regmap, SN_AUX_ADDR_19_16_REG, addr_len,
 556                           ARRAY_SIZE(addr_len));
 557
 558         if (request == DP_AUX_NATIVE_WRITE || request == DP_AUX_I2C_WRITE)
 559                 regmap_bulk_write(pdata->regmap, SN_AUX_WDATA_REG(0), buf, len);
 560
 561         /* Clear old status bits before start so we don't get confused */
 562         regmap_write(pdata->regmap, SN_AUX_CMD_STATUS_REG,
 563                      AUX_IRQ_STATUS_NAT_I2C_FAIL |
 564                      AUX_IRQ_STATUS_AUX_RPLY_TOUT |
 565                      AUX_IRQ_STATUS_AUX_SHORT);
 566
 567         regmap_write(pdata->regmap, SN_AUX_CMD_REG, request_val | AUX_CMD_SEND);
 568
 569         /* Zero delay loop because i2c transactions are slow already */
 570         ret = regmap_read_poll_timeout(pdata->regmap, SN_AUX_CMD_REG, val,
 571                                        !(val & AUX_CMD_SEND), 0, 50 * 1000);
 572         if (ret)
 573                 goto exit;
 574
 575         ret = regmap_read(pdata->regmap, SN_AUX_CMD_STATUS_REG, &val);
 576         if (ret)
 577                 goto exit;
 578
 579         if (val & AUX_IRQ_STATUS_AUX_RPLY_TOUT) {
 580                 /*
 581                  * The hardware tried the message seven times per the DP spec
 582                  * but it hit a timeout. We ignore defers here because they're
 583                  * handled in hardware.
 584                  */
 585                 ret = -ETIMEDOUT;
 586                 goto exit;
 587         }
 588
 589         if (val & AUX_IRQ_STATUS_AUX_SHORT) {
 590                 ret = regmap_read(pdata->regmap, SN_AUX_LENGTH_REG, &len);
 591                 if (ret)
 592                         goto exit;
 593         } else if (val & AUX_IRQ_STATUS_NAT_I2C_FAIL) {
 594                 switch (request) {
 595                 case DP_AUX_I2C_WRITE:
 596                 case DP_AUX_I2C_READ:
 597                         msg->reply |= DP_AUX_I2C_REPLY_NACK;
 598                         break;
 599                 case DP_AUX_NATIVE_READ:
 600                 case DP_AUX_NATIVE_WRITE:
 601                         msg->reply |= DP_AUX_NATIVE_REPLY_NACK;
 602                         break;
 603                 }
 604                 len = 0;
 605                 goto exit;
 606         }
 607
 608         if (request != DP_AUX_NATIVE_WRITE && request != DP_AUX_I2C_WRITE && len != 0)
 609                 ret = regmap_bulk_read(pdata->regmap, SN_AUX_RDATA_REG(0), buf, len);
 610
 611 exit:
 612         mutex_unlock(&pdata->comms_mutex);
 613         pm_runtime_mark_last_busy(pdata->dev);
 614         pm_runtime_put_autosuspend(pdata->dev);
 615
 616         if (ret)
 617                 return ret;
 618         return len;
 619 }
 620
 621 static int ti_sn_aux_wait_hpd_asserted(struct drm_dp_aux *aux, unsigned long wait_us)
 622 {
 623         /*
 624          * The HPD in this chip is a bit useless (See comment in
 625          * ti_sn65dsi86_enable_comms) so if our driver is expected to wait
 626          * for HPD, we just assume it's asserted after the wait_us delay.
 627          *
 628          * In case we are asked to wait forever (wait_us=0) take conservative
 629          * 500ms delay.
 630          */
 631         if (wait_us == 0)
 632                 wait_us = 500000;
 633
 634         usleep_range(wait_us, wait_us + 1000);
 635
 636         return 0;
 637 }
 638
 639 static int ti_sn_aux_probe(struct auxiliary_device *adev,
 640                            const struct auxiliary_device_id *id)
 641 {
 642         struct ti_sn65dsi86 *pdata = dev_get_drvdata(adev->dev.parent);
 643         int ret;
 644
 645         pdata->aux.name = "ti-sn65dsi86-aux";
 646         pdata->aux.dev = &adev->dev;
 647         pdata->aux.transfer = ti_sn_aux_transfer;
 648         pdata->aux.wait_hpd_asserted = ti_sn_aux_wait_hpd_asserted;
 649         drm_dp_aux_init(&pdata->aux);
 650
 651         ret = devm_of_dp_aux_populate_ep_devices(&pdata->aux);
 652         if (ret)
 653                 return ret;
 654
 655         /*
 656          * The eDP to MIPI bridge parts don't work until the AUX channel is
 657          * setup so we don't add it in the main driver probe, we add it now.
 658          */
 659         return ti_sn65dsi86_add_aux_device(pdata, &pdata->bridge_aux, "bridge");
 660 }
 661
 662 static const struct auxiliary_device_id ti_sn_aux_id_table[] = {
 663         { .name = "ti_sn65dsi86.aux", },
 664         {},
 665 };
 666
 667 static struct auxiliary_driver ti_sn_aux_driver = {
 668         .name = "aux",
 669         .probe = ti_sn_aux_probe,
 670         .id_table = ti_sn_aux_id_table,
 671 };
 672
 673 /*------------------------------------------------------------------------------
 674  * DRM Bridge
 675  */
 676
 677 static struct ti_sn65dsi86 *bridge_to_ti_sn65dsi86(struct drm_bridge *bridge)
 678 {
 679         return container_of(bridge, struct ti_sn65dsi86, bridge);
 680 }
 681
 682 static int ti_sn_attach_host(struct ti_sn65dsi86 *pdata)
 683 {
 684         int val;
 685         struct mipi_dsi_host *host;
 686         struct mipi_dsi_device *dsi;
 687         struct device *dev = pdata->dev;
 688         const struct mipi_dsi_device_info info = { .type = "ti_sn_bridge",
 689                                                    .channel = 0,
 690                                                    .node = NULL,
 691         };
 692
 693         host = of_find_mipi_dsi_host_by_node(pdata->host_node);
 694         if (!host)
 695                 return -EPROBE_DEFER;
 696
 697         dsi = devm_mipi_dsi_device_register_full(dev, host, &info);
 698         if (IS_ERR(dsi))
 699                 return PTR_ERR(dsi);
 700
 701         /* TODO: setting to 4 MIPI lanes always for now */
 702         dsi->lanes = 4;
 703         dsi->format = MIPI_DSI_FMT_RGB888;
 704         dsi->mode_flags = MIPI_DSI_MODE_VIDEO;
 705
 706         /* check if continuous dsi clock is required or not */
 707         pm_runtime_get_sync(dev);
 708         regmap_read(pdata->regmap, SN_DPPLL_SRC_REG, &val);
 709         pm_runtime_put_autosuspend(dev);
 710         if (!(val & DPPLL_CLK_SRC_DSICLK))
 711                 dsi->mode_flags |= MIPI_DSI_CLOCK_NON_CONTINUOUS;
 712
 713         pdata->dsi = dsi;
 714
 715         return devm_mipi_dsi_attach(dev, dsi);
 716 }
 717
 718 static int ti_sn_bridge_attach(struct drm_bridge *bridge,
 719                                enum drm_bridge_attach_flags flags)
 720 {
 721         struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge);
 722         int ret;
 723
 724         pdata->aux.drm_dev = bridge->dev;
 725         ret = drm_dp_aux_register(&pdata->aux);
 726         if (ret < 0) {
 727                 drm_err(bridge->dev, "Failed to register DP AUX channel: %d\n", ret);
 728                 return ret;
 729         }
 730
 731         /*
 732          * Attach the next bridge.
 733          * We never want the next bridge to *also* create a connector.
 734          */
 735         ret = drm_bridge_attach(bridge->encoder, pdata->next_bridge,
 736                                 &pdata->bridge, flags | DRM_BRIDGE_ATTACH_NO_CONNECTOR);
 737         if (ret < 0)
 738                 goto err_initted_aux;
 739
 740         if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)
 741                 return 0;
 742
 743         pdata->connector = drm_bridge_connector_init(pdata->bridge.dev,
 744                                                      pdata->bridge.encoder);
 745         if (IS_ERR(pdata->connector)) {
 746                 ret = PTR_ERR(pdata->connector);
 747                 goto err_initted_aux;
 748         }
 749
 750         drm_connector_attach_encoder(pdata->connector, pdata->bridge.encoder);
 751
 752         return 0;
 753
 754 err_initted_aux:
 755         drm_dp_aux_unregister(&pdata->aux);
 756         return ret;
 757 }
 758
 759 static void ti_sn_bridge_detach(struct drm_bridge *bridge)
 760 {
 761         drm_dp_aux_unregister(&bridge_to_ti_sn65dsi86(bridge)->aux);
 762 }
 763
 764 static enum drm_mode_status
 765 ti_sn_bridge_mode_valid(struct drm_bridge *bridge,
 766                         const struct drm_display_info *info,
 767                         const struct drm_display_mode *mode)
 768 {
 769         /* maximum supported resolution is 4K at 60 fps */
 770         if (mode->clock > 594000)
 771                 return MODE_CLOCK_HIGH;
 772
 773         /*
 774          * The front and back porch registers are 8 bits, and pulse width
 775          * registers are 15 bits, so reject any modes with larger periods.
 776          */
 777
 778         if ((mode->hsync_start - mode->hdisplay) > 0xff)
 779                 return MODE_HBLANK_WIDE;
 780
 781         if ((mode->vsync_start - mode->vdisplay) > 0xff)
 782                 return MODE_VBLANK_WIDE;
 783
 784         if ((mode->hsync_end - mode->hsync_start) > 0x7fff)
 785                 return MODE_HSYNC_WIDE;
 786
 787         if ((mode->vsync_end - mode->vsync_start) > 0x7fff)
 788                 return MODE_VSYNC_WIDE;
 789
 790         if ((mode->htotal - mode->hsync_end) > 0xff)
 791                 return MODE_HBLANK_WIDE;
 792
 793         if ((mode->vtotal - mode->vsync_end) > 0xff)
 794                 return MODE_VBLANK_WIDE;
 795
 796         return MODE_OK;
 797 }
 798
 799 static void ti_sn_bridge_atomic_disable(struct drm_bridge *bridge,
 800                                         struct drm_bridge_state *old_bridge_state)
 801 {
 802         struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge);
 803
 804         /* disable video stream */
 805         regmap_update_bits(pdata->regmap, SN_ENH_FRAME_REG, VSTREAM_ENABLE, 0);
 806 }
 807
 808 static void ti_sn_bridge_set_dsi_rate(struct ti_sn65dsi86 *pdata)
 809 {
 810         unsigned int bit_rate_mhz, clk_freq_mhz;
 811         unsigned int val;
 812         struct drm_display_mode *mode =
 813                 &pdata->bridge.encoder->crtc->state->adjusted_mode;
 814
 815         /* set DSIA clk frequency */
 816         bit_rate_mhz = (mode->clock / 1000) *
 817                         mipi_dsi_pixel_format_to_bpp(pdata->dsi->format);
 818         clk_freq_mhz = bit_rate_mhz / (pdata->dsi->lanes * 2);
 819
 820         /* for each increment in val, frequency increases by 5MHz */
 821         val = (MIN_DSI_CLK_FREQ_MHZ / 5) +
 822                 (((clk_freq_mhz - MIN_DSI_CLK_FREQ_MHZ) / 5) & 0xFF);
 823         regmap_write(pdata->regmap, SN_DSIA_CLK_FREQ_REG, val);
 824 }
 825
 826 static unsigned int ti_sn_bridge_get_bpp(struct drm_connector *connector)
 827 {
 828         if (connector->display_info.bpc <= 6)
 829                 return 18;
 830         else
 831                 return 24;
 832 }
 833
 834 /*
 835  * LUT index corresponds to register value and
 836  * LUT values corresponds to dp data rate supported
 837  * by the bridge in Mbps unit.
 838  */
 839 static const unsigned int ti_sn_bridge_dp_rate_lut[] = {
 840         0, 1620, 2160, 2430, 2700, 3240, 4320, 5400
 841 };
 842
 843 static int ti_sn_bridge_calc_min_dp_rate_idx(struct ti_sn65dsi86 *pdata, unsigned int bpp)
 844 {
 845         unsigned int bit_rate_khz, dp_rate_mhz;
 846         unsigned int i;
 847         struct drm_display_mode *mode =
 848                 &pdata->bridge.encoder->crtc->state->adjusted_mode;
 849
 850         /* Calculate minimum bit rate based on our pixel clock. */
 851         bit_rate_khz = mode->clock * bpp;
 852
 853         /* Calculate minimum DP data rate, taking 80% as per DP spec */
 854         dp_rate_mhz = DIV_ROUND_UP(bit_rate_khz * DP_CLK_FUDGE_NUM,
 855                                    1000 * pdata->dp_lanes * DP_CLK_FUDGE_DEN);
 856
 857         for (i = 1; i < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut) - 1; i++)
 858                 if (ti_sn_bridge_dp_rate_lut[i] >= dp_rate_mhz)
 859                         break;
 860
 861         return i;
 862 }
 863
 864 static unsigned int ti_sn_bridge_read_valid_rates(struct ti_sn65dsi86 *pdata)
 865 {
 866         unsigned int valid_rates = 0;
 867         unsigned int rate_per_200khz;
 868         unsigned int rate_mhz;
 869         u8 dpcd_val;
 870         int ret;
 871         int i, j;
 872
 873         ret = drm_dp_dpcd_readb(&pdata->aux, DP_EDP_DPCD_REV, &dpcd_val);
 874         if (ret != 1) {
 875                 DRM_DEV_ERROR(pdata->dev,
 876                               "Can't read eDP rev (%d), assuming 1.1\n", ret);
 877                 dpcd_val = DP_EDP_11;
 878         }
 879
 880         if (dpcd_val >= DP_EDP_14) {
 881                 /* eDP 1.4 devices must provide a custom table */
 882                 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
 883
 884                 ret = drm_dp_dpcd_read(&pdata->aux, DP_SUPPORTED_LINK_RATES,
 885                                        sink_rates, sizeof(sink_rates));
 886
 887                 if (ret != sizeof(sink_rates)) {
 888                         DRM_DEV_ERROR(pdata->dev,
 889                                 "Can't read supported rate table (%d)\n", ret);
 890
 891                         /* By zeroing we'll fall back to DP_MAX_LINK_RATE. */
 892                         memset(sink_rates, 0, sizeof(sink_rates));
 893                 }
 894
 895                 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
 896                         rate_per_200khz = le16_to_cpu(sink_rates[i]);
 897
 898                         if (!rate_per_200khz)
 899                                 break;
 900
 901                         rate_mhz = rate_per_200khz * 200 / 1000;
 902                         for (j = 0;
 903                              j < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut);
 904                              j++) {
 905                                 if (ti_sn_bridge_dp_rate_lut[j] == rate_mhz)
 906                                         valid_rates |= BIT(j);
 907                         }
 908                 }
 909
 910                 for (i = 0; i < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut); i++) {
 911                         if (valid_rates & BIT(i))
 912                                 return valid_rates;
 913                 }
 914                 DRM_DEV_ERROR(pdata->dev,
 915                               "No matching eDP rates in table; falling back\n");
 916         }
 917
 918         /* On older versions best we can do is use DP_MAX_LINK_RATE */
 919         ret = drm_dp_dpcd_readb(&pdata->aux, DP_MAX_LINK_RATE, &dpcd_val);
 920         if (ret != 1) {
 921                 DRM_DEV_ERROR(pdata->dev,
 922                               "Can't read max rate (%d); assuming 5.4 GHz\n",
 923                               ret);
 924                 dpcd_val = DP_LINK_BW_5_4;
 925         }
 926
 927         switch (dpcd_val) {
 928         default:
 929                 DRM_DEV_ERROR(pdata->dev,
 930                               "Unexpected max rate (%#x); assuming 5.4 GHz\n",
 931                               (int)dpcd_val);
 932                 fallthrough;
 933         case DP_LINK_BW_5_4:
 934                 valid_rates |= BIT(7);
 935                 fallthrough;
 936         case DP_LINK_BW_2_7:
 937                 valid_rates |= BIT(4);
 938                 fallthrough;
 939         case DP_LINK_BW_1_62:
 940                 valid_rates |= BIT(1);
 941                 break;
 942         }
 943
 944         return valid_rates;
 945 }
 946
 947 static void ti_sn_bridge_set_video_timings(struct ti_sn65dsi86 *pdata)
 948 {
 949         struct drm_display_mode *mode =
 950                 &pdata->bridge.encoder->crtc->state->adjusted_mode;
 951         u8 hsync_polarity = 0, vsync_polarity = 0;
 952
 953         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
 954                 hsync_polarity = CHA_HSYNC_POLARITY;
 955         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
 956                 vsync_polarity = CHA_VSYNC_POLARITY;
 957
 958         ti_sn65dsi86_write_u16(pdata, SN_CHA_ACTIVE_LINE_LENGTH_LOW_REG,
 959                                mode->hdisplay);
 960         ti_sn65dsi86_write_u16(pdata, SN_CHA_VERTICAL_DISPLAY_SIZE_LOW_REG,
 961                                mode->vdisplay);
 962         regmap_write(pdata->regmap, SN_CHA_HSYNC_PULSE_WIDTH_LOW_REG,
 963                      (mode->hsync_end - mode->hsync_start) & 0xFF);
 964         regmap_write(pdata->regmap, SN_CHA_HSYNC_PULSE_WIDTH_HIGH_REG,
 965                      (((mode->hsync_end - mode->hsync_start) >> 8) & 0x7F) |
 966                      hsync_polarity);
 967         regmap_write(pdata->regmap, SN_CHA_VSYNC_PULSE_WIDTH_LOW_REG,
 968                      (mode->vsync_end - mode->vsync_start) & 0xFF);
 969         regmap_write(pdata->regmap, SN_CHA_VSYNC_PULSE_WIDTH_HIGH_REG,
 970                      (((mode->vsync_end - mode->vsync_start) >> 8) & 0x7F) |
 971                      vsync_polarity);
 972
 973         regmap_write(pdata->regmap, SN_CHA_HORIZONTAL_BACK_PORCH_REG,
 974                      (mode->htotal - mode->hsync_end) & 0xFF);
 975         regmap_write(pdata->regmap, SN_CHA_VERTICAL_BACK_PORCH_REG,
 976                      (mode->vtotal - mode->vsync_end) & 0xFF);
 977
 978         regmap_write(pdata->regmap, SN_CHA_HORIZONTAL_FRONT_PORCH_REG,
 979                      (mode->hsync_start - mode->hdisplay) & 0xFF);
 980         regmap_write(pdata->regmap, SN_CHA_VERTICAL_FRONT_PORCH_REG,
 981                      (mode->vsync_start - mode->vdisplay) & 0xFF);
 982
 983         usleep_range(10000, 10500); /* 10ms delay recommended by spec */
 984 }
 985
 986 static unsigned int ti_sn_get_max_lanes(struct ti_sn65dsi86 *pdata)
 987 {
 988         u8 data;
 989         int ret;
 990
 991         ret = drm_dp_dpcd_readb(&pdata->aux, DP_MAX_LANE_COUNT, &data);
 992         if (ret != 1) {
 993                 DRM_DEV_ERROR(pdata->dev,
 994                               "Can't read lane count (%d); assuming 4\n", ret);
 995                 return 4;
 996         }
 997
 998         return data & DP_LANE_COUNT_MASK;
 999 }
1000
1001 static int ti_sn_link_training(struct ti_sn65dsi86 *pdata, int dp_rate_idx,
1002                                const char **last_err_str)
1003 {
1004         unsigned int val;
1005         int ret;
1006         int i;
1007
1008         /* set dp clk frequency value */
1009         regmap_update_bits(pdata->regmap, SN_DATARATE_CONFIG_REG,
1010                            DP_DATARATE_MASK, DP_DATARATE(dp_rate_idx));
1011
1012         /* enable DP PLL */
1013         regmap_write(pdata->regmap, SN_PLL_ENABLE_REG, 1);
1014
1015         ret = regmap_read_poll_timeout(pdata->regmap, SN_DPPLL_SRC_REG, val,
1016                                        val & DPPLL_SRC_DP_PLL_LOCK, 1000,
1017                                        50 * 1000);
1018         if (ret) {
1019                 *last_err_str = "DP_PLL_LOCK polling failed";
1020                 goto exit;
1021         }
1022
1023         /*
1024          * We'll try to link train several times.  As part of link training
1025          * the bridge chip will write DP_SET_POWER_D0 to DP_SET_POWER.  If
1026          * the panel isn't ready quite it might respond NAK here which means
1027          * we need to try again.
1028          */
1029         for (i = 0; i < SN_LINK_TRAINING_TRIES; i++) {
1030                 /* Semi auto link training mode */
1031                 regmap_write(pdata->regmap, SN_ML_TX_MODE_REG, 0x0A);
1032                 ret = regmap_read_poll_timeout(pdata->regmap, SN_ML_TX_MODE_REG, val,
1033                                                val == ML_TX_MAIN_LINK_OFF ||
1034                                                val == ML_TX_NORMAL_MODE, 1000,
1035                                                500 * 1000);
1036                 if (ret) {
1037                         *last_err_str = "Training complete polling failed";
1038                 } else if (val == ML_TX_MAIN_LINK_OFF) {
1039                         *last_err_str = "Link training failed, link is off";
1040                         ret = -EIO;
1041                         continue;
1042                 }
1043
1044                 break;
1045         }
1046
1047         /* If we saw quite a few retries, add a note about it */
1048         if (!ret && i > SN_LINK_TRAINING_TRIES / 2)
1049                 DRM_DEV_INFO(pdata->dev, "Link training needed %d retries\n", i);
1050
1051 exit:
1052         /* Disable the PLL if we failed */
1053         if (ret)
1054                 regmap_write(pdata->regmap, SN_PLL_ENABLE_REG, 0);
1055
1056         return ret;
1057 }
1058
1059 static void ti_sn_bridge_atomic_enable(struct drm_bridge *bridge,
1060                                        struct drm_bridge_state *old_bridge_state)
1061 {
1062         struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge);
1063         struct drm_connector *connector;
1064         const char *last_err_str = "No supported DP rate";
1065         unsigned int valid_rates;
1066         int dp_rate_idx;
1067         unsigned int val;
1068         int ret = -EINVAL;
1069         int max_dp_lanes;
1070         unsigned int bpp;
1071
1072         connector = drm_atomic_get_new_connector_for_encoder(old_bridge_state->base.state,
1073                                                              bridge->encoder);
1074         if (!connector) {
1075                 dev_err_ratelimited(pdata->dev, "Could not get the connector\n");
1076                 return;
1077         }
1078
1079         max_dp_lanes = ti_sn_get_max_lanes(pdata);
1080         pdata->dp_lanes = min(pdata->dp_lanes, max_dp_lanes);
1081
1082         /* DSI_A lane config */
1083         val = CHA_DSI_LANES(SN_MAX_DP_LANES - pdata->dsi->lanes);
1084         regmap_update_bits(pdata->regmap, SN_DSI_LANES_REG,
1085                            CHA_DSI_LANES_MASK, val);
1086
1087         regmap_write(pdata->regmap, SN_LN_ASSIGN_REG, pdata->ln_assign);
1088         regmap_update_bits(pdata->regmap, SN_ENH_FRAME_REG, LN_POLRS_MASK,
1089                            pdata->ln_polrs << LN_POLRS_OFFSET);
1090
1091         /* set dsi clk frequency value */
1092         ti_sn_bridge_set_dsi_rate(pdata);
1093
1094         /*
1095          * The SN65DSI86 only supports ASSR Display Authentication method and
1096          * this method is enabled for eDP panels. An eDP panel must support this
1097          * authentication method. We need to enable this method in the eDP panel
1098          * at DisplayPort address 0x0010A prior to link training.
1099          *
1100          * As only ASSR is supported by SN65DSI86, for full DisplayPort displays
1101          * we need to disable the scrambler.
1102          */
1103         if (pdata->bridge.type == DRM_MODE_CONNECTOR_eDP) {
1104                 drm_dp_dpcd_writeb(&pdata->aux, DP_EDP_CONFIGURATION_SET,
1105                                    DP_ALTERNATE_SCRAMBLER_RESET_ENABLE);
1106
1107                 regmap_update_bits(pdata->regmap, SN_TRAINING_SETTING_REG,
1108                                    SCRAMBLE_DISABLE, 0);
1109         } else {
1110                 regmap_update_bits(pdata->regmap, SN_TRAINING_SETTING_REG,
1111                                    SCRAMBLE_DISABLE, SCRAMBLE_DISABLE);
1112         }
1113
1114         bpp = ti_sn_bridge_get_bpp(connector);
1115         /* Set the DP output format (18 bpp or 24 bpp) */
1116         val = bpp == 18 ? BPP_18_RGB : 0;
1117         regmap_update_bits(pdata->regmap, SN_DATA_FORMAT_REG, BPP_18_RGB, val);
1118
1119         /* DP lane config */
1120         val = DP_NUM_LANES(min(pdata->dp_lanes, 3));
1121         regmap_update_bits(pdata->regmap, SN_SSC_CONFIG_REG, DP_NUM_LANES_MASK,
1122                            val);
1123
1124         valid_rates = ti_sn_bridge_read_valid_rates(pdata);
1125
1126         /* Train until we run out of rates */
1127         for (dp_rate_idx = ti_sn_bridge_calc_min_dp_rate_idx(pdata, bpp);
1128              dp_rate_idx < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut);
1129              dp_rate_idx++) {
1130                 if (!(valid_rates & BIT(dp_rate_idx)))
1131                         continue;
1132
1133                 ret = ti_sn_link_training(pdata, dp_rate_idx, &last_err_str);
1134                 if (!ret)
1135                         break;
1136         }
1137         if (ret) {
1138                 DRM_DEV_ERROR(pdata->dev, "%s (%d)\n", last_err_str, ret);
1139                 return;
1140         }
1141
1142         /* config video parameters */
1143         ti_sn_bridge_set_video_timings(pdata);
1144
1145         /* enable video stream */
1146         regmap_update_bits(pdata->regmap, SN_ENH_FRAME_REG, VSTREAM_ENABLE,
1147                            VSTREAM_ENABLE);
1148 }
1149
1150 static void ti_sn_bridge_atomic_pre_enable(struct drm_bridge *bridge,
1151                                            struct drm_bridge_state *old_bridge_state)
1152 {
1153         struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge);
1154
1155         pm_runtime_get_sync(pdata->dev);
1156
1157         if (!pdata->refclk)
1158                 ti_sn65dsi86_enable_comms(pdata);
1159
1160         /* td7: min 100 us after enable before DSI data */
1161         usleep_range(100, 110);
1162 }
1163
1164 static void ti_sn_bridge_atomic_post_disable(struct drm_bridge *bridge,
1165                                              struct drm_bridge_state *old_bridge_state)
1166 {
1167         struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge);
1168
1169         /* semi auto link training mode OFF */
1170         regmap_write(pdata->regmap, SN_ML_TX_MODE_REG, 0);
1171         /* Num lanes to 0 as per power sequencing in data sheet */
1172         regmap_update_bits(pdata->regmap, SN_SSC_CONFIG_REG, DP_NUM_LANES_MASK, 0);
1173         /* disable DP PLL */
1174         regmap_write(pdata->regmap, SN_PLL_ENABLE_REG, 0);
1175
1176         if (!pdata->refclk)
1177                 ti_sn65dsi86_disable_comms(pdata);
1178
1179         pm_runtime_put_sync(pdata->dev);
1180 }
1181
1182 static enum drm_connector_status ti_sn_bridge_detect(struct drm_bridge *bridge)
1183 {
1184         struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge);
1185         int val = 0;
1186
1187         pm_runtime_get_sync(pdata->dev);
1188         regmap_read(pdata->regmap, SN_HPD_DISABLE_REG, &val);
1189         pm_runtime_put_autosuspend(pdata->dev);
1190
1191         return val & HPD_DEBOUNCED_STATE ? connector_status_connected
1192                                          : connector_status_disconnected;
1193 }
1194
1195 static struct edid *ti_sn_bridge_get_edid(struct drm_bridge *bridge,
1196                                           struct drm_connector *connector)
1197 {
1198         struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge);
1199
1200         return drm_get_edid(connector, &pdata->aux.ddc);
1201 }
1202
1203 static const struct drm_bridge_funcs ti_sn_bridge_funcs = {
1204         .attach = ti_sn_bridge_attach,
1205         .detach = ti_sn_bridge_detach,
1206         .mode_valid = ti_sn_bridge_mode_valid,
1207         .get_edid = ti_sn_bridge_get_edid,
1208         .detect = ti_sn_bridge_detect,
1209         .atomic_pre_enable = ti_sn_bridge_atomic_pre_enable,
1210         .atomic_enable = ti_sn_bridge_atomic_enable,
1211         .atomic_disable = ti_sn_bridge_atomic_disable,
1212         .atomic_post_disable = ti_sn_bridge_atomic_post_disable,
1213         .atomic_reset = drm_atomic_helper_bridge_reset,
1214         .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state,
1215         .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state,
1216 };
1217
1218 static void ti_sn_bridge_parse_lanes(struct ti_sn65dsi86 *pdata,
1219                                      struct device_node *np)
1220 {
1221         u32 lane_assignments[SN_MAX_DP_LANES] = { 0, 1, 2, 3 };
1222         u32 lane_polarities[SN_MAX_DP_LANES] = { };
1223         struct device_node *endpoint;
1224         u8 ln_assign = 0;
1225         u8 ln_polrs = 0;
1226         int dp_lanes;
1227         int i;
1228
1229         /*
1230          * Read config from the device tree about lane remapping and lane
1231          * polarities.  These are optional and we assume identity map and
1232          * normal polarity if nothing is specified.  It's OK to specify just
1233          * data-lanes but not lane-polarities but not vice versa.
1234          *
1235          * Error checking is light (we just make sure we don't crash or
1236          * buffer overrun) and we assume dts is well formed and specifying
1237          * mappings that the hardware supports.
1238          */
1239         endpoint = of_graph_get_endpoint_by_regs(np, 1, -1);
1240         dp_lanes = drm_of_get_data_lanes_count(endpoint, 1, SN_MAX_DP_LANES);
1241         if (dp_lanes > 0) {
1242                 of_property_read_u32_array(endpoint, "data-lanes",
1243                                            lane_assignments, dp_lanes);
1244                 of_property_read_u32_array(endpoint, "lane-polarities",
1245                                            lane_polarities, dp_lanes);
1246         } else {
1247                 dp_lanes = SN_MAX_DP_LANES;
1248         }
1249         of_node_put(endpoint);
1250
1251         /*
1252          * Convert into register format.  Loop over all lanes even if
1253          * data-lanes had fewer elements so that we nicely initialize
1254          * the LN_ASSIGN register.
1255          */
1256         for (i = SN_MAX_DP_LANES - 1; i >= 0; i--) {
1257                 ln_assign = ln_assign << LN_ASSIGN_WIDTH | lane_assignments[i];
1258                 ln_polrs = ln_polrs << 1 | lane_polarities[i];
1259         }
1260
1261         /* Stash in our struct for when we power on */
1262         pdata->dp_lanes = dp_lanes;
1263         pdata->ln_assign = ln_assign;
1264         pdata->ln_polrs = ln_polrs;
1265 }
1266
1267 static int ti_sn_bridge_parse_dsi_host(struct ti_sn65dsi86 *pdata)
1268 {
1269         struct device_node *np = pdata->dev->of_node;
1270
1271         pdata->host_node = of_graph_get_remote_node(np, 0, 0);
1272
1273         if (!pdata->host_node) {
1274                 DRM_ERROR("remote dsi host node not found\n");
1275                 return -ENODEV;
1276         }
1277
1278         return 0;
1279 }
1280
1281 static int ti_sn_bridge_probe(struct auxiliary_device *adev,
1282                               const struct auxiliary_device_id *id)
1283 {
1284         struct ti_sn65dsi86 *pdata = dev_get_drvdata(adev->dev.parent);
1285         struct device_node *np = pdata->dev->of_node;
1286         int ret;
1287
1288         pdata->next_bridge = devm_drm_of_get_bridge(pdata->dev, np, 1, 0);
1289         if (IS_ERR(pdata->next_bridge))
1290                 return dev_err_probe(pdata->dev, PTR_ERR(pdata->next_bridge),
1291                                      "failed to create panel bridge\n");
1292
1293         ti_sn_bridge_parse_lanes(pdata, np);
1294
1295         ret = ti_sn_bridge_parse_dsi_host(pdata);
1296         if (ret)
1297                 return ret;
1298
1299         pdata->bridge.funcs = &ti_sn_bridge_funcs;
1300         pdata->bridge.of_node = np;
1301         pdata->bridge.type = pdata->next_bridge->type == DRM_MODE_CONNECTOR_DisplayPort
1302                            ? DRM_MODE_CONNECTOR_DisplayPort : DRM_MODE_CONNECTOR_eDP;
1303
1304         if (pdata->bridge.type == DRM_MODE_CONNECTOR_DisplayPort)
1305                 pdata->bridge.ops = DRM_BRIDGE_OP_EDID | DRM_BRIDGE_OP_DETECT;
1306
1307         drm_bridge_add(&pdata->bridge);
1308
1309         ret = ti_sn_attach_host(pdata);
1310         if (ret) {
1311                 dev_err_probe(pdata->dev, ret, "failed to attach dsi host\n");
1312                 goto err_remove_bridge;
1313         }
1314
1315         return 0;
1316
1317 err_remove_bridge:
1318         drm_bridge_remove(&pdata->bridge);
1319         return ret;
1320 }
1321
1322 static void ti_sn_bridge_remove(struct auxiliary_device *adev)
1323 {
1324         struct ti_sn65dsi86 *pdata = dev_get_drvdata(adev->dev.parent);
1325
1326         if (!pdata)
1327                 return;
1328
1329         drm_bridge_remove(&pdata->bridge);
1330
1331         of_node_put(pdata->host_node);
1332 }
1333
1334 static const struct auxiliary_device_id ti_sn_bridge_id_table[] = {
1335         { .name = "ti_sn65dsi86.bridge", },
1336         {},
1337 };
1338
1339 static struct auxiliary_driver ti_sn_bridge_driver = {
1340         .name = "bridge",
1341         .probe = ti_sn_bridge_probe,
1342         .remove = ti_sn_bridge_remove,
1343         .id_table = ti_sn_bridge_id_table,
1344 };
1345
1346 /* -----------------------------------------------------------------------------
1347  * PWM Controller
1348  */
1349 #if defined(CONFIG_PWM)
1350 static int ti_sn_pwm_pin_request(struct ti_sn65dsi86 *pdata)
1351 {
1352         return atomic_xchg(&pdata->pwm_pin_busy, 1) ? -EBUSY : 0;
1353 }
1354
1355 static void ti_sn_pwm_pin_release(struct ti_sn65dsi86 *pdata)
1356 {
1357         atomic_set(&pdata->pwm_pin_busy, 0);
1358 }
1359
1360 static struct ti_sn65dsi86 *pwm_chip_to_ti_sn_bridge(struct pwm_chip *chip)
1361 {
1362         return container_of(chip, struct ti_sn65dsi86, pchip);
1363 }
1364
1365 static int ti_sn_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
1366 {
1367         struct ti_sn65dsi86 *pdata = pwm_chip_to_ti_sn_bridge(chip);
1368
1369         return ti_sn_pwm_pin_request(pdata);
1370 }
1371
1372 static void ti_sn_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
1373 {
1374         struct ti_sn65dsi86 *pdata = pwm_chip_to_ti_sn_bridge(chip);
1375
1376         ti_sn_pwm_pin_release(pdata);
1377 }
1378
1379 /*
1380  * Limitations:
1381  * - The PWM signal is not driven when the chip is powered down, or in its
1382  *   reset state and the driver does not implement the "suspend state"
1383  *   described in the documentation. In order to save power, state->enabled is
1384  *   interpreted as denoting if the signal is expected to be valid, and is used
1385  *   to determine if the chip needs to be kept powered.
1386  * - Changing both period and duty_cycle is not done atomically, neither is the
1387  *   multi-byte register updates, so the output might briefly be undefined
1388  *   during update.
1389  */
1390 static int ti_sn_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
1391                            const struct pwm_state *state)
1392 {
1393         struct ti_sn65dsi86 *pdata = pwm_chip_to_ti_sn_bridge(chip);
1394         unsigned int pwm_en_inv;
1395         unsigned int backlight;
1396         unsigned int pre_div;
1397         unsigned int scale;
1398         u64 period_max;
1399         u64 period;
1400         int ret;
1401
1402         if (!pdata->pwm_enabled) {
1403                 ret = pm_runtime_get_sync(pdata->dev);
1404                 if (ret < 0) {
1405                         pm_runtime_put_sync(pdata->dev);
1406                         return ret;
1407                 }
1408         }
1409
1410         if (state->enabled) {
1411                 if (!pdata->pwm_enabled) {
1412                         /*
1413                          * The chip might have been powered down while we
1414                          * didn't hold a PM runtime reference, so mux in the
1415                          * PWM function on the GPIO pin again.
1416                          */
1417                         ret = regmap_update_bits(pdata->regmap, SN_GPIO_CTRL_REG,
1418                                                  SN_GPIO_MUX_MASK << (2 * SN_PWM_GPIO_IDX),
1419                                                  SN_GPIO_MUX_SPECIAL << (2 * SN_PWM_GPIO_IDX));
1420                         if (ret) {
1421                                 dev_err(pdata->dev, "failed to mux in PWM function\n");
1422                                 goto out;
1423                         }
1424                 }
1425
1426                 /*
1427                  * Per the datasheet the PWM frequency is given by:
1428                  *
1429                  *                          REFCLK_FREQ
1430                  *   PWM_FREQ = -----------------------------------
1431                  *               PWM_PRE_DIV * BACKLIGHT_SCALE + 1
1432                  *
1433                  * However, after careful review the author is convinced that
1434                  * the documentation has lost some parenthesis around
1435                  * "BACKLIGHT_SCALE + 1".
1436                  *
1437                  * With the period T_pwm = 1/PWM_FREQ this can be written:
1438                  *
1439                  *   T_pwm * REFCLK_FREQ = PWM_PRE_DIV * (BACKLIGHT_SCALE + 1)
1440                  *
1441                  * In order to keep BACKLIGHT_SCALE within its 16 bits,
1442                  * PWM_PRE_DIV must be:
1443                  *
1444                  *                     T_pwm * REFCLK_FREQ
1445                  *   PWM_PRE_DIV >= -------------------------
1446                  *                   BACKLIGHT_SCALE_MAX + 1
1447                  *
1448                  * To simplify the search and to favour higher resolution of
1449                  * the duty cycle over accuracy of the period, the lowest
1450                  * possible PWM_PRE_DIV is used. Finally the scale is
1451                  * calculated as:
1452                  *
1453                  *                      T_pwm * REFCLK_FREQ
1454                  *   BACKLIGHT_SCALE = ---------------------- - 1
1455                  *                          PWM_PRE_DIV
1456                  *
1457                  * Here T_pwm is represented in seconds, so appropriate scaling
1458                  * to nanoseconds is necessary.
1459                  */
1460
1461                 /* Minimum T_pwm is 1 / REFCLK_FREQ */
1462                 if (state->period <= NSEC_PER_SEC / pdata->pwm_refclk_freq) {
1463                         ret = -EINVAL;
1464                         goto out;
1465                 }
1466
1467                 /*
1468                  * Maximum T_pwm is 255 * (65535 + 1) / REFCLK_FREQ
1469                  * Limit period to this to avoid overflows
1470                  */
1471                 period_max = div_u64((u64)NSEC_PER_SEC * 255 * (65535 + 1),
1472                                      pdata->pwm_refclk_freq);
1473                 period = min(state->period, period_max);
1474
1475                 pre_div = DIV64_U64_ROUND_UP(period * pdata->pwm_refclk_freq,
1476                                              (u64)NSEC_PER_SEC * (BACKLIGHT_SCALE_MAX + 1));
1477                 scale = div64_u64(period * pdata->pwm_refclk_freq, (u64)NSEC_PER_SEC * pre_div) - 1;
1478
1479                 /*
1480                  * The documentation has the duty ratio given as:
1481                  *
1482                  *     duty          BACKLIGHT
1483                  *   ------- = ---------------------
1484                  *    period    BACKLIGHT_SCALE + 1
1485                  *
1486                  * Solve for BACKLIGHT, substituting BACKLIGHT_SCALE according
1487                  * to definition above and adjusting for nanosecond
1488                  * representation of duty cycle gives us:
1489                  */
1490                 backlight = div64_u64(state->duty_cycle * pdata->pwm_refclk_freq,
1491                                       (u64)NSEC_PER_SEC * pre_div);
1492                 if (backlight > scale)
1493                         backlight = scale;
1494
1495                 ret = regmap_write(pdata->regmap, SN_PWM_PRE_DIV_REG, pre_div);
1496                 if (ret) {
1497                         dev_err(pdata->dev, "failed to update PWM_PRE_DIV\n");
1498                         goto out;
1499                 }
1500
1501                 ti_sn65dsi86_write_u16(pdata, SN_BACKLIGHT_SCALE_REG, scale);
1502                 ti_sn65dsi86_write_u16(pdata, SN_BACKLIGHT_REG, backlight);
1503         }
1504
1505         pwm_en_inv = FIELD_PREP(SN_PWM_EN_MASK, state->enabled) |
1506                      FIELD_PREP(SN_PWM_INV_MASK, state->polarity == PWM_POLARITY_INVERSED);
1507         ret = regmap_write(pdata->regmap, SN_PWM_EN_INV_REG, pwm_en_inv);
1508         if (ret) {
1509                 dev_err(pdata->dev, "failed to update PWM_EN/PWM_INV\n");
1510                 goto out;
1511         }
1512
1513         pdata->pwm_enabled = state->enabled;
1514 out:
1515
1516         if (!pdata->pwm_enabled)
1517                 pm_runtime_put_sync(pdata->dev);
1518
1519         return ret;
1520 }
1521
1522 static int ti_sn_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm,
1523                                struct pwm_state *state)
1524 {
1525         struct ti_sn65dsi86 *pdata = pwm_chip_to_ti_sn_bridge(chip);
1526         unsigned int pwm_en_inv;
1527         unsigned int pre_div;
1528         u16 backlight;
1529         u16 scale;
1530         int ret;
1531
1532         ret = regmap_read(pdata->regmap, SN_PWM_EN_INV_REG, &pwm_en_inv);
1533         if (ret)
1534                 return ret;
1535
1536         ret = ti_sn65dsi86_read_u16(pdata, SN_BACKLIGHT_SCALE_REG, &scale);
1537         if (ret)
1538                 return ret;
1539
1540         ret = ti_sn65dsi86_read_u16(pdata, SN_BACKLIGHT_REG, &backlight);
1541         if (ret)
1542                 return ret;
1543
1544         ret = regmap_read(pdata->regmap, SN_PWM_PRE_DIV_REG, &pre_div);
1545         if (ret)
1546                 return ret;
1547
1548         state->enabled = FIELD_GET(SN_PWM_EN_MASK, pwm_en_inv);
1549         if (FIELD_GET(SN_PWM_INV_MASK, pwm_en_inv))
1550                 state->polarity = PWM_POLARITY_INVERSED;
1551         else
1552                 state->polarity = PWM_POLARITY_NORMAL;
1553
1554         state->period = DIV_ROUND_UP_ULL((u64)NSEC_PER_SEC * pre_div * (scale + 1),
1555                                          pdata->pwm_refclk_freq);
1556         state->duty_cycle = DIV_ROUND_UP_ULL((u64)NSEC_PER_SEC * pre_div * backlight,
1557                                              pdata->pwm_refclk_freq);
1558
1559         if (state->duty_cycle > state->period)
1560                 state->duty_cycle = state->period;
1561
1562         return 0;
1563 }
1564
1565 static const struct pwm_ops ti_sn_pwm_ops = {
1566         .request = ti_sn_pwm_request,
1567         .free = ti_sn_pwm_free,
1568         .apply = ti_sn_pwm_apply,
1569         .get_state = ti_sn_pwm_get_state,
1570         .owner = THIS_MODULE,
1571 };
1572
1573 static int ti_sn_pwm_probe(struct auxiliary_device *adev,
1574                            const struct auxiliary_device_id *id)
1575 {
1576         struct ti_sn65dsi86 *pdata = dev_get_drvdata(adev->dev.parent);
1577
1578         pdata->pchip.dev = pdata->dev;
1579         pdata->pchip.ops = &ti_sn_pwm_ops;
1580         pdata->pchip.npwm = 1;
1581         pdata->pchip.of_xlate = of_pwm_single_xlate;
1582         pdata->pchip.of_pwm_n_cells = 1;
1583
1584         return pwmchip_add(&pdata->pchip);
1585 }
1586
1587 static void ti_sn_pwm_remove(struct auxiliary_device *adev)
1588 {
1589         struct ti_sn65dsi86 *pdata = dev_get_drvdata(adev->dev.parent);
1590
1591         pwmchip_remove(&pdata->pchip);
1592
1593         if (pdata->pwm_enabled)
1594                 pm_runtime_put_sync(pdata->dev);
1595 }
1596
1597 static const struct auxiliary_device_id ti_sn_pwm_id_table[] = {
1598         { .name = "ti_sn65dsi86.pwm", },
1599         {},
1600 };
1601
1602 static struct auxiliary_driver ti_sn_pwm_driver = {
1603         .name = "pwm",
1604         .probe = ti_sn_pwm_probe,
1605         .remove = ti_sn_pwm_remove,
1606         .id_table = ti_sn_pwm_id_table,
1607 };
1608
1609 static int __init ti_sn_pwm_register(void)
1610 {
1611         return auxiliary_driver_register(&ti_sn_pwm_driver);
1612 }
1613
1614 static void ti_sn_pwm_unregister(void)
1615 {
1616         auxiliary_driver_unregister(&ti_sn_pwm_driver);
1617 }
1618
1619 #else
1620 static inline int ti_sn_pwm_pin_request(struct ti_sn65dsi86 *pdata) { return 0; }
1621 static inline void ti_sn_pwm_pin_release(struct ti_sn65dsi86 *pdata) {}
1622
1623 static inline int ti_sn_pwm_register(void) { return 0; }
1624 static inline void ti_sn_pwm_unregister(void) {}
1625 #endif
1626
1627 /* -----------------------------------------------------------------------------
1628  * GPIO Controller
1629  */
1630 #if defined(CONFIG_OF_GPIO)
1631
1632 static int tn_sn_bridge_of_xlate(struct gpio_chip *chip,
1633                                  const struct of_phandle_args *gpiospec,
1634                                  u32 *flags)
1635 {
1636         if (WARN_ON(gpiospec->args_count < chip->of_gpio_n_cells))
1637                 return -EINVAL;
1638
1639         if (gpiospec->args[0] > chip->ngpio || gpiospec->args[0] < 1)
1640                 return -EINVAL;
1641
1642         if (flags)
1643                 *flags = gpiospec->args[1];
1644
1645         return gpiospec->args[0] - SN_GPIO_PHYSICAL_OFFSET;
1646 }
1647
1648 static int ti_sn_bridge_gpio_get_direction(struct gpio_chip *chip,
1649                                            unsigned int offset)
1650 {
1651         struct ti_sn65dsi86 *pdata = gpiochip_get_data(chip);
1652
1653         /*
1654          * We already have to keep track of the direction because we use
1655          * that to figure out whether we've powered the device.  We can
1656          * just return that rather than (maybe) powering up the device
1657          * to ask its direction.
1658          */
1659         return test_bit(offset, pdata->gchip_output) ?
1660                 GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN;
1661 }
1662
1663 static int ti_sn_bridge_gpio_get(struct gpio_chip *chip, unsigned int offset)
1664 {
1665         struct ti_sn65dsi86 *pdata = gpiochip_get_data(chip);
1666         unsigned int val;
1667         int ret;
1668
1669         /*
1670          * When the pin is an input we don't forcibly keep the bridge
1671          * powered--we just power it on to read the pin.  NOTE: part of
1672          * the reason this works is that the bridge defaults (when
1673          * powered back on) to all 4 GPIOs being configured as GPIO input.
1674          * Also note that if something else is keeping the chip powered the
1675          * pm_runtime functions are lightweight increments of a refcount.
1676          */
1677         pm_runtime_get_sync(pdata->dev);
1678         ret = regmap_read(pdata->regmap, SN_GPIO_IO_REG, &val);
1679         pm_runtime_put_autosuspend(pdata->dev);
1680
1681         if (ret)
1682                 return ret;
1683
1684         return !!(val & BIT(SN_GPIO_INPUT_SHIFT + offset));
1685 }
1686
1687 static void ti_sn_bridge_gpio_set(struct gpio_chip *chip, unsigned int offset,
1688                                   int val)
1689 {
1690         struct ti_sn65dsi86 *pdata = gpiochip_get_data(chip);
1691         int ret;
1692
1693         if (!test_bit(offset, pdata->gchip_output)) {
1694                 dev_err(pdata->dev, "Ignoring GPIO set while input\n");
1695                 return;
1696         }
1697
1698         val &= 1;
1699         ret = regmap_update_bits(pdata->regmap, SN_GPIO_IO_REG,
1700                                  BIT(SN_GPIO_OUTPUT_SHIFT + offset),
1701                                  val << (SN_GPIO_OUTPUT_SHIFT + offset));
1702         if (ret)
1703                 dev_warn(pdata->dev,
1704                          "Failed to set bridge GPIO %u: %d\n", offset, ret);
1705 }
1706
1707 static int ti_sn_bridge_gpio_direction_input(struct gpio_chip *chip,
1708                                              unsigned int offset)
1709 {
1710         struct ti_sn65dsi86 *pdata = gpiochip_get_data(chip);
1711         int shift = offset * 2;
1712         int ret;
1713
1714         if (!test_and_clear_bit(offset, pdata->gchip_output))
1715                 return 0;
1716
1717         ret = regmap_update_bits(pdata->regmap, SN_GPIO_CTRL_REG,
1718                                  SN_GPIO_MUX_MASK << shift,
1719                                  SN_GPIO_MUX_INPUT << shift);
1720         if (ret) {
1721                 set_bit(offset, pdata->gchip_output);
1722                 return ret;
1723         }
1724
1725         /*
1726          * NOTE: if nobody else is powering the device this may fully power
1727          * it off and when it comes back it will have lost all state, but
1728          * that's OK because the default is input and we're now an input.
1729          */
1730         pm_runtime_put_autosuspend(pdata->dev);
1731
1732         return 0;
1733 }
1734
1735 static int ti_sn_bridge_gpio_direction_output(struct gpio_chip *chip,
1736                                               unsigned int offset, int val)
1737 {
1738         struct ti_sn65dsi86 *pdata = gpiochip_get_data(chip);
1739         int shift = offset * 2;
1740         int ret;
1741
1742         if (test_and_set_bit(offset, pdata->gchip_output))
1743                 return 0;
1744
1745         pm_runtime_get_sync(pdata->dev);
1746
1747         /* Set value first to avoid glitching */
1748         ti_sn_bridge_gpio_set(chip, offset, val);
1749
1750         /* Set direction */
1751         ret = regmap_update_bits(pdata->regmap, SN_GPIO_CTRL_REG,
1752                                  SN_GPIO_MUX_MASK << shift,
1753                                  SN_GPIO_MUX_OUTPUT << shift);
1754         if (ret) {
1755                 clear_bit(offset, pdata->gchip_output);
1756                 pm_runtime_put_autosuspend(pdata->dev);
1757         }
1758
1759         return ret;
1760 }
1761
1762 static int ti_sn_bridge_gpio_request(struct gpio_chip *chip, unsigned int offset)
1763 {
1764         struct ti_sn65dsi86 *pdata = gpiochip_get_data(chip);
1765
1766         if (offset == SN_PWM_GPIO_IDX)
1767                 return ti_sn_pwm_pin_request(pdata);
1768
1769         return 0;
1770 }
1771
1772 static void ti_sn_bridge_gpio_free(struct gpio_chip *chip, unsigned int offset)
1773 {
1774         struct ti_sn65dsi86 *pdata = gpiochip_get_data(chip);
1775
1776         /* We won't keep pm_runtime if we're input, so switch there on free */
1777         ti_sn_bridge_gpio_direction_input(chip, offset);
1778
1779         if (offset == SN_PWM_GPIO_IDX)
1780                 ti_sn_pwm_pin_release(pdata);
1781 }
1782
1783 static const char * const ti_sn_bridge_gpio_names[SN_NUM_GPIOS] = {
1784         "GPIO1", "GPIO2", "GPIO3", "GPIO4"
1785 };
1786
1787 static int ti_sn_gpio_probe(struct auxiliary_device *adev,
1788                             const struct auxiliary_device_id *id)
1789 {
1790         struct ti_sn65dsi86 *pdata = dev_get_drvdata(adev->dev.parent);
1791         int ret;
1792
1793         /* Only init if someone is going to use us as a GPIO controller */
1794         if (!of_property_read_bool(pdata->dev->of_node, "gpio-controller"))
1795                 return 0;
1796
1797         pdata->gchip.label = dev_name(pdata->dev);
1798         pdata->gchip.parent = pdata->dev;
1799         pdata->gchip.owner = THIS_MODULE;
1800         pdata->gchip.of_xlate = tn_sn_bridge_of_xlate;
1801         pdata->gchip.of_gpio_n_cells = 2;
1802         pdata->gchip.request = ti_sn_bridge_gpio_request;
1803         pdata->gchip.free = ti_sn_bridge_gpio_free;
1804         pdata->gchip.get_direction = ti_sn_bridge_gpio_get_direction;
1805         pdata->gchip.direction_input = ti_sn_bridge_gpio_direction_input;
1806         pdata->gchip.direction_output = ti_sn_bridge_gpio_direction_output;
1807         pdata->gchip.get = ti_sn_bridge_gpio_get;
1808         pdata->gchip.set = ti_sn_bridge_gpio_set;
1809         pdata->gchip.can_sleep = true;
1810         pdata->gchip.names = ti_sn_bridge_gpio_names;
1811         pdata->gchip.ngpio = SN_NUM_GPIOS;
1812         pdata->gchip.base = -1;
1813         ret = devm_gpiochip_add_data(&adev->dev, &pdata->gchip, pdata);
1814         if (ret)
1815                 dev_err(pdata->dev, "can't add gpio chip\n");
1816
1817         return ret;
1818 }
1819
1820 static const struct auxiliary_device_id ti_sn_gpio_id_table[] = {
1821         { .name = "ti_sn65dsi86.gpio", },
1822         {},
1823 };
1824
1825 MODULE_DEVICE_TABLE(auxiliary, ti_sn_gpio_id_table);
1826
1827 static struct auxiliary_driver ti_sn_gpio_driver = {
1828         .name = "gpio",
1829         .probe = ti_sn_gpio_probe,
1830         .id_table = ti_sn_gpio_id_table,
1831 };
1832
1833 static int __init ti_sn_gpio_register(void)
1834 {
1835         return auxiliary_driver_register(&ti_sn_gpio_driver);
1836 }
1837
1838 static void ti_sn_gpio_unregister(void)
1839 {
1840         auxiliary_driver_unregister(&ti_sn_gpio_driver);
1841 }
1842
1843 #else
1844
1845 static inline int ti_sn_gpio_register(void) { return 0; }
1846 static inline void ti_sn_gpio_unregister(void) {}
1847
1848 #endif
1849
1850 /* -----------------------------------------------------------------------------
1851  * Probe & Remove
1852  */
1853
1854 static void ti_sn65dsi86_runtime_disable(void *data)
1855 {
1856         pm_runtime_dont_use_autosuspend(data);
1857         pm_runtime_disable(data);
1858 }
1859
1860 static int ti_sn65dsi86_parse_regulators(struct ti_sn65dsi86 *pdata)
1861 {
1862         unsigned int i;
1863         const char * const ti_sn_bridge_supply_names[] = {
1864                 "vcca", "vcc", "vccio", "vpll",
1865         };
1866
1867         for (i = 0; i < SN_REGULATOR_SUPPLY_NUM; i++)
1868                 pdata->supplies[i].supply = ti_sn_bridge_supply_names[i];
1869
1870         return devm_regulator_bulk_get(pdata->dev, SN_REGULATOR_SUPPLY_NUM,
1871                                        pdata->supplies);
1872 }
1873
1874 static int ti_sn65dsi86_probe(struct i2c_client *client)
1875 {
1876         struct device *dev = &client->dev;
1877         struct ti_sn65dsi86 *pdata;
1878         int ret;
1879
1880         if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
1881                 DRM_ERROR("device doesn't support I2C\n");
1882                 return -ENODEV;
1883         }
1884
1885         pdata = devm_kzalloc(dev, sizeof(struct ti_sn65dsi86), GFP_KERNEL);
1886         if (!pdata)
1887                 return -ENOMEM;
1888         dev_set_drvdata(dev, pdata);
1889         pdata->dev = dev;
1890
1891         mutex_init(&pdata->comms_mutex);
1892
1893         pdata->regmap = devm_regmap_init_i2c(client,
1894                                              &ti_sn65dsi86_regmap_config);
1895         if (IS_ERR(pdata->regmap))
1896                 return dev_err_probe(dev, PTR_ERR(pdata->regmap),
1897                                      "regmap i2c init failed\n");
1898
1899         pdata->enable_gpio = devm_gpiod_get_optional(dev, "enable",
1900                                                      GPIOD_OUT_LOW);
1901         if (IS_ERR(pdata->enable_gpio))
1902                 return dev_err_probe(dev, PTR_ERR(pdata->enable_gpio),
1903                                      "failed to get enable gpio from DT\n");
1904
1905         ret = ti_sn65dsi86_parse_regulators(pdata);
1906         if (ret)
1907                 return dev_err_probe(dev, ret, "failed to parse regulators\n");
1908
1909         pdata->refclk = devm_clk_get_optional(dev, "refclk");
1910         if (IS_ERR(pdata->refclk))
1911                 return dev_err_probe(dev, PTR_ERR(pdata->refclk),
1912                                      "failed to get reference clock\n");
1913
1914         pm_runtime_enable(dev);
1915         pm_runtime_set_autosuspend_delay(pdata->dev, 500);
1916         pm_runtime_use_autosuspend(pdata->dev);
1917         ret = devm_add_action_or_reset(dev, ti_sn65dsi86_runtime_disable, dev);
1918         if (ret)
1919                 return ret;
1920
1921         ti_sn65dsi86_debugfs_init(pdata);
1922
1923         /*
1924          * Break ourselves up into a collection of aux devices. The only real
1925          * motiviation here is to solve the chicken-and-egg problem of probe
1926          * ordering. The bridge wants the panel to be there when it probes.
1927          * The panel wants its HPD GPIO (provided by sn65dsi86 on some boards)
1928          * when it probes. The panel and maybe backlight might want the DDC
1929          * bus or the pwm_chip. Having sub-devices allows the some sub devices
1930          * to finish probing even if others return -EPROBE_DEFER and gets us
1931          * around the problems.
1932          */
1933
1934         if (IS_ENABLED(CONFIG_OF_GPIO)) {
1935                 ret = ti_sn65dsi86_add_aux_device(pdata, &pdata->gpio_aux, "gpio");
1936                 if (ret)
1937                         return ret;
1938         }
1939
1940         if (IS_ENABLED(CONFIG_PWM)) {
1941                 ret = ti_sn65dsi86_add_aux_device(pdata, &pdata->pwm_aux, "pwm");
1942                 if (ret)
1943                         return ret;
1944         }
1945
1946         /*
1947          * NOTE: At the end of the AUX channel probe we'll add the aux device
1948          * for the bridge. This is because the bridge can't be used until the
1949          * AUX channel is there and this is a very simple solution to the
1950          * dependency problem.
1951          */
1952         return ti_sn65dsi86_add_aux_device(pdata, &pdata->aux_aux, "aux");
1953 }
1954
1955 static struct i2c_device_id ti_sn65dsi86_id[] = {
1956         { "ti,sn65dsi86", 0},
1957         {},
1958 };
1959 MODULE_DEVICE_TABLE(i2c, ti_sn65dsi86_id);
1960
1961 static const struct of_device_id ti_sn65dsi86_match_table[] = {
1962         {.compatible = "ti,sn65dsi86"},
1963         {},
1964 };
1965 MODULE_DEVICE_TABLE(of, ti_sn65dsi86_match_table);
1966
1967 static struct i2c_driver ti_sn65dsi86_driver = {
1968         .driver = {
1969                 .name = "ti_sn65dsi86",
1970                 .of_match_table = ti_sn65dsi86_match_table,
1971                 .pm = &ti_sn65dsi86_pm_ops,
1972         },
1973         .probe = ti_sn65dsi86_probe,
1974         .id_table = ti_sn65dsi86_id,
1975 };
1976
1977 static int __init ti_sn65dsi86_init(void)
1978 {
1979         int ret;
1980
1981         ret = i2c_add_driver(&ti_sn65dsi86_driver);
1982         if (ret)
1983                 return ret;
1984
1985         ret = ti_sn_gpio_register();
1986         if (ret)
1987                 goto err_main_was_registered;
1988
1989         ret = ti_sn_pwm_register();
1990         if (ret)
1991                 goto err_gpio_was_registered;
1992
1993         ret = auxiliary_driver_register(&ti_sn_aux_driver);
1994         if (ret)
1995                 goto err_pwm_was_registered;
1996
1997         ret = auxiliary_driver_register(&ti_sn_bridge_driver);
1998         if (ret)
1999                 goto err_aux_was_registered;
2000
2001         return 0;
2002
2003 err_aux_was_registered:
2004         auxiliary_driver_unregister(&ti_sn_aux_driver);
2005 err_pwm_was_registered:
2006         ti_sn_pwm_unregister();
2007 err_gpio_was_registered:
2008         ti_sn_gpio_unregister();
2009 err_main_was_registered:
2010         i2c_del_driver(&ti_sn65dsi86_driver);
2011
2012         return ret;
2013 }
2014 module_init(ti_sn65dsi86_init);
2015
2016 static void __exit ti_sn65dsi86_exit(void)
2017 {
2018         auxiliary_driver_unregister(&ti_sn_bridge_driver);
2019         auxiliary_driver_unregister(&ti_sn_aux_driver);
2020         ti_sn_pwm_unregister();
2021         ti_sn_gpio_unregister();
2022         i2c_del_driver(&ti_sn65dsi86_driver);
2023 }
2024 module_exit(ti_sn65dsi86_exit);
2025
2026 MODULE_AUTHOR("Sandeep Panda <[email protected]>");
2027 MODULE_DESCRIPTION("sn65dsi86 DSI to eDP bridge driver");
2028 MODULE_LICENSE("GPL v2");