drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_crc.c

   1 /*
   2  * Copyright 2015 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: AMD
  23  *
  24  */
  25
  26 #include <drm/drm_crtc.h>
  27 #include <drm/drm_vblank.h>
  28
  29 #include "amdgpu.h"
  30 #include "amdgpu_dm.h"
  31 #include "dc.h"
  32 #include "amdgpu_securedisplay.h"
  33
  34 static const char *const pipe_crc_sources[] = {
  35         "none",
  36         "crtc",
  37         "crtc dither",
  38         "dprx",
  39         "dprx dither",
  40         "auto",
  41 };
  42
  43 static enum amdgpu_dm_pipe_crc_source dm_parse_crc_source(const char *source)
  44 {
  45         if (!source || !strcmp(source, "none"))
  46                 return AMDGPU_DM_PIPE_CRC_SOURCE_NONE;
  47         if (!strcmp(source, "auto") || !strcmp(source, "crtc"))
  48                 return AMDGPU_DM_PIPE_CRC_SOURCE_CRTC;
  49         if (!strcmp(source, "dprx"))
  50                 return AMDGPU_DM_PIPE_CRC_SOURCE_DPRX;
  51         if (!strcmp(source, "crtc dither"))
  52                 return AMDGPU_DM_PIPE_CRC_SOURCE_CRTC_DITHER;
  53         if (!strcmp(source, "dprx dither"))
  54                 return AMDGPU_DM_PIPE_CRC_SOURCE_DPRX_DITHER;
  55
  56         return AMDGPU_DM_PIPE_CRC_SOURCE_INVALID;
  57 }
  58
  59 static bool dm_is_crc_source_crtc(enum amdgpu_dm_pipe_crc_source src)
  60 {
  61         return (src == AMDGPU_DM_PIPE_CRC_SOURCE_CRTC) ||
  62                (src == AMDGPU_DM_PIPE_CRC_SOURCE_CRTC_DITHER);
  63 }
  64
  65 static bool dm_is_crc_source_dprx(enum amdgpu_dm_pipe_crc_source src)
  66 {
  67         return (src == AMDGPU_DM_PIPE_CRC_SOURCE_DPRX) ||
  68                (src == AMDGPU_DM_PIPE_CRC_SOURCE_DPRX_DITHER);
  69 }
  70
  71 static bool dm_need_crc_dither(enum amdgpu_dm_pipe_crc_source src)
  72 {
  73         return (src == AMDGPU_DM_PIPE_CRC_SOURCE_CRTC_DITHER) ||
  74                (src == AMDGPU_DM_PIPE_CRC_SOURCE_DPRX_DITHER) ||
  75                (src == AMDGPU_DM_PIPE_CRC_SOURCE_NONE);
  76 }
  77
  78 const char *const *amdgpu_dm_crtc_get_crc_sources(struct drm_crtc *crtc,
  79                                                   size_t *count)
  80 {
  81         *count = ARRAY_SIZE(pipe_crc_sources);
  82         return pipe_crc_sources;
  83 }
  84
  85 #ifdef CONFIG_DRM_AMD_SECURE_DISPLAY
  86 static void amdgpu_dm_set_crc_window_default(struct drm_crtc *crtc, struct dc_stream_state *stream)
  87 {
  88         struct drm_device *drm_dev = crtc->dev;
  89         struct amdgpu_display_manager *dm = &drm_to_adev(drm_dev)->dm;
  90         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
  91         bool was_activated;
  92
  93         spin_lock_irq(&drm_dev->event_lock);
  94         was_activated = acrtc->dm_irq_params.window_param.activated;
  95         acrtc->dm_irq_params.window_param.x_start = 0;
  96         acrtc->dm_irq_params.window_param.y_start = 0;
  97         acrtc->dm_irq_params.window_param.x_end = 0;
  98         acrtc->dm_irq_params.window_param.y_end = 0;
  99         acrtc->dm_irq_params.window_param.activated = false;
 100         acrtc->dm_irq_params.window_param.update_win = false;
 101         acrtc->dm_irq_params.window_param.skip_frame_cnt = 0;
 102         spin_unlock_irq(&drm_dev->event_lock);
 103
 104         /* Disable secure_display if it was enabled */
 105         if (was_activated) {
 106                 /* stop ROI update on this crtc */
 107                 flush_work(&dm->secure_display_ctxs[crtc->index].notify_ta_work);
 108                 flush_work(&dm->secure_display_ctxs[crtc->index].forward_roi_work);
 109                 dc_stream_forward_crc_window(stream, NULL, true);
 110         }
 111 }
 112
 113 static void amdgpu_dm_crtc_notify_ta_to_read(struct work_struct *work)
 114 {
 115         struct secure_display_context *secure_display_ctx;
 116         struct psp_context *psp;
 117         struct ta_securedisplay_cmd *securedisplay_cmd;
 118         struct drm_crtc *crtc;
 119         struct dc_stream_state *stream;
 120         uint8_t phy_inst;
 121         int ret;
 122
 123         secure_display_ctx = container_of(work, struct secure_display_context, notify_ta_work);
 124         crtc = secure_display_ctx->crtc;
 125
 126         if (!crtc) {
 127                 return;
 128         }
 129
 130         psp = &drm_to_adev(crtc->dev)->psp;
 131
 132         if (!psp->securedisplay_context.context.initialized) {
 133                 DRM_DEBUG_DRIVER("Secure Display fails to notify PSP TA\n");
 134                 return;
 135         }
 136
 137         stream = to_amdgpu_crtc(crtc)->dm_irq_params.stream;
 138         phy_inst = stream->link->link_enc_hw_inst;
 139
 140         /* need lock for multiple crtcs to use the command buffer */
 141         mutex_lock(&psp->securedisplay_context.mutex);
 142
 143         psp_prep_securedisplay_cmd_buf(psp, &securedisplay_cmd,
 144                                                 TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC);
 145
 146         securedisplay_cmd->securedisplay_in_message.send_roi_crc.phy_id = phy_inst;
 147
 148         /* PSP TA is expected to finish data transmission over I2C within current frame,
 149          * even there are up to 4 crtcs request to send in this frame.
 150          */
 151         ret = psp_securedisplay_invoke(psp, TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC);
 152
 153         if (!ret) {
 154                 if (securedisplay_cmd->status != TA_SECUREDISPLAY_STATUS__SUCCESS) {
 155                         psp_securedisplay_parse_resp_status(psp, securedisplay_cmd->status);
 156                 }
 157         }
 158
 159         mutex_unlock(&psp->securedisplay_context.mutex);
 160 }
 161
 162 static void
 163 amdgpu_dm_forward_crc_window(struct work_struct *work)
 164 {
 165         struct secure_display_context *secure_display_ctx;
 166         struct amdgpu_display_manager *dm;
 167         struct drm_crtc *crtc;
 168         struct dc_stream_state *stream;
 169
 170         secure_display_ctx = container_of(work, struct secure_display_context, forward_roi_work);
 171         crtc = secure_display_ctx->crtc;
 172
 173         if (!crtc)
 174                 return;
 175
 176         dm = &drm_to_adev(crtc->dev)->dm;
 177         stream = to_amdgpu_crtc(crtc)->dm_irq_params.stream;
 178
 179         mutex_lock(&dm->dc_lock);
 180         dc_stream_forward_crc_window(stream, &secure_display_ctx->rect, false);
 181         mutex_unlock(&dm->dc_lock);
 182 }
 183
 184 bool amdgpu_dm_crc_window_is_activated(struct drm_crtc *crtc)
 185 {
 186         struct drm_device *drm_dev = crtc->dev;
 187         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
 188         bool ret = false;
 189
 190         spin_lock_irq(&drm_dev->event_lock);
 191         ret = acrtc->dm_irq_params.window_param.activated;
 192         spin_unlock_irq(&drm_dev->event_lock);
 193
 194         return ret;
 195 }
 196 #endif
 197
 198 int
 199 amdgpu_dm_crtc_verify_crc_source(struct drm_crtc *crtc, const char *src_name,
 200                                  size_t *values_cnt)
 201 {
 202         enum amdgpu_dm_pipe_crc_source source = dm_parse_crc_source(src_name);
 203
 204         if (source < 0) {
 205                 DRM_DEBUG_DRIVER("Unknown CRC source %s for CRTC%d\n",
 206                                  src_name, crtc->index);
 207                 return -EINVAL;
 208         }
 209
 210         *values_cnt = 3;
 211         return 0;
 212 }
 213
 214 int amdgpu_dm_crtc_configure_crc_source(struct drm_crtc *crtc,
 215                                         struct dm_crtc_state *dm_crtc_state,
 216                                         enum amdgpu_dm_pipe_crc_source source)
 217 {
 218         struct amdgpu_device *adev = drm_to_adev(crtc->dev);
 219         struct dc_stream_state *stream_state = dm_crtc_state->stream;
 220         bool enable = amdgpu_dm_is_valid_crc_source(source);
 221         int ret = 0;
 222
 223         /* Configuration will be deferred to stream enable. */
 224         if (!stream_state)
 225                 return -EINVAL;
 226
 227         mutex_lock(&adev->dm.dc_lock);
 228
 229         /* Enable or disable CRTC CRC generation */
 230         if (dm_is_crc_source_crtc(source) || source == AMDGPU_DM_PIPE_CRC_SOURCE_NONE) {
 231                 if (!dc_stream_configure_crc(stream_state->ctx->dc,
 232                                              stream_state, NULL, enable, enable)) {
 233                         ret = -EINVAL;
 234                         goto unlock;
 235                 }
 236         }
 237
 238         /* Configure dithering */
 239         if (!dm_need_crc_dither(source)) {
 240                 dc_stream_set_dither_option(stream_state, DITHER_OPTION_TRUN8);
 241                 dc_stream_set_dyn_expansion(stream_state->ctx->dc, stream_state,
 242                                             DYN_EXPANSION_DISABLE);
 243         } else {
 244                 dc_stream_set_dither_option(stream_state,
 245                                             DITHER_OPTION_DEFAULT);
 246                 dc_stream_set_dyn_expansion(stream_state->ctx->dc, stream_state,
 247                                             DYN_EXPANSION_AUTO);
 248         }
 249
 250 unlock:
 251         mutex_unlock(&adev->dm.dc_lock);
 252
 253         return ret;
 254 }
 255
 256 int amdgpu_dm_crtc_set_crc_source(struct drm_crtc *crtc, const char *src_name)
 257 {
 258         enum amdgpu_dm_pipe_crc_source source = dm_parse_crc_source(src_name);
 259         enum amdgpu_dm_pipe_crc_source cur_crc_src;
 260         struct drm_crtc_commit *commit;
 261         struct dm_crtc_state *crtc_state;
 262         struct drm_device *drm_dev = crtc->dev;
 263         struct amdgpu_crtc *acrtc = to_amdgpu_crtc(crtc);
 264         struct drm_dp_aux *aux = NULL;
 265         bool enable = false;
 266         bool enabled = false;
 267         int ret = 0;
 268
 269         if (source < 0) {
 270                 DRM_DEBUG_DRIVER("Unknown CRC source %s for CRTC%d\n",
 271                                  src_name, crtc->index);
 272                 return -EINVAL;
 273         }
 274
 275         ret = drm_modeset_lock(&crtc->mutex, NULL);
 276         if (ret)
 277                 return ret;
 278
 279         spin_lock(&crtc->commit_lock);
 280         commit = list_first_entry_or_null(&crtc->commit_list,
 281                                           struct drm_crtc_commit, commit_entry);
 282         if (commit)
 283                 drm_crtc_commit_get(commit);
 284         spin_unlock(&crtc->commit_lock);
 285
 286         if (commit) {
 287                 /*
 288                  * Need to wait for all outstanding programming to complete
 289                  * in commit tail since it can modify CRC related fields and
 290                  * hardware state. Since we're holding the CRTC lock we're
 291                  * guaranteed that no other commit work can be queued off
 292                  * before we modify the state below.
 293                  */
 294                 ret = wait_for_completion_interruptible_timeout(
 295                         &commit->hw_done, 10 * HZ);
 296                 if (ret)
 297                         goto cleanup;
 298         }
 299
 300         enable = amdgpu_dm_is_valid_crc_source(source);
 301         crtc_state = to_dm_crtc_state(crtc->state);
 302         spin_lock_irq(&drm_dev->event_lock);
 303         cur_crc_src = acrtc->dm_irq_params.crc_src;
 304         spin_unlock_irq(&drm_dev->event_lock);
 305
 306         /*
 307          * USER REQ SRC | CURRENT SRC | BEHAVIOR
 308          * -----------------------------
 309          * None         | None        | Do nothing
 310          * None         | CRTC        | Disable CRTC CRC, set default to dither
 311          * None         | DPRX        | Disable DPRX CRC, need 'aux', set default to dither
 312          * None         | CRTC DITHER | Disable CRTC CRC
 313          * None         | DPRX DITHER | Disable DPRX CRC, need 'aux'
 314          * CRTC         | XXXX        | Enable CRTC CRC, no dither
 315          * DPRX         | XXXX        | Enable DPRX CRC, need 'aux', no dither
 316          * CRTC DITHER  | XXXX        | Enable CRTC CRC, set dither
 317          * DPRX DITHER  | XXXX        | Enable DPRX CRC, need 'aux', set dither
 318          */
 319         if (dm_is_crc_source_dprx(source) ||
 320             (source == AMDGPU_DM_PIPE_CRC_SOURCE_NONE &&
 321              dm_is_crc_source_dprx(cur_crc_src))) {
 322                 struct amdgpu_dm_connector *aconn = NULL;
 323                 struct drm_connector *connector;
 324                 struct drm_connector_list_iter conn_iter;
 325
 326                 drm_connector_list_iter_begin(crtc->dev, &conn_iter);
 327                 drm_for_each_connector_iter(connector, &conn_iter) {
 328                         if (!connector->state || connector->state->crtc != crtc)
 329                                 continue;
 330
 331                         aconn = to_amdgpu_dm_connector(connector);
 332                         break;
 333                 }
 334                 drm_connector_list_iter_end(&conn_iter);
 335
 336                 if (!aconn) {
 337                         DRM_DEBUG_DRIVER("No amd connector matching CRTC-%d\n", crtc->index);
 338                         ret = -EINVAL;
 339                         goto cleanup;
 340                 }
 341
 342                 aux = (aconn->mst_output_port) ? &aconn->mst_output_port->aux : &aconn->dm_dp_aux.aux;
 343
 344                 if (!aux) {
 345                         DRM_DEBUG_DRIVER("No dp aux for amd connector\n");
 346                         ret = -EINVAL;
 347                         goto cleanup;
 348                 }
 349
 350                 if ((aconn->base.connector_type != DRM_MODE_CONNECTOR_DisplayPort) &&
 351                                 (aconn->base.connector_type != DRM_MODE_CONNECTOR_eDP)) {
 352                         DRM_DEBUG_DRIVER("No DP connector available for CRC source\n");
 353                         ret = -EINVAL;
 354                         goto cleanup;
 355                 }
 356
 357         }
 358
 359 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
 360         /* Reset secure_display when we change crc source from debugfs */
 361         amdgpu_dm_set_crc_window_default(crtc, crtc_state->stream);
 362 #endif
 363
 364         if (amdgpu_dm_crtc_configure_crc_source(crtc, crtc_state, source)) {
 365                 ret = -EINVAL;
 366                 goto cleanup;
 367         }
 368
 369         /*
 370          * Reading the CRC requires the vblank interrupt handler to be
 371          * enabled. Keep a reference until CRC capture stops.
 372          */
 373         enabled = amdgpu_dm_is_valid_crc_source(cur_crc_src);
 374         if (!enabled && enable) {
 375                 ret = drm_crtc_vblank_get(crtc);
 376                 if (ret)
 377                         goto cleanup;
 378
 379                 if (dm_is_crc_source_dprx(source)) {
 380                         if (drm_dp_start_crc(aux, crtc)) {
 381                                 DRM_DEBUG_DRIVER("dp start crc failed\n");
 382                                 ret = -EINVAL;
 383                                 goto cleanup;
 384                         }
 385                 }
 386         } else if (enabled && !enable) {
 387                 drm_crtc_vblank_put(crtc);
 388                 if (dm_is_crc_source_dprx(source)) {
 389                         if (drm_dp_stop_crc(aux)) {
 390                                 DRM_DEBUG_DRIVER("dp stop crc failed\n");
 391                                 ret = -EINVAL;
 392                                 goto cleanup;
 393                         }
 394                 }
 395         }
 396
 397         spin_lock_irq(&drm_dev->event_lock);
 398         acrtc->dm_irq_params.crc_src = source;
 399         spin_unlock_irq(&drm_dev->event_lock);
 400
 401         /* Reset crc_skipped on dm state */
 402         crtc_state->crc_skip_count = 0;
 403
 404 cleanup:
 405         if (commit)
 406                 drm_crtc_commit_put(commit);
 407
 408         drm_modeset_unlock(&crtc->mutex);
 409
 410         return ret;
 411 }
 412
 413 /**
 414  * amdgpu_dm_crtc_handle_crc_irq: Report to DRM the CRC on given CRTC.
 415  * @crtc: DRM CRTC object.
 416  *
 417  * This function should be called at the end of a vblank, when the fb has been
 418  * fully processed through the pipe.
 419  */
 420 void amdgpu_dm_crtc_handle_crc_irq(struct drm_crtc *crtc)
 421 {
 422         struct dm_crtc_state *crtc_state;
 423         struct dc_stream_state *stream_state;
 424         struct drm_device *drm_dev = NULL;
 425         enum amdgpu_dm_pipe_crc_source cur_crc_src;
 426         struct amdgpu_crtc *acrtc = NULL;
 427         uint32_t crcs[3];
 428         unsigned long flags;
 429
 430         if (crtc == NULL)
 431                 return;
 432
 433         crtc_state = to_dm_crtc_state(crtc->state);
 434         stream_state = crtc_state->stream;
 435         acrtc = to_amdgpu_crtc(crtc);
 436         drm_dev = crtc->dev;
 437
 438         spin_lock_irqsave(&drm_dev->event_lock, flags);
 439         cur_crc_src = acrtc->dm_irq_params.crc_src;
 440         spin_unlock_irqrestore(&drm_dev->event_lock, flags);
 441
 442         /* Early return if CRC capture is not enabled. */
 443         if (!amdgpu_dm_is_valid_crc_source(cur_crc_src))
 444                 return;
 445
 446         /*
 447          * Since flipping and crc enablement happen asynchronously, we - more
 448          * often than not - will be returning an 'uncooked' crc on first frame.
 449          * Probably because hw isn't ready yet. For added security, skip the
 450          * first two CRC values.
 451          */
 452         if (crtc_state->crc_skip_count < 2) {
 453                 crtc_state->crc_skip_count += 1;
 454                 return;
 455         }
 456
 457         if (dm_is_crc_source_crtc(cur_crc_src)) {
 458                 if (!dc_stream_get_crc(stream_state->ctx->dc, stream_state,
 459                                        &crcs[0], &crcs[1], &crcs[2]))
 460                         return;
 461
 462                 drm_crtc_add_crc_entry(crtc, true,
 463                                        drm_crtc_accurate_vblank_count(crtc), crcs);
 464         }
 465 }
 466
 467 #if defined(CONFIG_DRM_AMD_SECURE_DISPLAY)
 468 void amdgpu_dm_crtc_handle_crc_window_irq(struct drm_crtc *crtc)
 469 {
 470         struct drm_device *drm_dev = NULL;
 471         enum amdgpu_dm_pipe_crc_source cur_crc_src;
 472         struct amdgpu_crtc *acrtc = NULL;
 473         struct amdgpu_device *adev = NULL;
 474         struct secure_display_context *secure_display_ctx = NULL;
 475         unsigned long flags1;
 476
 477         if (crtc == NULL)
 478                 return;
 479
 480         acrtc = to_amdgpu_crtc(crtc);
 481         adev = drm_to_adev(crtc->dev);
 482         drm_dev = crtc->dev;
 483
 484         spin_lock_irqsave(&drm_dev->event_lock, flags1);
 485         cur_crc_src = acrtc->dm_irq_params.crc_src;
 486
 487         /* Early return if CRC capture is not enabled. */
 488         if (!amdgpu_dm_is_valid_crc_source(cur_crc_src) ||
 489                 !dm_is_crc_source_crtc(cur_crc_src))
 490                 goto cleanup;
 491
 492         if (!acrtc->dm_irq_params.window_param.activated)
 493                 goto cleanup;
 494
 495         if (acrtc->dm_irq_params.window_param.skip_frame_cnt) {
 496                 acrtc->dm_irq_params.window_param.skip_frame_cnt -= 1;
 497                 goto cleanup;
 498         }
 499
 500         secure_display_ctx = &adev->dm.secure_display_ctxs[acrtc->crtc_id];
 501         if (WARN_ON(secure_display_ctx->crtc != crtc)) {
 502                 /* We have set the crtc when creating secure_display_context,
 503                  * don't expect it to be changed here.
 504                  */
 505                 secure_display_ctx->crtc = crtc;
 506         }
 507
 508         if (acrtc->dm_irq_params.window_param.update_win) {
 509                 /* prepare work for dmub to update ROI */
 510                 secure_display_ctx->rect.x = acrtc->dm_irq_params.window_param.x_start;
 511                 secure_display_ctx->rect.y = acrtc->dm_irq_params.window_param.y_start;
 512                 secure_display_ctx->rect.width = acrtc->dm_irq_params.window_param.x_end -
 513                                                                 acrtc->dm_irq_params.window_param.x_start;
 514                 secure_display_ctx->rect.height = acrtc->dm_irq_params.window_param.y_end -
 515                                                                 acrtc->dm_irq_params.window_param.y_start;
 516                 schedule_work(&secure_display_ctx->forward_roi_work);
 517
 518                 acrtc->dm_irq_params.window_param.update_win = false;
 519
 520                 /* Statically skip 1 frame, because we may need to wait below things
 521                  * before sending ROI to dmub:
 522                  * 1. We defer the work by using system workqueue.
 523                  * 2. We may need to wait for dc_lock before accessing dmub.
 524                  */
 525                 acrtc->dm_irq_params.window_param.skip_frame_cnt = 1;
 526
 527         } else {
 528                 /* prepare work for psp to read ROI/CRC and send to I2C */
 529                 schedule_work(&secure_display_ctx->notify_ta_work);
 530         }
 531
 532 cleanup:
 533         spin_unlock_irqrestore(&drm_dev->event_lock, flags1);
 534 }
 535
 536 struct secure_display_context *
 537 amdgpu_dm_crtc_secure_display_create_contexts(struct amdgpu_device *adev)
 538 {
 539         struct secure_display_context *secure_display_ctxs = NULL;
 540         int i;
 541
 542         secure_display_ctxs = kcalloc(adev->mode_info.num_crtc,
 543                                       sizeof(struct secure_display_context),
 544                                       GFP_KERNEL);
 545
 546         if (!secure_display_ctxs)
 547                 return NULL;
 548
 549         for (i = 0; i < adev->mode_info.num_crtc; i++) {
 550                 INIT_WORK(&secure_display_ctxs[i].forward_roi_work, amdgpu_dm_forward_crc_window);
 551                 INIT_WORK(&secure_display_ctxs[i].notify_ta_work, amdgpu_dm_crtc_notify_ta_to_read);
 552                 secure_display_ctxs[i].crtc = &adev->mode_info.crtcs[i]->base;
 553         }
 554
 555         return secure_display_ctxs;
 556 }
 557 #endif