drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Author: Huang Rui
  23  *
  24  */
  25
  26 #include <linux/firmware.h>
  27 #include <drm/drm_drv.h>
  28
  29 #include "amdgpu.h"
  30 #include "amdgpu_psp.h"
  31 #include "amdgpu_ucode.h"
  32 #include "amdgpu_xgmi.h"
  33 #include "soc15_common.h"
  34 #include "psp_v3_1.h"
  35 #include "psp_v10_0.h"
  36 #include "psp_v11_0.h"
  37 #include "psp_v11_0_8.h"
  38 #include "psp_v12_0.h"
  39 #include "psp_v13_0.h"
  40 #include "psp_v13_0_4.h"
  41
  42 #include "amdgpu_ras.h"
  43 #include "amdgpu_securedisplay.h"
  44 #include "amdgpu_atomfirmware.h"
  45
  46 #define AMD_VBIOS_FILE_MAX_SIZE_B      (1024*1024*3)
  47
  48 static int psp_sysfs_init(struct amdgpu_device *adev);
  49 static void psp_sysfs_fini(struct amdgpu_device *adev);
  50
  51 static int psp_load_smu_fw(struct psp_context *psp);
  52 static int psp_rap_terminate(struct psp_context *psp);
  53 static int psp_securedisplay_terminate(struct psp_context *psp);
  54
  55 static int psp_ring_init(struct psp_context *psp,
  56                          enum psp_ring_type ring_type)
  57 {
  58         int ret = 0;
  59         struct psp_ring *ring;
  60         struct amdgpu_device *adev = psp->adev;
  61
  62         ring = &psp->km_ring;
  63
  64         ring->ring_type = ring_type;
  65
  66         /* allocate 4k Page of Local Frame Buffer memory for ring */
  67         ring->ring_size = 0x1000;
  68         ret = amdgpu_bo_create_kernel(adev, ring->ring_size, PAGE_SIZE,
  69                                       AMDGPU_GEM_DOMAIN_VRAM |
  70                                       AMDGPU_GEM_DOMAIN_GTT,
  71                                       &adev->firmware.rbuf,
  72                                       &ring->ring_mem_mc_addr,
  73                                       (void **)&ring->ring_mem);
  74         if (ret) {
  75                 ring->ring_size = 0;
  76                 return ret;
  77         }
  78
  79         return 0;
  80 }
  81
  82 /*
  83  * Due to DF Cstate management centralized to PMFW, the firmware
  84  * loading sequence will be updated as below:
  85  *   - Load KDB
  86  *   - Load SYS_DRV
  87  *   - Load tOS
  88  *   - Load PMFW
  89  *   - Setup TMR
  90  *   - Load other non-psp fw
  91  *   - Load ASD
  92  *   - Load XGMI/RAS/HDCP/DTM TA if any
  93  *
  94  * This new sequence is required for
  95  *   - Arcturus and onwards
  96  */
  97 static void psp_check_pmfw_centralized_cstate_management(struct psp_context *psp)
  98 {
  99         struct amdgpu_device *adev = psp->adev;
 100
 101         if (amdgpu_sriov_vf(adev)) {
 102                 psp->pmfw_centralized_cstate_management = false;
 103                 return;
 104         }
 105
 106         switch (adev->ip_versions[MP0_HWIP][0]) {
 107         case IP_VERSION(11, 0, 0):
 108         case IP_VERSION(11, 0, 4):
 109         case IP_VERSION(11, 0, 5):
 110         case IP_VERSION(11, 0, 7):
 111         case IP_VERSION(11, 0, 9):
 112         case IP_VERSION(11, 0, 11):
 113         case IP_VERSION(11, 0, 12):
 114         case IP_VERSION(11, 0, 13):
 115         case IP_VERSION(13, 0, 0):
 116         case IP_VERSION(13, 0, 2):
 117         case IP_VERSION(13, 0, 7):
 118                 psp->pmfw_centralized_cstate_management = true;
 119                 break;
 120         default:
 121                 psp->pmfw_centralized_cstate_management = false;
 122                 break;
 123         }
 124 }
 125
 126 static int psp_init_sriov_microcode(struct psp_context *psp)
 127 {
 128         struct amdgpu_device *adev = psp->adev;
 129         char ucode_prefix[30];
 130         int ret = 0;
 131
 132         amdgpu_ucode_ip_version_decode(adev, MP0_HWIP, ucode_prefix, sizeof(ucode_prefix));
 133
 134         switch (adev->ip_versions[MP0_HWIP][0]) {
 135         case IP_VERSION(9, 0, 0):
 136         case IP_VERSION(11, 0, 7):
 137         case IP_VERSION(11, 0, 9):
 138                 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
 139                 ret = psp_init_cap_microcode(psp, ucode_prefix);
 140                 break;
 141         case IP_VERSION(13, 0, 2):
 142                 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
 143                 ret = psp_init_cap_microcode(psp, ucode_prefix);
 144                 ret &= psp_init_ta_microcode(psp, ucode_prefix);
 145                 break;
 146         case IP_VERSION(13, 0, 0):
 147                 adev->virt.autoload_ucode_id = 0;
 148                 break;
 149         case IP_VERSION(13, 0, 6):
 150                 ret = psp_init_cap_microcode(psp, ucode_prefix);
 151                 break;
 152         case IP_VERSION(13, 0, 10):
 153                 adev->virt.autoload_ucode_id = AMDGPU_UCODE_ID_CP_MES1_DATA;
 154                 ret = psp_init_cap_microcode(psp, ucode_prefix);
 155                 break;
 156         default:
 157                 return -EINVAL;
 158         }
 159         return ret;
 160 }
 161
 162 static int psp_early_init(void *handle)
 163 {
 164         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 165         struct psp_context *psp = &adev->psp;
 166
 167         switch (adev->ip_versions[MP0_HWIP][0]) {
 168         case IP_VERSION(9, 0, 0):
 169                 psp_v3_1_set_psp_funcs(psp);
 170                 psp->autoload_supported = false;
 171                 break;
 172         case IP_VERSION(10, 0, 0):
 173         case IP_VERSION(10, 0, 1):
 174                 psp_v10_0_set_psp_funcs(psp);
 175                 psp->autoload_supported = false;
 176                 break;
 177         case IP_VERSION(11, 0, 2):
 178         case IP_VERSION(11, 0, 4):
 179                 psp_v11_0_set_psp_funcs(psp);
 180                 psp->autoload_supported = false;
 181                 break;
 182         case IP_VERSION(11, 0, 0):
 183         case IP_VERSION(11, 0, 5):
 184         case IP_VERSION(11, 0, 9):
 185         case IP_VERSION(11, 0, 7):
 186         case IP_VERSION(11, 0, 11):
 187         case IP_VERSION(11, 5, 0):
 188         case IP_VERSION(11, 0, 12):
 189         case IP_VERSION(11, 0, 13):
 190                 psp_v11_0_set_psp_funcs(psp);
 191                 psp->autoload_supported = true;
 192                 break;
 193         case IP_VERSION(11, 0, 3):
 194         case IP_VERSION(12, 0, 1):
 195                 psp_v12_0_set_psp_funcs(psp);
 196                 break;
 197         case IP_VERSION(13, 0, 2):
 198         case IP_VERSION(13, 0, 6):
 199                 psp_v13_0_set_psp_funcs(psp);
 200                 break;
 201         case IP_VERSION(13, 0, 1):
 202         case IP_VERSION(13, 0, 3):
 203         case IP_VERSION(13, 0, 5):
 204         case IP_VERSION(13, 0, 8):
 205         case IP_VERSION(13, 0, 10):
 206         case IP_VERSION(13, 0, 11):
 207                 psp_v13_0_set_psp_funcs(psp);
 208                 psp->autoload_supported = true;
 209                 break;
 210         case IP_VERSION(11, 0, 8):
 211                 if (adev->apu_flags & AMD_APU_IS_CYAN_SKILLFISH2) {
 212                         psp_v11_0_8_set_psp_funcs(psp);
 213                         psp->autoload_supported = false;
 214                 }
 215                 break;
 216         case IP_VERSION(13, 0, 0):
 217         case IP_VERSION(13, 0, 7):
 218                 psp_v13_0_set_psp_funcs(psp);
 219                 psp->autoload_supported = true;
 220                 break;
 221         case IP_VERSION(13, 0, 4):
 222                 psp_v13_0_4_set_psp_funcs(psp);
 223                 psp->autoload_supported = true;
 224                 break;
 225         default:
 226                 return -EINVAL;
 227         }
 228
 229         psp->adev = adev;
 230
 231         psp_check_pmfw_centralized_cstate_management(psp);
 232
 233         if (amdgpu_sriov_vf(adev))
 234                 return psp_init_sriov_microcode(psp);
 235         else
 236                 return psp_init_microcode(psp);
 237 }
 238
 239 void psp_ta_free_shared_buf(struct ta_mem_context *mem_ctx)
 240 {
 241         amdgpu_bo_free_kernel(&mem_ctx->shared_bo, &mem_ctx->shared_mc_addr,
 242                               &mem_ctx->shared_buf);
 243         mem_ctx->shared_bo = NULL;
 244 }
 245
 246 static void psp_free_shared_bufs(struct psp_context *psp)
 247 {
 248         void *tmr_buf;
 249         void **pptr;
 250
 251         /* free TMR memory buffer */
 252         pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL;
 253         amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, pptr);
 254         psp->tmr_bo = NULL;
 255
 256         /* free xgmi shared memory */
 257         psp_ta_free_shared_buf(&psp->xgmi_context.context.mem_context);
 258
 259         /* free ras shared memory */
 260         psp_ta_free_shared_buf(&psp->ras_context.context.mem_context);
 261
 262         /* free hdcp shared memory */
 263         psp_ta_free_shared_buf(&psp->hdcp_context.context.mem_context);
 264
 265         /* free dtm shared memory */
 266         psp_ta_free_shared_buf(&psp->dtm_context.context.mem_context);
 267
 268         /* free rap shared memory */
 269         psp_ta_free_shared_buf(&psp->rap_context.context.mem_context);
 270
 271         /* free securedisplay shared memory */
 272         psp_ta_free_shared_buf(&psp->securedisplay_context.context.mem_context);
 273
 274
 275 }
 276
 277 static void psp_memory_training_fini(struct psp_context *psp)
 278 {
 279         struct psp_memory_training_context *ctx = &psp->mem_train_ctx;
 280
 281         ctx->init = PSP_MEM_TRAIN_NOT_SUPPORT;
 282         kfree(ctx->sys_cache);
 283         ctx->sys_cache = NULL;
 284 }
 285
 286 static int psp_memory_training_init(struct psp_context *psp)
 287 {
 288         int ret;
 289         struct psp_memory_training_context *ctx = &psp->mem_train_ctx;
 290
 291         if (ctx->init != PSP_MEM_TRAIN_RESERVE_SUCCESS) {
 292                 DRM_DEBUG("memory training is not supported!\n");
 293                 return 0;
 294         }
 295
 296         ctx->sys_cache = kzalloc(ctx->train_data_size, GFP_KERNEL);
 297         if (ctx->sys_cache == NULL) {
 298                 DRM_ERROR("alloc mem_train_ctx.sys_cache failed!\n");
 299                 ret = -ENOMEM;
 300                 goto Err_out;
 301         }
 302
 303         DRM_DEBUG("train_data_size:%llx,p2c_train_data_offset:%llx,c2p_train_data_offset:%llx.\n",
 304                   ctx->train_data_size,
 305                   ctx->p2c_train_data_offset,
 306                   ctx->c2p_train_data_offset);
 307         ctx->init = PSP_MEM_TRAIN_INIT_SUCCESS;
 308         return 0;
 309
 310 Err_out:
 311         psp_memory_training_fini(psp);
 312         return ret;
 313 }
 314
 315 /*
 316  * Helper funciton to query psp runtime database entry
 317  *
 318  * @adev: amdgpu_device pointer
 319  * @entry_type: the type of psp runtime database entry
 320  * @db_entry: runtime database entry pointer
 321  *
 322  * Return false if runtime database doesn't exit or entry is invalid
 323  * or true if the specific database entry is found, and copy to @db_entry
 324  */
 325 static bool psp_get_runtime_db_entry(struct amdgpu_device *adev,
 326                                      enum psp_runtime_entry_type entry_type,
 327                                      void *db_entry)
 328 {
 329         uint64_t db_header_pos, db_dir_pos;
 330         struct psp_runtime_data_header db_header = {0};
 331         struct psp_runtime_data_directory db_dir = {0};
 332         bool ret = false;
 333         int i;
 334
 335         if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 6))
 336                 return false;
 337
 338         db_header_pos = adev->gmc.mc_vram_size - PSP_RUNTIME_DB_OFFSET;
 339         db_dir_pos = db_header_pos + sizeof(struct psp_runtime_data_header);
 340
 341         /* read runtime db header from vram */
 342         amdgpu_device_vram_access(adev, db_header_pos, (uint32_t *)&db_header,
 343                         sizeof(struct psp_runtime_data_header), false);
 344
 345         if (db_header.cookie != PSP_RUNTIME_DB_COOKIE_ID) {
 346                 /* runtime db doesn't exist, exit */
 347                 dev_dbg(adev->dev, "PSP runtime database doesn't exist\n");
 348                 return false;
 349         }
 350
 351         /* read runtime database entry from vram */
 352         amdgpu_device_vram_access(adev, db_dir_pos, (uint32_t *)&db_dir,
 353                         sizeof(struct psp_runtime_data_directory), false);
 354
 355         if (db_dir.entry_count >= PSP_RUNTIME_DB_DIAG_ENTRY_MAX_COUNT) {
 356                 /* invalid db entry count, exit */
 357                 dev_warn(adev->dev, "Invalid PSP runtime database entry count\n");
 358                 return false;
 359         }
 360
 361         /* look up for requested entry type */
 362         for (i = 0; i < db_dir.entry_count && !ret; i++) {
 363                 if (db_dir.entry_list[i].entry_type == entry_type) {
 364                         switch (entry_type) {
 365                         case PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG:
 366                                 if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_boot_cfg_entry)) {
 367                                         /* invalid db entry size */
 368                                         dev_warn(adev->dev, "Invalid PSP runtime database boot cfg entry size\n");
 369                                         return false;
 370                                 }
 371                                 /* read runtime database entry */
 372                                 amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset,
 373                                                           (uint32_t *)db_entry, sizeof(struct psp_runtime_boot_cfg_entry), false);
 374                                 ret = true;
 375                                 break;
 376                         case PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS:
 377                                 if (db_dir.entry_list[i].size < sizeof(struct psp_runtime_scpm_entry)) {
 378                                         /* invalid db entry size */
 379                                         dev_warn(adev->dev, "Invalid PSP runtime database scpm entry size\n");
 380                                         return false;
 381                                 }
 382                                 /* read runtime database entry */
 383                                 amdgpu_device_vram_access(adev, db_header_pos + db_dir.entry_list[i].offset,
 384                                                           (uint32_t *)db_entry, sizeof(struct psp_runtime_scpm_entry), false);
 385                                 ret = true;
 386                                 break;
 387                         default:
 388                                 ret = false;
 389                                 break;
 390                         }
 391                 }
 392         }
 393
 394         return ret;
 395 }
 396
 397 static int psp_sw_init(void *handle)
 398 {
 399         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 400         struct psp_context *psp = &adev->psp;
 401         int ret;
 402         struct psp_runtime_boot_cfg_entry boot_cfg_entry;
 403         struct psp_memory_training_context *mem_training_ctx = &psp->mem_train_ctx;
 404         struct psp_runtime_scpm_entry scpm_entry;
 405
 406         psp->cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 407         if (!psp->cmd) {
 408                 DRM_ERROR("Failed to allocate memory to command buffer!\n");
 409                 ret = -ENOMEM;
 410         }
 411
 412         adev->psp.xgmi_context.supports_extended_data =
 413                 !adev->gmc.xgmi.connected_to_cpu &&
 414                         adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2);
 415
 416         memset(&scpm_entry, 0, sizeof(scpm_entry));
 417         if ((psp_get_runtime_db_entry(adev,
 418                                 PSP_RUNTIME_ENTRY_TYPE_PPTABLE_ERR_STATUS,
 419                                 &scpm_entry)) &&
 420             (scpm_entry.scpm_status != SCPM_DISABLE)) {
 421                 adev->scpm_enabled = true;
 422                 adev->scpm_status = scpm_entry.scpm_status;
 423         } else {
 424                 adev->scpm_enabled = false;
 425                 adev->scpm_status = SCPM_DISABLE;
 426         }
 427
 428         /* TODO: stop gpu driver services and print alarm if scpm is enabled with error status */
 429
 430         memset(&boot_cfg_entry, 0, sizeof(boot_cfg_entry));
 431         if (psp_get_runtime_db_entry(adev,
 432                                 PSP_RUNTIME_ENTRY_TYPE_BOOT_CONFIG,
 433                                 &boot_cfg_entry)) {
 434                 psp->boot_cfg_bitmask = boot_cfg_entry.boot_cfg_bitmask;
 435                 if ((psp->boot_cfg_bitmask) &
 436                     BOOT_CFG_FEATURE_TWO_STAGE_DRAM_TRAINING) {
 437                         /* If psp runtime database exists, then
 438                          * only enable two stage memory training
 439                          * when TWO_STAGE_DRAM_TRAINING bit is set
 440                          * in runtime database */
 441                         mem_training_ctx->enable_mem_training = true;
 442                 }
 443
 444         } else {
 445                 /* If psp runtime database doesn't exist or
 446                  * is invalid, force enable two stage memory
 447                  * training */
 448                 mem_training_ctx->enable_mem_training = true;
 449         }
 450
 451         if (mem_training_ctx->enable_mem_training) {
 452                 ret = psp_memory_training_init(psp);
 453                 if (ret) {
 454                         DRM_ERROR("Failed to initialize memory training!\n");
 455                         return ret;
 456                 }
 457
 458                 ret = psp_mem_training(psp, PSP_MEM_TRAIN_COLD_BOOT);
 459                 if (ret) {
 460                         DRM_ERROR("Failed to process memory training!\n");
 461                         return ret;
 462                 }
 463         }
 464
 465         if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 0) ||
 466             adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7)) {
 467                 ret = psp_sysfs_init(adev);
 468                 if (ret)
 469                         return ret;
 470         }
 471
 472         ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG,
 473                                       amdgpu_sriov_vf(adev) ?
 474                                       AMDGPU_GEM_DOMAIN_VRAM : AMDGPU_GEM_DOMAIN_GTT,
 475                                       &psp->fw_pri_bo,
 476                                       &psp->fw_pri_mc_addr,
 477                                       &psp->fw_pri_buf);
 478         if (ret)
 479                 return ret;
 480
 481         ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE,
 482                                       AMDGPU_GEM_DOMAIN_VRAM |
 483                                       AMDGPU_GEM_DOMAIN_GTT,
 484                                       &psp->fence_buf_bo,
 485                                       &psp->fence_buf_mc_addr,
 486                                       &psp->fence_buf);
 487         if (ret)
 488                 goto failed1;
 489
 490         ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE,
 491                                       AMDGPU_GEM_DOMAIN_VRAM |
 492                                       AMDGPU_GEM_DOMAIN_GTT,
 493                                       &psp->cmd_buf_bo, &psp->cmd_buf_mc_addr,
 494                                       (void **)&psp->cmd_buf_mem);
 495         if (ret)
 496                 goto failed2;
 497
 498         return 0;
 499
 500 failed2:
 501         amdgpu_bo_free_kernel(&psp->fw_pri_bo,
 502                               &psp->fw_pri_mc_addr, &psp->fw_pri_buf);
 503 failed1:
 504         amdgpu_bo_free_kernel(&psp->fence_buf_bo,
 505                               &psp->fence_buf_mc_addr, &psp->fence_buf);
 506         return ret;
 507 }
 508
 509 static int psp_sw_fini(void *handle)
 510 {
 511         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 512         struct psp_context *psp = &adev->psp;
 513         struct psp_gfx_cmd_resp *cmd = psp->cmd;
 514
 515         psp_memory_training_fini(psp);
 516
 517         amdgpu_ucode_release(&psp->sos_fw);
 518         amdgpu_ucode_release(&psp->asd_fw);
 519         amdgpu_ucode_release(&psp->ta_fw);
 520         amdgpu_ucode_release(&psp->cap_fw);
 521         amdgpu_ucode_release(&psp->toc_fw);
 522
 523         if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 0) ||
 524             adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7))
 525                 psp_sysfs_fini(adev);
 526
 527         kfree(cmd);
 528         cmd = NULL;
 529
 530         psp_free_shared_bufs(psp);
 531
 532         if (psp->km_ring.ring_mem)
 533                 amdgpu_bo_free_kernel(&adev->firmware.rbuf,
 534                                       &psp->km_ring.ring_mem_mc_addr,
 535                                       (void **)&psp->km_ring.ring_mem);
 536
 537         amdgpu_bo_free_kernel(&psp->fw_pri_bo,
 538                               &psp->fw_pri_mc_addr, &psp->fw_pri_buf);
 539         amdgpu_bo_free_kernel(&psp->fence_buf_bo,
 540                               &psp->fence_buf_mc_addr, &psp->fence_buf);
 541         amdgpu_bo_free_kernel(&psp->cmd_buf_bo, &psp->cmd_buf_mc_addr,
 542                               (void **)&psp->cmd_buf_mem);
 543
 544         return 0;
 545 }
 546
 547 int psp_wait_for(struct psp_context *psp, uint32_t reg_index,
 548                  uint32_t reg_val, uint32_t mask, bool check_changed)
 549 {
 550         uint32_t val;
 551         int i;
 552         struct amdgpu_device *adev = psp->adev;
 553
 554         if (psp->adev->no_hw_access)
 555                 return 0;
 556
 557         for (i = 0; i < adev->usec_timeout; i++) {
 558                 val = RREG32(reg_index);
 559                 if (check_changed) {
 560                         if (val != reg_val)
 561                                 return 0;
 562                 } else {
 563                         if ((val & mask) == reg_val)
 564                                 return 0;
 565                 }
 566                 udelay(1);
 567         }
 568
 569         return -ETIME;
 570 }
 571
 572 static const char *psp_gfx_cmd_name(enum psp_gfx_cmd_id cmd_id)
 573 {
 574         switch (cmd_id) {
 575         case GFX_CMD_ID_LOAD_TA:
 576                 return "LOAD_TA";
 577         case GFX_CMD_ID_UNLOAD_TA:
 578                 return "UNLOAD_TA";
 579         case GFX_CMD_ID_INVOKE_CMD:
 580                 return "INVOKE_CMD";
 581         case GFX_CMD_ID_LOAD_ASD:
 582                 return "LOAD_ASD";
 583         case GFX_CMD_ID_SETUP_TMR:
 584                 return "SETUP_TMR";
 585         case GFX_CMD_ID_LOAD_IP_FW:
 586                 return "LOAD_IP_FW";
 587         case GFX_CMD_ID_DESTROY_TMR:
 588                 return "DESTROY_TMR";
 589         case GFX_CMD_ID_SAVE_RESTORE:
 590                 return "SAVE_RESTORE_IP_FW";
 591         case GFX_CMD_ID_SETUP_VMR:
 592                 return "SETUP_VMR";
 593         case GFX_CMD_ID_DESTROY_VMR:
 594                 return "DESTROY_VMR";
 595         case GFX_CMD_ID_PROG_REG:
 596                 return "PROG_REG";
 597         case GFX_CMD_ID_GET_FW_ATTESTATION:
 598                 return "GET_FW_ATTESTATION";
 599         case GFX_CMD_ID_LOAD_TOC:
 600                 return "ID_LOAD_TOC";
 601         case GFX_CMD_ID_AUTOLOAD_RLC:
 602                 return "AUTOLOAD_RLC";
 603         case GFX_CMD_ID_BOOT_CFG:
 604                 return "BOOT_CFG";
 605         default:
 606                 return "UNKNOWN CMD";
 607         }
 608 }
 609
 610 static int
 611 psp_cmd_submit_buf(struct psp_context *psp,
 612                    struct amdgpu_firmware_info *ucode,
 613                    struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr)
 614 {
 615         int ret;
 616         int index;
 617         int timeout = 20000;
 618         bool ras_intr = false;
 619         bool skip_unsupport = false;
 620
 621         if (psp->adev->no_hw_access)
 622                 return 0;
 623
 624         memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE);
 625
 626         memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp));
 627
 628         index = atomic_inc_return(&psp->fence_value);
 629         ret = psp_ring_cmd_submit(psp, psp->cmd_buf_mc_addr, fence_mc_addr, index);
 630         if (ret) {
 631                 atomic_dec(&psp->fence_value);
 632                 goto exit;
 633         }
 634
 635         amdgpu_device_invalidate_hdp(psp->adev, NULL);
 636         while (*((unsigned int *)psp->fence_buf) != index) {
 637                 if (--timeout == 0)
 638                         break;
 639                 /*
 640                  * Shouldn't wait for timeout when err_event_athub occurs,
 641                  * because gpu reset thread triggered and lock resource should
 642                  * be released for psp resume sequence.
 643                  */
 644                 ras_intr = amdgpu_ras_intr_triggered();
 645                 if (ras_intr)
 646                         break;
 647                 usleep_range(10, 100);
 648                 amdgpu_device_invalidate_hdp(psp->adev, NULL);
 649         }
 650
 651         /* We allow TEE_ERROR_NOT_SUPPORTED for VMR command and PSP_ERR_UNKNOWN_COMMAND in SRIOV */
 652         skip_unsupport = (psp->cmd_buf_mem->resp.status == TEE_ERROR_NOT_SUPPORTED ||
 653                 psp->cmd_buf_mem->resp.status == PSP_ERR_UNKNOWN_COMMAND) && amdgpu_sriov_vf(psp->adev);
 654
 655         memcpy(&cmd->resp, &psp->cmd_buf_mem->resp, sizeof(struct psp_gfx_resp));
 656
 657         /* In some cases, psp response status is not 0 even there is no
 658          * problem while the command is submitted. Some version of PSP FW
 659          * doesn't write 0 to that field.
 660          * So here we would like to only print a warning instead of an error
 661          * during psp initialization to avoid breaking hw_init and it doesn't
 662          * return -EINVAL.
 663          */
 664         if (!skip_unsupport && (psp->cmd_buf_mem->resp.status || !timeout) && !ras_intr) {
 665                 if (ucode)
 666                         DRM_WARN("failed to load ucode %s(0x%X) ",
 667                                   amdgpu_ucode_name(ucode->ucode_id), ucode->ucode_id);
 668                 DRM_WARN("psp gfx command %s(0x%X) failed and response status is (0x%X)\n",
 669                          psp_gfx_cmd_name(psp->cmd_buf_mem->cmd_id), psp->cmd_buf_mem->cmd_id,
 670                          psp->cmd_buf_mem->resp.status);
 671                 /* If any firmware (including CAP) load fails under SRIOV, it should
 672                  * return failure to stop the VF from initializing.
 673                  * Also return failure in case of timeout
 674                  */
 675                 if ((ucode && amdgpu_sriov_vf(psp->adev)) || !timeout) {
 676                         ret = -EINVAL;
 677                         goto exit;
 678                 }
 679         }
 680
 681         if (ucode) {
 682                 ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo;
 683                 ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi;
 684         }
 685
 686 exit:
 687         return ret;
 688 }
 689
 690 static struct psp_gfx_cmd_resp *acquire_psp_cmd_buf(struct psp_context *psp)
 691 {
 692         struct psp_gfx_cmd_resp *cmd = psp->cmd;
 693
 694         mutex_lock(&psp->mutex);
 695
 696         memset(cmd, 0, sizeof(struct psp_gfx_cmd_resp));
 697
 698         return cmd;
 699 }
 700
 701 static void release_psp_cmd_buf(struct psp_context *psp)
 702 {
 703         mutex_unlock(&psp->mutex);
 704 }
 705
 706 static void psp_prep_tmr_cmd_buf(struct psp_context *psp,
 707                                  struct psp_gfx_cmd_resp *cmd,
 708                                  uint64_t tmr_mc, struct amdgpu_bo *tmr_bo)
 709 {
 710         struct amdgpu_device *adev = psp->adev;
 711         uint32_t size = 0;
 712         uint64_t tmr_pa = 0;
 713
 714         if (tmr_bo) {
 715                 size = amdgpu_bo_size(tmr_bo);
 716                 tmr_pa = amdgpu_gmc_vram_pa(adev, tmr_bo);
 717         }
 718
 719         if (amdgpu_sriov_vf(psp->adev))
 720                 cmd->cmd_id = GFX_CMD_ID_SETUP_VMR;
 721         else
 722                 cmd->cmd_id = GFX_CMD_ID_SETUP_TMR;
 723         cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc);
 724         cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc);
 725         cmd->cmd.cmd_setup_tmr.buf_size = size;
 726         cmd->cmd.cmd_setup_tmr.bitfield.virt_phy_addr = 1;
 727         cmd->cmd.cmd_setup_tmr.system_phy_addr_lo = lower_32_bits(tmr_pa);
 728         cmd->cmd.cmd_setup_tmr.system_phy_addr_hi = upper_32_bits(tmr_pa);
 729 }
 730
 731 static void psp_prep_load_toc_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 732                                       uint64_t pri_buf_mc, uint32_t size)
 733 {
 734         cmd->cmd_id = GFX_CMD_ID_LOAD_TOC;
 735         cmd->cmd.cmd_load_toc.toc_phy_addr_lo = lower_32_bits(pri_buf_mc);
 736         cmd->cmd.cmd_load_toc.toc_phy_addr_hi = upper_32_bits(pri_buf_mc);
 737         cmd->cmd.cmd_load_toc.toc_size = size;
 738 }
 739
 740 /* Issue LOAD TOC cmd to PSP to part toc and calculate tmr size needed */
 741 static int psp_load_toc(struct psp_context *psp,
 742                         uint32_t *tmr_size)
 743 {
 744         int ret;
 745         struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
 746
 747         /* Copy toc to psp firmware private buffer */
 748         psp_copy_fw(psp, psp->toc.start_addr, psp->toc.size_bytes);
 749
 750         psp_prep_load_toc_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->toc.size_bytes);
 751
 752         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 753                                  psp->fence_buf_mc_addr);
 754         if (!ret)
 755                 *tmr_size = psp->cmd_buf_mem->resp.tmr_size;
 756
 757         release_psp_cmd_buf(psp);
 758
 759         return ret;
 760 }
 761
 762 static bool psp_boottime_tmr(struct psp_context *psp)
 763 {
 764         switch (psp->adev->ip_versions[MP0_HWIP][0]) {
 765         case IP_VERSION(13, 0, 6):
 766                 return true;
 767         default:
 768                 return false;
 769         }
 770 }
 771
 772 /* Set up Trusted Memory Region */
 773 static int psp_tmr_init(struct psp_context *psp)
 774 {
 775         int ret = 0;
 776         int tmr_size;
 777         void *tmr_buf;
 778         void **pptr;
 779
 780         /*
 781          * According to HW engineer, they prefer the TMR address be "naturally
 782          * aligned" , e.g. the start address be an integer divide of TMR size.
 783          *
 784          * Note: this memory need be reserved till the driver
 785          * uninitializes.
 786          */
 787         tmr_size = PSP_TMR_SIZE(psp->adev);
 788
 789         /* For ASICs support RLC autoload, psp will parse the toc
 790          * and calculate the total size of TMR needed */
 791         if (!amdgpu_sriov_vf(psp->adev) &&
 792             psp->toc.start_addr &&
 793             psp->toc.size_bytes &&
 794             psp->fw_pri_buf) {
 795                 ret = psp_load_toc(psp, &tmr_size);
 796                 if (ret) {
 797                         DRM_ERROR("Failed to load toc\n");
 798                         return ret;
 799                 }
 800         }
 801
 802         if (!psp->tmr_bo) {
 803                 pptr = amdgpu_sriov_vf(psp->adev) ? &tmr_buf : NULL;
 804                 ret = amdgpu_bo_create_kernel(psp->adev, tmr_size,
 805                                               PSP_TMR_ALIGNMENT,
 806                                               AMDGPU_HAS_VRAM(psp->adev) ?
 807                                               AMDGPU_GEM_DOMAIN_VRAM :
 808                                               AMDGPU_GEM_DOMAIN_GTT,
 809                                               &psp->tmr_bo, &psp->tmr_mc_addr,
 810                                               pptr);
 811         }
 812
 813         return ret;
 814 }
 815
 816 static bool psp_skip_tmr(struct psp_context *psp)
 817 {
 818         switch (psp->adev->ip_versions[MP0_HWIP][0]) {
 819         case IP_VERSION(11, 0, 9):
 820         case IP_VERSION(11, 0, 7):
 821         case IP_VERSION(13, 0, 2):
 822         case IP_VERSION(13, 0, 10):
 823                 return true;
 824         default:
 825                 return false;
 826         }
 827 }
 828
 829 static int psp_tmr_load(struct psp_context *psp)
 830 {
 831         int ret;
 832         struct psp_gfx_cmd_resp *cmd;
 833
 834         /* For Navi12 and CHIP_SIENNA_CICHLID SRIOV, do not set up TMR.
 835          * Already set up by host driver.
 836          */
 837         if (amdgpu_sriov_vf(psp->adev) && psp_skip_tmr(psp))
 838                 return 0;
 839
 840         cmd = acquire_psp_cmd_buf(psp);
 841
 842         psp_prep_tmr_cmd_buf(psp, cmd, psp->tmr_mc_addr, psp->tmr_bo);
 843         if (psp->tmr_bo)
 844                 DRM_INFO("reserve 0x%lx from 0x%llx for PSP TMR\n",
 845                          amdgpu_bo_size(psp->tmr_bo), psp->tmr_mc_addr);
 846
 847         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 848                                  psp->fence_buf_mc_addr);
 849
 850         release_psp_cmd_buf(psp);
 851
 852         return ret;
 853 }
 854
 855 static void psp_prep_tmr_unload_cmd_buf(struct psp_context *psp,
 856                                         struct psp_gfx_cmd_resp *cmd)
 857 {
 858         if (amdgpu_sriov_vf(psp->adev))
 859                 cmd->cmd_id = GFX_CMD_ID_DESTROY_VMR;
 860         else
 861                 cmd->cmd_id = GFX_CMD_ID_DESTROY_TMR;
 862 }
 863
 864 static int psp_tmr_unload(struct psp_context *psp)
 865 {
 866         int ret;
 867         struct psp_gfx_cmd_resp *cmd;
 868
 869         /* skip TMR unload for Navi12 and CHIP_SIENNA_CICHLID SRIOV,
 870          * as TMR is not loaded at all
 871          */
 872         if (amdgpu_sriov_vf(psp->adev) && psp_skip_tmr(psp))
 873                 return 0;
 874
 875         cmd = acquire_psp_cmd_buf(psp);
 876
 877         psp_prep_tmr_unload_cmd_buf(psp, cmd);
 878         dev_dbg(psp->adev->dev, "free PSP TMR buffer\n");
 879
 880         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 881                                  psp->fence_buf_mc_addr);
 882
 883         release_psp_cmd_buf(psp);
 884
 885         return ret;
 886 }
 887
 888 static int psp_tmr_terminate(struct psp_context *psp)
 889 {
 890         return psp_tmr_unload(psp);
 891 }
 892
 893 int psp_get_fw_attestation_records_addr(struct psp_context *psp,
 894                                         uint64_t *output_ptr)
 895 {
 896         int ret;
 897         struct psp_gfx_cmd_resp *cmd;
 898
 899         if (!output_ptr)
 900                 return -EINVAL;
 901
 902         if (amdgpu_sriov_vf(psp->adev))
 903                 return 0;
 904
 905         cmd = acquire_psp_cmd_buf(psp);
 906
 907         cmd->cmd_id = GFX_CMD_ID_GET_FW_ATTESTATION;
 908
 909         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 910                                  psp->fence_buf_mc_addr);
 911
 912         if (!ret) {
 913                 *output_ptr = ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_lo) +
 914                               ((uint64_t)cmd->resp.uresp.fwar_db_info.fwar_db_addr_hi << 32);
 915         }
 916
 917         release_psp_cmd_buf(psp);
 918
 919         return ret;
 920 }
 921
 922 static int psp_boot_config_get(struct amdgpu_device *adev, uint32_t *boot_cfg)
 923 {
 924         struct psp_context *psp = &adev->psp;
 925         struct psp_gfx_cmd_resp *cmd;
 926         int ret;
 927
 928         if (amdgpu_sriov_vf(adev))
 929                 return 0;
 930
 931         cmd = acquire_psp_cmd_buf(psp);
 932
 933         cmd->cmd_id = GFX_CMD_ID_BOOT_CFG;
 934         cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_GET;
 935
 936         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
 937         if (!ret) {
 938                 *boot_cfg =
 939                         (cmd->resp.uresp.boot_cfg.boot_cfg & BOOT_CONFIG_GECC) ? 1 : 0;
 940         }
 941
 942         release_psp_cmd_buf(psp);
 943
 944         return ret;
 945 }
 946
 947 static int psp_boot_config_set(struct amdgpu_device *adev, uint32_t boot_cfg)
 948 {
 949         int ret;
 950         struct psp_context *psp = &adev->psp;
 951         struct psp_gfx_cmd_resp *cmd;
 952
 953         if (amdgpu_sriov_vf(adev))
 954                 return 0;
 955
 956         cmd = acquire_psp_cmd_buf(psp);
 957
 958         cmd->cmd_id = GFX_CMD_ID_BOOT_CFG;
 959         cmd->cmd.boot_cfg.sub_cmd = BOOTCFG_CMD_SET;
 960         cmd->cmd.boot_cfg.boot_config = boot_cfg;
 961         cmd->cmd.boot_cfg.boot_config_valid = boot_cfg;
 962
 963         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
 964
 965         release_psp_cmd_buf(psp);
 966
 967         return ret;
 968 }
 969
 970 static int psp_rl_load(struct amdgpu_device *adev)
 971 {
 972         int ret;
 973         struct psp_context *psp = &adev->psp;
 974         struct psp_gfx_cmd_resp *cmd;
 975
 976         if (!is_psp_fw_valid(psp->rl))
 977                 return 0;
 978
 979         cmd = acquire_psp_cmd_buf(psp);
 980
 981         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
 982         memcpy(psp->fw_pri_buf, psp->rl.start_addr, psp->rl.size_bytes);
 983
 984         cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW;
 985         cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(psp->fw_pri_mc_addr);
 986         cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(psp->fw_pri_mc_addr);
 987         cmd->cmd.cmd_load_ip_fw.fw_size = psp->rl.size_bytes;
 988         cmd->cmd.cmd_load_ip_fw.fw_type = GFX_FW_TYPE_REG_LIST;
 989
 990         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
 991
 992         release_psp_cmd_buf(psp);
 993
 994         return ret;
 995 }
 996
 997 int psp_spatial_partition(struct psp_context *psp, int mode)
 998 {
 999         struct psp_gfx_cmd_resp *cmd;
1000         int ret;
1001
1002         if (amdgpu_sriov_vf(psp->adev))
1003                 return 0;
1004
1005         cmd = acquire_psp_cmd_buf(psp);
1006
1007         cmd->cmd_id = GFX_CMD_ID_SRIOV_SPATIAL_PART;
1008         cmd->cmd.cmd_spatial_part.mode = mode;
1009
1010         dev_info(psp->adev->dev, "Requesting %d partitions through PSP", mode);
1011         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1012
1013         release_psp_cmd_buf(psp);
1014
1015         return ret;
1016 }
1017
1018 static int psp_asd_initialize(struct psp_context *psp)
1019 {
1020         int ret;
1021
1022         /* If PSP version doesn't match ASD version, asd loading will be failed.
1023          * add workaround to bypass it for sriov now.
1024          * TODO: add version check to make it common
1025          */
1026         if (amdgpu_sriov_vf(psp->adev) || !psp->asd_context.bin_desc.size_bytes)
1027                 return 0;
1028
1029         psp->asd_context.mem_context.shared_mc_addr  = 0;
1030         psp->asd_context.mem_context.shared_mem_size = PSP_ASD_SHARED_MEM_SIZE;
1031         psp->asd_context.ta_load_type                = GFX_CMD_ID_LOAD_ASD;
1032
1033         ret = psp_ta_load(psp, &psp->asd_context);
1034         if (!ret)
1035                 psp->asd_context.initialized = true;
1036
1037         return ret;
1038 }
1039
1040 static void psp_prep_ta_unload_cmd_buf(struct psp_gfx_cmd_resp *cmd,
1041                                        uint32_t session_id)
1042 {
1043         cmd->cmd_id = GFX_CMD_ID_UNLOAD_TA;
1044         cmd->cmd.cmd_unload_ta.session_id = session_id;
1045 }
1046
1047 int psp_ta_unload(struct psp_context *psp, struct ta_context *context)
1048 {
1049         int ret;
1050         struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
1051
1052         psp_prep_ta_unload_cmd_buf(cmd, context->session_id);
1053
1054         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1055
1056         context->resp_status = cmd->resp.status;
1057
1058         release_psp_cmd_buf(psp);
1059
1060         return ret;
1061 }
1062
1063 static int psp_asd_terminate(struct psp_context *psp)
1064 {
1065         int ret;
1066
1067         if (amdgpu_sriov_vf(psp->adev))
1068                 return 0;
1069
1070         if (!psp->asd_context.initialized)
1071                 return 0;
1072
1073         ret = psp_ta_unload(psp, &psp->asd_context);
1074         if (!ret)
1075                 psp->asd_context.initialized = false;
1076
1077         return ret;
1078 }
1079
1080 static void psp_prep_reg_prog_cmd_buf(struct psp_gfx_cmd_resp *cmd,
1081                 uint32_t id, uint32_t value)
1082 {
1083         cmd->cmd_id = GFX_CMD_ID_PROG_REG;
1084         cmd->cmd.cmd_setup_reg_prog.reg_value = value;
1085         cmd->cmd.cmd_setup_reg_prog.reg_id = id;
1086 }
1087
1088 int psp_reg_program(struct psp_context *psp, enum psp_reg_prog_id reg,
1089                 uint32_t value)
1090 {
1091         struct psp_gfx_cmd_resp *cmd;
1092         int ret = 0;
1093
1094         if (reg >= PSP_REG_LAST)
1095                 return -EINVAL;
1096
1097         cmd = acquire_psp_cmd_buf(psp);
1098
1099         psp_prep_reg_prog_cmd_buf(cmd, reg, value);
1100         ret = psp_cmd_submit_buf(psp, NULL, cmd, psp->fence_buf_mc_addr);
1101         if (ret)
1102                 DRM_ERROR("PSP failed to program reg id %d", reg);
1103
1104         release_psp_cmd_buf(psp);
1105
1106         return ret;
1107 }
1108
1109 static void psp_prep_ta_load_cmd_buf(struct psp_gfx_cmd_resp *cmd,
1110                                      uint64_t ta_bin_mc,
1111                                      struct ta_context *context)
1112 {
1113         cmd->cmd_id                             = context->ta_load_type;
1114         cmd->cmd.cmd_load_ta.app_phy_addr_lo    = lower_32_bits(ta_bin_mc);
1115         cmd->cmd.cmd_load_ta.app_phy_addr_hi    = upper_32_bits(ta_bin_mc);
1116         cmd->cmd.cmd_load_ta.app_len            = context->bin_desc.size_bytes;
1117
1118         cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo =
1119                 lower_32_bits(context->mem_context.shared_mc_addr);
1120         cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi =
1121                 upper_32_bits(context->mem_context.shared_mc_addr);
1122         cmd->cmd.cmd_load_ta.cmd_buf_len = context->mem_context.shared_mem_size;
1123 }
1124
1125 int psp_ta_init_shared_buf(struct psp_context *psp,
1126                                   struct ta_mem_context *mem_ctx)
1127 {
1128         /*
1129         * Allocate 16k memory aligned to 4k from Frame Buffer (local
1130         * physical) for ta to host memory
1131         */
1132         return amdgpu_bo_create_kernel(psp->adev, mem_ctx->shared_mem_size,
1133                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM |
1134                                       AMDGPU_GEM_DOMAIN_GTT,
1135                                       &mem_ctx->shared_bo,
1136                                       &mem_ctx->shared_mc_addr,
1137                                       &mem_ctx->shared_buf);
1138 }
1139
1140 static void psp_prep_ta_invoke_cmd_buf(struct psp_gfx_cmd_resp *cmd,
1141                                        uint32_t ta_cmd_id,
1142                                        uint32_t session_id)
1143 {
1144         cmd->cmd_id                             = GFX_CMD_ID_INVOKE_CMD;
1145         cmd->cmd.cmd_invoke_cmd.session_id      = session_id;
1146         cmd->cmd.cmd_invoke_cmd.ta_cmd_id       = ta_cmd_id;
1147 }
1148
1149 int psp_ta_invoke(struct psp_context *psp,
1150                   uint32_t ta_cmd_id,
1151                   struct ta_context *context)
1152 {
1153         int ret;
1154         struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
1155
1156         psp_prep_ta_invoke_cmd_buf(cmd, ta_cmd_id, context->session_id);
1157
1158         ret = psp_cmd_submit_buf(psp, NULL, cmd,
1159                                  psp->fence_buf_mc_addr);
1160
1161         context->resp_status = cmd->resp.status;
1162
1163         release_psp_cmd_buf(psp);
1164
1165         return ret;
1166 }
1167
1168 int psp_ta_load(struct psp_context *psp, struct ta_context *context)
1169 {
1170         int ret;
1171         struct psp_gfx_cmd_resp *cmd;
1172
1173         cmd = acquire_psp_cmd_buf(psp);
1174
1175         psp_copy_fw(psp, context->bin_desc.start_addr,
1176                     context->bin_desc.size_bytes);
1177
1178         psp_prep_ta_load_cmd_buf(cmd, psp->fw_pri_mc_addr, context);
1179
1180         ret = psp_cmd_submit_buf(psp, NULL, cmd,
1181                                  psp->fence_buf_mc_addr);
1182
1183         context->resp_status = cmd->resp.status;
1184
1185         if (!ret)
1186                 context->session_id = cmd->resp.session_id;
1187
1188         release_psp_cmd_buf(psp);
1189
1190         return ret;
1191 }
1192
1193 int psp_xgmi_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1194 {
1195         return psp_ta_invoke(psp, ta_cmd_id, &psp->xgmi_context.context);
1196 }
1197
1198 int psp_xgmi_terminate(struct psp_context *psp)
1199 {
1200         int ret;
1201         struct amdgpu_device *adev = psp->adev;
1202
1203         /* XGMI TA unload currently is not supported on Arcturus/Aldebaran A+A */
1204         if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 4) ||
1205             (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2) &&
1206              adev->gmc.xgmi.connected_to_cpu))
1207                 return 0;
1208
1209         if (!psp->xgmi_context.context.initialized)
1210                 return 0;
1211
1212         ret = psp_ta_unload(psp, &psp->xgmi_context.context);
1213
1214         psp->xgmi_context.context.initialized = false;
1215
1216         return ret;
1217 }
1218
1219 int psp_xgmi_initialize(struct psp_context *psp, bool set_extended_data, bool load_ta)
1220 {
1221         struct ta_xgmi_shared_memory *xgmi_cmd;
1222         int ret;
1223
1224         if (!psp->ta_fw ||
1225             !psp->xgmi_context.context.bin_desc.size_bytes ||
1226             !psp->xgmi_context.context.bin_desc.start_addr)
1227                 return -ENOENT;
1228
1229         if (!load_ta)
1230                 goto invoke;
1231
1232         psp->xgmi_context.context.mem_context.shared_mem_size = PSP_XGMI_SHARED_MEM_SIZE;
1233         psp->xgmi_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;
1234
1235         if (!psp->xgmi_context.context.mem_context.shared_buf) {
1236                 ret = psp_ta_init_shared_buf(psp, &psp->xgmi_context.context.mem_context);
1237                 if (ret)
1238                         return ret;
1239         }
1240
1241         /* Load XGMI TA */
1242         ret = psp_ta_load(psp, &psp->xgmi_context.context);
1243         if (!ret)
1244                 psp->xgmi_context.context.initialized = true;
1245         else
1246                 return ret;
1247
1248 invoke:
1249         /* Initialize XGMI session */
1250         xgmi_cmd = (struct ta_xgmi_shared_memory *)(psp->xgmi_context.context.mem_context.shared_buf);
1251         memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
1252         xgmi_cmd->flag_extend_link_record = set_extended_data;
1253         xgmi_cmd->cmd_id = TA_COMMAND_XGMI__INITIALIZE;
1254
1255         ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
1256
1257         return ret;
1258 }
1259
1260 int psp_xgmi_get_hive_id(struct psp_context *psp, uint64_t *hive_id)
1261 {
1262         struct ta_xgmi_shared_memory *xgmi_cmd;
1263         int ret;
1264
1265         xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf;
1266         memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
1267
1268         xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_HIVE_ID;
1269
1270         /* Invoke xgmi ta to get hive id */
1271         ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
1272         if (ret)
1273                 return ret;
1274
1275         *hive_id = xgmi_cmd->xgmi_out_message.get_hive_id.hive_id;
1276
1277         return 0;
1278 }
1279
1280 int psp_xgmi_get_node_id(struct psp_context *psp, uint64_t *node_id)
1281 {
1282         struct ta_xgmi_shared_memory *xgmi_cmd;
1283         int ret;
1284
1285         xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf;
1286         memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
1287
1288         xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_NODE_ID;
1289
1290         /* Invoke xgmi ta to get the node id */
1291         ret = psp_xgmi_invoke(psp, xgmi_cmd->cmd_id);
1292         if (ret)
1293                 return ret;
1294
1295         *node_id = xgmi_cmd->xgmi_out_message.get_node_id.node_id;
1296
1297         return 0;
1298 }
1299
1300 static bool psp_xgmi_peer_link_info_supported(struct psp_context *psp)
1301 {
1302         return (psp->adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 2) &&
1303                 psp->xgmi_context.context.bin_desc.fw_version >= 0x2000000b) ||
1304                 psp->adev->ip_versions[MP0_HWIP][0] >= IP_VERSION(13, 0, 6);
1305 }
1306
1307 /*
1308  * Chips that support extended topology information require the driver to
1309  * reflect topology information in the opposite direction.  This is
1310  * because the TA has already exceeded its link record limit and if the
1311  * TA holds bi-directional information, the driver would have to do
1312  * multiple fetches instead of just two.
1313  */
1314 static void psp_xgmi_reflect_topology_info(struct psp_context *psp,
1315                                         struct psp_xgmi_node_info node_info)
1316 {
1317         struct amdgpu_device *mirror_adev;
1318         struct amdgpu_hive_info *hive;
1319         uint64_t src_node_id = psp->adev->gmc.xgmi.node_id;
1320         uint64_t dst_node_id = node_info.node_id;
1321         uint8_t dst_num_hops = node_info.num_hops;
1322         uint8_t dst_num_links = node_info.num_links;
1323
1324         hive = amdgpu_get_xgmi_hive(psp->adev);
1325         list_for_each_entry(mirror_adev, &hive->device_list, gmc.xgmi.head) {
1326                 struct psp_xgmi_topology_info *mirror_top_info;
1327                 int j;
1328
1329                 if (mirror_adev->gmc.xgmi.node_id != dst_node_id)
1330                         continue;
1331
1332                 mirror_top_info = &mirror_adev->psp.xgmi_context.top_info;
1333                 for (j = 0; j < mirror_top_info->num_nodes; j++) {
1334                         if (mirror_top_info->nodes[j].node_id != src_node_id)
1335                                 continue;
1336
1337                         mirror_top_info->nodes[j].num_hops = dst_num_hops;
1338                         /*
1339                          * prevent 0 num_links value re-reflection since reflection
1340                          * criteria is based on num_hops (direct or indirect).
1341                          *
1342                          */
1343                         if (dst_num_links)
1344                                 mirror_top_info->nodes[j].num_links = dst_num_links;
1345
1346                         break;
1347                 }
1348
1349                 break;
1350         }
1351
1352         amdgpu_put_xgmi_hive(hive);
1353 }
1354
1355 int psp_xgmi_get_topology_info(struct psp_context *psp,
1356                                int number_devices,
1357                                struct psp_xgmi_topology_info *topology,
1358                                bool get_extended_data)
1359 {
1360         struct ta_xgmi_shared_memory *xgmi_cmd;
1361         struct ta_xgmi_cmd_get_topology_info_input *topology_info_input;
1362         struct ta_xgmi_cmd_get_topology_info_output *topology_info_output;
1363         int i;
1364         int ret;
1365
1366         if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES)
1367                 return -EINVAL;
1368
1369         xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf;
1370         memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
1371         xgmi_cmd->flag_extend_link_record = get_extended_data;
1372
1373         /* Fill in the shared memory with topology information as input */
1374         topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info;
1375         xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO;
1376         topology_info_input->num_nodes = number_devices;
1377
1378         for (i = 0; i < topology_info_input->num_nodes; i++) {
1379                 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id;
1380                 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops;
1381                 topology_info_input->nodes[i].is_sharing_enabled = topology->nodes[i].is_sharing_enabled;
1382                 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine;
1383         }
1384
1385         /* Invoke xgmi ta to get the topology information */
1386         ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_GET_TOPOLOGY_INFO);
1387         if (ret)
1388                 return ret;
1389
1390         /* Read the output topology information from the shared memory */
1391         topology_info_output = &xgmi_cmd->xgmi_out_message.get_topology_info;
1392         topology->num_nodes = xgmi_cmd->xgmi_out_message.get_topology_info.num_nodes;
1393         for (i = 0; i < topology->num_nodes; i++) {
1394                 /* extended data will either be 0 or equal to non-extended data */
1395                 if (topology_info_output->nodes[i].num_hops)
1396                         topology->nodes[i].num_hops = topology_info_output->nodes[i].num_hops;
1397
1398                 /* non-extended data gets everything here so no need to update */
1399                 if (!get_extended_data) {
1400                         topology->nodes[i].node_id = topology_info_output->nodes[i].node_id;
1401                         topology->nodes[i].is_sharing_enabled =
1402                                         topology_info_output->nodes[i].is_sharing_enabled;
1403                         topology->nodes[i].sdma_engine =
1404                                         topology_info_output->nodes[i].sdma_engine;
1405                 }
1406
1407         }
1408
1409         /* Invoke xgmi ta again to get the link information */
1410         if (psp_xgmi_peer_link_info_supported(psp)) {
1411                 struct ta_xgmi_cmd_get_peer_link_info_output *link_info_output;
1412                 bool requires_reflection =
1413                         (psp->xgmi_context.supports_extended_data && get_extended_data) ||
1414                                 psp->adev->ip_versions[MP0_HWIP][0] == IP_VERSION(13, 0, 6);
1415
1416                 xgmi_cmd->cmd_id = TA_COMMAND_XGMI__GET_PEER_LINKS;
1417
1418                 ret = psp_xgmi_invoke(psp, TA_COMMAND_XGMI__GET_PEER_LINKS);
1419
1420                 if (ret)
1421                         return ret;
1422
1423                 link_info_output = &xgmi_cmd->xgmi_out_message.get_link_info;
1424                 for (i = 0; i < topology->num_nodes; i++) {
1425                         /* accumulate num_links on extended data */
1426                         topology->nodes[i].num_links = get_extended_data ?
1427                                         topology->nodes[i].num_links +
1428                                                         link_info_output->nodes[i].num_links :
1429                                         ((requires_reflection && topology->nodes[i].num_links) ? topology->nodes[i].num_links :
1430                                          link_info_output->nodes[i].num_links);
1431
1432                         /* reflect the topology information for bi-directionality */
1433                         if (requires_reflection && topology->nodes[i].num_hops)
1434                                 psp_xgmi_reflect_topology_info(psp, topology->nodes[i]);
1435                 }
1436         }
1437
1438         return 0;
1439 }
1440
1441 int psp_xgmi_set_topology_info(struct psp_context *psp,
1442                                int number_devices,
1443                                struct psp_xgmi_topology_info *topology)
1444 {
1445         struct ta_xgmi_shared_memory *xgmi_cmd;
1446         struct ta_xgmi_cmd_get_topology_info_input *topology_info_input;
1447         int i;
1448
1449         if (!topology || topology->num_nodes > TA_XGMI__MAX_CONNECTED_NODES)
1450                 return -EINVAL;
1451
1452         xgmi_cmd = (struct ta_xgmi_shared_memory *)psp->xgmi_context.context.mem_context.shared_buf;
1453         memset(xgmi_cmd, 0, sizeof(struct ta_xgmi_shared_memory));
1454
1455         topology_info_input = &xgmi_cmd->xgmi_in_message.get_topology_info;
1456         xgmi_cmd->cmd_id = TA_COMMAND_XGMI__SET_TOPOLOGY_INFO;
1457         topology_info_input->num_nodes = number_devices;
1458
1459         for (i = 0; i < topology_info_input->num_nodes; i++) {
1460                 topology_info_input->nodes[i].node_id = topology->nodes[i].node_id;
1461                 topology_info_input->nodes[i].num_hops = topology->nodes[i].num_hops;
1462                 topology_info_input->nodes[i].is_sharing_enabled = 1;
1463                 topology_info_input->nodes[i].sdma_engine = topology->nodes[i].sdma_engine;
1464         }
1465
1466         /* Invoke xgmi ta to set topology information */
1467         return psp_xgmi_invoke(psp, TA_COMMAND_XGMI__SET_TOPOLOGY_INFO);
1468 }
1469
1470 // ras begin
1471 static void psp_ras_ta_check_status(struct psp_context *psp)
1472 {
1473         struct ta_ras_shared_memory *ras_cmd =
1474                 (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf;
1475
1476         switch (ras_cmd->ras_status) {
1477         case TA_RAS_STATUS__ERROR_UNSUPPORTED_IP:
1478                 dev_warn(psp->adev->dev,
1479                                 "RAS WARNING: cmd failed due to unsupported ip\n");
1480                 break;
1481         case TA_RAS_STATUS__ERROR_UNSUPPORTED_ERROR_INJ:
1482                 dev_warn(psp->adev->dev,
1483                                 "RAS WARNING: cmd failed due to unsupported error injection\n");
1484                 break;
1485         case TA_RAS_STATUS__SUCCESS:
1486                 break;
1487         case TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED:
1488                 if (ras_cmd->cmd_id == TA_RAS_COMMAND__TRIGGER_ERROR)
1489                         dev_warn(psp->adev->dev,
1490                                         "RAS WARNING: Inject error to critical region is not allowed\n");
1491                 break;
1492         default:
1493                 dev_warn(psp->adev->dev,
1494                                 "RAS WARNING: ras status = 0x%X\n", ras_cmd->ras_status);
1495                 break;
1496         }
1497 }
1498
1499 int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1500 {
1501         struct ta_ras_shared_memory *ras_cmd;
1502         int ret;
1503
1504         ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf;
1505
1506         /*
1507          * TODO: bypass the loading in sriov for now
1508          */
1509         if (amdgpu_sriov_vf(psp->adev))
1510                 return 0;
1511
1512         ret = psp_ta_invoke(psp, ta_cmd_id, &psp->ras_context.context);
1513
1514         if (amdgpu_ras_intr_triggered())
1515                 return ret;
1516
1517         if (ras_cmd->if_version > RAS_TA_HOST_IF_VER) {
1518                 DRM_WARN("RAS: Unsupported Interface");
1519                 return -EINVAL;
1520         }
1521
1522         if (!ret) {
1523                 if (ras_cmd->ras_out_message.flags.err_inject_switch_disable_flag) {
1524                         dev_warn(psp->adev->dev, "ECC switch disabled\n");
1525
1526                         ras_cmd->ras_status = TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE;
1527                 } else if (ras_cmd->ras_out_message.flags.reg_access_failure_flag)
1528                         dev_warn(psp->adev->dev,
1529                                  "RAS internal register access blocked\n");
1530
1531                 psp_ras_ta_check_status(psp);
1532         }
1533
1534         return ret;
1535 }
1536
1537 int psp_ras_enable_features(struct psp_context *psp,
1538                 union ta_ras_cmd_input *info, bool enable)
1539 {
1540         struct ta_ras_shared_memory *ras_cmd;
1541         int ret;
1542
1543         if (!psp->ras_context.context.initialized)
1544                 return -EINVAL;
1545
1546         ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf;
1547         memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory));
1548
1549         if (enable)
1550                 ras_cmd->cmd_id = TA_RAS_COMMAND__ENABLE_FEATURES;
1551         else
1552                 ras_cmd->cmd_id = TA_RAS_COMMAND__DISABLE_FEATURES;
1553
1554         ras_cmd->ras_in_message = *info;
1555
1556         ret = psp_ras_invoke(psp, ras_cmd->cmd_id);
1557         if (ret)
1558                 return -EINVAL;
1559
1560         return 0;
1561 }
1562
1563 int psp_ras_terminate(struct psp_context *psp)
1564 {
1565         int ret;
1566
1567         /*
1568          * TODO: bypass the terminate in sriov for now
1569          */
1570         if (amdgpu_sriov_vf(psp->adev))
1571                 return 0;
1572
1573         if (!psp->ras_context.context.initialized)
1574                 return 0;
1575
1576         ret = psp_ta_unload(psp, &psp->ras_context.context);
1577
1578         psp->ras_context.context.initialized = false;
1579
1580         return ret;
1581 }
1582
1583 int psp_ras_initialize(struct psp_context *psp)
1584 {
1585         int ret;
1586         uint32_t boot_cfg = 0xFF;
1587         struct amdgpu_device *adev = psp->adev;
1588         struct ta_ras_shared_memory *ras_cmd;
1589
1590         /*
1591          * TODO: bypass the initialize in sriov for now
1592          */
1593         if (amdgpu_sriov_vf(adev))
1594                 return 0;
1595
1596         if (!adev->psp.ras_context.context.bin_desc.size_bytes ||
1597             !adev->psp.ras_context.context.bin_desc.start_addr) {
1598                 dev_info(adev->dev, "RAS: optional ras ta ucode is not available\n");
1599                 return 0;
1600         }
1601
1602         if (amdgpu_atomfirmware_dynamic_boot_config_supported(adev)) {
1603                 /* query GECC enablement status from boot config
1604                  * boot_cfg: 1: GECC is enabled or 0: GECC is disabled
1605                  */
1606                 ret = psp_boot_config_get(adev, &boot_cfg);
1607                 if (ret)
1608                         dev_warn(adev->dev, "PSP get boot config failed\n");
1609
1610                 if (!amdgpu_ras_is_supported(psp->adev, AMDGPU_RAS_BLOCK__UMC)) {
1611                         if (!boot_cfg) {
1612                                 dev_info(adev->dev, "GECC is disabled\n");
1613                         } else {
1614                                 /* disable GECC in next boot cycle if ras is
1615                                  * disabled by module parameter amdgpu_ras_enable
1616                                  * and/or amdgpu_ras_mask, or boot_config_get call
1617                                  * is failed
1618                                  */
1619                                 ret = psp_boot_config_set(adev, 0);
1620                                 if (ret)
1621                                         dev_warn(adev->dev, "PSP set boot config failed\n");
1622                                 else
1623                                         dev_warn(adev->dev, "GECC will be disabled in next boot cycle if set amdgpu_ras_enable and/or amdgpu_ras_mask to 0x0\n");
1624                         }
1625                 } else {
1626                         if (boot_cfg == 1) {
1627                                 dev_info(adev->dev, "GECC is enabled\n");
1628                         } else {
1629                                 /* enable GECC in next boot cycle if it is disabled
1630                                  * in boot config, or force enable GECC if failed to
1631                                  * get boot configuration
1632                                  */
1633                                 ret = psp_boot_config_set(adev, BOOT_CONFIG_GECC);
1634                                 if (ret)
1635                                         dev_warn(adev->dev, "PSP set boot config failed\n");
1636                                 else
1637                                         dev_warn(adev->dev, "GECC will be enabled in next boot cycle\n");
1638                         }
1639                 }
1640         }
1641
1642         psp->ras_context.context.mem_context.shared_mem_size = PSP_RAS_SHARED_MEM_SIZE;
1643         psp->ras_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;
1644
1645         if (!psp->ras_context.context.mem_context.shared_buf) {
1646                 ret = psp_ta_init_shared_buf(psp, &psp->ras_context.context.mem_context);
1647                 if (ret)
1648                         return ret;
1649         }
1650
1651         ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf;
1652         memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory));
1653
1654         if (amdgpu_ras_is_poison_mode_supported(adev))
1655                 ras_cmd->ras_in_message.init_flags.poison_mode_en = 1;
1656         if (!adev->gmc.xgmi.connected_to_cpu)
1657                 ras_cmd->ras_in_message.init_flags.dgpu_mode = 1;
1658         ras_cmd->ras_in_message.init_flags.xcc_mask =
1659                 adev->gfx.xcc_mask;
1660
1661         ret = psp_ta_load(psp, &psp->ras_context.context);
1662
1663         if (!ret && !ras_cmd->ras_status)
1664                 psp->ras_context.context.initialized = true;
1665         else {
1666                 if (ras_cmd->ras_status)
1667                         dev_warn(psp->adev->dev, "RAS Init Status: 0x%X\n", ras_cmd->ras_status);
1668
1669                 /* fail to load RAS TA */
1670                 psp->ras_context.context.initialized = false;
1671         }
1672
1673         return ret;
1674 }
1675
1676 int psp_ras_trigger_error(struct psp_context *psp,
1677                           struct ta_ras_trigger_error_input *info, uint32_t instance_mask)
1678 {
1679         struct ta_ras_shared_memory *ras_cmd;
1680         struct amdgpu_device *adev = psp->adev;
1681         int ret;
1682         uint32_t dev_mask;
1683
1684         if (!psp->ras_context.context.initialized)
1685                 return -EINVAL;
1686
1687         switch (info->block_id) {
1688         case TA_RAS_BLOCK__GFX:
1689                 dev_mask = GET_MASK(GC, instance_mask);
1690                 break;
1691         case TA_RAS_BLOCK__SDMA:
1692                 dev_mask = GET_MASK(SDMA0, instance_mask);
1693                 break;
1694         case TA_RAS_BLOCK__VCN:
1695         case TA_RAS_BLOCK__JPEG:
1696                 dev_mask = GET_MASK(VCN, instance_mask);
1697                 break;
1698         default:
1699                 dev_mask = instance_mask;
1700                 break;
1701         }
1702
1703         /* reuse sub_block_index for backward compatibility */
1704         dev_mask <<= AMDGPU_RAS_INST_SHIFT;
1705         dev_mask &= AMDGPU_RAS_INST_MASK;
1706         info->sub_block_index |= dev_mask;
1707
1708         ras_cmd = (struct ta_ras_shared_memory *)psp->ras_context.context.mem_context.shared_buf;
1709         memset(ras_cmd, 0, sizeof(struct ta_ras_shared_memory));
1710
1711         ras_cmd->cmd_id = TA_RAS_COMMAND__TRIGGER_ERROR;
1712         ras_cmd->ras_in_message.trigger_error = *info;
1713
1714         ret = psp_ras_invoke(psp, ras_cmd->cmd_id);
1715         if (ret)
1716                 return -EINVAL;
1717
1718         /* If err_event_athub occurs error inject was successful, however
1719            return status from TA is no long reliable */
1720         if (amdgpu_ras_intr_triggered())
1721                 return 0;
1722
1723         if (ras_cmd->ras_status == TA_RAS_STATUS__TEE_ERROR_ACCESS_DENIED)
1724                 return -EACCES;
1725         else if (ras_cmd->ras_status)
1726                 return -EINVAL;
1727
1728         return 0;
1729 }
1730 // ras end
1731
1732 // HDCP start
1733 static int psp_hdcp_initialize(struct psp_context *psp)
1734 {
1735         int ret;
1736
1737         /*
1738          * TODO: bypass the initialize in sriov for now
1739          */
1740         if (amdgpu_sriov_vf(psp->adev))
1741                 return 0;
1742
1743         if (!psp->hdcp_context.context.bin_desc.size_bytes ||
1744             !psp->hdcp_context.context.bin_desc.start_addr) {
1745                 dev_info(psp->adev->dev, "HDCP: optional hdcp ta ucode is not available\n");
1746                 return 0;
1747         }
1748
1749         psp->hdcp_context.context.mem_context.shared_mem_size = PSP_HDCP_SHARED_MEM_SIZE;
1750         psp->hdcp_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;
1751
1752         if (!psp->hdcp_context.context.mem_context.shared_buf) {
1753                 ret = psp_ta_init_shared_buf(psp, &psp->hdcp_context.context.mem_context);
1754                 if (ret)
1755                         return ret;
1756         }
1757
1758         ret = psp_ta_load(psp, &psp->hdcp_context.context);
1759         if (!ret) {
1760                 psp->hdcp_context.context.initialized = true;
1761                 mutex_init(&psp->hdcp_context.mutex);
1762         }
1763
1764         return ret;
1765 }
1766
1767 int psp_hdcp_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1768 {
1769         /*
1770          * TODO: bypass the loading in sriov for now
1771          */
1772         if (amdgpu_sriov_vf(psp->adev))
1773                 return 0;
1774
1775         return psp_ta_invoke(psp, ta_cmd_id, &psp->hdcp_context.context);
1776 }
1777
1778 static int psp_hdcp_terminate(struct psp_context *psp)
1779 {
1780         int ret;
1781
1782         /*
1783          * TODO: bypass the terminate in sriov for now
1784          */
1785         if (amdgpu_sriov_vf(psp->adev))
1786                 return 0;
1787
1788         if (!psp->hdcp_context.context.initialized)
1789                 return 0;
1790
1791         ret = psp_ta_unload(psp, &psp->hdcp_context.context);
1792
1793         psp->hdcp_context.context.initialized = false;
1794
1795         return ret;
1796 }
1797 // HDCP end
1798
1799 // DTM start
1800 static int psp_dtm_initialize(struct psp_context *psp)
1801 {
1802         int ret;
1803
1804         /*
1805          * TODO: bypass the initialize in sriov for now
1806          */
1807         if (amdgpu_sriov_vf(psp->adev))
1808                 return 0;
1809
1810         if (!psp->dtm_context.context.bin_desc.size_bytes ||
1811             !psp->dtm_context.context.bin_desc.start_addr) {
1812                 dev_info(psp->adev->dev, "DTM: optional dtm ta ucode is not available\n");
1813                 return 0;
1814         }
1815
1816         psp->dtm_context.context.mem_context.shared_mem_size = PSP_DTM_SHARED_MEM_SIZE;
1817         psp->dtm_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;
1818
1819         if (!psp->dtm_context.context.mem_context.shared_buf) {
1820                 ret = psp_ta_init_shared_buf(psp, &psp->dtm_context.context.mem_context);
1821                 if (ret)
1822                         return ret;
1823         }
1824
1825         ret = psp_ta_load(psp, &psp->dtm_context.context);
1826         if (!ret) {
1827                 psp->dtm_context.context.initialized = true;
1828                 mutex_init(&psp->dtm_context.mutex);
1829         }
1830
1831         return ret;
1832 }
1833
1834 int psp_dtm_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
1835 {
1836         /*
1837          * TODO: bypass the loading in sriov for now
1838          */
1839         if (amdgpu_sriov_vf(psp->adev))
1840                 return 0;
1841
1842         return psp_ta_invoke(psp, ta_cmd_id, &psp->dtm_context.context);
1843 }
1844
1845 static int psp_dtm_terminate(struct psp_context *psp)
1846 {
1847         int ret;
1848
1849         /*
1850          * TODO: bypass the terminate in sriov for now
1851          */
1852         if (amdgpu_sriov_vf(psp->adev))
1853                 return 0;
1854
1855         if (!psp->dtm_context.context.initialized)
1856                 return 0;
1857
1858         ret = psp_ta_unload(psp, &psp->dtm_context.context);
1859
1860         psp->dtm_context.context.initialized = false;
1861
1862         return ret;
1863 }
1864 // DTM end
1865
1866 // RAP start
1867 static int psp_rap_initialize(struct psp_context *psp)
1868 {
1869         int ret;
1870         enum ta_rap_status status = TA_RAP_STATUS__SUCCESS;
1871
1872         /*
1873          * TODO: bypass the initialize in sriov for now
1874          */
1875         if (amdgpu_sriov_vf(psp->adev))
1876                 return 0;
1877
1878         if (!psp->rap_context.context.bin_desc.size_bytes ||
1879             !psp->rap_context.context.bin_desc.start_addr) {
1880                 dev_info(psp->adev->dev, "RAP: optional rap ta ucode is not available\n");
1881                 return 0;
1882         }
1883
1884         psp->rap_context.context.mem_context.shared_mem_size = PSP_RAP_SHARED_MEM_SIZE;
1885         psp->rap_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;
1886
1887         if (!psp->rap_context.context.mem_context.shared_buf) {
1888                 ret = psp_ta_init_shared_buf(psp, &psp->rap_context.context.mem_context);
1889                 if (ret)
1890                         return ret;
1891         }
1892
1893         ret = psp_ta_load(psp, &psp->rap_context.context);
1894         if (!ret) {
1895                 psp->rap_context.context.initialized = true;
1896                 mutex_init(&psp->rap_context.mutex);
1897         } else
1898                 return ret;
1899
1900         ret = psp_rap_invoke(psp, TA_CMD_RAP__INITIALIZE, &status);
1901         if (ret || status != TA_RAP_STATUS__SUCCESS) {
1902                 psp_rap_terminate(psp);
1903                 /* free rap shared memory */
1904                 psp_ta_free_shared_buf(&psp->rap_context.context.mem_context);
1905
1906                 dev_warn(psp->adev->dev, "RAP TA initialize fail (%d) status %d.\n",
1907                          ret, status);
1908
1909                 return ret;
1910         }
1911
1912         return 0;
1913 }
1914
1915 static int psp_rap_terminate(struct psp_context *psp)
1916 {
1917         int ret;
1918
1919         if (!psp->rap_context.context.initialized)
1920                 return 0;
1921
1922         ret = psp_ta_unload(psp, &psp->rap_context.context);
1923
1924         psp->rap_context.context.initialized = false;
1925
1926         return ret;
1927 }
1928
1929 int psp_rap_invoke(struct psp_context *psp, uint32_t ta_cmd_id, enum ta_rap_status *status)
1930 {
1931         struct ta_rap_shared_memory *rap_cmd;
1932         int ret = 0;
1933
1934         if (!psp->rap_context.context.initialized)
1935                 return 0;
1936
1937         if (ta_cmd_id != TA_CMD_RAP__INITIALIZE &&
1938             ta_cmd_id != TA_CMD_RAP__VALIDATE_L0)
1939                 return -EINVAL;
1940
1941         mutex_lock(&psp->rap_context.mutex);
1942
1943         rap_cmd = (struct ta_rap_shared_memory *)
1944                   psp->rap_context.context.mem_context.shared_buf;
1945         memset(rap_cmd, 0, sizeof(struct ta_rap_shared_memory));
1946
1947         rap_cmd->cmd_id = ta_cmd_id;
1948         rap_cmd->validation_method_id = METHOD_A;
1949
1950         ret = psp_ta_invoke(psp, rap_cmd->cmd_id, &psp->rap_context.context);
1951         if (ret)
1952                 goto out_unlock;
1953
1954         if (status)
1955                 *status = rap_cmd->rap_status;
1956
1957 out_unlock:
1958         mutex_unlock(&psp->rap_context.mutex);
1959
1960         return ret;
1961 }
1962 // RAP end
1963
1964 /* securedisplay start */
1965 static int psp_securedisplay_initialize(struct psp_context *psp)
1966 {
1967         int ret;
1968         struct ta_securedisplay_cmd *securedisplay_cmd;
1969
1970         /*
1971          * TODO: bypass the initialize in sriov for now
1972          */
1973         if (amdgpu_sriov_vf(psp->adev))
1974                 return 0;
1975
1976         if (!psp->securedisplay_context.context.bin_desc.size_bytes ||
1977             !psp->securedisplay_context.context.bin_desc.start_addr) {
1978                 dev_info(psp->adev->dev, "SECUREDISPLAY: securedisplay ta ucode is not available\n");
1979                 return 0;
1980         }
1981
1982         psp->securedisplay_context.context.mem_context.shared_mem_size =
1983                 PSP_SECUREDISPLAY_SHARED_MEM_SIZE;
1984         psp->securedisplay_context.context.ta_load_type = GFX_CMD_ID_LOAD_TA;
1985
1986         if (!psp->securedisplay_context.context.initialized) {
1987                 ret = psp_ta_init_shared_buf(psp,
1988                                              &psp->securedisplay_context.context.mem_context);
1989                 if (ret)
1990                         return ret;
1991         }
1992
1993         ret = psp_ta_load(psp, &psp->securedisplay_context.context);
1994         if (!ret) {
1995                 psp->securedisplay_context.context.initialized = true;
1996                 mutex_init(&psp->securedisplay_context.mutex);
1997         } else
1998                 return ret;
1999
2000         mutex_lock(&psp->securedisplay_context.mutex);
2001
2002         psp_prep_securedisplay_cmd_buf(psp, &securedisplay_cmd,
2003                         TA_SECUREDISPLAY_COMMAND__QUERY_TA);
2004
2005         ret = psp_securedisplay_invoke(psp, TA_SECUREDISPLAY_COMMAND__QUERY_TA);
2006
2007         mutex_unlock(&psp->securedisplay_context.mutex);
2008
2009         if (ret) {
2010                 psp_securedisplay_terminate(psp);
2011                 /* free securedisplay shared memory */
2012                 psp_ta_free_shared_buf(&psp->securedisplay_context.context.mem_context);
2013                 dev_err(psp->adev->dev, "SECUREDISPLAY TA initialize fail.\n");
2014                 return -EINVAL;
2015         }
2016
2017         if (securedisplay_cmd->status != TA_SECUREDISPLAY_STATUS__SUCCESS) {
2018                 psp_securedisplay_parse_resp_status(psp, securedisplay_cmd->status);
2019                 dev_err(psp->adev->dev, "SECUREDISPLAY: query securedisplay TA failed. ret 0x%x\n",
2020                         securedisplay_cmd->securedisplay_out_message.query_ta.query_cmd_ret);
2021         }
2022
2023         return 0;
2024 }
2025
2026 static int psp_securedisplay_terminate(struct psp_context *psp)
2027 {
2028         int ret;
2029
2030         /*
2031          * TODO:bypass the terminate in sriov for now
2032          */
2033         if (amdgpu_sriov_vf(psp->adev))
2034                 return 0;
2035
2036         if (!psp->securedisplay_context.context.initialized)
2037                 return 0;
2038
2039         ret = psp_ta_unload(psp, &psp->securedisplay_context.context);
2040
2041         psp->securedisplay_context.context.initialized = false;
2042
2043         return ret;
2044 }
2045
2046 int psp_securedisplay_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
2047 {
2048         int ret;
2049
2050         if (!psp->securedisplay_context.context.initialized)
2051                 return -EINVAL;
2052
2053         if (ta_cmd_id != TA_SECUREDISPLAY_COMMAND__QUERY_TA &&
2054             ta_cmd_id != TA_SECUREDISPLAY_COMMAND__SEND_ROI_CRC)
2055                 return -EINVAL;
2056
2057         ret = psp_ta_invoke(psp, ta_cmd_id, &psp->securedisplay_context.context);
2058
2059         return ret;
2060 }
2061 /* SECUREDISPLAY end */
2062
2063 static int psp_hw_start(struct psp_context *psp)
2064 {
2065         struct amdgpu_device *adev = psp->adev;
2066         int ret;
2067
2068         if (!amdgpu_sriov_vf(adev)) {
2069                 if ((is_psp_fw_valid(psp->kdb)) &&
2070                     (psp->funcs->bootloader_load_kdb != NULL)) {
2071                         ret = psp_bootloader_load_kdb(psp);
2072                         if (ret) {
2073                                 DRM_ERROR("PSP load kdb failed!\n");
2074                                 return ret;
2075                         }
2076                 }
2077
2078                 if ((is_psp_fw_valid(psp->spl)) &&
2079                     (psp->funcs->bootloader_load_spl != NULL)) {
2080                         ret = psp_bootloader_load_spl(psp);
2081                         if (ret) {
2082                                 DRM_ERROR("PSP load spl failed!\n");
2083                                 return ret;
2084                         }
2085                 }
2086
2087                 if ((is_psp_fw_valid(psp->sys)) &&
2088                     (psp->funcs->bootloader_load_sysdrv != NULL)) {
2089                         ret = psp_bootloader_load_sysdrv(psp);
2090                         if (ret) {
2091                                 DRM_ERROR("PSP load sys drv failed!\n");
2092                                 return ret;
2093                         }
2094                 }
2095
2096                 if ((is_psp_fw_valid(psp->soc_drv)) &&
2097                     (psp->funcs->bootloader_load_soc_drv != NULL)) {
2098                         ret = psp_bootloader_load_soc_drv(psp);
2099                         if (ret) {
2100                                 DRM_ERROR("PSP load soc drv failed!\n");
2101                                 return ret;
2102                         }
2103                 }
2104
2105                 if ((is_psp_fw_valid(psp->intf_drv)) &&
2106                     (psp->funcs->bootloader_load_intf_drv != NULL)) {
2107                         ret = psp_bootloader_load_intf_drv(psp);
2108                         if (ret) {
2109                                 DRM_ERROR("PSP load intf drv failed!\n");
2110                                 return ret;
2111                         }
2112                 }
2113
2114                 if ((is_psp_fw_valid(psp->dbg_drv)) &&
2115                     (psp->funcs->bootloader_load_dbg_drv != NULL)) {
2116                         ret = psp_bootloader_load_dbg_drv(psp);
2117                         if (ret) {
2118                                 DRM_ERROR("PSP load dbg drv failed!\n");
2119                                 return ret;
2120                         }
2121                 }
2122
2123                 if ((is_psp_fw_valid(psp->ras_drv)) &&
2124                     (psp->funcs->bootloader_load_ras_drv != NULL)) {
2125                         ret = psp_bootloader_load_ras_drv(psp);
2126                         if (ret) {
2127                                 DRM_ERROR("PSP load ras_drv failed!\n");
2128                                 return ret;
2129                         }
2130                 }
2131
2132                 if ((is_psp_fw_valid(psp->sos)) &&
2133                     (psp->funcs->bootloader_load_sos != NULL)) {
2134                         ret = psp_bootloader_load_sos(psp);
2135                         if (ret) {
2136                                 DRM_ERROR("PSP load sos failed!\n");
2137                                 return ret;
2138                         }
2139                 }
2140         }
2141
2142         ret = psp_ring_create(psp, PSP_RING_TYPE__KM);
2143         if (ret) {
2144                 DRM_ERROR("PSP create ring failed!\n");
2145                 return ret;
2146         }
2147
2148         if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev))
2149                 goto skip_pin_bo;
2150
2151         if (!psp_boottime_tmr(psp)) {
2152                 ret = psp_tmr_init(psp);
2153                 if (ret) {
2154                         DRM_ERROR("PSP tmr init failed!\n");
2155                         return ret;
2156                 }
2157         }
2158
2159 skip_pin_bo:
2160         /*
2161          * For ASICs with DF Cstate management centralized
2162          * to PMFW, TMR setup should be performed after PMFW
2163          * loaded and before other non-psp firmware loaded.
2164          */
2165         if (psp->pmfw_centralized_cstate_management) {
2166                 ret = psp_load_smu_fw(psp);
2167                 if (ret)
2168                         return ret;
2169         }
2170
2171         ret = psp_tmr_load(psp);
2172         if (ret) {
2173                 DRM_ERROR("PSP load tmr failed!\n");
2174                 return ret;
2175         }
2176
2177         return 0;
2178 }
2179
2180 static int psp_get_fw_type(struct amdgpu_firmware_info *ucode,
2181                            enum psp_gfx_fw_type *type)
2182 {
2183         switch (ucode->ucode_id) {
2184         case AMDGPU_UCODE_ID_CAP:
2185                 *type = GFX_FW_TYPE_CAP;
2186                 break;
2187         case AMDGPU_UCODE_ID_SDMA0:
2188                 *type = GFX_FW_TYPE_SDMA0;
2189                 break;
2190         case AMDGPU_UCODE_ID_SDMA1:
2191                 *type = GFX_FW_TYPE_SDMA1;
2192                 break;
2193         case AMDGPU_UCODE_ID_SDMA2:
2194                 *type = GFX_FW_TYPE_SDMA2;
2195                 break;
2196         case AMDGPU_UCODE_ID_SDMA3:
2197                 *type = GFX_FW_TYPE_SDMA3;
2198                 break;
2199         case AMDGPU_UCODE_ID_SDMA4:
2200                 *type = GFX_FW_TYPE_SDMA4;
2201                 break;
2202         case AMDGPU_UCODE_ID_SDMA5:
2203                 *type = GFX_FW_TYPE_SDMA5;
2204                 break;
2205         case AMDGPU_UCODE_ID_SDMA6:
2206                 *type = GFX_FW_TYPE_SDMA6;
2207                 break;
2208         case AMDGPU_UCODE_ID_SDMA7:
2209                 *type = GFX_FW_TYPE_SDMA7;
2210                 break;
2211         case AMDGPU_UCODE_ID_CP_MES:
2212                 *type = GFX_FW_TYPE_CP_MES;
2213                 break;
2214         case AMDGPU_UCODE_ID_CP_MES_DATA:
2215                 *type = GFX_FW_TYPE_MES_STACK;
2216                 break;
2217         case AMDGPU_UCODE_ID_CP_MES1:
2218                 *type = GFX_FW_TYPE_CP_MES_KIQ;
2219                 break;
2220         case AMDGPU_UCODE_ID_CP_MES1_DATA:
2221                 *type = GFX_FW_TYPE_MES_KIQ_STACK;
2222                 break;
2223         case AMDGPU_UCODE_ID_CP_CE:
2224                 *type = GFX_FW_TYPE_CP_CE;
2225                 break;
2226         case AMDGPU_UCODE_ID_CP_PFP:
2227                 *type = GFX_FW_TYPE_CP_PFP;
2228                 break;
2229         case AMDGPU_UCODE_ID_CP_ME:
2230                 *type = GFX_FW_TYPE_CP_ME;
2231                 break;
2232         case AMDGPU_UCODE_ID_CP_MEC1:
2233                 *type = GFX_FW_TYPE_CP_MEC;
2234                 break;
2235         case AMDGPU_UCODE_ID_CP_MEC1_JT:
2236                 *type = GFX_FW_TYPE_CP_MEC_ME1;
2237                 break;
2238         case AMDGPU_UCODE_ID_CP_MEC2:
2239                 *type = GFX_FW_TYPE_CP_MEC;
2240                 break;
2241         case AMDGPU_UCODE_ID_CP_MEC2_JT:
2242                 *type = GFX_FW_TYPE_CP_MEC_ME2;
2243                 break;
2244         case AMDGPU_UCODE_ID_RLC_P:
2245                 *type = GFX_FW_TYPE_RLC_P;
2246                 break;
2247         case AMDGPU_UCODE_ID_RLC_V:
2248                 *type = GFX_FW_TYPE_RLC_V;
2249                 break;
2250         case AMDGPU_UCODE_ID_RLC_G:
2251                 *type = GFX_FW_TYPE_RLC_G;
2252                 break;
2253         case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL:
2254                 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_CNTL;
2255                 break;
2256         case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM:
2257                 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_GPM_MEM;
2258                 break;
2259         case AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM:
2260                 *type = GFX_FW_TYPE_RLC_RESTORE_LIST_SRM_MEM;
2261                 break;
2262         case AMDGPU_UCODE_ID_RLC_IRAM:
2263                 *type = GFX_FW_TYPE_RLC_IRAM;
2264                 break;
2265         case AMDGPU_UCODE_ID_RLC_DRAM:
2266                 *type = GFX_FW_TYPE_RLC_DRAM_BOOT;
2267                 break;
2268         case AMDGPU_UCODE_ID_GLOBAL_TAP_DELAYS:
2269                 *type = GFX_FW_TYPE_GLOBAL_TAP_DELAYS;
2270                 break;
2271         case AMDGPU_UCODE_ID_SE0_TAP_DELAYS:
2272                 *type = GFX_FW_TYPE_SE0_TAP_DELAYS;
2273                 break;
2274         case AMDGPU_UCODE_ID_SE1_TAP_DELAYS:
2275                 *type = GFX_FW_TYPE_SE1_TAP_DELAYS;
2276                 break;
2277         case AMDGPU_UCODE_ID_SE2_TAP_DELAYS:
2278                 *type = GFX_FW_TYPE_SE2_TAP_DELAYS;
2279                 break;
2280         case AMDGPU_UCODE_ID_SE3_TAP_DELAYS:
2281                 *type = GFX_FW_TYPE_SE3_TAP_DELAYS;
2282                 break;
2283         case AMDGPU_UCODE_ID_SMC:
2284                 *type = GFX_FW_TYPE_SMU;
2285                 break;
2286         case AMDGPU_UCODE_ID_PPTABLE:
2287                 *type = GFX_FW_TYPE_PPTABLE;
2288                 break;
2289         case AMDGPU_UCODE_ID_UVD:
2290                 *type = GFX_FW_TYPE_UVD;
2291                 break;
2292         case AMDGPU_UCODE_ID_UVD1:
2293                 *type = GFX_FW_TYPE_UVD1;
2294                 break;
2295         case AMDGPU_UCODE_ID_VCE:
2296                 *type = GFX_FW_TYPE_VCE;
2297                 break;
2298         case AMDGPU_UCODE_ID_VCN:
2299                 *type = GFX_FW_TYPE_VCN;
2300                 break;
2301         case AMDGPU_UCODE_ID_VCN1:
2302                 *type = GFX_FW_TYPE_VCN1;
2303                 break;
2304         case AMDGPU_UCODE_ID_DMCU_ERAM:
2305                 *type = GFX_FW_TYPE_DMCU_ERAM;
2306                 break;
2307         case AMDGPU_UCODE_ID_DMCU_INTV:
2308                 *type = GFX_FW_TYPE_DMCU_ISR;
2309                 break;
2310         case AMDGPU_UCODE_ID_VCN0_RAM:
2311                 *type = GFX_FW_TYPE_VCN0_RAM;
2312                 break;
2313         case AMDGPU_UCODE_ID_VCN1_RAM:
2314                 *type = GFX_FW_TYPE_VCN1_RAM;
2315                 break;
2316         case AMDGPU_UCODE_ID_DMCUB:
2317                 *type = GFX_FW_TYPE_DMUB;
2318                 break;
2319         case AMDGPU_UCODE_ID_SDMA_UCODE_TH0:
2320                 *type = GFX_FW_TYPE_SDMA_UCODE_TH0;
2321                 break;
2322         case AMDGPU_UCODE_ID_SDMA_UCODE_TH1:
2323                 *type = GFX_FW_TYPE_SDMA_UCODE_TH1;
2324                 break;
2325         case AMDGPU_UCODE_ID_IMU_I:
2326                 *type = GFX_FW_TYPE_IMU_I;
2327                 break;
2328         case AMDGPU_UCODE_ID_IMU_D:
2329                 *type = GFX_FW_TYPE_IMU_D;
2330                 break;
2331         case AMDGPU_UCODE_ID_CP_RS64_PFP:
2332                 *type = GFX_FW_TYPE_RS64_PFP;
2333                 break;
2334         case AMDGPU_UCODE_ID_CP_RS64_ME:
2335                 *type = GFX_FW_TYPE_RS64_ME;
2336                 break;
2337         case AMDGPU_UCODE_ID_CP_RS64_MEC:
2338                 *type = GFX_FW_TYPE_RS64_MEC;
2339                 break;
2340         case AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK:
2341                 *type = GFX_FW_TYPE_RS64_PFP_P0_STACK;
2342                 break;
2343         case AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK:
2344                 *type = GFX_FW_TYPE_RS64_PFP_P1_STACK;
2345                 break;
2346         case AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK:
2347                 *type = GFX_FW_TYPE_RS64_ME_P0_STACK;
2348                 break;
2349         case AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK:
2350                 *type = GFX_FW_TYPE_RS64_ME_P1_STACK;
2351                 break;
2352         case AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK:
2353                 *type = GFX_FW_TYPE_RS64_MEC_P0_STACK;
2354                 break;
2355         case AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK:
2356                 *type = GFX_FW_TYPE_RS64_MEC_P1_STACK;
2357                 break;
2358         case AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK:
2359                 *type = GFX_FW_TYPE_RS64_MEC_P2_STACK;
2360                 break;
2361         case AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK:
2362                 *type = GFX_FW_TYPE_RS64_MEC_P3_STACK;
2363                 break;
2364         case AMDGPU_UCODE_ID_MAXIMUM:
2365         default:
2366                 return -EINVAL;
2367         }
2368
2369         return 0;
2370 }
2371
2372 static void psp_print_fw_hdr(struct psp_context *psp,
2373                              struct amdgpu_firmware_info *ucode)
2374 {
2375         struct amdgpu_device *adev = psp->adev;
2376         struct common_firmware_header *hdr;
2377
2378         switch (ucode->ucode_id) {
2379         case AMDGPU_UCODE_ID_SDMA0:
2380         case AMDGPU_UCODE_ID_SDMA1:
2381         case AMDGPU_UCODE_ID_SDMA2:
2382         case AMDGPU_UCODE_ID_SDMA3:
2383         case AMDGPU_UCODE_ID_SDMA4:
2384         case AMDGPU_UCODE_ID_SDMA5:
2385         case AMDGPU_UCODE_ID_SDMA6:
2386         case AMDGPU_UCODE_ID_SDMA7:
2387                 hdr = (struct common_firmware_header *)
2388                         adev->sdma.instance[ucode->ucode_id - AMDGPU_UCODE_ID_SDMA0].fw->data;
2389                 amdgpu_ucode_print_sdma_hdr(hdr);
2390                 break;
2391         case AMDGPU_UCODE_ID_CP_CE:
2392                 hdr = (struct common_firmware_header *)adev->gfx.ce_fw->data;
2393                 amdgpu_ucode_print_gfx_hdr(hdr);
2394                 break;
2395         case AMDGPU_UCODE_ID_CP_PFP:
2396                 hdr = (struct common_firmware_header *)adev->gfx.pfp_fw->data;
2397                 amdgpu_ucode_print_gfx_hdr(hdr);
2398                 break;
2399         case AMDGPU_UCODE_ID_CP_ME:
2400                 hdr = (struct common_firmware_header *)adev->gfx.me_fw->data;
2401                 amdgpu_ucode_print_gfx_hdr(hdr);
2402                 break;
2403         case AMDGPU_UCODE_ID_CP_MEC1:
2404                 hdr = (struct common_firmware_header *)adev->gfx.mec_fw->data;
2405                 amdgpu_ucode_print_gfx_hdr(hdr);
2406                 break;
2407         case AMDGPU_UCODE_ID_RLC_G:
2408                 hdr = (struct common_firmware_header *)adev->gfx.rlc_fw->data;
2409                 amdgpu_ucode_print_rlc_hdr(hdr);
2410                 break;
2411         case AMDGPU_UCODE_ID_SMC:
2412                 hdr = (struct common_firmware_header *)adev->pm.fw->data;
2413                 amdgpu_ucode_print_smc_hdr(hdr);
2414                 break;
2415         default:
2416                 break;
2417         }
2418 }
2419
2420 static int psp_prep_load_ip_fw_cmd_buf(struct amdgpu_firmware_info *ucode,
2421                                        struct psp_gfx_cmd_resp *cmd)
2422 {
2423         int ret;
2424         uint64_t fw_mem_mc_addr = ucode->mc_addr;
2425
2426         cmd->cmd_id = GFX_CMD_ID_LOAD_IP_FW;
2427         cmd->cmd.cmd_load_ip_fw.fw_phy_addr_lo = lower_32_bits(fw_mem_mc_addr);
2428         cmd->cmd.cmd_load_ip_fw.fw_phy_addr_hi = upper_32_bits(fw_mem_mc_addr);
2429         cmd->cmd.cmd_load_ip_fw.fw_size = ucode->ucode_size;
2430
2431         ret = psp_get_fw_type(ucode, &cmd->cmd.cmd_load_ip_fw.fw_type);
2432         if (ret)
2433                 DRM_ERROR("Unknown firmware type\n");
2434
2435         return ret;
2436 }
2437
2438 static int psp_execute_non_psp_fw_load(struct psp_context *psp,
2439                                   struct amdgpu_firmware_info *ucode)
2440 {
2441         int ret = 0;
2442         struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
2443
2444         ret = psp_prep_load_ip_fw_cmd_buf(ucode, cmd);
2445         if (!ret) {
2446                 ret = psp_cmd_submit_buf(psp, ucode, cmd,
2447                                          psp->fence_buf_mc_addr);
2448         }
2449
2450         release_psp_cmd_buf(psp);
2451
2452         return ret;
2453 }
2454
2455 static int psp_load_smu_fw(struct psp_context *psp)
2456 {
2457         int ret;
2458         struct amdgpu_device *adev = psp->adev;
2459         struct amdgpu_firmware_info *ucode =
2460                         &adev->firmware.ucode[AMDGPU_UCODE_ID_SMC];
2461         struct amdgpu_ras *ras = psp->ras_context.ras;
2462
2463         /*
2464          * Skip SMU FW reloading in case of using BACO for runpm only,
2465          * as SMU is always alive.
2466          */
2467         if (adev->in_runpm && (adev->pm.rpm_mode == AMDGPU_RUNPM_BACO))
2468                 return 0;
2469
2470         if (!ucode->fw || amdgpu_sriov_vf(psp->adev))
2471                 return 0;
2472
2473         if ((amdgpu_in_reset(adev) &&
2474              ras && adev->ras_enabled &&
2475              (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 4) ||
2476               adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 2)))) {
2477                 ret = amdgpu_dpm_set_mp1_state(adev, PP_MP1_STATE_UNLOAD);
2478                 if (ret)
2479                         DRM_WARN("Failed to set MP1 state prepare for reload\n");
2480         }
2481
2482         ret = psp_execute_non_psp_fw_load(psp, ucode);
2483
2484         if (ret)
2485                 DRM_ERROR("PSP load smu failed!\n");
2486
2487         return ret;
2488 }
2489
2490 static bool fw_load_skip_check(struct psp_context *psp,
2491                                struct amdgpu_firmware_info *ucode)
2492 {
2493         if (!ucode->fw || !ucode->ucode_size)
2494                 return true;
2495
2496         if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC &&
2497             (psp_smu_reload_quirk(psp) ||
2498              psp->autoload_supported ||
2499              psp->pmfw_centralized_cstate_management))
2500                 return true;
2501
2502         if (amdgpu_sriov_vf(psp->adev) &&
2503             amdgpu_virt_fw_load_skip_check(psp->adev, ucode->ucode_id))
2504                 return true;
2505
2506         if (psp->autoload_supported &&
2507             (ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC1_JT ||
2508              ucode->ucode_id == AMDGPU_UCODE_ID_CP_MEC2_JT))
2509                 /* skip mec JT when autoload is enabled */
2510                 return true;
2511
2512         return false;
2513 }
2514
2515 int psp_load_fw_list(struct psp_context *psp,
2516                      struct amdgpu_firmware_info **ucode_list, int ucode_count)
2517 {
2518         int ret = 0, i;
2519         struct amdgpu_firmware_info *ucode;
2520
2521         for (i = 0; i < ucode_count; ++i) {
2522                 ucode = ucode_list[i];
2523                 psp_print_fw_hdr(psp, ucode);
2524                 ret = psp_execute_non_psp_fw_load(psp, ucode);
2525                 if (ret)
2526                         return ret;
2527         }
2528         return ret;
2529 }
2530
2531 static int psp_load_non_psp_fw(struct psp_context *psp)
2532 {
2533         int i, ret;
2534         struct amdgpu_firmware_info *ucode;
2535         struct amdgpu_device *adev = psp->adev;
2536
2537         if (psp->autoload_supported &&
2538             !psp->pmfw_centralized_cstate_management) {
2539                 ret = psp_load_smu_fw(psp);
2540                 if (ret)
2541                         return ret;
2542         }
2543
2544         for (i = 0; i < adev->firmware.max_ucodes; i++) {
2545                 ucode = &adev->firmware.ucode[i];
2546
2547                 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC &&
2548                     !fw_load_skip_check(psp, ucode)) {
2549                         ret = psp_load_smu_fw(psp);
2550                         if (ret)
2551                                 return ret;
2552                         continue;
2553                 }
2554
2555                 if (fw_load_skip_check(psp, ucode))
2556                         continue;
2557
2558                 if (psp->autoload_supported &&
2559                     (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7) ||
2560                      adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 11) ||
2561                      adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 12)) &&
2562                     (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1 ||
2563                      ucode->ucode_id == AMDGPU_UCODE_ID_SDMA2 ||
2564                      ucode->ucode_id == AMDGPU_UCODE_ID_SDMA3))
2565                         /* PSP only receive one SDMA fw for sienna_cichlid,
2566                          * as all four sdma fw are same */
2567                         continue;
2568
2569                 psp_print_fw_hdr(psp, ucode);
2570
2571                 ret = psp_execute_non_psp_fw_load(psp, ucode);
2572                 if (ret)
2573                         return ret;
2574
2575                 /* Start rlc autoload after psp recieved all the gfx firmware */
2576                 if (psp->autoload_supported && ucode->ucode_id == (amdgpu_sriov_vf(adev) ?
2577                     adev->virt.autoload_ucode_id : AMDGPU_UCODE_ID_RLC_G)) {
2578                         ret = psp_rlc_autoload_start(psp);
2579                         if (ret) {
2580                                 DRM_ERROR("Failed to start rlc autoload\n");
2581                                 return ret;
2582                         }
2583                 }
2584         }
2585
2586         return 0;
2587 }
2588
2589 static int psp_load_fw(struct amdgpu_device *adev)
2590 {
2591         int ret;
2592         struct psp_context *psp = &adev->psp;
2593
2594         if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) {
2595                 /* should not destroy ring, only stop */
2596                 psp_ring_stop(psp, PSP_RING_TYPE__KM);
2597         } else {
2598                 memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE);
2599
2600                 ret = psp_ring_init(psp, PSP_RING_TYPE__KM);
2601                 if (ret) {
2602                         DRM_ERROR("PSP ring init failed!\n");
2603                         goto failed;
2604                 }
2605         }
2606
2607         ret = psp_hw_start(psp);
2608         if (ret)
2609                 goto failed;
2610
2611         ret = psp_load_non_psp_fw(psp);
2612         if (ret)
2613                 goto failed1;
2614
2615         ret = psp_asd_initialize(psp);
2616         if (ret) {
2617                 DRM_ERROR("PSP load asd failed!\n");
2618                 goto failed1;
2619         }
2620
2621         ret = psp_rl_load(adev);
2622         if (ret) {
2623                 DRM_ERROR("PSP load RL failed!\n");
2624                 goto failed1;
2625         }
2626
2627         if (amdgpu_sriov_vf(adev) && amdgpu_in_reset(adev)) {
2628                 if (adev->gmc.xgmi.num_physical_nodes > 1) {
2629                         ret = psp_xgmi_initialize(psp, false, true);
2630                         /* Warning the XGMI seesion initialize failure
2631                         * Instead of stop driver initialization
2632                         */
2633                         if (ret)
2634                                 dev_err(psp->adev->dev,
2635                                         "XGMI: Failed to initialize XGMI session\n");
2636                 }
2637         }
2638
2639         if (psp->ta_fw) {
2640                 ret = psp_ras_initialize(psp);
2641                 if (ret)
2642                         dev_err(psp->adev->dev,
2643                                         "RAS: Failed to initialize RAS\n");
2644
2645                 ret = psp_hdcp_initialize(psp);
2646                 if (ret)
2647                         dev_err(psp->adev->dev,
2648                                 "HDCP: Failed to initialize HDCP\n");
2649
2650                 ret = psp_dtm_initialize(psp);
2651                 if (ret)
2652                         dev_err(psp->adev->dev,
2653                                 "DTM: Failed to initialize DTM\n");
2654
2655                 ret = psp_rap_initialize(psp);
2656                 if (ret)
2657                         dev_err(psp->adev->dev,
2658                                 "RAP: Failed to initialize RAP\n");
2659
2660                 ret = psp_securedisplay_initialize(psp);
2661                 if (ret)
2662                         dev_err(psp->adev->dev,
2663                                 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n");
2664         }
2665
2666         return 0;
2667
2668 failed1:
2669         psp_free_shared_bufs(psp);
2670 failed:
2671         /*
2672          * all cleanup jobs (xgmi terminate, ras terminate,
2673          * ring destroy, cmd/fence/fw buffers destory,
2674          * psp->cmd destory) are delayed to psp_hw_fini
2675          */
2676         psp_ring_destroy(psp, PSP_RING_TYPE__KM);
2677         return ret;
2678 }
2679
2680 static int psp_hw_init(void *handle)
2681 {
2682         int ret;
2683         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2684
2685         mutex_lock(&adev->firmware.mutex);
2686         /*
2687          * This sequence is just used on hw_init only once, no need on
2688          * resume.
2689          */
2690         ret = amdgpu_ucode_init_bo(adev);
2691         if (ret)
2692                 goto failed;
2693
2694         ret = psp_load_fw(adev);
2695         if (ret) {
2696                 DRM_ERROR("PSP firmware loading failed\n");
2697                 goto failed;
2698         }
2699
2700         mutex_unlock(&adev->firmware.mutex);
2701         return 0;
2702
2703 failed:
2704         adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT;
2705         mutex_unlock(&adev->firmware.mutex);
2706         return -EINVAL;
2707 }
2708
2709 static int psp_hw_fini(void *handle)
2710 {
2711         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2712         struct psp_context *psp = &adev->psp;
2713
2714         if (psp->ta_fw) {
2715                 psp_ras_terminate(psp);
2716                 psp_securedisplay_terminate(psp);
2717                 psp_rap_terminate(psp);
2718                 psp_dtm_terminate(psp);
2719                 psp_hdcp_terminate(psp);
2720
2721                 if (adev->gmc.xgmi.num_physical_nodes > 1)
2722                         psp_xgmi_terminate(psp);
2723         }
2724
2725         psp_asd_terminate(psp);
2726         psp_tmr_terminate(psp);
2727
2728         psp_ring_destroy(psp, PSP_RING_TYPE__KM);
2729
2730         return 0;
2731 }
2732
2733 static int psp_suspend(void *handle)
2734 {
2735         int ret = 0;
2736         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2737         struct psp_context *psp = &adev->psp;
2738
2739         if (adev->gmc.xgmi.num_physical_nodes > 1 &&
2740             psp->xgmi_context.context.initialized) {
2741                 ret = psp_xgmi_terminate(psp);
2742                 if (ret) {
2743                         DRM_ERROR("Failed to terminate xgmi ta\n");
2744                         goto out;
2745                 }
2746         }
2747
2748         if (psp->ta_fw) {
2749                 ret = psp_ras_terminate(psp);
2750                 if (ret) {
2751                         DRM_ERROR("Failed to terminate ras ta\n");
2752                         goto out;
2753                 }
2754                 ret = psp_hdcp_terminate(psp);
2755                 if (ret) {
2756                         DRM_ERROR("Failed to terminate hdcp ta\n");
2757                         goto out;
2758                 }
2759                 ret = psp_dtm_terminate(psp);
2760                 if (ret) {
2761                         DRM_ERROR("Failed to terminate dtm ta\n");
2762                         goto out;
2763                 }
2764                 ret = psp_rap_terminate(psp);
2765                 if (ret) {
2766                         DRM_ERROR("Failed to terminate rap ta\n");
2767                         goto out;
2768                 }
2769                 ret = psp_securedisplay_terminate(psp);
2770                 if (ret) {
2771                         DRM_ERROR("Failed to terminate securedisplay ta\n");
2772                         goto out;
2773                 }
2774         }
2775
2776         ret = psp_asd_terminate(psp);
2777         if (ret) {
2778                 DRM_ERROR("Failed to terminate asd\n");
2779                 goto out;
2780         }
2781
2782         ret = psp_tmr_terminate(psp);
2783         if (ret) {
2784                 DRM_ERROR("Failed to terminate tmr\n");
2785                 goto out;
2786         }
2787
2788         ret = psp_ring_stop(psp, PSP_RING_TYPE__KM);
2789         if (ret)
2790                 DRM_ERROR("PSP ring stop failed\n");
2791
2792 out:
2793         return ret;
2794 }
2795
2796 static int psp_resume(void *handle)
2797 {
2798         int ret;
2799         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
2800         struct psp_context *psp = &adev->psp;
2801
2802         DRM_INFO("PSP is resuming...\n");
2803
2804         if (psp->mem_train_ctx.enable_mem_training) {
2805                 ret = psp_mem_training(psp, PSP_MEM_TRAIN_RESUME);
2806                 if (ret) {
2807                         DRM_ERROR("Failed to process memory training!\n");
2808                         return ret;
2809                 }
2810         }
2811
2812         mutex_lock(&adev->firmware.mutex);
2813
2814         ret = psp_hw_start(psp);
2815         if (ret)
2816                 goto failed;
2817
2818         ret = psp_load_non_psp_fw(psp);
2819         if (ret)
2820                 goto failed;
2821
2822         ret = psp_asd_initialize(psp);
2823         if (ret) {
2824                 DRM_ERROR("PSP load asd failed!\n");
2825                 goto failed;
2826         }
2827
2828         ret = psp_rl_load(adev);
2829         if (ret) {
2830                 dev_err(adev->dev, "PSP load RL failed!\n");
2831                 goto failed;
2832         }
2833
2834         if (adev->gmc.xgmi.num_physical_nodes > 1) {
2835                 ret = psp_xgmi_initialize(psp, false, true);
2836                 /* Warning the XGMI seesion initialize failure
2837                  * Instead of stop driver initialization
2838                  */
2839                 if (ret)
2840                         dev_err(psp->adev->dev,
2841                                 "XGMI: Failed to initialize XGMI session\n");
2842         }
2843
2844         if (psp->ta_fw) {
2845                 ret = psp_ras_initialize(psp);
2846                 if (ret)
2847                         dev_err(psp->adev->dev,
2848                                         "RAS: Failed to initialize RAS\n");
2849
2850                 ret = psp_hdcp_initialize(psp);
2851                 if (ret)
2852                         dev_err(psp->adev->dev,
2853                                 "HDCP: Failed to initialize HDCP\n");
2854
2855                 ret = psp_dtm_initialize(psp);
2856                 if (ret)
2857                         dev_err(psp->adev->dev,
2858                                 "DTM: Failed to initialize DTM\n");
2859
2860                 ret = psp_rap_initialize(psp);
2861                 if (ret)
2862                         dev_err(psp->adev->dev,
2863                                 "RAP: Failed to initialize RAP\n");
2864
2865                 ret = psp_securedisplay_initialize(psp);
2866                 if (ret)
2867                         dev_err(psp->adev->dev,
2868                                 "SECUREDISPLAY: Failed to initialize SECUREDISPLAY\n");
2869         }
2870
2871         mutex_unlock(&adev->firmware.mutex);
2872
2873         return 0;
2874
2875 failed:
2876         DRM_ERROR("PSP resume failed\n");
2877         mutex_unlock(&adev->firmware.mutex);
2878         return ret;
2879 }
2880
2881 int psp_gpu_reset(struct amdgpu_device *adev)
2882 {
2883         int ret;
2884
2885         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
2886                 return 0;
2887
2888         mutex_lock(&adev->psp.mutex);
2889         ret = psp_mode1_reset(&adev->psp);
2890         mutex_unlock(&adev->psp.mutex);
2891
2892         return ret;
2893 }
2894
2895 int psp_rlc_autoload_start(struct psp_context *psp)
2896 {
2897         int ret;
2898         struct psp_gfx_cmd_resp *cmd = acquire_psp_cmd_buf(psp);
2899
2900         cmd->cmd_id = GFX_CMD_ID_AUTOLOAD_RLC;
2901
2902         ret = psp_cmd_submit_buf(psp, NULL, cmd,
2903                                  psp->fence_buf_mc_addr);
2904
2905         release_psp_cmd_buf(psp);
2906
2907         return ret;
2908 }
2909
2910 int psp_update_vcn_sram(struct amdgpu_device *adev, int inst_idx,
2911                         uint64_t cmd_gpu_addr, int cmd_size)
2912 {
2913         struct amdgpu_firmware_info ucode = {0};
2914
2915         ucode.ucode_id = inst_idx ? AMDGPU_UCODE_ID_VCN1_RAM :
2916                 AMDGPU_UCODE_ID_VCN0_RAM;
2917         ucode.mc_addr = cmd_gpu_addr;
2918         ucode.ucode_size = cmd_size;
2919
2920         return psp_execute_non_psp_fw_load(&adev->psp, &ucode);
2921 }
2922
2923 int psp_ring_cmd_submit(struct psp_context *psp,
2924                         uint64_t cmd_buf_mc_addr,
2925                         uint64_t fence_mc_addr,
2926                         int index)
2927 {
2928         unsigned int psp_write_ptr_reg = 0;
2929         struct psp_gfx_rb_frame *write_frame;
2930         struct psp_ring *ring = &psp->km_ring;
2931         struct psp_gfx_rb_frame *ring_buffer_start = ring->ring_mem;
2932         struct psp_gfx_rb_frame *ring_buffer_end = ring_buffer_start +
2933                 ring->ring_size / sizeof(struct psp_gfx_rb_frame) - 1;
2934         struct amdgpu_device *adev = psp->adev;
2935         uint32_t ring_size_dw = ring->ring_size / 4;
2936         uint32_t rb_frame_size_dw = sizeof(struct psp_gfx_rb_frame) / 4;
2937
2938         /* KM (GPCOM) prepare write pointer */
2939         psp_write_ptr_reg = psp_ring_get_wptr(psp);
2940
2941         /* Update KM RB frame pointer to new frame */
2942         /* write_frame ptr increments by size of rb_frame in bytes */
2943         /* psp_write_ptr_reg increments by size of rb_frame in DWORDs */
2944         if ((psp_write_ptr_reg % ring_size_dw) == 0)
2945                 write_frame = ring_buffer_start;
2946         else
2947                 write_frame = ring_buffer_start + (psp_write_ptr_reg / rb_frame_size_dw);
2948         /* Check invalid write_frame ptr address */
2949         if ((write_frame < ring_buffer_start) || (ring_buffer_end < write_frame)) {
2950                 DRM_ERROR("ring_buffer_start = %p; ring_buffer_end = %p; write_frame = %p\n",
2951                           ring_buffer_start, ring_buffer_end, write_frame);
2952                 DRM_ERROR("write_frame is pointing to address out of bounds\n");
2953                 return -EINVAL;
2954         }
2955
2956         /* Initialize KM RB frame */
2957         memset(write_frame, 0, sizeof(struct psp_gfx_rb_frame));
2958
2959         /* Update KM RB frame */
2960         write_frame->cmd_buf_addr_hi = upper_32_bits(cmd_buf_mc_addr);
2961         write_frame->cmd_buf_addr_lo = lower_32_bits(cmd_buf_mc_addr);
2962         write_frame->fence_addr_hi = upper_32_bits(fence_mc_addr);
2963         write_frame->fence_addr_lo = lower_32_bits(fence_mc_addr);
2964         write_frame->fence_value = index;
2965         amdgpu_device_flush_hdp(adev, NULL);
2966
2967         /* Update the write Pointer in DWORDs */
2968         psp_write_ptr_reg = (psp_write_ptr_reg + rb_frame_size_dw) % ring_size_dw;
2969         psp_ring_set_wptr(psp, psp_write_ptr_reg);
2970         return 0;
2971 }
2972
2973 int psp_init_asd_microcode(struct psp_context *psp, const char *chip_name)
2974 {
2975         struct amdgpu_device *adev = psp->adev;
2976         char fw_name[PSP_FW_NAME_LEN];
2977         const struct psp_firmware_header_v1_0 *asd_hdr;
2978         int err = 0;
2979
2980         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_asd.bin", chip_name);
2981         err = amdgpu_ucode_request(adev, &adev->psp.asd_fw, fw_name);
2982         if (err)
2983                 goto out;
2984
2985         asd_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.asd_fw->data;
2986         adev->psp.asd_context.bin_desc.fw_version = le32_to_cpu(asd_hdr->header.ucode_version);
2987         adev->psp.asd_context.bin_desc.feature_version = le32_to_cpu(asd_hdr->sos.fw_version);
2988         adev->psp.asd_context.bin_desc.size_bytes = le32_to_cpu(asd_hdr->header.ucode_size_bytes);
2989         adev->psp.asd_context.bin_desc.start_addr = (uint8_t *)asd_hdr +
2990                                 le32_to_cpu(asd_hdr->header.ucode_array_offset_bytes);
2991         return 0;
2992 out:
2993         amdgpu_ucode_release(&adev->psp.asd_fw);
2994         return err;
2995 }
2996
2997 int psp_init_toc_microcode(struct psp_context *psp, const char *chip_name)
2998 {
2999         struct amdgpu_device *adev = psp->adev;
3000         char fw_name[PSP_FW_NAME_LEN];
3001         const struct psp_firmware_header_v1_0 *toc_hdr;
3002         int err = 0;
3003
3004         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_toc.bin", chip_name);
3005         err = amdgpu_ucode_request(adev, &adev->psp.toc_fw, fw_name);
3006         if (err)
3007                 goto out;
3008
3009         toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data;
3010         adev->psp.toc.fw_version = le32_to_cpu(toc_hdr->header.ucode_version);
3011         adev->psp.toc.feature_version = le32_to_cpu(toc_hdr->sos.fw_version);
3012         adev->psp.toc.size_bytes = le32_to_cpu(toc_hdr->header.ucode_size_bytes);
3013         adev->psp.toc.start_addr = (uint8_t *)toc_hdr +
3014                                 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes);
3015         return 0;
3016 out:
3017         amdgpu_ucode_release(&adev->psp.toc_fw);
3018         return err;
3019 }
3020
3021 static int parse_sos_bin_descriptor(struct psp_context *psp,
3022                                    const struct psp_fw_bin_desc *desc,
3023                                    const struct psp_firmware_header_v2_0 *sos_hdr)
3024 {
3025         uint8_t *ucode_start_addr  = NULL;
3026
3027         if (!psp || !desc || !sos_hdr)
3028                 return -EINVAL;
3029
3030         ucode_start_addr  = (uint8_t *)sos_hdr +
3031                             le32_to_cpu(desc->offset_bytes) +
3032                             le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes);
3033
3034         switch (desc->fw_type) {
3035         case PSP_FW_TYPE_PSP_SOS:
3036                 psp->sos.fw_version        = le32_to_cpu(desc->fw_version);
3037                 psp->sos.feature_version   = le32_to_cpu(desc->fw_version);
3038                 psp->sos.size_bytes        = le32_to_cpu(desc->size_bytes);
3039                 psp->sos.start_addr        = ucode_start_addr;
3040                 break;
3041         case PSP_FW_TYPE_PSP_SYS_DRV:
3042                 psp->sys.fw_version        = le32_to_cpu(desc->fw_version);
3043                 psp->sys.feature_version   = le32_to_cpu(desc->fw_version);
3044                 psp->sys.size_bytes        = le32_to_cpu(desc->size_bytes);
3045                 psp->sys.start_addr        = ucode_start_addr;
3046                 break;
3047         case PSP_FW_TYPE_PSP_KDB:
3048                 psp->kdb.fw_version        = le32_to_cpu(desc->fw_version);
3049                 psp->kdb.feature_version   = le32_to_cpu(desc->fw_version);
3050                 psp->kdb.size_bytes        = le32_to_cpu(desc->size_bytes);
3051                 psp->kdb.start_addr        = ucode_start_addr;
3052                 break;
3053         case PSP_FW_TYPE_PSP_TOC:
3054                 psp->toc.fw_version        = le32_to_cpu(desc->fw_version);
3055                 psp->toc.feature_version   = le32_to_cpu(desc->fw_version);
3056                 psp->toc.size_bytes        = le32_to_cpu(desc->size_bytes);
3057                 psp->toc.start_addr        = ucode_start_addr;
3058                 break;
3059         case PSP_FW_TYPE_PSP_SPL:
3060                 psp->spl.fw_version        = le32_to_cpu(desc->fw_version);
3061                 psp->spl.feature_version   = le32_to_cpu(desc->fw_version);
3062                 psp->spl.size_bytes        = le32_to_cpu(desc->size_bytes);
3063                 psp->spl.start_addr        = ucode_start_addr;
3064                 break;
3065         case PSP_FW_TYPE_PSP_RL:
3066                 psp->rl.fw_version         = le32_to_cpu(desc->fw_version);
3067                 psp->rl.feature_version    = le32_to_cpu(desc->fw_version);
3068                 psp->rl.size_bytes         = le32_to_cpu(desc->size_bytes);
3069                 psp->rl.start_addr         = ucode_start_addr;
3070                 break;
3071         case PSP_FW_TYPE_PSP_SOC_DRV:
3072                 psp->soc_drv.fw_version         = le32_to_cpu(desc->fw_version);
3073                 psp->soc_drv.feature_version    = le32_to_cpu(desc->fw_version);
3074                 psp->soc_drv.size_bytes         = le32_to_cpu(desc->size_bytes);
3075                 psp->soc_drv.start_addr         = ucode_start_addr;
3076                 break;
3077         case PSP_FW_TYPE_PSP_INTF_DRV:
3078                 psp->intf_drv.fw_version        = le32_to_cpu(desc->fw_version);
3079                 psp->intf_drv.feature_version   = le32_to_cpu(desc->fw_version);
3080                 psp->intf_drv.size_bytes        = le32_to_cpu(desc->size_bytes);
3081                 psp->intf_drv.start_addr        = ucode_start_addr;
3082                 break;
3083         case PSP_FW_TYPE_PSP_DBG_DRV:
3084                 psp->dbg_drv.fw_version         = le32_to_cpu(desc->fw_version);
3085                 psp->dbg_drv.feature_version    = le32_to_cpu(desc->fw_version);
3086                 psp->dbg_drv.size_bytes         = le32_to_cpu(desc->size_bytes);
3087                 psp->dbg_drv.start_addr         = ucode_start_addr;
3088                 break;
3089         case PSP_FW_TYPE_PSP_RAS_DRV:
3090                 psp->ras_drv.fw_version         = le32_to_cpu(desc->fw_version);
3091                 psp->ras_drv.feature_version    = le32_to_cpu(desc->fw_version);
3092                 psp->ras_drv.size_bytes         = le32_to_cpu(desc->size_bytes);
3093                 psp->ras_drv.start_addr         = ucode_start_addr;
3094                 break;
3095         default:
3096                 dev_warn(psp->adev->dev, "Unsupported PSP FW type: %d\n", desc->fw_type);
3097                 break;
3098         }
3099
3100         return 0;
3101 }
3102
3103 static int psp_init_sos_base_fw(struct amdgpu_device *adev)
3104 {
3105         const struct psp_firmware_header_v1_0 *sos_hdr;
3106         const struct psp_firmware_header_v1_3 *sos_hdr_v1_3;
3107         uint8_t *ucode_array_start_addr;
3108
3109         sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data;
3110         ucode_array_start_addr = (uint8_t *)sos_hdr +
3111                 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes);
3112
3113         if (adev->gmc.xgmi.connected_to_cpu ||
3114             (adev->ip_versions[MP0_HWIP][0] != IP_VERSION(13, 0, 2))) {
3115                 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr->header.ucode_version);
3116                 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr->sos.fw_version);
3117
3118                 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr->sos.offset_bytes);
3119                 adev->psp.sys.start_addr = ucode_array_start_addr;
3120
3121                 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr->sos.size_bytes);
3122                 adev->psp.sos.start_addr = ucode_array_start_addr +
3123                                 le32_to_cpu(sos_hdr->sos.offset_bytes);
3124         } else {
3125                 /* Load alternate PSP SOS FW */
3126                 sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data;
3127
3128                 adev->psp.sos.fw_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version);
3129                 adev->psp.sos.feature_version = le32_to_cpu(sos_hdr_v1_3->sos_aux.fw_version);
3130
3131                 adev->psp.sys.size_bytes = le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.size_bytes);
3132                 adev->psp.sys.start_addr = ucode_array_start_addr +
3133                         le32_to_cpu(sos_hdr_v1_3->sys_drv_aux.offset_bytes);
3134
3135                 adev->psp.sos.size_bytes = le32_to_cpu(sos_hdr_v1_3->sos_aux.size_bytes);
3136                 adev->psp.sos.start_addr = ucode_array_start_addr +
3137                         le32_to_cpu(sos_hdr_v1_3->sos_aux.offset_bytes);
3138         }
3139
3140         if ((adev->psp.sys.size_bytes == 0) || (adev->psp.sos.size_bytes == 0)) {
3141                 dev_warn(adev->dev, "PSP SOS FW not available");
3142                 return -EINVAL;
3143         }
3144
3145         return 0;
3146 }
3147
3148 int psp_init_sos_microcode(struct psp_context *psp, const char *chip_name)
3149 {
3150         struct amdgpu_device *adev = psp->adev;
3151         char fw_name[PSP_FW_NAME_LEN];
3152         const struct psp_firmware_header_v1_0 *sos_hdr;
3153         const struct psp_firmware_header_v1_1 *sos_hdr_v1_1;
3154         const struct psp_firmware_header_v1_2 *sos_hdr_v1_2;
3155         const struct psp_firmware_header_v1_3 *sos_hdr_v1_3;
3156         const struct psp_firmware_header_v2_0 *sos_hdr_v2_0;
3157         int err = 0;
3158         uint8_t *ucode_array_start_addr;
3159         int fw_index = 0;
3160
3161         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sos.bin", chip_name);
3162         err = amdgpu_ucode_request(adev, &adev->psp.sos_fw, fw_name);
3163         if (err)
3164                 goto out;
3165
3166         sos_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.sos_fw->data;
3167         ucode_array_start_addr = (uint8_t *)sos_hdr +
3168                 le32_to_cpu(sos_hdr->header.ucode_array_offset_bytes);
3169         amdgpu_ucode_print_psp_hdr(&sos_hdr->header);
3170
3171         switch (sos_hdr->header.header_version_major) {
3172         case 1:
3173                 err = psp_init_sos_base_fw(adev);
3174                 if (err)
3175                         goto out;
3176
3177                 if (sos_hdr->header.header_version_minor == 1) {
3178                         sos_hdr_v1_1 = (const struct psp_firmware_header_v1_1 *)adev->psp.sos_fw->data;
3179                         adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_1->toc.size_bytes);
3180                         adev->psp.toc.start_addr = (uint8_t *)adev->psp.sys.start_addr +
3181                                         le32_to_cpu(sos_hdr_v1_1->toc.offset_bytes);
3182                         adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_1->kdb.size_bytes);
3183                         adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr +
3184                                         le32_to_cpu(sos_hdr_v1_1->kdb.offset_bytes);
3185                 }
3186                 if (sos_hdr->header.header_version_minor == 2) {
3187                         sos_hdr_v1_2 = (const struct psp_firmware_header_v1_2 *)adev->psp.sos_fw->data;
3188                         adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_2->kdb.size_bytes);
3189                         adev->psp.kdb.start_addr = (uint8_t *)adev->psp.sys.start_addr +
3190                                                     le32_to_cpu(sos_hdr_v1_2->kdb.offset_bytes);
3191                 }
3192                 if (sos_hdr->header.header_version_minor == 3) {
3193                         sos_hdr_v1_3 = (const struct psp_firmware_header_v1_3 *)adev->psp.sos_fw->data;
3194                         adev->psp.toc.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.toc.size_bytes);
3195                         adev->psp.toc.start_addr = ucode_array_start_addr +
3196                                 le32_to_cpu(sos_hdr_v1_3->v1_1.toc.offset_bytes);
3197                         adev->psp.kdb.size_bytes = le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.size_bytes);
3198                         adev->psp.kdb.start_addr = ucode_array_start_addr +
3199                                 le32_to_cpu(sos_hdr_v1_3->v1_1.kdb.offset_bytes);
3200                         adev->psp.spl.size_bytes = le32_to_cpu(sos_hdr_v1_3->spl.size_bytes);
3201                         adev->psp.spl.start_addr = ucode_array_start_addr +
3202                                 le32_to_cpu(sos_hdr_v1_3->spl.offset_bytes);
3203                         adev->psp.rl.size_bytes = le32_to_cpu(sos_hdr_v1_3->rl.size_bytes);
3204                         adev->psp.rl.start_addr = ucode_array_start_addr +
3205                                 le32_to_cpu(sos_hdr_v1_3->rl.offset_bytes);
3206                 }
3207                 break;
3208         case 2:
3209                 sos_hdr_v2_0 = (const struct psp_firmware_header_v2_0 *)adev->psp.sos_fw->data;
3210
3211                 if (le32_to_cpu(sos_hdr_v2_0->psp_fw_bin_count) >= UCODE_MAX_PSP_PACKAGING) {
3212                         dev_err(adev->dev, "packed SOS count exceeds maximum limit\n");
3213                         err = -EINVAL;
3214                         goto out;
3215                 }
3216
3217                 for (fw_index = 0; fw_index < le32_to_cpu(sos_hdr_v2_0->psp_fw_bin_count); fw_index++) {
3218                         err = parse_sos_bin_descriptor(psp,
3219                                                        &sos_hdr_v2_0->psp_fw_bin[fw_index],
3220                                                        sos_hdr_v2_0);
3221                         if (err)
3222                                 goto out;
3223                 }
3224                 break;
3225         default:
3226                 dev_err(adev->dev,
3227                         "unsupported psp sos firmware\n");
3228                 err = -EINVAL;
3229                 goto out;
3230         }
3231
3232         return 0;
3233 out:
3234         amdgpu_ucode_release(&adev->psp.sos_fw);
3235
3236         return err;
3237 }
3238
3239 static int parse_ta_bin_descriptor(struct psp_context *psp,
3240                                    const struct psp_fw_bin_desc *desc,
3241                                    const struct ta_firmware_header_v2_0 *ta_hdr)
3242 {
3243         uint8_t *ucode_start_addr  = NULL;
3244
3245         if (!psp || !desc || !ta_hdr)
3246                 return -EINVAL;
3247
3248         ucode_start_addr  = (uint8_t *)ta_hdr +
3249                             le32_to_cpu(desc->offset_bytes) +
3250                             le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes);
3251
3252         switch (desc->fw_type) {
3253         case TA_FW_TYPE_PSP_ASD:
3254                 psp->asd_context.bin_desc.fw_version        = le32_to_cpu(desc->fw_version);
3255                 psp->asd_context.bin_desc.feature_version   = le32_to_cpu(desc->fw_version);
3256                 psp->asd_context.bin_desc.size_bytes        = le32_to_cpu(desc->size_bytes);
3257                 psp->asd_context.bin_desc.start_addr        = ucode_start_addr;
3258                 break;
3259         case TA_FW_TYPE_PSP_XGMI:
3260                 psp->xgmi_context.context.bin_desc.fw_version       = le32_to_cpu(desc->fw_version);
3261                 psp->xgmi_context.context.bin_desc.size_bytes       = le32_to_cpu(desc->size_bytes);
3262                 psp->xgmi_context.context.bin_desc.start_addr       = ucode_start_addr;
3263                 break;
3264         case TA_FW_TYPE_PSP_RAS:
3265                 psp->ras_context.context.bin_desc.fw_version        = le32_to_cpu(desc->fw_version);
3266                 psp->ras_context.context.bin_desc.size_bytes        = le32_to_cpu(desc->size_bytes);
3267                 psp->ras_context.context.bin_desc.start_addr        = ucode_start_addr;
3268                 break;
3269         case TA_FW_TYPE_PSP_HDCP:
3270                 psp->hdcp_context.context.bin_desc.fw_version       = le32_to_cpu(desc->fw_version);
3271                 psp->hdcp_context.context.bin_desc.size_bytes       = le32_to_cpu(desc->size_bytes);
3272                 psp->hdcp_context.context.bin_desc.start_addr       = ucode_start_addr;
3273                 break;
3274         case TA_FW_TYPE_PSP_DTM:
3275                 psp->dtm_context.context.bin_desc.fw_version       = le32_to_cpu(desc->fw_version);
3276                 psp->dtm_context.context.bin_desc.size_bytes       = le32_to_cpu(desc->size_bytes);
3277                 psp->dtm_context.context.bin_desc.start_addr       = ucode_start_addr;
3278                 break;
3279         case TA_FW_TYPE_PSP_RAP:
3280                 psp->rap_context.context.bin_desc.fw_version       = le32_to_cpu(desc->fw_version);
3281                 psp->rap_context.context.bin_desc.size_bytes       = le32_to_cpu(desc->size_bytes);
3282                 psp->rap_context.context.bin_desc.start_addr       = ucode_start_addr;
3283                 break;
3284         case TA_FW_TYPE_PSP_SECUREDISPLAY:
3285                 psp->securedisplay_context.context.bin_desc.fw_version =
3286                         le32_to_cpu(desc->fw_version);
3287                 psp->securedisplay_context.context.bin_desc.size_bytes =
3288                         le32_to_cpu(desc->size_bytes);
3289                 psp->securedisplay_context.context.bin_desc.start_addr =
3290                         ucode_start_addr;
3291                 break;
3292         default:
3293                 dev_warn(psp->adev->dev, "Unsupported TA type: %d\n", desc->fw_type);
3294                 break;
3295         }
3296
3297         return 0;
3298 }
3299
3300 static int parse_ta_v1_microcode(struct psp_context *psp)
3301 {
3302         const struct ta_firmware_header_v1_0 *ta_hdr;
3303         struct amdgpu_device *adev = psp->adev;
3304
3305         ta_hdr = (const struct ta_firmware_header_v1_0 *) adev->psp.ta_fw->data;
3306
3307         if (le16_to_cpu(ta_hdr->header.header_version_major) != 1)
3308                 return -EINVAL;
3309
3310         adev->psp.xgmi_context.context.bin_desc.fw_version =
3311                 le32_to_cpu(ta_hdr->xgmi.fw_version);
3312         adev->psp.xgmi_context.context.bin_desc.size_bytes =
3313                 le32_to_cpu(ta_hdr->xgmi.size_bytes);
3314         adev->psp.xgmi_context.context.bin_desc.start_addr =
3315                 (uint8_t *)ta_hdr +
3316                 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes);
3317
3318         adev->psp.ras_context.context.bin_desc.fw_version =
3319                 le32_to_cpu(ta_hdr->ras.fw_version);
3320         adev->psp.ras_context.context.bin_desc.size_bytes =
3321                 le32_to_cpu(ta_hdr->ras.size_bytes);
3322         adev->psp.ras_context.context.bin_desc.start_addr =
3323                 (uint8_t *)adev->psp.xgmi_context.context.bin_desc.start_addr +
3324                 le32_to_cpu(ta_hdr->ras.offset_bytes);
3325
3326         adev->psp.hdcp_context.context.bin_desc.fw_version =
3327                 le32_to_cpu(ta_hdr->hdcp.fw_version);
3328         adev->psp.hdcp_context.context.bin_desc.size_bytes =
3329                 le32_to_cpu(ta_hdr->hdcp.size_bytes);
3330         adev->psp.hdcp_context.context.bin_desc.start_addr =
3331                 (uint8_t *)ta_hdr +
3332                 le32_to_cpu(ta_hdr->header.ucode_array_offset_bytes);
3333
3334         adev->psp.dtm_context.context.bin_desc.fw_version =
3335                 le32_to_cpu(ta_hdr->dtm.fw_version);
3336         adev->psp.dtm_context.context.bin_desc.size_bytes =
3337                 le32_to_cpu(ta_hdr->dtm.size_bytes);
3338         adev->psp.dtm_context.context.bin_desc.start_addr =
3339                 (uint8_t *)adev->psp.hdcp_context.context.bin_desc.start_addr +
3340                 le32_to_cpu(ta_hdr->dtm.offset_bytes);
3341
3342         adev->psp.securedisplay_context.context.bin_desc.fw_version =
3343                 le32_to_cpu(ta_hdr->securedisplay.fw_version);
3344         adev->psp.securedisplay_context.context.bin_desc.size_bytes =
3345                 le32_to_cpu(ta_hdr->securedisplay.size_bytes);
3346         adev->psp.securedisplay_context.context.bin_desc.start_addr =
3347                 (uint8_t *)adev->psp.hdcp_context.context.bin_desc.start_addr +
3348                 le32_to_cpu(ta_hdr->securedisplay.offset_bytes);
3349
3350         adev->psp.ta_fw_version = le32_to_cpu(ta_hdr->header.ucode_version);
3351
3352         return 0;
3353 }
3354
3355 static int parse_ta_v2_microcode(struct psp_context *psp)
3356 {
3357         const struct ta_firmware_header_v2_0 *ta_hdr;
3358         struct amdgpu_device *adev = psp->adev;
3359         int err = 0;
3360         int ta_index = 0;
3361
3362         ta_hdr = (const struct ta_firmware_header_v2_0 *)adev->psp.ta_fw->data;
3363
3364         if (le16_to_cpu(ta_hdr->header.header_version_major) != 2)
3365                 return -EINVAL;
3366
3367         if (le32_to_cpu(ta_hdr->ta_fw_bin_count) >= UCODE_MAX_PSP_PACKAGING) {
3368                 dev_err(adev->dev, "packed TA count exceeds maximum limit\n");
3369                 return -EINVAL;
3370         }
3371
3372         for (ta_index = 0; ta_index < le32_to_cpu(ta_hdr->ta_fw_bin_count); ta_index++) {
3373                 err = parse_ta_bin_descriptor(psp,
3374                                               &ta_hdr->ta_fw_bin[ta_index],
3375                                               ta_hdr);
3376                 if (err)
3377                         return err;
3378         }
3379
3380         return 0;
3381 }
3382
3383 int psp_init_ta_microcode(struct psp_context *psp, const char *chip_name)
3384 {
3385         const struct common_firmware_header *hdr;
3386         struct amdgpu_device *adev = psp->adev;
3387         char fw_name[PSP_FW_NAME_LEN];
3388         int err;
3389
3390         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ta.bin", chip_name);
3391         err = amdgpu_ucode_request(adev, &adev->psp.ta_fw, fw_name);
3392         if (err)
3393                 return err;
3394
3395         hdr = (const struct common_firmware_header *)adev->psp.ta_fw->data;
3396         switch (le16_to_cpu(hdr->header_version_major)) {
3397         case 1:
3398                 err = parse_ta_v1_microcode(psp);
3399                 break;
3400         case 2:
3401                 err = parse_ta_v2_microcode(psp);
3402                 break;
3403         default:
3404                 dev_err(adev->dev, "unsupported TA header version\n");
3405                 err = -EINVAL;
3406         }
3407
3408         if (err)
3409                 amdgpu_ucode_release(&adev->psp.ta_fw);
3410
3411         return err;
3412 }
3413
3414 int psp_init_cap_microcode(struct psp_context *psp, const char *chip_name)
3415 {
3416         struct amdgpu_device *adev = psp->adev;
3417         char fw_name[PSP_FW_NAME_LEN];
3418         const struct psp_firmware_header_v1_0 *cap_hdr_v1_0;
3419         struct amdgpu_firmware_info *info = NULL;
3420         int err = 0;
3421
3422         if (!amdgpu_sriov_vf(adev)) {
3423                 dev_err(adev->dev, "cap microcode should only be loaded under SRIOV\n");
3424                 return -EINVAL;
3425         }
3426
3427         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_cap.bin", chip_name);
3428         err = amdgpu_ucode_request(adev, &adev->psp.cap_fw, fw_name);
3429         if (err) {
3430                 if (err == -ENODEV) {
3431                         dev_warn(adev->dev, "cap microcode does not exist, skip\n");
3432                         err = 0;
3433                         goto out;
3434                 }
3435                 dev_err(adev->dev, "fail to initialize cap microcode\n");
3436         }
3437
3438         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CAP];
3439         info->ucode_id = AMDGPU_UCODE_ID_CAP;
3440         info->fw = adev->psp.cap_fw;
3441         cap_hdr_v1_0 = (const struct psp_firmware_header_v1_0 *)
3442                 adev->psp.cap_fw->data;
3443         adev->firmware.fw_size += ALIGN(
3444                         le32_to_cpu(cap_hdr_v1_0->header.ucode_size_bytes), PAGE_SIZE);
3445         adev->psp.cap_fw_version = le32_to_cpu(cap_hdr_v1_0->header.ucode_version);
3446         adev->psp.cap_feature_version = le32_to_cpu(cap_hdr_v1_0->sos.fw_version);
3447         adev->psp.cap_ucode_size = le32_to_cpu(cap_hdr_v1_0->header.ucode_size_bytes);
3448
3449         return 0;
3450
3451 out:
3452         amdgpu_ucode_release(&adev->psp.cap_fw);
3453         return err;
3454 }
3455
3456 static int psp_set_clockgating_state(void *handle,
3457                                      enum amd_clockgating_state state)
3458 {
3459         return 0;
3460 }
3461
3462 static int psp_set_powergating_state(void *handle,
3463                                      enum amd_powergating_state state)
3464 {
3465         return 0;
3466 }
3467
3468 static ssize_t psp_usbc_pd_fw_sysfs_read(struct device *dev,
3469                                          struct device_attribute *attr,
3470                                          char *buf)
3471 {
3472         struct drm_device *ddev = dev_get_drvdata(dev);
3473         struct amdgpu_device *adev = drm_to_adev(ddev);
3474         uint32_t fw_ver;
3475         int ret;
3476
3477         if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) {
3478                 DRM_INFO("PSP block is not ready yet.");
3479                 return -EBUSY;
3480         }
3481
3482         mutex_lock(&adev->psp.mutex);
3483         ret = psp_read_usbc_pd_fw(&adev->psp, &fw_ver);
3484         mutex_unlock(&adev->psp.mutex);
3485
3486         if (ret) {
3487                 DRM_ERROR("Failed to read USBC PD FW, err = %d", ret);
3488                 return ret;
3489         }
3490
3491         return sysfs_emit(buf, "%x\n", fw_ver);
3492 }
3493
3494 static ssize_t psp_usbc_pd_fw_sysfs_write(struct device *dev,
3495                                                        struct device_attribute *attr,
3496                                                        const char *buf,
3497                                                        size_t count)
3498 {
3499         struct drm_device *ddev = dev_get_drvdata(dev);
3500         struct amdgpu_device *adev = drm_to_adev(ddev);
3501         int ret, idx;
3502         char fw_name[100];
3503         const struct firmware *usbc_pd_fw;
3504         struct amdgpu_bo *fw_buf_bo = NULL;
3505         uint64_t fw_pri_mc_addr;
3506         void *fw_pri_cpu_addr;
3507
3508         if (!adev->ip_blocks[AMD_IP_BLOCK_TYPE_PSP].status.late_initialized) {
3509                 DRM_INFO("PSP block is not ready yet.");
3510                 return -EBUSY;
3511         }
3512
3513         if (!drm_dev_enter(ddev, &idx))
3514                 return -ENODEV;
3515
3516         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s", buf);
3517         ret = request_firmware(&usbc_pd_fw, fw_name, adev->dev);
3518         if (ret)
3519                 goto fail;
3520
3521         /* LFB address which is aligned to 1MB boundary per PSP request */
3522         ret = amdgpu_bo_create_kernel(adev, usbc_pd_fw->size, 0x100000,
3523                                       AMDGPU_GEM_DOMAIN_VRAM |
3524                                       AMDGPU_GEM_DOMAIN_GTT,
3525                                       &fw_buf_bo, &fw_pri_mc_addr,
3526                                       &fw_pri_cpu_addr);
3527         if (ret)
3528                 goto rel_buf;
3529
3530         memcpy_toio(fw_pri_cpu_addr, usbc_pd_fw->data, usbc_pd_fw->size);
3531
3532         mutex_lock(&adev->psp.mutex);
3533         ret = psp_load_usbc_pd_fw(&adev->psp, fw_pri_mc_addr);
3534         mutex_unlock(&adev->psp.mutex);
3535
3536         amdgpu_bo_free_kernel(&fw_buf_bo, &fw_pri_mc_addr, &fw_pri_cpu_addr);
3537
3538 rel_buf:
3539         release_firmware(usbc_pd_fw);
3540 fail:
3541         if (ret) {
3542                 DRM_ERROR("Failed to load USBC PD FW, err = %d", ret);
3543                 count = ret;
3544         }
3545
3546         drm_dev_exit(idx);
3547         return count;
3548 }
3549
3550 void psp_copy_fw(struct psp_context *psp, uint8_t *start_addr, uint32_t bin_size)
3551 {
3552         int idx;
3553
3554         if (!drm_dev_enter(adev_to_drm(psp->adev), &idx))
3555                 return;
3556
3557         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
3558         memcpy(psp->fw_pri_buf, start_addr, bin_size);
3559
3560         drm_dev_exit(idx);
3561 }
3562
3563 static DEVICE_ATTR(usbc_pd_fw, 0644,
3564                    psp_usbc_pd_fw_sysfs_read,
3565                    psp_usbc_pd_fw_sysfs_write);
3566
3567 int is_psp_fw_valid(struct psp_bin_desc bin)
3568 {
3569         return bin.size_bytes;
3570 }
3571
3572 static ssize_t amdgpu_psp_vbflash_write(struct file *filp, struct kobject *kobj,
3573                                         struct bin_attribute *bin_attr,
3574                                         char *buffer, loff_t pos, size_t count)
3575 {
3576         struct device *dev = kobj_to_dev(kobj);
3577         struct drm_device *ddev = dev_get_drvdata(dev);
3578         struct amdgpu_device *adev = drm_to_adev(ddev);
3579
3580         adev->psp.vbflash_done = false;
3581
3582         /* Safeguard against memory drain */
3583         if (adev->psp.vbflash_image_size > AMD_VBIOS_FILE_MAX_SIZE_B) {
3584                 dev_err(adev->dev, "File size cannot exceed %u", AMD_VBIOS_FILE_MAX_SIZE_B);
3585                 kvfree(adev->psp.vbflash_tmp_buf);
3586                 adev->psp.vbflash_tmp_buf = NULL;
3587                 adev->psp.vbflash_image_size = 0;
3588                 return -ENOMEM;
3589         }
3590
3591         /* TODO Just allocate max for now and optimize to realloc later if needed */
3592         if (!adev->psp.vbflash_tmp_buf) {
3593                 adev->psp.vbflash_tmp_buf = kvmalloc(AMD_VBIOS_FILE_MAX_SIZE_B, GFP_KERNEL);
3594                 if (!adev->psp.vbflash_tmp_buf)
3595                         return -ENOMEM;
3596         }
3597
3598         mutex_lock(&adev->psp.mutex);
3599         memcpy(adev->psp.vbflash_tmp_buf + pos, buffer, count);
3600         adev->psp.vbflash_image_size += count;
3601         mutex_unlock(&adev->psp.mutex);
3602
3603         dev_info(adev->dev, "VBIOS flash write PSP done");
3604
3605         return count;
3606 }
3607
3608 static ssize_t amdgpu_psp_vbflash_read(struct file *filp, struct kobject *kobj,
3609                                        struct bin_attribute *bin_attr, char *buffer,
3610                                        loff_t pos, size_t count)
3611 {
3612         struct device *dev = kobj_to_dev(kobj);
3613         struct drm_device *ddev = dev_get_drvdata(dev);
3614         struct amdgpu_device *adev = drm_to_adev(ddev);
3615         struct amdgpu_bo *fw_buf_bo = NULL;
3616         uint64_t fw_pri_mc_addr;
3617         void *fw_pri_cpu_addr;
3618         int ret;
3619
3620         if (adev->psp.vbflash_image_size == 0)
3621                 return -EINVAL;
3622
3623         dev_info(adev->dev, "VBIOS flash to PSP started");
3624
3625         ret = amdgpu_bo_create_kernel(adev, adev->psp.vbflash_image_size,
3626                                         AMDGPU_GPU_PAGE_SIZE,
3627                                         AMDGPU_GEM_DOMAIN_VRAM,
3628                                         &fw_buf_bo,
3629                                         &fw_pri_mc_addr,
3630                                         &fw_pri_cpu_addr);
3631         if (ret)
3632                 goto rel_buf;
3633
3634         memcpy_toio(fw_pri_cpu_addr, adev->psp.vbflash_tmp_buf, adev->psp.vbflash_image_size);
3635
3636         mutex_lock(&adev->psp.mutex);
3637         ret = psp_update_spirom(&adev->psp, fw_pri_mc_addr);
3638         mutex_unlock(&adev->psp.mutex);
3639
3640         amdgpu_bo_free_kernel(&fw_buf_bo, &fw_pri_mc_addr, &fw_pri_cpu_addr);
3641
3642 rel_buf:
3643         kvfree(adev->psp.vbflash_tmp_buf);
3644         adev->psp.vbflash_tmp_buf = NULL;
3645         adev->psp.vbflash_image_size = 0;
3646
3647         if (ret) {
3648                 dev_err(adev->dev, "Failed to load VBIOS FW, err = %d", ret);
3649                 return ret;
3650         }
3651
3652         dev_info(adev->dev, "VBIOS flash to PSP done");
3653         return 0;
3654 }
3655
3656 static ssize_t amdgpu_psp_vbflash_status(struct device *dev,
3657                                          struct device_attribute *attr,
3658                                          char *buf)
3659 {
3660         struct drm_device *ddev = dev_get_drvdata(dev);
3661         struct amdgpu_device *adev = drm_to_adev(ddev);
3662         uint32_t vbflash_status;
3663
3664         vbflash_status = psp_vbflash_status(&adev->psp);
3665         if (!adev->psp.vbflash_done)
3666                 vbflash_status = 0;
3667         else if (adev->psp.vbflash_done && !(vbflash_status & 0x80000000))
3668                 vbflash_status = 1;
3669
3670         return sysfs_emit(buf, "0x%x\n", vbflash_status);
3671 }
3672
3673 static const struct bin_attribute psp_vbflash_bin_attr = {
3674         .attr = {.name = "psp_vbflash", .mode = 0660},
3675         .size = 0,
3676         .write = amdgpu_psp_vbflash_write,
3677         .read = amdgpu_psp_vbflash_read,
3678 };
3679
3680 static DEVICE_ATTR(psp_vbflash_status, 0440, amdgpu_psp_vbflash_status, NULL);
3681
3682 int amdgpu_psp_sysfs_init(struct amdgpu_device *adev)
3683 {
3684         int ret = 0;
3685         struct psp_context *psp = &adev->psp;
3686
3687         if (amdgpu_sriov_vf(adev))
3688                 return -EINVAL;
3689
3690         switch (adev->ip_versions[MP0_HWIP][0]) {
3691         case IP_VERSION(13, 0, 0):
3692         case IP_VERSION(13, 0, 7):
3693         case IP_VERSION(13, 0, 10):
3694                 if (!psp->adev) {
3695                         psp->adev = adev;
3696                         psp_v13_0_set_psp_funcs(psp);
3697                 }
3698                 ret = sysfs_create_bin_file(&adev->dev->kobj, &psp_vbflash_bin_attr);
3699                 if (ret)
3700                         dev_err(adev->dev, "Failed to create device file psp_vbflash");
3701                 ret = device_create_file(adev->dev, &dev_attr_psp_vbflash_status);
3702                 if (ret)
3703                         dev_err(adev->dev, "Failed to create device file psp_vbflash_status");
3704                 return ret;
3705         default:
3706                 return 0;
3707         }
3708 }
3709
3710 const struct amd_ip_funcs psp_ip_funcs = {
3711         .name = "psp",
3712         .early_init = psp_early_init,
3713         .late_init = NULL,
3714         .sw_init = psp_sw_init,
3715         .sw_fini = psp_sw_fini,
3716         .hw_init = psp_hw_init,
3717         .hw_fini = psp_hw_fini,
3718         .suspend = psp_suspend,
3719         .resume = psp_resume,
3720         .is_idle = NULL,
3721         .check_soft_reset = NULL,
3722         .wait_for_idle = NULL,
3723         .soft_reset = NULL,
3724         .set_clockgating_state = psp_set_clockgating_state,
3725         .set_powergating_state = psp_set_powergating_state,
3726 };
3727
3728 static int psp_sysfs_init(struct amdgpu_device *adev)
3729 {
3730         int ret = device_create_file(adev->dev, &dev_attr_usbc_pd_fw);
3731
3732         if (ret)
3733                 DRM_ERROR("Failed to create USBC PD FW control file!");
3734
3735         return ret;
3736 }
3737
3738 void amdgpu_psp_sysfs_fini(struct amdgpu_device *adev)
3739 {
3740         sysfs_remove_bin_file(&adev->dev->kobj, &psp_vbflash_bin_attr);
3741         device_remove_file(adev->dev, &dev_attr_psp_vbflash_status);
3742 }
3743
3744 static void psp_sysfs_fini(struct amdgpu_device *adev)
3745 {
3746         device_remove_file(adev->dev, &dev_attr_usbc_pd_fw);
3747 }
3748
3749 const struct amdgpu_ip_block_version psp_v3_1_ip_block = {
3750         .type = AMD_IP_BLOCK_TYPE_PSP,
3751         .major = 3,
3752         .minor = 1,
3753         .rev = 0,
3754         .funcs = &psp_ip_funcs,
3755 };
3756
3757 const struct amdgpu_ip_block_version psp_v10_0_ip_block = {
3758         .type = AMD_IP_BLOCK_TYPE_PSP,
3759         .major = 10,
3760         .minor = 0,
3761         .rev = 0,
3762         .funcs = &psp_ip_funcs,
3763 };
3764
3765 const struct amdgpu_ip_block_version psp_v11_0_ip_block = {
3766         .type = AMD_IP_BLOCK_TYPE_PSP,
3767         .major = 11,
3768         .minor = 0,
3769         .rev = 0,
3770         .funcs = &psp_ip_funcs,
3771 };
3772
3773 const struct amdgpu_ip_block_version psp_v11_0_8_ip_block = {
3774         .type = AMD_IP_BLOCK_TYPE_PSP,
3775         .major = 11,
3776         .minor = 0,
3777         .rev = 8,
3778         .funcs = &psp_ip_funcs,
3779 };
3780
3781 const struct amdgpu_ip_block_version psp_v12_0_ip_block = {
3782         .type = AMD_IP_BLOCK_TYPE_PSP,
3783         .major = 12,
3784         .minor = 0,
3785         .rev = 0,
3786         .funcs = &psp_ip_funcs,
3787 };
3788
3789 const struct amdgpu_ip_block_version psp_v13_0_ip_block = {
3790         .type = AMD_IP_BLOCK_TYPE_PSP,
3791         .major = 13,
3792         .minor = 0,
3793         .rev = 0,
3794         .funcs = &psp_ip_funcs,
3795 };
3796
3797 const struct amdgpu_ip_block_version psp_v13_0_4_ip_block = {
3798         .type = AMD_IP_BLOCK_TYPE_PSP,
3799         .major = 13,
3800         .minor = 0,
3801         .rev = 4,
3802         .funcs = &psp_ip_funcs,
3803 };