2 * Copyright 2009 Jerome Glisse.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
31 #include <linux/seq_file.h>
32 #include <linux/atomic.h>
33 #include <linux/wait.h>
34 #include <linux/kref.h>
35 #include <linux/slab.h>
36 #include <linux/firmware.h>
37 #include <linux/pm_runtime.h>
39 #include <drm/drm_drv.h>
41 #include "amdgpu_trace.h"
42 #include "amdgpu_reset.h"
45 * Fences mark an event in the GPUs pipeline and are used
46 * for GPU/CPU synchronization. When the fence is written,
47 * it is expected that all buffers associated with that fence
48 * are no longer in use by the associated ring on the GPU and
49 * that the relevant GPU caches have been flushed.
53 struct dma_fence base;
56 struct amdgpu_ring *ring;
57 ktime_t start_timestamp;
60 static struct kmem_cache *amdgpu_fence_slab;
62 int amdgpu_fence_slab_init(void)
64 amdgpu_fence_slab = kmem_cache_create(
65 "amdgpu_fence", sizeof(struct amdgpu_fence), 0,
66 SLAB_HWCACHE_ALIGN, NULL);
67 if (!amdgpu_fence_slab)
72 void amdgpu_fence_slab_fini(void)
75 kmem_cache_destroy(amdgpu_fence_slab);
80 static const struct dma_fence_ops amdgpu_fence_ops;
81 static const struct dma_fence_ops amdgpu_job_fence_ops;
82 static inline struct amdgpu_fence *to_amdgpu_fence(struct dma_fence *f)
84 struct amdgpu_fence *__f = container_of(f, struct amdgpu_fence, base);
86 if (__f->base.ops == &amdgpu_fence_ops ||
87 __f->base.ops == &amdgpu_job_fence_ops)
94 * amdgpu_fence_write - write a fence value
96 * @ring: ring the fence is associated with
97 * @seq: sequence number to write
99 * Writes a fence value to memory (all asics).
101 static void amdgpu_fence_write(struct amdgpu_ring *ring, u32 seq)
103 struct amdgpu_fence_driver *drv = &ring->fence_drv;
106 *drv->cpu_addr = cpu_to_le32(seq);
110 * amdgpu_fence_read - read a fence value
112 * @ring: ring the fence is associated with
114 * Reads a fence value from memory (all asics).
115 * Returns the value of the fence read from memory.
117 static u32 amdgpu_fence_read(struct amdgpu_ring *ring)
119 struct amdgpu_fence_driver *drv = &ring->fence_drv;
123 seq = le32_to_cpu(*drv->cpu_addr);
125 seq = atomic_read(&drv->last_seq);
131 * amdgpu_fence_emit - emit a fence on the requested ring
133 * @ring: ring the fence is associated with
134 * @f: resulting fence object
135 * @job: job the fence is embedded in
136 * @flags: flags to pass into the subordinate .emit_fence() call
138 * Emits a fence command on the requested ring (all asics).
139 * Returns 0 on success, -ENOMEM on failure.
141 int amdgpu_fence_emit(struct amdgpu_ring *ring, struct dma_fence **f, struct amdgpu_job *job,
144 struct amdgpu_device *adev = ring->adev;
145 struct dma_fence *fence;
146 struct amdgpu_fence *am_fence;
147 struct dma_fence __rcu **ptr;
152 /* create a sperate hw fence */
153 am_fence = kmem_cache_alloc(amdgpu_fence_slab, GFP_ATOMIC);
154 if (am_fence == NULL)
156 fence = &am_fence->base;
157 am_fence->ring = ring;
159 /* take use of job-embedded fence */
160 fence = &job->hw_fence;
163 seq = ++ring->fence_drv.sync_seq;
164 if (job && job->job_run_counter) {
165 /* reinit seq for resubmitted jobs */
167 /* TO be inline with external fence creation and other drivers */
168 dma_fence_get(fence);
171 dma_fence_init(fence, &amdgpu_job_fence_ops,
172 &ring->fence_drv.lock,
173 adev->fence_context + ring->idx, seq);
174 /* Against remove in amdgpu_job_{free, free_cb} */
175 dma_fence_get(fence);
177 dma_fence_init(fence, &amdgpu_fence_ops,
178 &ring->fence_drv.lock,
179 adev->fence_context + ring->idx, seq);
183 amdgpu_ring_emit_fence(ring, ring->fence_drv.gpu_addr,
184 seq, flags | AMDGPU_FENCE_FLAG_INT);
185 pm_runtime_get_noresume(adev_to_drm(adev)->dev);
186 ptr = &ring->fence_drv.fences[seq & ring->fence_drv.num_fences_mask];
187 if (unlikely(rcu_dereference_protected(*ptr, 1))) {
188 struct dma_fence *old;
191 old = dma_fence_get_rcu_safe(ptr);
195 r = dma_fence_wait(old, false);
202 to_amdgpu_fence(fence)->start_timestamp = ktime_get();
204 /* This function can't be called concurrently anyway, otherwise
205 * emitting the fence would mess up the hardware ring buffer.
207 rcu_assign_pointer(*ptr, dma_fence_get(fence));
215 * amdgpu_fence_emit_polling - emit a fence on the requeste ring
217 * @ring: ring the fence is associated with
218 * @s: resulting sequence number
219 * @timeout: the timeout for waiting in usecs
221 * Emits a fence command on the requested ring (all asics).
222 * Used For polling fence.
223 * Returns 0 on success, -ENOMEM on failure.
225 int amdgpu_fence_emit_polling(struct amdgpu_ring *ring, uint32_t *s,
234 seq = ++ring->fence_drv.sync_seq;
235 r = amdgpu_fence_wait_polling(ring,
236 seq - ring->fence_drv.num_fences_mask,
241 amdgpu_ring_emit_fence(ring, ring->fence_drv.gpu_addr,
250 * amdgpu_fence_schedule_fallback - schedule fallback check
252 * @ring: pointer to struct amdgpu_ring
254 * Start a timer as fallback to our interrupts.
256 static void amdgpu_fence_schedule_fallback(struct amdgpu_ring *ring)
258 mod_timer(&ring->fence_drv.fallback_timer,
259 jiffies + AMDGPU_FENCE_JIFFIES_TIMEOUT);
263 * amdgpu_fence_process - check for fence activity
265 * @ring: pointer to struct amdgpu_ring
267 * Checks the current fence value and calculates the last
268 * signalled fence value. Wakes the fence queue if the
269 * sequence number has increased.
271 * Returns true if fence was processed
273 bool amdgpu_fence_process(struct amdgpu_ring *ring)
275 struct amdgpu_fence_driver *drv = &ring->fence_drv;
276 struct amdgpu_device *adev = ring->adev;
277 uint32_t seq, last_seq;
280 last_seq = atomic_read(&ring->fence_drv.last_seq);
281 seq = amdgpu_fence_read(ring);
283 } while (atomic_cmpxchg(&drv->last_seq, last_seq, seq) != last_seq);
285 if (del_timer(&ring->fence_drv.fallback_timer) &&
286 seq != ring->fence_drv.sync_seq)
287 amdgpu_fence_schedule_fallback(ring);
289 if (unlikely(seq == last_seq))
292 last_seq &= drv->num_fences_mask;
293 seq &= drv->num_fences_mask;
296 struct dma_fence *fence, **ptr;
299 last_seq &= drv->num_fences_mask;
300 ptr = &drv->fences[last_seq];
302 /* There is always exactly one thread signaling this fence slot */
303 fence = rcu_dereference_protected(*ptr, 1);
304 RCU_INIT_POINTER(*ptr, NULL);
309 dma_fence_signal(fence);
310 dma_fence_put(fence);
311 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
312 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
313 } while (last_seq != seq);
319 * amdgpu_fence_fallback - fallback for hardware interrupts
321 * @t: timer context used to obtain the pointer to ring structure
323 * Checks for fence activity.
325 static void amdgpu_fence_fallback(struct timer_list *t)
327 struct amdgpu_ring *ring = from_timer(ring, t,
328 fence_drv.fallback_timer);
330 if (amdgpu_fence_process(ring))
331 DRM_WARN("Fence fallback timer expired on ring %s\n", ring->name);
335 * amdgpu_fence_wait_empty - wait for all fences to signal
337 * @ring: ring index the fence is associated with
339 * Wait for all fences on the requested ring to signal (all asics).
340 * Returns 0 if the fences have passed, error for all other cases.
342 int amdgpu_fence_wait_empty(struct amdgpu_ring *ring)
344 uint64_t seq = READ_ONCE(ring->fence_drv.sync_seq);
345 struct dma_fence *fence, **ptr;
351 ptr = &ring->fence_drv.fences[seq & ring->fence_drv.num_fences_mask];
353 fence = rcu_dereference(*ptr);
354 if (!fence || !dma_fence_get_rcu(fence)) {
360 r = dma_fence_wait(fence, false);
361 dma_fence_put(fence);
366 * amdgpu_fence_wait_polling - busy wait for givn sequence number
368 * @ring: ring index the fence is associated with
369 * @wait_seq: sequence number to wait
370 * @timeout: the timeout for waiting in usecs
372 * Wait for all fences on the requested ring to signal (all asics).
373 * Returns left time if no timeout, 0 or minus if timeout.
375 signed long amdgpu_fence_wait_polling(struct amdgpu_ring *ring,
380 while ((int32_t)(wait_seq - amdgpu_fence_read(ring)) > 0 && timeout > 0) {
384 return timeout > 0 ? timeout : 0;
387 * amdgpu_fence_count_emitted - get the count of emitted fences
389 * @ring: ring the fence is associated with
391 * Get the number of fences emitted on the requested ring (all asics).
392 * Returns the number of emitted fences on the ring. Used by the
393 * dynpm code to ring track activity.
395 unsigned int amdgpu_fence_count_emitted(struct amdgpu_ring *ring)
399 /* We are not protected by ring lock when reading the last sequence
400 * but it's ok to report slightly wrong fence count here.
402 emitted = 0x100000000ull;
403 emitted -= atomic_read(&ring->fence_drv.last_seq);
404 emitted += READ_ONCE(ring->fence_drv.sync_seq);
405 return lower_32_bits(emitted);
409 * amdgpu_fence_last_unsignaled_time_us - the time fence emitted until now
410 * @ring: ring the fence is associated with
412 * Find the earliest fence unsignaled until now, calculate the time delta
413 * between the time fence emitted and now.
415 u64 amdgpu_fence_last_unsignaled_time_us(struct amdgpu_ring *ring)
417 struct amdgpu_fence_driver *drv = &ring->fence_drv;
418 struct dma_fence *fence;
419 uint32_t last_seq, sync_seq;
421 last_seq = atomic_read(&ring->fence_drv.last_seq);
422 sync_seq = READ_ONCE(ring->fence_drv.sync_seq);
423 if (last_seq == sync_seq)
427 last_seq &= drv->num_fences_mask;
428 fence = drv->fences[last_seq];
432 return ktime_us_delta(ktime_get(),
433 to_amdgpu_fence(fence)->start_timestamp);
437 * amdgpu_fence_update_start_timestamp - update the timestamp of the fence
438 * @ring: ring the fence is associated with
439 * @seq: the fence seq number to update.
440 * @timestamp: the start timestamp to update.
442 * The function called at the time the fence and related ib is about to
443 * resubmit to gpu in MCBP scenario. Thus we do not consider race condition
444 * with amdgpu_fence_process to modify the same fence.
446 void amdgpu_fence_update_start_timestamp(struct amdgpu_ring *ring, uint32_t seq, ktime_t timestamp)
448 struct amdgpu_fence_driver *drv = &ring->fence_drv;
449 struct dma_fence *fence;
451 seq &= drv->num_fences_mask;
452 fence = drv->fences[seq];
456 to_amdgpu_fence(fence)->start_timestamp = timestamp;
460 * amdgpu_fence_driver_start_ring - make the fence driver
461 * ready for use on the requested ring.
463 * @ring: ring to start the fence driver on
464 * @irq_src: interrupt source to use for this ring
465 * @irq_type: interrupt type to use for this ring
467 * Make the fence driver ready for processing (all asics).
468 * Not all asics have all rings, so each asic will only
469 * start the fence driver on the rings it has.
470 * Returns 0 for success, errors for failure.
472 int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring,
473 struct amdgpu_irq_src *irq_src,
474 unsigned int irq_type)
476 struct amdgpu_device *adev = ring->adev;
479 if (ring->funcs->type != AMDGPU_RING_TYPE_UVD) {
480 ring->fence_drv.cpu_addr = ring->fence_cpu_addr;
481 ring->fence_drv.gpu_addr = ring->fence_gpu_addr;
483 /* put fence directly behind firmware */
484 index = ALIGN(adev->uvd.fw->size, 8);
485 ring->fence_drv.cpu_addr = adev->uvd.inst[ring->me].cpu_addr + index;
486 ring->fence_drv.gpu_addr = adev->uvd.inst[ring->me].gpu_addr + index;
488 amdgpu_fence_write(ring, atomic_read(&ring->fence_drv.last_seq));
490 ring->fence_drv.irq_src = irq_src;
491 ring->fence_drv.irq_type = irq_type;
492 ring->fence_drv.initialized = true;
494 DRM_DEV_DEBUG(adev->dev, "fence driver on ring %s use gpu addr 0x%016llx\n",
495 ring->name, ring->fence_drv.gpu_addr);
500 * amdgpu_fence_driver_init_ring - init the fence driver
501 * for the requested ring.
503 * @ring: ring to init the fence driver on
505 * Init the fence driver for the requested ring (all asics).
506 * Helper function for amdgpu_fence_driver_init().
508 int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring)
510 struct amdgpu_device *adev = ring->adev;
515 if (!is_power_of_2(ring->num_hw_submission))
518 ring->fence_drv.cpu_addr = NULL;
519 ring->fence_drv.gpu_addr = 0;
520 ring->fence_drv.sync_seq = 0;
521 atomic_set(&ring->fence_drv.last_seq, 0);
522 ring->fence_drv.initialized = false;
524 timer_setup(&ring->fence_drv.fallback_timer, amdgpu_fence_fallback, 0);
526 ring->fence_drv.num_fences_mask = ring->num_hw_submission * 2 - 1;
527 spin_lock_init(&ring->fence_drv.lock);
528 ring->fence_drv.fences = kcalloc(ring->num_hw_submission * 2, sizeof(void *),
531 if (!ring->fence_drv.fences)
538 * amdgpu_fence_driver_sw_init - init the fence driver
539 * for all possible rings.
541 * @adev: amdgpu device pointer
543 * Init the fence driver for all possible rings (all asics).
544 * Not all asics have all rings, so each asic will only
545 * start the fence driver on the rings it has using
546 * amdgpu_fence_driver_start_ring().
547 * Returns 0 for success.
549 int amdgpu_fence_driver_sw_init(struct amdgpu_device *adev)
555 * amdgpu_fence_driver_hw_fini - tear down the fence driver
556 * for all possible rings.
558 * @adev: amdgpu device pointer
560 * Tear down the fence driver for all possible rings (all asics).
562 void amdgpu_fence_driver_hw_fini(struct amdgpu_device *adev)
566 for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
567 struct amdgpu_ring *ring = adev->rings[i];
569 if (!ring || !ring->fence_drv.initialized)
572 /* You can't wait for HW to signal if it's gone */
573 if (!drm_dev_is_unplugged(adev_to_drm(adev)))
574 r = amdgpu_fence_wait_empty(ring);
577 /* no need to trigger GPU reset as we are unloading */
579 amdgpu_fence_driver_force_completion(ring);
581 if (!drm_dev_is_unplugged(adev_to_drm(adev)) &&
582 ring->fence_drv.irq_src)
583 amdgpu_irq_put(adev, ring->fence_drv.irq_src,
584 ring->fence_drv.irq_type);
586 del_timer_sync(&ring->fence_drv.fallback_timer);
590 /* Will either stop and flush handlers for amdgpu interrupt or reanble it */
591 void amdgpu_fence_driver_isr_toggle(struct amdgpu_device *adev, bool stop)
595 for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
596 struct amdgpu_ring *ring = adev->rings[i];
598 if (!ring || !ring->fence_drv.initialized || !ring->fence_drv.irq_src)
602 disable_irq(adev->irq.irq);
604 enable_irq(adev->irq.irq);
608 void amdgpu_fence_driver_sw_fini(struct amdgpu_device *adev)
612 for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
613 struct amdgpu_ring *ring = adev->rings[i];
615 if (!ring || !ring->fence_drv.initialized)
619 * Notice we check for sched.ops since there's some
620 * override on the meaning of sched.ready by amdgpu.
621 * The natural check would be sched.ready, which is
622 * set as drm_sched_init() finishes...
625 drm_sched_fini(&ring->sched);
627 for (j = 0; j <= ring->fence_drv.num_fences_mask; ++j)
628 dma_fence_put(ring->fence_drv.fences[j]);
629 kfree(ring->fence_drv.fences);
630 ring->fence_drv.fences = NULL;
631 ring->fence_drv.initialized = false;
636 * amdgpu_fence_driver_hw_init - enable the fence driver
637 * for all possible rings.
639 * @adev: amdgpu device pointer
641 * Enable the fence driver for all possible rings (all asics).
642 * Not all asics have all rings, so each asic will only
643 * start the fence driver on the rings it has using
644 * amdgpu_fence_driver_start_ring().
645 * Returns 0 for success.
647 void amdgpu_fence_driver_hw_init(struct amdgpu_device *adev)
651 for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
652 struct amdgpu_ring *ring = adev->rings[i];
654 if (!ring || !ring->fence_drv.initialized)
657 /* enable the interrupt */
658 if (ring->fence_drv.irq_src)
659 amdgpu_irq_get(adev, ring->fence_drv.irq_src,
660 ring->fence_drv.irq_type);
665 * amdgpu_fence_driver_clear_job_fences - clear job embedded fences of ring
667 * @ring: fence of the ring to be cleared
670 void amdgpu_fence_driver_clear_job_fences(struct amdgpu_ring *ring)
673 struct dma_fence *old, **ptr;
675 for (i = 0; i <= ring->fence_drv.num_fences_mask; i++) {
676 ptr = &ring->fence_drv.fences[i];
677 old = rcu_dereference_protected(*ptr, 1);
678 if (old && old->ops == &amdgpu_job_fence_ops) {
679 struct amdgpu_job *job;
681 /* For non-scheduler bad job, i.e. failed ib test, we need to signal
682 * it right here or we won't be able to track them in fence_drv
683 * and they will remain unsignaled during sa_bo free.
685 job = container_of(old, struct amdgpu_job, hw_fence);
686 if (!job->base.s_fence && !dma_fence_is_signaled(old))
687 dma_fence_signal(old);
688 RCU_INIT_POINTER(*ptr, NULL);
695 * amdgpu_fence_driver_force_completion - force signal latest fence of ring
697 * @ring: fence of the ring to signal
700 void amdgpu_fence_driver_force_completion(struct amdgpu_ring *ring)
702 amdgpu_fence_write(ring, ring->fence_drv.sync_seq);
703 amdgpu_fence_process(ring);
707 * Common fence implementation
710 static const char *amdgpu_fence_get_driver_name(struct dma_fence *fence)
715 static const char *amdgpu_fence_get_timeline_name(struct dma_fence *f)
717 return (const char *)to_amdgpu_fence(f)->ring->name;
720 static const char *amdgpu_job_fence_get_timeline_name(struct dma_fence *f)
722 struct amdgpu_job *job = container_of(f, struct amdgpu_job, hw_fence);
724 return (const char *)to_amdgpu_ring(job->base.sched)->name;
728 * amdgpu_fence_enable_signaling - enable signalling on fence
731 * This function is called with fence_queue lock held, and adds a callback
732 * to fence_queue that checks if this fence is signaled, and if so it
733 * signals the fence and removes itself.
735 static bool amdgpu_fence_enable_signaling(struct dma_fence *f)
737 if (!timer_pending(&to_amdgpu_fence(f)->ring->fence_drv.fallback_timer))
738 amdgpu_fence_schedule_fallback(to_amdgpu_fence(f)->ring);
744 * amdgpu_job_fence_enable_signaling - enable signalling on job fence
747 * This is the simliar function with amdgpu_fence_enable_signaling above, it
748 * only handles the job embedded fence.
750 static bool amdgpu_job_fence_enable_signaling(struct dma_fence *f)
752 struct amdgpu_job *job = container_of(f, struct amdgpu_job, hw_fence);
754 if (!timer_pending(&to_amdgpu_ring(job->base.sched)->fence_drv.fallback_timer))
755 amdgpu_fence_schedule_fallback(to_amdgpu_ring(job->base.sched));
761 * amdgpu_fence_free - free up the fence memory
763 * @rcu: RCU callback head
765 * Free up the fence memory after the RCU grace period.
767 static void amdgpu_fence_free(struct rcu_head *rcu)
769 struct dma_fence *f = container_of(rcu, struct dma_fence, rcu);
771 /* free fence_slab if it's separated fence*/
772 kmem_cache_free(amdgpu_fence_slab, to_amdgpu_fence(f));
776 * amdgpu_job_fence_free - free up the job with embedded fence
778 * @rcu: RCU callback head
780 * Free up the job with embedded fence after the RCU grace period.
782 static void amdgpu_job_fence_free(struct rcu_head *rcu)
784 struct dma_fence *f = container_of(rcu, struct dma_fence, rcu);
786 /* free job if fence has a parent job */
787 kfree(container_of(f, struct amdgpu_job, hw_fence));
791 * amdgpu_fence_release - callback that fence can be freed
795 * This function is called when the reference count becomes zero.
796 * It just RCU schedules freeing up the fence.
798 static void amdgpu_fence_release(struct dma_fence *f)
800 call_rcu(&f->rcu, amdgpu_fence_free);
804 * amdgpu_job_fence_release - callback that job embedded fence can be freed
808 * This is the simliar function with amdgpu_fence_release above, it
809 * only handles the job embedded fence.
811 static void amdgpu_job_fence_release(struct dma_fence *f)
813 call_rcu(&f->rcu, amdgpu_job_fence_free);
816 static const struct dma_fence_ops amdgpu_fence_ops = {
817 .get_driver_name = amdgpu_fence_get_driver_name,
818 .get_timeline_name = amdgpu_fence_get_timeline_name,
819 .enable_signaling = amdgpu_fence_enable_signaling,
820 .release = amdgpu_fence_release,
823 static const struct dma_fence_ops amdgpu_job_fence_ops = {
824 .get_driver_name = amdgpu_fence_get_driver_name,
825 .get_timeline_name = amdgpu_job_fence_get_timeline_name,
826 .enable_signaling = amdgpu_job_fence_enable_signaling,
827 .release = amdgpu_job_fence_release,
833 #if defined(CONFIG_DEBUG_FS)
834 static int amdgpu_debugfs_fence_info_show(struct seq_file *m, void *unused)
836 struct amdgpu_device *adev = m->private;
839 for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
840 struct amdgpu_ring *ring = adev->rings[i];
842 if (!ring || !ring->fence_drv.initialized)
845 amdgpu_fence_process(ring);
847 seq_printf(m, "--- ring %d (%s) ---\n", i, ring->name);
848 seq_printf(m, "Last signaled fence 0x%08x\n",
849 atomic_read(&ring->fence_drv.last_seq));
850 seq_printf(m, "Last emitted 0x%08x\n",
851 ring->fence_drv.sync_seq);
853 if (ring->funcs->type == AMDGPU_RING_TYPE_GFX ||
854 ring->funcs->type == AMDGPU_RING_TYPE_SDMA) {
855 seq_printf(m, "Last signaled trailing fence 0x%08x\n",
856 le32_to_cpu(*ring->trail_fence_cpu_addr));
857 seq_printf(m, "Last emitted 0x%08x\n",
861 if (ring->funcs->type != AMDGPU_RING_TYPE_GFX)
864 /* set in CP_VMID_PREEMPT and preemption occurred */
865 seq_printf(m, "Last preempted 0x%08x\n",
866 le32_to_cpu(*(ring->fence_drv.cpu_addr + 2)));
867 /* set in CP_VMID_RESET and reset occurred */
868 seq_printf(m, "Last reset 0x%08x\n",
869 le32_to_cpu(*(ring->fence_drv.cpu_addr + 4)));
870 /* Both preemption and reset occurred */
871 seq_printf(m, "Last both 0x%08x\n",
872 le32_to_cpu(*(ring->fence_drv.cpu_addr + 6)));
878 * amdgpu_debugfs_gpu_recover - manually trigger a gpu reset & recover
880 * Manually trigger a gpu reset at the next fence wait.
882 static int gpu_recover_get(void *data, u64 *val)
884 struct amdgpu_device *adev = (struct amdgpu_device *)data;
885 struct drm_device *dev = adev_to_drm(adev);
888 r = pm_runtime_get_sync(dev->dev);
890 pm_runtime_put_autosuspend(dev->dev);
894 if (amdgpu_reset_domain_schedule(adev->reset_domain, &adev->reset_work))
895 flush_work(&adev->reset_work);
897 *val = atomic_read(&adev->reset_domain->reset_res);
899 pm_runtime_mark_last_busy(dev->dev);
900 pm_runtime_put_autosuspend(dev->dev);
905 DEFINE_SHOW_ATTRIBUTE(amdgpu_debugfs_fence_info);
906 DEFINE_DEBUGFS_ATTRIBUTE(amdgpu_debugfs_gpu_recover_fops, gpu_recover_get, NULL,
909 static void amdgpu_debugfs_reset_work(struct work_struct *work)
911 struct amdgpu_device *adev = container_of(work, struct amdgpu_device,
914 struct amdgpu_reset_context reset_context;
916 memset(&reset_context, 0, sizeof(reset_context));
918 reset_context.method = AMD_RESET_METHOD_NONE;
919 reset_context.reset_req_dev = adev;
920 set_bit(AMDGPU_NEED_FULL_RESET, &reset_context.flags);
922 amdgpu_device_gpu_recover(adev, NULL, &reset_context);
927 void amdgpu_debugfs_fence_init(struct amdgpu_device *adev)
929 #if defined(CONFIG_DEBUG_FS)
930 struct drm_minor *minor = adev_to_drm(adev)->primary;
931 struct dentry *root = minor->debugfs_root;
933 debugfs_create_file("amdgpu_fence_info", 0444, root, adev,
934 &amdgpu_debugfs_fence_info_fops);
936 if (!amdgpu_sriov_vf(adev)) {
938 INIT_WORK(&adev->reset_work, amdgpu_debugfs_reset_work);
939 debugfs_create_file("amdgpu_gpu_recover", 0444, root, adev,
940 &amdgpu_debugfs_gpu_recover_fops);