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Merge tag 'amd-drm-next-6.5-2023-06-09' of https://gitlab.freedesktop.org/agd5f/linux...
[linux.git] / arch / arm64 / include / asm / insn.h
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * Copyright (C) 2013 Huawei Ltd.
4  * Author: Jiang Liu <[email protected]>
5  *
6  * Copyright (C) 2014 Zi Shen Lim <[email protected]>
7  */
8 #ifndef __ASM_INSN_H
9 #define __ASM_INSN_H
10 #include <linux/build_bug.h>
11 #include <linux/types.h>
12
13 #include <asm/insn-def.h>
14
15 #ifndef __ASSEMBLY__
16
17 enum aarch64_insn_hint_cr_op {
18         AARCH64_INSN_HINT_NOP   = 0x0 << 5,
19         AARCH64_INSN_HINT_YIELD = 0x1 << 5,
20         AARCH64_INSN_HINT_WFE   = 0x2 << 5,
21         AARCH64_INSN_HINT_WFI   = 0x3 << 5,
22         AARCH64_INSN_HINT_SEV   = 0x4 << 5,
23         AARCH64_INSN_HINT_SEVL  = 0x5 << 5,
24
25         AARCH64_INSN_HINT_XPACLRI    = 0x07 << 5,
26         AARCH64_INSN_HINT_PACIA_1716 = 0x08 << 5,
27         AARCH64_INSN_HINT_PACIB_1716 = 0x0A << 5,
28         AARCH64_INSN_HINT_AUTIA_1716 = 0x0C << 5,
29         AARCH64_INSN_HINT_AUTIB_1716 = 0x0E << 5,
30         AARCH64_INSN_HINT_PACIAZ     = 0x18 << 5,
31         AARCH64_INSN_HINT_PACIASP    = 0x19 << 5,
32         AARCH64_INSN_HINT_PACIBZ     = 0x1A << 5,
33         AARCH64_INSN_HINT_PACIBSP    = 0x1B << 5,
34         AARCH64_INSN_HINT_AUTIAZ     = 0x1C << 5,
35         AARCH64_INSN_HINT_AUTIASP    = 0x1D << 5,
36         AARCH64_INSN_HINT_AUTIBZ     = 0x1E << 5,
37         AARCH64_INSN_HINT_AUTIBSP    = 0x1F << 5,
38
39         AARCH64_INSN_HINT_ESB  = 0x10 << 5,
40         AARCH64_INSN_HINT_PSB  = 0x11 << 5,
41         AARCH64_INSN_HINT_TSB  = 0x12 << 5,
42         AARCH64_INSN_HINT_CSDB = 0x14 << 5,
43         AARCH64_INSN_HINT_CLEARBHB = 0x16 << 5,
44
45         AARCH64_INSN_HINT_BTI   = 0x20 << 5,
46         AARCH64_INSN_HINT_BTIC  = 0x22 << 5,
47         AARCH64_INSN_HINT_BTIJ  = 0x24 << 5,
48         AARCH64_INSN_HINT_BTIJC = 0x26 << 5,
49 };
50
51 enum aarch64_insn_imm_type {
52         AARCH64_INSN_IMM_ADR,
53         AARCH64_INSN_IMM_26,
54         AARCH64_INSN_IMM_19,
55         AARCH64_INSN_IMM_16,
56         AARCH64_INSN_IMM_14,
57         AARCH64_INSN_IMM_12,
58         AARCH64_INSN_IMM_9,
59         AARCH64_INSN_IMM_7,
60         AARCH64_INSN_IMM_6,
61         AARCH64_INSN_IMM_S,
62         AARCH64_INSN_IMM_R,
63         AARCH64_INSN_IMM_N,
64         AARCH64_INSN_IMM_MAX
65 };
66
67 enum aarch64_insn_register_type {
68         AARCH64_INSN_REGTYPE_RT,
69         AARCH64_INSN_REGTYPE_RN,
70         AARCH64_INSN_REGTYPE_RT2,
71         AARCH64_INSN_REGTYPE_RM,
72         AARCH64_INSN_REGTYPE_RD,
73         AARCH64_INSN_REGTYPE_RA,
74         AARCH64_INSN_REGTYPE_RS,
75 };
76
77 enum aarch64_insn_register {
78         AARCH64_INSN_REG_0  = 0,
79         AARCH64_INSN_REG_1  = 1,
80         AARCH64_INSN_REG_2  = 2,
81         AARCH64_INSN_REG_3  = 3,
82         AARCH64_INSN_REG_4  = 4,
83         AARCH64_INSN_REG_5  = 5,
84         AARCH64_INSN_REG_6  = 6,
85         AARCH64_INSN_REG_7  = 7,
86         AARCH64_INSN_REG_8  = 8,
87         AARCH64_INSN_REG_9  = 9,
88         AARCH64_INSN_REG_10 = 10,
89         AARCH64_INSN_REG_11 = 11,
90         AARCH64_INSN_REG_12 = 12,
91         AARCH64_INSN_REG_13 = 13,
92         AARCH64_INSN_REG_14 = 14,
93         AARCH64_INSN_REG_15 = 15,
94         AARCH64_INSN_REG_16 = 16,
95         AARCH64_INSN_REG_17 = 17,
96         AARCH64_INSN_REG_18 = 18,
97         AARCH64_INSN_REG_19 = 19,
98         AARCH64_INSN_REG_20 = 20,
99         AARCH64_INSN_REG_21 = 21,
100         AARCH64_INSN_REG_22 = 22,
101         AARCH64_INSN_REG_23 = 23,
102         AARCH64_INSN_REG_24 = 24,
103         AARCH64_INSN_REG_25 = 25,
104         AARCH64_INSN_REG_26 = 26,
105         AARCH64_INSN_REG_27 = 27,
106         AARCH64_INSN_REG_28 = 28,
107         AARCH64_INSN_REG_29 = 29,
108         AARCH64_INSN_REG_FP = 29, /* Frame pointer */
109         AARCH64_INSN_REG_30 = 30,
110         AARCH64_INSN_REG_LR = 30, /* Link register */
111         AARCH64_INSN_REG_ZR = 31, /* Zero: as source register */
112         AARCH64_INSN_REG_SP = 31  /* Stack pointer: as load/store base reg */
113 };
114
115 enum aarch64_insn_special_register {
116         AARCH64_INSN_SPCLREG_SPSR_EL1   = 0xC200,
117         AARCH64_INSN_SPCLREG_ELR_EL1    = 0xC201,
118         AARCH64_INSN_SPCLREG_SP_EL0     = 0xC208,
119         AARCH64_INSN_SPCLREG_SPSEL      = 0xC210,
120         AARCH64_INSN_SPCLREG_CURRENTEL  = 0xC212,
121         AARCH64_INSN_SPCLREG_DAIF       = 0xDA11,
122         AARCH64_INSN_SPCLREG_NZCV       = 0xDA10,
123         AARCH64_INSN_SPCLREG_FPCR       = 0xDA20,
124         AARCH64_INSN_SPCLREG_DSPSR_EL0  = 0xDA28,
125         AARCH64_INSN_SPCLREG_DLR_EL0    = 0xDA29,
126         AARCH64_INSN_SPCLREG_SPSR_EL2   = 0xE200,
127         AARCH64_INSN_SPCLREG_ELR_EL2    = 0xE201,
128         AARCH64_INSN_SPCLREG_SP_EL1     = 0xE208,
129         AARCH64_INSN_SPCLREG_SPSR_INQ   = 0xE218,
130         AARCH64_INSN_SPCLREG_SPSR_ABT   = 0xE219,
131         AARCH64_INSN_SPCLREG_SPSR_UND   = 0xE21A,
132         AARCH64_INSN_SPCLREG_SPSR_FIQ   = 0xE21B,
133         AARCH64_INSN_SPCLREG_SPSR_EL3   = 0xF200,
134         AARCH64_INSN_SPCLREG_ELR_EL3    = 0xF201,
135         AARCH64_INSN_SPCLREG_SP_EL2     = 0xF210
136 };
137
138 enum aarch64_insn_variant {
139         AARCH64_INSN_VARIANT_32BIT,
140         AARCH64_INSN_VARIANT_64BIT
141 };
142
143 enum aarch64_insn_condition {
144         AARCH64_INSN_COND_EQ = 0x0, /* == */
145         AARCH64_INSN_COND_NE = 0x1, /* != */
146         AARCH64_INSN_COND_CS = 0x2, /* unsigned >= */
147         AARCH64_INSN_COND_CC = 0x3, /* unsigned < */
148         AARCH64_INSN_COND_MI = 0x4, /* < 0 */
149         AARCH64_INSN_COND_PL = 0x5, /* >= 0 */
150         AARCH64_INSN_COND_VS = 0x6, /* overflow */
151         AARCH64_INSN_COND_VC = 0x7, /* no overflow */
152         AARCH64_INSN_COND_HI = 0x8, /* unsigned > */
153         AARCH64_INSN_COND_LS = 0x9, /* unsigned <= */
154         AARCH64_INSN_COND_GE = 0xa, /* signed >= */
155         AARCH64_INSN_COND_LT = 0xb, /* signed < */
156         AARCH64_INSN_COND_GT = 0xc, /* signed > */
157         AARCH64_INSN_COND_LE = 0xd, /* signed <= */
158         AARCH64_INSN_COND_AL = 0xe, /* always */
159 };
160
161 enum aarch64_insn_branch_type {
162         AARCH64_INSN_BRANCH_NOLINK,
163         AARCH64_INSN_BRANCH_LINK,
164         AARCH64_INSN_BRANCH_RETURN,
165         AARCH64_INSN_BRANCH_COMP_ZERO,
166         AARCH64_INSN_BRANCH_COMP_NONZERO,
167 };
168
169 enum aarch64_insn_size_type {
170         AARCH64_INSN_SIZE_8,
171         AARCH64_INSN_SIZE_16,
172         AARCH64_INSN_SIZE_32,
173         AARCH64_INSN_SIZE_64,
174 };
175
176 enum aarch64_insn_ldst_type {
177         AARCH64_INSN_LDST_LOAD_REG_OFFSET,
178         AARCH64_INSN_LDST_STORE_REG_OFFSET,
179         AARCH64_INSN_LDST_LOAD_IMM_OFFSET,
180         AARCH64_INSN_LDST_STORE_IMM_OFFSET,
181         AARCH64_INSN_LDST_LOAD_PAIR_PRE_INDEX,
182         AARCH64_INSN_LDST_STORE_PAIR_PRE_INDEX,
183         AARCH64_INSN_LDST_LOAD_PAIR_POST_INDEX,
184         AARCH64_INSN_LDST_STORE_PAIR_POST_INDEX,
185         AARCH64_INSN_LDST_LOAD_EX,
186         AARCH64_INSN_LDST_LOAD_ACQ_EX,
187         AARCH64_INSN_LDST_STORE_EX,
188         AARCH64_INSN_LDST_STORE_REL_EX,
189 };
190
191 enum aarch64_insn_adsb_type {
192         AARCH64_INSN_ADSB_ADD,
193         AARCH64_INSN_ADSB_SUB,
194         AARCH64_INSN_ADSB_ADD_SETFLAGS,
195         AARCH64_INSN_ADSB_SUB_SETFLAGS
196 };
197
198 enum aarch64_insn_movewide_type {
199         AARCH64_INSN_MOVEWIDE_ZERO,
200         AARCH64_INSN_MOVEWIDE_KEEP,
201         AARCH64_INSN_MOVEWIDE_INVERSE
202 };
203
204 enum aarch64_insn_bitfield_type {
205         AARCH64_INSN_BITFIELD_MOVE,
206         AARCH64_INSN_BITFIELD_MOVE_UNSIGNED,
207         AARCH64_INSN_BITFIELD_MOVE_SIGNED
208 };
209
210 enum aarch64_insn_data1_type {
211         AARCH64_INSN_DATA1_REVERSE_16,
212         AARCH64_INSN_DATA1_REVERSE_32,
213         AARCH64_INSN_DATA1_REVERSE_64,
214 };
215
216 enum aarch64_insn_data2_type {
217         AARCH64_INSN_DATA2_UDIV,
218         AARCH64_INSN_DATA2_SDIV,
219         AARCH64_INSN_DATA2_LSLV,
220         AARCH64_INSN_DATA2_LSRV,
221         AARCH64_INSN_DATA2_ASRV,
222         AARCH64_INSN_DATA2_RORV,
223 };
224
225 enum aarch64_insn_data3_type {
226         AARCH64_INSN_DATA3_MADD,
227         AARCH64_INSN_DATA3_MSUB,
228 };
229
230 enum aarch64_insn_logic_type {
231         AARCH64_INSN_LOGIC_AND,
232         AARCH64_INSN_LOGIC_BIC,
233         AARCH64_INSN_LOGIC_ORR,
234         AARCH64_INSN_LOGIC_ORN,
235         AARCH64_INSN_LOGIC_EOR,
236         AARCH64_INSN_LOGIC_EON,
237         AARCH64_INSN_LOGIC_AND_SETFLAGS,
238         AARCH64_INSN_LOGIC_BIC_SETFLAGS
239 };
240
241 enum aarch64_insn_prfm_type {
242         AARCH64_INSN_PRFM_TYPE_PLD,
243         AARCH64_INSN_PRFM_TYPE_PLI,
244         AARCH64_INSN_PRFM_TYPE_PST,
245 };
246
247 enum aarch64_insn_prfm_target {
248         AARCH64_INSN_PRFM_TARGET_L1,
249         AARCH64_INSN_PRFM_TARGET_L2,
250         AARCH64_INSN_PRFM_TARGET_L3,
251 };
252
253 enum aarch64_insn_prfm_policy {
254         AARCH64_INSN_PRFM_POLICY_KEEP,
255         AARCH64_INSN_PRFM_POLICY_STRM,
256 };
257
258 enum aarch64_insn_adr_type {
259         AARCH64_INSN_ADR_TYPE_ADRP,
260         AARCH64_INSN_ADR_TYPE_ADR,
261 };
262
263 enum aarch64_insn_mem_atomic_op {
264         AARCH64_INSN_MEM_ATOMIC_ADD,
265         AARCH64_INSN_MEM_ATOMIC_CLR,
266         AARCH64_INSN_MEM_ATOMIC_EOR,
267         AARCH64_INSN_MEM_ATOMIC_SET,
268         AARCH64_INSN_MEM_ATOMIC_SWP,
269 };
270
271 enum aarch64_insn_mem_order_type {
272         AARCH64_INSN_MEM_ORDER_NONE,
273         AARCH64_INSN_MEM_ORDER_ACQ,
274         AARCH64_INSN_MEM_ORDER_REL,
275         AARCH64_INSN_MEM_ORDER_ACQREL,
276 };
277
278 enum aarch64_insn_mb_type {
279         AARCH64_INSN_MB_SY,
280         AARCH64_INSN_MB_ST,
281         AARCH64_INSN_MB_LD,
282         AARCH64_INSN_MB_ISH,
283         AARCH64_INSN_MB_ISHST,
284         AARCH64_INSN_MB_ISHLD,
285         AARCH64_INSN_MB_NSH,
286         AARCH64_INSN_MB_NSHST,
287         AARCH64_INSN_MB_NSHLD,
288         AARCH64_INSN_MB_OSH,
289         AARCH64_INSN_MB_OSHST,
290         AARCH64_INSN_MB_OSHLD,
291 };
292
293 #define __AARCH64_INSN_FUNCS(abbr, mask, val)                           \
294 static __always_inline bool aarch64_insn_is_##abbr(u32 code)            \
295 {                                                                       \
296         BUILD_BUG_ON(~(mask) & (val));                                  \
297         return (code & (mask)) == (val);                                \
298 }                                                                       \
299 static __always_inline u32 aarch64_insn_get_##abbr##_value(void)        \
300 {                                                                       \
301         return (val);                                                   \
302 }
303
304 /*
305  * ARM Architecture Reference Manual for ARMv8 Profile-A, Issue A.a
306  * Section C3.1 "A64 instruction index by encoding":
307  * AArch64 main encoding table
308  *  Bit position
309  *   28 27 26 25        Encoding Group
310  *   0  0  -  -         Unallocated
311  *   1  0  0  -         Data processing, immediate
312  *   1  0  1  -         Branch, exception generation and system instructions
313  *   -  1  -  0         Loads and stores
314  *   -  1  0  1         Data processing - register
315  *   0  1  1  1         Data processing - SIMD and floating point
316  *   1  1  1  1         Data processing - SIMD and floating point
317  * "-" means "don't care"
318  */
319 __AARCH64_INSN_FUNCS(class_branch_sys,  0x1c000000, 0x14000000)
320
321 __AARCH64_INSN_FUNCS(adr,       0x9F000000, 0x10000000)
322 __AARCH64_INSN_FUNCS(adrp,      0x9F000000, 0x90000000)
323 __AARCH64_INSN_FUNCS(prfm,      0x3FC00000, 0x39800000)
324 __AARCH64_INSN_FUNCS(prfm_lit,  0xFF000000, 0xD8000000)
325 __AARCH64_INSN_FUNCS(store_imm, 0x3FC00000, 0x39000000)
326 __AARCH64_INSN_FUNCS(load_imm,  0x3FC00000, 0x39400000)
327 __AARCH64_INSN_FUNCS(store_pre, 0x3FE00C00, 0x38000C00)
328 __AARCH64_INSN_FUNCS(load_pre,  0x3FE00C00, 0x38400C00)
329 __AARCH64_INSN_FUNCS(store_post,        0x3FE00C00, 0x38000400)
330 __AARCH64_INSN_FUNCS(load_post, 0x3FE00C00, 0x38400400)
331 __AARCH64_INSN_FUNCS(str_reg,   0x3FE0EC00, 0x38206800)
332 __AARCH64_INSN_FUNCS(str_imm,   0x3FC00000, 0x39000000)
333 __AARCH64_INSN_FUNCS(ldadd,     0x3F20FC00, 0x38200000)
334 __AARCH64_INSN_FUNCS(ldclr,     0x3F20FC00, 0x38201000)
335 __AARCH64_INSN_FUNCS(ldeor,     0x3F20FC00, 0x38202000)
336 __AARCH64_INSN_FUNCS(ldset,     0x3F20FC00, 0x38203000)
337 __AARCH64_INSN_FUNCS(swp,       0x3F20FC00, 0x38208000)
338 __AARCH64_INSN_FUNCS(cas,       0x3FA07C00, 0x08A07C00)
339 __AARCH64_INSN_FUNCS(ldr_reg,   0x3FE0EC00, 0x38606800)
340 __AARCH64_INSN_FUNCS(ldr_imm,   0x3FC00000, 0x39400000)
341 __AARCH64_INSN_FUNCS(ldr_lit,   0xBF000000, 0x18000000)
342 __AARCH64_INSN_FUNCS(ldrsw_lit, 0xFF000000, 0x98000000)
343 __AARCH64_INSN_FUNCS(exclusive, 0x3F800000, 0x08000000)
344 __AARCH64_INSN_FUNCS(load_ex,   0x3F400000, 0x08400000)
345 __AARCH64_INSN_FUNCS(store_ex,  0x3F400000, 0x08000000)
346 __AARCH64_INSN_FUNCS(stp,       0x7FC00000, 0x29000000)
347 __AARCH64_INSN_FUNCS(ldp,       0x7FC00000, 0x29400000)
348 __AARCH64_INSN_FUNCS(stp_post,  0x7FC00000, 0x28800000)
349 __AARCH64_INSN_FUNCS(ldp_post,  0x7FC00000, 0x28C00000)
350 __AARCH64_INSN_FUNCS(stp_pre,   0x7FC00000, 0x29800000)
351 __AARCH64_INSN_FUNCS(ldp_pre,   0x7FC00000, 0x29C00000)
352 __AARCH64_INSN_FUNCS(add_imm,   0x7F000000, 0x11000000)
353 __AARCH64_INSN_FUNCS(adds_imm,  0x7F000000, 0x31000000)
354 __AARCH64_INSN_FUNCS(sub_imm,   0x7F000000, 0x51000000)
355 __AARCH64_INSN_FUNCS(subs_imm,  0x7F000000, 0x71000000)
356 __AARCH64_INSN_FUNCS(movn,      0x7F800000, 0x12800000)
357 __AARCH64_INSN_FUNCS(sbfm,      0x7F800000, 0x13000000)
358 __AARCH64_INSN_FUNCS(bfm,       0x7F800000, 0x33000000)
359 __AARCH64_INSN_FUNCS(movz,      0x7F800000, 0x52800000)
360 __AARCH64_INSN_FUNCS(ubfm,      0x7F800000, 0x53000000)
361 __AARCH64_INSN_FUNCS(movk,      0x7F800000, 0x72800000)
362 __AARCH64_INSN_FUNCS(add,       0x7F200000, 0x0B000000)
363 __AARCH64_INSN_FUNCS(adds,      0x7F200000, 0x2B000000)
364 __AARCH64_INSN_FUNCS(sub,       0x7F200000, 0x4B000000)
365 __AARCH64_INSN_FUNCS(subs,      0x7F200000, 0x6B000000)
366 __AARCH64_INSN_FUNCS(madd,      0x7FE08000, 0x1B000000)
367 __AARCH64_INSN_FUNCS(msub,      0x7FE08000, 0x1B008000)
368 __AARCH64_INSN_FUNCS(udiv,      0x7FE0FC00, 0x1AC00800)
369 __AARCH64_INSN_FUNCS(sdiv,      0x7FE0FC00, 0x1AC00C00)
370 __AARCH64_INSN_FUNCS(lslv,      0x7FE0FC00, 0x1AC02000)
371 __AARCH64_INSN_FUNCS(lsrv,      0x7FE0FC00, 0x1AC02400)
372 __AARCH64_INSN_FUNCS(asrv,      0x7FE0FC00, 0x1AC02800)
373 __AARCH64_INSN_FUNCS(rorv,      0x7FE0FC00, 0x1AC02C00)
374 __AARCH64_INSN_FUNCS(rev16,     0x7FFFFC00, 0x5AC00400)
375 __AARCH64_INSN_FUNCS(rev32,     0x7FFFFC00, 0x5AC00800)
376 __AARCH64_INSN_FUNCS(rev64,     0x7FFFFC00, 0x5AC00C00)
377 __AARCH64_INSN_FUNCS(and,       0x7F200000, 0x0A000000)
378 __AARCH64_INSN_FUNCS(bic,       0x7F200000, 0x0A200000)
379 __AARCH64_INSN_FUNCS(orr,       0x7F200000, 0x2A000000)
380 __AARCH64_INSN_FUNCS(mov_reg,   0x7FE0FFE0, 0x2A0003E0)
381 __AARCH64_INSN_FUNCS(orn,       0x7F200000, 0x2A200000)
382 __AARCH64_INSN_FUNCS(eor,       0x7F200000, 0x4A000000)
383 __AARCH64_INSN_FUNCS(eon,       0x7F200000, 0x4A200000)
384 __AARCH64_INSN_FUNCS(ands,      0x7F200000, 0x6A000000)
385 __AARCH64_INSN_FUNCS(bics,      0x7F200000, 0x6A200000)
386 __AARCH64_INSN_FUNCS(and_imm,   0x7F800000, 0x12000000)
387 __AARCH64_INSN_FUNCS(orr_imm,   0x7F800000, 0x32000000)
388 __AARCH64_INSN_FUNCS(eor_imm,   0x7F800000, 0x52000000)
389 __AARCH64_INSN_FUNCS(ands_imm,  0x7F800000, 0x72000000)
390 __AARCH64_INSN_FUNCS(extr,      0x7FA00000, 0x13800000)
391 __AARCH64_INSN_FUNCS(b,         0xFC000000, 0x14000000)
392 __AARCH64_INSN_FUNCS(bl,        0xFC000000, 0x94000000)
393 __AARCH64_INSN_FUNCS(cbz,       0x7F000000, 0x34000000)
394 __AARCH64_INSN_FUNCS(cbnz,      0x7F000000, 0x35000000)
395 __AARCH64_INSN_FUNCS(tbz,       0x7F000000, 0x36000000)
396 __AARCH64_INSN_FUNCS(tbnz,      0x7F000000, 0x37000000)
397 __AARCH64_INSN_FUNCS(bcond,     0xFF000010, 0x54000000)
398 __AARCH64_INSN_FUNCS(svc,       0xFFE0001F, 0xD4000001)
399 __AARCH64_INSN_FUNCS(hvc,       0xFFE0001F, 0xD4000002)
400 __AARCH64_INSN_FUNCS(smc,       0xFFE0001F, 0xD4000003)
401 __AARCH64_INSN_FUNCS(brk,       0xFFE0001F, 0xD4200000)
402 __AARCH64_INSN_FUNCS(exception, 0xFF000000, 0xD4000000)
403 __AARCH64_INSN_FUNCS(hint,      0xFFFFF01F, 0xD503201F)
404 __AARCH64_INSN_FUNCS(br,        0xFFFFFC1F, 0xD61F0000)
405 __AARCH64_INSN_FUNCS(br_auth,   0xFEFFF800, 0xD61F0800)
406 __AARCH64_INSN_FUNCS(blr,       0xFFFFFC1F, 0xD63F0000)
407 __AARCH64_INSN_FUNCS(blr_auth,  0xFEFFF800, 0xD63F0800)
408 __AARCH64_INSN_FUNCS(ret,       0xFFFFFC1F, 0xD65F0000)
409 __AARCH64_INSN_FUNCS(ret_auth,  0xFFFFFBFF, 0xD65F0BFF)
410 __AARCH64_INSN_FUNCS(eret,      0xFFFFFFFF, 0xD69F03E0)
411 __AARCH64_INSN_FUNCS(eret_auth, 0xFFFFFBFF, 0xD69F0BFF)
412 __AARCH64_INSN_FUNCS(mrs,       0xFFF00000, 0xD5300000)
413 __AARCH64_INSN_FUNCS(msr_imm,   0xFFF8F01F, 0xD500401F)
414 __AARCH64_INSN_FUNCS(msr_reg,   0xFFF00000, 0xD5100000)
415 __AARCH64_INSN_FUNCS(dmb,       0xFFFFF0FF, 0xD50330BF)
416 __AARCH64_INSN_FUNCS(dsb_base,  0xFFFFF0FF, 0xD503309F)
417 __AARCH64_INSN_FUNCS(dsb_nxs,   0xFFFFF3FF, 0xD503323F)
418 __AARCH64_INSN_FUNCS(isb,       0xFFFFF0FF, 0xD50330DF)
419 __AARCH64_INSN_FUNCS(sb,        0xFFFFFFFF, 0xD50330FF)
420 __AARCH64_INSN_FUNCS(clrex,     0xFFFFF0FF, 0xD503305F)
421 __AARCH64_INSN_FUNCS(ssbb,      0xFFFFFFFF, 0xD503309F)
422 __AARCH64_INSN_FUNCS(pssbb,     0xFFFFFFFF, 0xD503349F)
423 __AARCH64_INSN_FUNCS(bti,       0xFFFFFF3F, 0xD503241f)
424
425 #undef  __AARCH64_INSN_FUNCS
426
427 static __always_inline bool aarch64_insn_is_steppable_hint(u32 insn)
428 {
429         if (!aarch64_insn_is_hint(insn))
430                 return false;
431
432         switch (insn & 0xFE0) {
433         case AARCH64_INSN_HINT_XPACLRI:
434         case AARCH64_INSN_HINT_PACIA_1716:
435         case AARCH64_INSN_HINT_PACIB_1716:
436         case AARCH64_INSN_HINT_PACIAZ:
437         case AARCH64_INSN_HINT_PACIASP:
438         case AARCH64_INSN_HINT_PACIBZ:
439         case AARCH64_INSN_HINT_PACIBSP:
440         case AARCH64_INSN_HINT_BTI:
441         case AARCH64_INSN_HINT_BTIC:
442         case AARCH64_INSN_HINT_BTIJ:
443         case AARCH64_INSN_HINT_BTIJC:
444         case AARCH64_INSN_HINT_NOP:
445                 return true;
446         default:
447                 return false;
448         }
449 }
450
451 static __always_inline bool aarch64_insn_is_branch(u32 insn)
452 {
453         /* b, bl, cb*, tb*, ret*, b.cond, br*, blr* */
454
455         return aarch64_insn_is_b(insn) ||
456                aarch64_insn_is_bl(insn) ||
457                aarch64_insn_is_cbz(insn) ||
458                aarch64_insn_is_cbnz(insn) ||
459                aarch64_insn_is_tbz(insn) ||
460                aarch64_insn_is_tbnz(insn) ||
461                aarch64_insn_is_ret(insn) ||
462                aarch64_insn_is_ret_auth(insn) ||
463                aarch64_insn_is_br(insn) ||
464                aarch64_insn_is_br_auth(insn) ||
465                aarch64_insn_is_blr(insn) ||
466                aarch64_insn_is_blr_auth(insn) ||
467                aarch64_insn_is_bcond(insn);
468 }
469
470 static __always_inline bool aarch64_insn_is_branch_imm(u32 insn)
471 {
472         return aarch64_insn_is_b(insn) ||
473                aarch64_insn_is_bl(insn) ||
474                aarch64_insn_is_tbz(insn) ||
475                aarch64_insn_is_tbnz(insn) ||
476                aarch64_insn_is_cbz(insn) ||
477                aarch64_insn_is_cbnz(insn) ||
478                aarch64_insn_is_bcond(insn);
479 }
480
481 static __always_inline bool aarch64_insn_is_adr_adrp(u32 insn)
482 {
483         return aarch64_insn_is_adr(insn) ||
484                aarch64_insn_is_adrp(insn);
485 }
486
487 static __always_inline bool aarch64_insn_is_dsb(u32 insn)
488 {
489         return aarch64_insn_is_dsb_base(insn) ||
490                aarch64_insn_is_dsb_nxs(insn);
491 }
492
493 static __always_inline bool aarch64_insn_is_barrier(u32 insn)
494 {
495         return aarch64_insn_is_dmb(insn) ||
496                aarch64_insn_is_dsb(insn) ||
497                aarch64_insn_is_isb(insn) ||
498                aarch64_insn_is_sb(insn) ||
499                aarch64_insn_is_clrex(insn) ||
500                aarch64_insn_is_ssbb(insn) ||
501                aarch64_insn_is_pssbb(insn);
502 }
503
504 static __always_inline bool aarch64_insn_is_store_single(u32 insn)
505 {
506         return aarch64_insn_is_store_imm(insn) ||
507                aarch64_insn_is_store_pre(insn) ||
508                aarch64_insn_is_store_post(insn);
509 }
510
511 static __always_inline bool aarch64_insn_is_store_pair(u32 insn)
512 {
513         return aarch64_insn_is_stp(insn) ||
514                aarch64_insn_is_stp_pre(insn) ||
515                aarch64_insn_is_stp_post(insn);
516 }
517
518 static __always_inline bool aarch64_insn_is_load_single(u32 insn)
519 {
520         return aarch64_insn_is_load_imm(insn) ||
521                aarch64_insn_is_load_pre(insn) ||
522                aarch64_insn_is_load_post(insn);
523 }
524
525 static __always_inline bool aarch64_insn_is_load_pair(u32 insn)
526 {
527         return aarch64_insn_is_ldp(insn) ||
528                aarch64_insn_is_ldp_pre(insn) ||
529                aarch64_insn_is_ldp_post(insn);
530 }
531
532 static __always_inline bool aarch64_insn_uses_literal(u32 insn)
533 {
534         /* ldr/ldrsw (literal), prfm */
535
536         return aarch64_insn_is_ldr_lit(insn) ||
537                aarch64_insn_is_ldrsw_lit(insn) ||
538                aarch64_insn_is_adr_adrp(insn) ||
539                aarch64_insn_is_prfm_lit(insn);
540 }
541
542 enum aarch64_insn_encoding_class aarch64_get_insn_class(u32 insn);
543 u64 aarch64_insn_decode_immediate(enum aarch64_insn_imm_type type, u32 insn);
544 u32 aarch64_insn_encode_immediate(enum aarch64_insn_imm_type type,
545                                   u32 insn, u64 imm);
546 u32 aarch64_insn_decode_register(enum aarch64_insn_register_type type,
547                                          u32 insn);
548 u32 aarch64_insn_gen_branch_imm(unsigned long pc, unsigned long addr,
549                                 enum aarch64_insn_branch_type type);
550 u32 aarch64_insn_gen_comp_branch_imm(unsigned long pc, unsigned long addr,
551                                      enum aarch64_insn_register reg,
552                                      enum aarch64_insn_variant variant,
553                                      enum aarch64_insn_branch_type type);
554 u32 aarch64_insn_gen_cond_branch_imm(unsigned long pc, unsigned long addr,
555                                      enum aarch64_insn_condition cond);
556
557 static __always_inline u32
558 aarch64_insn_gen_hint(enum aarch64_insn_hint_cr_op op)
559 {
560         return aarch64_insn_get_hint_value() | op;
561 }
562
563 static __always_inline u32 aarch64_insn_gen_nop(void)
564 {
565         return aarch64_insn_gen_hint(AARCH64_INSN_HINT_NOP);
566 }
567
568 u32 aarch64_insn_gen_branch_reg(enum aarch64_insn_register reg,
569                                 enum aarch64_insn_branch_type type);
570 u32 aarch64_insn_gen_load_store_reg(enum aarch64_insn_register reg,
571                                     enum aarch64_insn_register base,
572                                     enum aarch64_insn_register offset,
573                                     enum aarch64_insn_size_type size,
574                                     enum aarch64_insn_ldst_type type);
575 u32 aarch64_insn_gen_load_store_imm(enum aarch64_insn_register reg,
576                                     enum aarch64_insn_register base,
577                                     unsigned int imm,
578                                     enum aarch64_insn_size_type size,
579                                     enum aarch64_insn_ldst_type type);
580 u32 aarch64_insn_gen_load_literal(unsigned long pc, unsigned long addr,
581                                   enum aarch64_insn_register reg,
582                                   bool is64bit);
583 u32 aarch64_insn_gen_load_store_pair(enum aarch64_insn_register reg1,
584                                      enum aarch64_insn_register reg2,
585                                      enum aarch64_insn_register base,
586                                      int offset,
587                                      enum aarch64_insn_variant variant,
588                                      enum aarch64_insn_ldst_type type);
589 u32 aarch64_insn_gen_load_store_ex(enum aarch64_insn_register reg,
590                                    enum aarch64_insn_register base,
591                                    enum aarch64_insn_register state,
592                                    enum aarch64_insn_size_type size,
593                                    enum aarch64_insn_ldst_type type);
594 u32 aarch64_insn_gen_add_sub_imm(enum aarch64_insn_register dst,
595                                  enum aarch64_insn_register src,
596                                  int imm, enum aarch64_insn_variant variant,
597                                  enum aarch64_insn_adsb_type type);
598 u32 aarch64_insn_gen_adr(unsigned long pc, unsigned long addr,
599                          enum aarch64_insn_register reg,
600                          enum aarch64_insn_adr_type type);
601 u32 aarch64_insn_gen_bitfield(enum aarch64_insn_register dst,
602                               enum aarch64_insn_register src,
603                               int immr, int imms,
604                               enum aarch64_insn_variant variant,
605                               enum aarch64_insn_bitfield_type type);
606 u32 aarch64_insn_gen_movewide(enum aarch64_insn_register dst,
607                               int imm, int shift,
608                               enum aarch64_insn_variant variant,
609                               enum aarch64_insn_movewide_type type);
610 u32 aarch64_insn_gen_add_sub_shifted_reg(enum aarch64_insn_register dst,
611                                          enum aarch64_insn_register src,
612                                          enum aarch64_insn_register reg,
613                                          int shift,
614                                          enum aarch64_insn_variant variant,
615                                          enum aarch64_insn_adsb_type type);
616 u32 aarch64_insn_gen_data1(enum aarch64_insn_register dst,
617                            enum aarch64_insn_register src,
618                            enum aarch64_insn_variant variant,
619                            enum aarch64_insn_data1_type type);
620 u32 aarch64_insn_gen_data2(enum aarch64_insn_register dst,
621                            enum aarch64_insn_register src,
622                            enum aarch64_insn_register reg,
623                            enum aarch64_insn_variant variant,
624                            enum aarch64_insn_data2_type type);
625 u32 aarch64_insn_gen_data3(enum aarch64_insn_register dst,
626                            enum aarch64_insn_register src,
627                            enum aarch64_insn_register reg1,
628                            enum aarch64_insn_register reg2,
629                            enum aarch64_insn_variant variant,
630                            enum aarch64_insn_data3_type type);
631 u32 aarch64_insn_gen_logical_shifted_reg(enum aarch64_insn_register dst,
632                                          enum aarch64_insn_register src,
633                                          enum aarch64_insn_register reg,
634                                          int shift,
635                                          enum aarch64_insn_variant variant,
636                                          enum aarch64_insn_logic_type type);
637 u32 aarch64_insn_gen_move_reg(enum aarch64_insn_register dst,
638                               enum aarch64_insn_register src,
639                               enum aarch64_insn_variant variant);
640 u32 aarch64_insn_gen_logical_immediate(enum aarch64_insn_logic_type type,
641                                        enum aarch64_insn_variant variant,
642                                        enum aarch64_insn_register Rn,
643                                        enum aarch64_insn_register Rd,
644                                        u64 imm);
645 u32 aarch64_insn_gen_extr(enum aarch64_insn_variant variant,
646                           enum aarch64_insn_register Rm,
647                           enum aarch64_insn_register Rn,
648                           enum aarch64_insn_register Rd,
649                           u8 lsb);
650 #ifdef CONFIG_ARM64_LSE_ATOMICS
651 u32 aarch64_insn_gen_atomic_ld_op(enum aarch64_insn_register result,
652                                   enum aarch64_insn_register address,
653                                   enum aarch64_insn_register value,
654                                   enum aarch64_insn_size_type size,
655                                   enum aarch64_insn_mem_atomic_op op,
656                                   enum aarch64_insn_mem_order_type order);
657 u32 aarch64_insn_gen_cas(enum aarch64_insn_register result,
658                          enum aarch64_insn_register address,
659                          enum aarch64_insn_register value,
660                          enum aarch64_insn_size_type size,
661                          enum aarch64_insn_mem_order_type order);
662 #else
663 static inline
664 u32 aarch64_insn_gen_atomic_ld_op(enum aarch64_insn_register result,
665                                   enum aarch64_insn_register address,
666                                   enum aarch64_insn_register value,
667                                   enum aarch64_insn_size_type size,
668                                   enum aarch64_insn_mem_atomic_op op,
669                                   enum aarch64_insn_mem_order_type order)
670 {
671         return AARCH64_BREAK_FAULT;
672 }
673
674 static inline
675 u32 aarch64_insn_gen_cas(enum aarch64_insn_register result,
676                          enum aarch64_insn_register address,
677                          enum aarch64_insn_register value,
678                          enum aarch64_insn_size_type size,
679                          enum aarch64_insn_mem_order_type order)
680 {
681         return AARCH64_BREAK_FAULT;
682 }
683 #endif
684 u32 aarch64_insn_gen_dmb(enum aarch64_insn_mb_type type);
685
686 s32 aarch64_get_branch_offset(u32 insn);
687 u32 aarch64_set_branch_offset(u32 insn, s32 offset);
688
689 s32 aarch64_insn_adrp_get_offset(u32 insn);
690 u32 aarch64_insn_adrp_set_offset(u32 insn, s32 offset);
691
692 bool aarch32_insn_is_wide(u32 insn);
693
694 #define A32_RN_OFFSET   16
695 #define A32_RT_OFFSET   12
696 #define A32_RT2_OFFSET   0
697
698 u32 aarch64_insn_extract_system_reg(u32 insn);
699 u32 aarch32_insn_extract_reg_num(u32 insn, int offset);
700 u32 aarch32_insn_mcr_extract_opc2(u32 insn);
701 u32 aarch32_insn_mcr_extract_crm(u32 insn);
702
703 typedef bool (pstate_check_t)(unsigned long);
704 extern pstate_check_t * const aarch32_opcode_cond_checks[16];
705
706 #endif /* __ASSEMBLY__ */
707
708 #endif  /* __ASM_INSN_H */
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