arch/x86/net/bpf_jit_comp.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * BPF JIT compiler
   4  *
   5  * Copyright (C) 2011-2013 Eric Dumazet ([email protected])
   6  * Copyright (c) 2011-2014 PLUMgrid, http://plumgrid.com
   7  */
   8 #include <linux/netdevice.h>
   9 #include <linux/filter.h>
  10 #include <linux/if_vlan.h>
  11 #include <linux/bpf.h>
  12 #include <linux/memory.h>
  13 #include <linux/sort.h>
  14 #include <asm/extable.h>
  15 #include <asm/ftrace.h>
  16 #include <asm/set_memory.h>
  17 #include <asm/nospec-branch.h>
  18 #include <asm/text-patching.h>
  19
  20 static u8 *emit_code(u8 *ptr, u32 bytes, unsigned int len)
  21 {
  22         if (len == 1)
  23                 *ptr = bytes;
  24         else if (len == 2)
  25                 *(u16 *)ptr = bytes;
  26         else {
  27                 *(u32 *)ptr = bytes;
  28                 barrier();
  29         }
  30         return ptr + len;
  31 }
  32
  33 #define EMIT(bytes, len) \
  34         do { prog = emit_code(prog, bytes, len); } while (0)
  35
  36 #define EMIT1(b1)               EMIT(b1, 1)
  37 #define EMIT2(b1, b2)           EMIT((b1) + ((b2) << 8), 2)
  38 #define EMIT3(b1, b2, b3)       EMIT((b1) + ((b2) << 8) + ((b3) << 16), 3)
  39 #define EMIT4(b1, b2, b3, b4)   EMIT((b1) + ((b2) << 8) + ((b3) << 16) + ((b4) << 24), 4)
  40
  41 #define EMIT1_off32(b1, off) \
  42         do { EMIT1(b1); EMIT(off, 4); } while (0)
  43 #define EMIT2_off32(b1, b2, off) \
  44         do { EMIT2(b1, b2); EMIT(off, 4); } while (0)
  45 #define EMIT3_off32(b1, b2, b3, off) \
  46         do { EMIT3(b1, b2, b3); EMIT(off, 4); } while (0)
  47 #define EMIT4_off32(b1, b2, b3, b4, off) \
  48         do { EMIT4(b1, b2, b3, b4); EMIT(off, 4); } while (0)
  49
  50 #ifdef CONFIG_X86_KERNEL_IBT
  51 #define EMIT_ENDBR()    EMIT(gen_endbr(), 4)
  52 #else
  53 #define EMIT_ENDBR()
  54 #endif
  55
  56 static bool is_imm8(int value)
  57 {
  58         return value <= 127 && value >= -128;
  59 }
  60
  61 static bool is_simm32(s64 value)
  62 {
  63         return value == (s64)(s32)value;
  64 }
  65
  66 static bool is_uimm32(u64 value)
  67 {
  68         return value == (u64)(u32)value;
  69 }
  70
  71 /* mov dst, src */
  72 #define EMIT_mov(DST, SRC)                                                               \
  73         do {                                                                             \
  74                 if (DST != SRC)                                                          \
  75                         EMIT3(add_2mod(0x48, DST, SRC), 0x89, add_2reg(0xC0, DST, SRC)); \
  76         } while (0)
  77
  78 static int bpf_size_to_x86_bytes(int bpf_size)
  79 {
  80         if (bpf_size == BPF_W)
  81                 return 4;
  82         else if (bpf_size == BPF_H)
  83                 return 2;
  84         else if (bpf_size == BPF_B)
  85                 return 1;
  86         else if (bpf_size == BPF_DW)
  87                 return 4; /* imm32 */
  88         else
  89                 return 0;
  90 }
  91
  92 /*
  93  * List of x86 cond jumps opcodes (. + s8)
  94  * Add 0x10 (and an extra 0x0f) to generate far jumps (. + s32)
  95  */
  96 #define X86_JB  0x72
  97 #define X86_JAE 0x73
  98 #define X86_JE  0x74
  99 #define X86_JNE 0x75
 100 #define X86_JBE 0x76
 101 #define X86_JA  0x77
 102 #define X86_JL  0x7C
 103 #define X86_JGE 0x7D
 104 #define X86_JLE 0x7E
 105 #define X86_JG  0x7F
 106
 107 /* Pick a register outside of BPF range for JIT internal work */
 108 #define AUX_REG (MAX_BPF_JIT_REG + 1)
 109 #define X86_REG_R9 (MAX_BPF_JIT_REG + 2)
 110
 111 /*
 112  * The following table maps BPF registers to x86-64 registers.
 113  *
 114  * x86-64 register R12 is unused, since if used as base address
 115  * register in load/store instructions, it always needs an
 116  * extra byte of encoding and is callee saved.
 117  *
 118  * x86-64 register R9 is not used by BPF programs, but can be used by BPF
 119  * trampoline. x86-64 register R10 is used for blinding (if enabled).
 120  */
 121 static const int reg2hex[] = {
 122         [BPF_REG_0] = 0,  /* RAX */
 123         [BPF_REG_1] = 7,  /* RDI */
 124         [BPF_REG_2] = 6,  /* RSI */
 125         [BPF_REG_3] = 2,  /* RDX */
 126         [BPF_REG_4] = 1,  /* RCX */
 127         [BPF_REG_5] = 0,  /* R8  */
 128         [BPF_REG_6] = 3,  /* RBX callee saved */
 129         [BPF_REG_7] = 5,  /* R13 callee saved */
 130         [BPF_REG_8] = 6,  /* R14 callee saved */
 131         [BPF_REG_9] = 7,  /* R15 callee saved */
 132         [BPF_REG_FP] = 5, /* RBP readonly */
 133         [BPF_REG_AX] = 2, /* R10 temp register */
 134         [AUX_REG] = 3,    /* R11 temp register */
 135         [X86_REG_R9] = 1, /* R9 register, 6th function argument */
 136 };
 137
 138 static const int reg2pt_regs[] = {
 139         [BPF_REG_0] = offsetof(struct pt_regs, ax),
 140         [BPF_REG_1] = offsetof(struct pt_regs, di),
 141         [BPF_REG_2] = offsetof(struct pt_regs, si),
 142         [BPF_REG_3] = offsetof(struct pt_regs, dx),
 143         [BPF_REG_4] = offsetof(struct pt_regs, cx),
 144         [BPF_REG_5] = offsetof(struct pt_regs, r8),
 145         [BPF_REG_6] = offsetof(struct pt_regs, bx),
 146         [BPF_REG_7] = offsetof(struct pt_regs, r13),
 147         [BPF_REG_8] = offsetof(struct pt_regs, r14),
 148         [BPF_REG_9] = offsetof(struct pt_regs, r15),
 149 };
 150
 151 /*
 152  * is_ereg() == true if BPF register 'reg' maps to x86-64 r8..r15
 153  * which need extra byte of encoding.
 154  * rax,rcx,...,rbp have simpler encoding
 155  */
 156 static bool is_ereg(u32 reg)
 157 {
 158         return (1 << reg) & (BIT(BPF_REG_5) |
 159                              BIT(AUX_REG) |
 160                              BIT(BPF_REG_7) |
 161                              BIT(BPF_REG_8) |
 162                              BIT(BPF_REG_9) |
 163                              BIT(X86_REG_R9) |
 164                              BIT(BPF_REG_AX));
 165 }
 166
 167 /*
 168  * is_ereg_8l() == true if BPF register 'reg' is mapped to access x86-64
 169  * lower 8-bit registers dil,sil,bpl,spl,r8b..r15b, which need extra byte
 170  * of encoding. al,cl,dl,bl have simpler encoding.
 171  */
 172 static bool is_ereg_8l(u32 reg)
 173 {
 174         return is_ereg(reg) ||
 175             (1 << reg) & (BIT(BPF_REG_1) |
 176                           BIT(BPF_REG_2) |
 177                           BIT(BPF_REG_FP));
 178 }
 179
 180 static bool is_axreg(u32 reg)
 181 {
 182         return reg == BPF_REG_0;
 183 }
 184
 185 /* Add modifiers if 'reg' maps to x86-64 registers R8..R15 */
 186 static u8 add_1mod(u8 byte, u32 reg)
 187 {
 188         if (is_ereg(reg))
 189                 byte |= 1;
 190         return byte;
 191 }
 192
 193 static u8 add_2mod(u8 byte, u32 r1, u32 r2)
 194 {
 195         if (is_ereg(r1))
 196                 byte |= 1;
 197         if (is_ereg(r2))
 198                 byte |= 4;
 199         return byte;
 200 }
 201
 202 /* Encode 'dst_reg' register into x86-64 opcode 'byte' */
 203 static u8 add_1reg(u8 byte, u32 dst_reg)
 204 {
 205         return byte + reg2hex[dst_reg];
 206 }
 207
 208 /* Encode 'dst_reg' and 'src_reg' registers into x86-64 opcode 'byte' */
 209 static u8 add_2reg(u8 byte, u32 dst_reg, u32 src_reg)
 210 {
 211         return byte + reg2hex[dst_reg] + (reg2hex[src_reg] << 3);
 212 }
 213
 214 /* Some 1-byte opcodes for binary ALU operations */
 215 static u8 simple_alu_opcodes[] = {
 216         [BPF_ADD] = 0x01,
 217         [BPF_SUB] = 0x29,
 218         [BPF_AND] = 0x21,
 219         [BPF_OR] = 0x09,
 220         [BPF_XOR] = 0x31,
 221         [BPF_LSH] = 0xE0,
 222         [BPF_RSH] = 0xE8,
 223         [BPF_ARSH] = 0xF8,
 224 };
 225
 226 static void jit_fill_hole(void *area, unsigned int size)
 227 {
 228         /* Fill whole space with INT3 instructions */
 229         memset(area, 0xcc, size);
 230 }
 231
 232 int bpf_arch_text_invalidate(void *dst, size_t len)
 233 {
 234         return IS_ERR_OR_NULL(text_poke_set(dst, 0xcc, len));
 235 }
 236
 237 struct jit_context {
 238         int cleanup_addr; /* Epilogue code offset */
 239
 240         /*
 241          * Program specific offsets of labels in the code; these rely on the
 242          * JIT doing at least 2 passes, recording the position on the first
 243          * pass, only to generate the correct offset on the second pass.
 244          */
 245         int tail_call_direct_label;
 246         int tail_call_indirect_label;
 247 };
 248
 249 /* Maximum number of bytes emitted while JITing one eBPF insn */
 250 #define BPF_MAX_INSN_SIZE       128
 251 #define BPF_INSN_SAFETY         64
 252
 253 /* Number of bytes emit_patch() needs to generate instructions */
 254 #define X86_PATCH_SIZE          5
 255 /* Number of bytes that will be skipped on tailcall */
 256 #define X86_TAIL_CALL_OFFSET    (11 + ENDBR_INSN_SIZE)
 257
 258 static void push_callee_regs(u8 **pprog, bool *callee_regs_used)
 259 {
 260         u8 *prog = *pprog;
 261
 262         if (callee_regs_used[0])
 263                 EMIT1(0x53);         /* push rbx */
 264         if (callee_regs_used[1])
 265                 EMIT2(0x41, 0x55);   /* push r13 */
 266         if (callee_regs_used[2])
 267                 EMIT2(0x41, 0x56);   /* push r14 */
 268         if (callee_regs_used[3])
 269                 EMIT2(0x41, 0x57);   /* push r15 */
 270         *pprog = prog;
 271 }
 272
 273 static void pop_callee_regs(u8 **pprog, bool *callee_regs_used)
 274 {
 275         u8 *prog = *pprog;
 276
 277         if (callee_regs_used[3])
 278                 EMIT2(0x41, 0x5F);   /* pop r15 */
 279         if (callee_regs_used[2])
 280                 EMIT2(0x41, 0x5E);   /* pop r14 */
 281         if (callee_regs_used[1])
 282                 EMIT2(0x41, 0x5D);   /* pop r13 */
 283         if (callee_regs_used[0])
 284                 EMIT1(0x5B);         /* pop rbx */
 285         *pprog = prog;
 286 }
 287
 288 /*
 289  * Emit x86-64 prologue code for BPF program.
 290  * bpf_tail_call helper will skip the first X86_TAIL_CALL_OFFSET bytes
 291  * while jumping to another program
 292  */
 293 static void emit_prologue(u8 **pprog, u32 stack_depth, bool ebpf_from_cbpf,
 294                           bool tail_call_reachable, bool is_subprog)
 295 {
 296         u8 *prog = *pprog;
 297
 298         /* BPF trampoline can be made to work without these nops,
 299          * but let's waste 5 bytes for now and optimize later
 300          */
 301         EMIT_ENDBR();
 302         memcpy(prog, x86_nops[5], X86_PATCH_SIZE);
 303         prog += X86_PATCH_SIZE;
 304         if (!ebpf_from_cbpf) {
 305                 if (tail_call_reachable && !is_subprog)
 306                         EMIT2(0x31, 0xC0); /* xor eax, eax */
 307                 else
 308                         EMIT2(0x66, 0x90); /* nop2 */
 309         }
 310         EMIT1(0x55);             /* push rbp */
 311         EMIT3(0x48, 0x89, 0xE5); /* mov rbp, rsp */
 312
 313         /* X86_TAIL_CALL_OFFSET is here */
 314         EMIT_ENDBR();
 315
 316         /* sub rsp, rounded_stack_depth */
 317         if (stack_depth)
 318                 EMIT3_off32(0x48, 0x81, 0xEC, round_up(stack_depth, 8));
 319         if (tail_call_reachable)
 320                 EMIT1(0x50);         /* push rax */
 321         *pprog = prog;
 322 }
 323
 324 static int emit_patch(u8 **pprog, void *func, void *ip, u8 opcode)
 325 {
 326         u8 *prog = *pprog;
 327         s64 offset;
 328
 329         offset = func - (ip + X86_PATCH_SIZE);
 330         if (!is_simm32(offset)) {
 331                 pr_err("Target call %p is out of range\n", func);
 332                 return -ERANGE;
 333         }
 334         EMIT1_off32(opcode, offset);
 335         *pprog = prog;
 336         return 0;
 337 }
 338
 339 static int emit_call(u8 **pprog, void *func, void *ip)
 340 {
 341         return emit_patch(pprog, func, ip, 0xE8);
 342 }
 343
 344 static int emit_rsb_call(u8 **pprog, void *func, void *ip)
 345 {
 346         OPTIMIZER_HIDE_VAR(func);
 347         x86_call_depth_emit_accounting(pprog, func);
 348         return emit_patch(pprog, func, ip, 0xE8);
 349 }
 350
 351 static int emit_jump(u8 **pprog, void *func, void *ip)
 352 {
 353         return emit_patch(pprog, func, ip, 0xE9);
 354 }
 355
 356 static int __bpf_arch_text_poke(void *ip, enum bpf_text_poke_type t,
 357                                 void *old_addr, void *new_addr)
 358 {
 359         const u8 *nop_insn = x86_nops[5];
 360         u8 old_insn[X86_PATCH_SIZE];
 361         u8 new_insn[X86_PATCH_SIZE];
 362         u8 *prog;
 363         int ret;
 364
 365         memcpy(old_insn, nop_insn, X86_PATCH_SIZE);
 366         if (old_addr) {
 367                 prog = old_insn;
 368                 ret = t == BPF_MOD_CALL ?
 369                       emit_call(&prog, old_addr, ip) :
 370                       emit_jump(&prog, old_addr, ip);
 371                 if (ret)
 372                         return ret;
 373         }
 374
 375         memcpy(new_insn, nop_insn, X86_PATCH_SIZE);
 376         if (new_addr) {
 377                 prog = new_insn;
 378                 ret = t == BPF_MOD_CALL ?
 379                       emit_call(&prog, new_addr, ip) :
 380                       emit_jump(&prog, new_addr, ip);
 381                 if (ret)
 382                         return ret;
 383         }
 384
 385         ret = -EBUSY;
 386         mutex_lock(&text_mutex);
 387         if (memcmp(ip, old_insn, X86_PATCH_SIZE))
 388                 goto out;
 389         ret = 1;
 390         if (memcmp(ip, new_insn, X86_PATCH_SIZE)) {
 391                 text_poke_bp(ip, new_insn, X86_PATCH_SIZE, NULL);
 392                 ret = 0;
 393         }
 394 out:
 395         mutex_unlock(&text_mutex);
 396         return ret;
 397 }
 398
 399 int bpf_arch_text_poke(void *ip, enum bpf_text_poke_type t,
 400                        void *old_addr, void *new_addr)
 401 {
 402         if (!is_kernel_text((long)ip) &&
 403             !is_bpf_text_address((long)ip))
 404                 /* BPF poking in modules is not supported */
 405                 return -EINVAL;
 406
 407         /*
 408          * See emit_prologue(), for IBT builds the trampoline hook is preceded
 409          * with an ENDBR instruction.
 410          */
 411         if (is_endbr(*(u32 *)ip))
 412                 ip += ENDBR_INSN_SIZE;
 413
 414         return __bpf_arch_text_poke(ip, t, old_addr, new_addr);
 415 }
 416
 417 #define EMIT_LFENCE()   EMIT3(0x0F, 0xAE, 0xE8)
 418
 419 static void emit_indirect_jump(u8 **pprog, int reg, u8 *ip)
 420 {
 421         u8 *prog = *pprog;
 422
 423         if (cpu_feature_enabled(X86_FEATURE_RETPOLINE_LFENCE)) {
 424                 EMIT_LFENCE();
 425                 EMIT2(0xFF, 0xE0 + reg);
 426         } else if (cpu_feature_enabled(X86_FEATURE_RETPOLINE)) {
 427                 OPTIMIZER_HIDE_VAR(reg);
 428                 if (cpu_feature_enabled(X86_FEATURE_CALL_DEPTH))
 429                         emit_jump(&prog, &__x86_indirect_jump_thunk_array[reg], ip);
 430                 else
 431                         emit_jump(&prog, &__x86_indirect_thunk_array[reg], ip);
 432         } else {
 433                 EMIT2(0xFF, 0xE0 + reg);        /* jmp *%\reg */
 434                 if (IS_ENABLED(CONFIG_RETPOLINE) || IS_ENABLED(CONFIG_SLS))
 435                         EMIT1(0xCC);            /* int3 */
 436         }
 437
 438         *pprog = prog;
 439 }
 440
 441 static void emit_return(u8 **pprog, u8 *ip)
 442 {
 443         u8 *prog = *pprog;
 444
 445         if (cpu_feature_enabled(X86_FEATURE_RETHUNK)) {
 446                 emit_jump(&prog, x86_return_thunk, ip);
 447         } else {
 448                 EMIT1(0xC3);            /* ret */
 449                 if (IS_ENABLED(CONFIG_SLS))
 450                         EMIT1(0xCC);    /* int3 */
 451         }
 452
 453         *pprog = prog;
 454 }
 455
 456 /*
 457  * Generate the following code:
 458  *
 459  * ... bpf_tail_call(void *ctx, struct bpf_array *array, u64 index) ...
 460  *   if (index >= array->map.max_entries)
 461  *     goto out;
 462  *   if (tail_call_cnt++ >= MAX_TAIL_CALL_CNT)
 463  *     goto out;
 464  *   prog = array->ptrs[index];
 465  *   if (prog == NULL)
 466  *     goto out;
 467  *   goto *(prog->bpf_func + prologue_size);
 468  * out:
 469  */
 470 static void emit_bpf_tail_call_indirect(u8 **pprog, bool *callee_regs_used,
 471                                         u32 stack_depth, u8 *ip,
 472                                         struct jit_context *ctx)
 473 {
 474         int tcc_off = -4 - round_up(stack_depth, 8);
 475         u8 *prog = *pprog, *start = *pprog;
 476         int offset;
 477
 478         /*
 479          * rdi - pointer to ctx
 480          * rsi - pointer to bpf_array
 481          * rdx - index in bpf_array
 482          */
 483
 484         /*
 485          * if (index >= array->map.max_entries)
 486          *      goto out;
 487          */
 488         EMIT2(0x89, 0xD2);                        /* mov edx, edx */
 489         EMIT3(0x39, 0x56,                         /* cmp dword ptr [rsi + 16], edx */
 490               offsetof(struct bpf_array, map.max_entries));
 491
 492         offset = ctx->tail_call_indirect_label - (prog + 2 - start);
 493         EMIT2(X86_JBE, offset);                   /* jbe out */
 494
 495         /*
 496          * if (tail_call_cnt++ >= MAX_TAIL_CALL_CNT)
 497          *      goto out;
 498          */
 499         EMIT2_off32(0x8B, 0x85, tcc_off);         /* mov eax, dword ptr [rbp - tcc_off] */
 500         EMIT3(0x83, 0xF8, MAX_TAIL_CALL_CNT);     /* cmp eax, MAX_TAIL_CALL_CNT */
 501
 502         offset = ctx->tail_call_indirect_label - (prog + 2 - start);
 503         EMIT2(X86_JAE, offset);                   /* jae out */
 504         EMIT3(0x83, 0xC0, 0x01);                  /* add eax, 1 */
 505         EMIT2_off32(0x89, 0x85, tcc_off);         /* mov dword ptr [rbp - tcc_off], eax */
 506
 507         /* prog = array->ptrs[index]; */
 508         EMIT4_off32(0x48, 0x8B, 0x8C, 0xD6,       /* mov rcx, [rsi + rdx * 8 + offsetof(...)] */
 509                     offsetof(struct bpf_array, ptrs));
 510
 511         /*
 512          * if (prog == NULL)
 513          *      goto out;
 514          */
 515         EMIT3(0x48, 0x85, 0xC9);                  /* test rcx,rcx */
 516
 517         offset = ctx->tail_call_indirect_label - (prog + 2 - start);
 518         EMIT2(X86_JE, offset);                    /* je out */
 519
 520         pop_callee_regs(&prog, callee_regs_used);
 521
 522         EMIT1(0x58);                              /* pop rax */
 523         if (stack_depth)
 524                 EMIT3_off32(0x48, 0x81, 0xC4,     /* add rsp, sd */
 525                             round_up(stack_depth, 8));
 526
 527         /* goto *(prog->bpf_func + X86_TAIL_CALL_OFFSET); */
 528         EMIT4(0x48, 0x8B, 0x49,                   /* mov rcx, qword ptr [rcx + 32] */
 529               offsetof(struct bpf_prog, bpf_func));
 530         EMIT4(0x48, 0x83, 0xC1,                   /* add rcx, X86_TAIL_CALL_OFFSET */
 531               X86_TAIL_CALL_OFFSET);
 532         /*
 533          * Now we're ready to jump into next BPF program
 534          * rdi == ctx (1st arg)
 535          * rcx == prog->bpf_func + X86_TAIL_CALL_OFFSET
 536          */
 537         emit_indirect_jump(&prog, 1 /* rcx */, ip + (prog - start));
 538
 539         /* out: */
 540         ctx->tail_call_indirect_label = prog - start;
 541         *pprog = prog;
 542 }
 543
 544 static void emit_bpf_tail_call_direct(struct bpf_jit_poke_descriptor *poke,
 545                                       u8 **pprog, u8 *ip,
 546                                       bool *callee_regs_used, u32 stack_depth,
 547                                       struct jit_context *ctx)
 548 {
 549         int tcc_off = -4 - round_up(stack_depth, 8);
 550         u8 *prog = *pprog, *start = *pprog;
 551         int offset;
 552
 553         /*
 554          * if (tail_call_cnt++ >= MAX_TAIL_CALL_CNT)
 555          *      goto out;
 556          */
 557         EMIT2_off32(0x8B, 0x85, tcc_off);             /* mov eax, dword ptr [rbp - tcc_off] */
 558         EMIT3(0x83, 0xF8, MAX_TAIL_CALL_CNT);         /* cmp eax, MAX_TAIL_CALL_CNT */
 559
 560         offset = ctx->tail_call_direct_label - (prog + 2 - start);
 561         EMIT2(X86_JAE, offset);                       /* jae out */
 562         EMIT3(0x83, 0xC0, 0x01);                      /* add eax, 1 */
 563         EMIT2_off32(0x89, 0x85, tcc_off);             /* mov dword ptr [rbp - tcc_off], eax */
 564
 565         poke->tailcall_bypass = ip + (prog - start);
 566         poke->adj_off = X86_TAIL_CALL_OFFSET;
 567         poke->tailcall_target = ip + ctx->tail_call_direct_label - X86_PATCH_SIZE;
 568         poke->bypass_addr = (u8 *)poke->tailcall_target + X86_PATCH_SIZE;
 569
 570         emit_jump(&prog, (u8 *)poke->tailcall_target + X86_PATCH_SIZE,
 571                   poke->tailcall_bypass);
 572
 573         pop_callee_regs(&prog, callee_regs_used);
 574         EMIT1(0x58);                                  /* pop rax */
 575         if (stack_depth)
 576                 EMIT3_off32(0x48, 0x81, 0xC4, round_up(stack_depth, 8));
 577
 578         memcpy(prog, x86_nops[5], X86_PATCH_SIZE);
 579         prog += X86_PATCH_SIZE;
 580
 581         /* out: */
 582         ctx->tail_call_direct_label = prog - start;
 583
 584         *pprog = prog;
 585 }
 586
 587 static void bpf_tail_call_direct_fixup(struct bpf_prog *prog)
 588 {
 589         struct bpf_jit_poke_descriptor *poke;
 590         struct bpf_array *array;
 591         struct bpf_prog *target;
 592         int i, ret;
 593
 594         for (i = 0; i < prog->aux->size_poke_tab; i++) {
 595                 poke = &prog->aux->poke_tab[i];
 596                 if (poke->aux && poke->aux != prog->aux)
 597                         continue;
 598
 599                 WARN_ON_ONCE(READ_ONCE(poke->tailcall_target_stable));
 600
 601                 if (poke->reason != BPF_POKE_REASON_TAIL_CALL)
 602                         continue;
 603
 604                 array = container_of(poke->tail_call.map, struct bpf_array, map);
 605                 mutex_lock(&array->aux->poke_mutex);
 606                 target = array->ptrs[poke->tail_call.key];
 607                 if (target) {
 608                         ret = __bpf_arch_text_poke(poke->tailcall_target,
 609                                                    BPF_MOD_JUMP, NULL,
 610                                                    (u8 *)target->bpf_func +
 611                                                    poke->adj_off);
 612                         BUG_ON(ret < 0);
 613                         ret = __bpf_arch_text_poke(poke->tailcall_bypass,
 614                                                    BPF_MOD_JUMP,
 615                                                    (u8 *)poke->tailcall_target +
 616                                                    X86_PATCH_SIZE, NULL);
 617                         BUG_ON(ret < 0);
 618                 }
 619                 WRITE_ONCE(poke->tailcall_target_stable, true);
 620                 mutex_unlock(&array->aux->poke_mutex);
 621         }
 622 }
 623
 624 static void emit_mov_imm32(u8 **pprog, bool sign_propagate,
 625                            u32 dst_reg, const u32 imm32)
 626 {
 627         u8 *prog = *pprog;
 628         u8 b1, b2, b3;
 629
 630         /*
 631          * Optimization: if imm32 is positive, use 'mov %eax, imm32'
 632          * (which zero-extends imm32) to save 2 bytes.
 633          */
 634         if (sign_propagate && (s32)imm32 < 0) {
 635                 /* 'mov %rax, imm32' sign extends imm32 */
 636                 b1 = add_1mod(0x48, dst_reg);
 637                 b2 = 0xC7;
 638                 b3 = 0xC0;
 639                 EMIT3_off32(b1, b2, add_1reg(b3, dst_reg), imm32);
 640                 goto done;
 641         }
 642
 643         /*
 644          * Optimization: if imm32 is zero, use 'xor %eax, %eax'
 645          * to save 3 bytes.
 646          */
 647         if (imm32 == 0) {
 648                 if (is_ereg(dst_reg))
 649                         EMIT1(add_2mod(0x40, dst_reg, dst_reg));
 650                 b2 = 0x31; /* xor */
 651                 b3 = 0xC0;
 652                 EMIT2(b2, add_2reg(b3, dst_reg, dst_reg));
 653                 goto done;
 654         }
 655
 656         /* mov %eax, imm32 */
 657         if (is_ereg(dst_reg))
 658                 EMIT1(add_1mod(0x40, dst_reg));
 659         EMIT1_off32(add_1reg(0xB8, dst_reg), imm32);
 660 done:
 661         *pprog = prog;
 662 }
 663
 664 static void emit_mov_imm64(u8 **pprog, u32 dst_reg,
 665                            const u32 imm32_hi, const u32 imm32_lo)
 666 {
 667         u8 *prog = *pprog;
 668
 669         if (is_uimm32(((u64)imm32_hi << 32) | (u32)imm32_lo)) {
 670                 /*
 671                  * For emitting plain u32, where sign bit must not be
 672                  * propagated LLVM tends to load imm64 over mov32
 673                  * directly, so save couple of bytes by just doing
 674                  * 'mov %eax, imm32' instead.
 675                  */
 676                 emit_mov_imm32(&prog, false, dst_reg, imm32_lo);
 677         } else {
 678                 /* movabsq rax, imm64 */
 679                 EMIT2(add_1mod(0x48, dst_reg), add_1reg(0xB8, dst_reg));
 680                 EMIT(imm32_lo, 4);
 681                 EMIT(imm32_hi, 4);
 682         }
 683
 684         *pprog = prog;
 685 }
 686
 687 static void emit_mov_reg(u8 **pprog, bool is64, u32 dst_reg, u32 src_reg)
 688 {
 689         u8 *prog = *pprog;
 690
 691         if (is64) {
 692                 /* mov dst, src */
 693                 EMIT_mov(dst_reg, src_reg);
 694         } else {
 695                 /* mov32 dst, src */
 696                 if (is_ereg(dst_reg) || is_ereg(src_reg))
 697                         EMIT1(add_2mod(0x40, dst_reg, src_reg));
 698                 EMIT2(0x89, add_2reg(0xC0, dst_reg, src_reg));
 699         }
 700
 701         *pprog = prog;
 702 }
 703
 704 /* Emit the suffix (ModR/M etc) for addressing *(ptr_reg + off) and val_reg */
 705 static void emit_insn_suffix(u8 **pprog, u32 ptr_reg, u32 val_reg, int off)
 706 {
 707         u8 *prog = *pprog;
 708
 709         if (is_imm8(off)) {
 710                 /* 1-byte signed displacement.
 711                  *
 712                  * If off == 0 we could skip this and save one extra byte, but
 713                  * special case of x86 R13 which always needs an offset is not
 714                  * worth the hassle
 715                  */
 716                 EMIT2(add_2reg(0x40, ptr_reg, val_reg), off);
 717         } else {
 718                 /* 4-byte signed displacement */
 719                 EMIT1_off32(add_2reg(0x80, ptr_reg, val_reg), off);
 720         }
 721         *pprog = prog;
 722 }
 723
 724 /*
 725  * Emit a REX byte if it will be necessary to address these registers
 726  */
 727 static void maybe_emit_mod(u8 **pprog, u32 dst_reg, u32 src_reg, bool is64)
 728 {
 729         u8 *prog = *pprog;
 730
 731         if (is64)
 732                 EMIT1(add_2mod(0x48, dst_reg, src_reg));
 733         else if (is_ereg(dst_reg) || is_ereg(src_reg))
 734                 EMIT1(add_2mod(0x40, dst_reg, src_reg));
 735         *pprog = prog;
 736 }
 737
 738 /*
 739  * Similar version of maybe_emit_mod() for a single register
 740  */
 741 static void maybe_emit_1mod(u8 **pprog, u32 reg, bool is64)
 742 {
 743         u8 *prog = *pprog;
 744
 745         if (is64)
 746                 EMIT1(add_1mod(0x48, reg));
 747         else if (is_ereg(reg))
 748                 EMIT1(add_1mod(0x40, reg));
 749         *pprog = prog;
 750 }
 751
 752 /* LDX: dst_reg = *(u8*)(src_reg + off) */
 753 static void emit_ldx(u8 **pprog, u32 size, u32 dst_reg, u32 src_reg, int off)
 754 {
 755         u8 *prog = *pprog;
 756
 757         switch (size) {
 758         case BPF_B:
 759                 /* Emit 'movzx rax, byte ptr [rax + off]' */
 760                 EMIT3(add_2mod(0x48, src_reg, dst_reg), 0x0F, 0xB6);
 761                 break;
 762         case BPF_H:
 763                 /* Emit 'movzx rax, word ptr [rax + off]' */
 764                 EMIT3(add_2mod(0x48, src_reg, dst_reg), 0x0F, 0xB7);
 765                 break;
 766         case BPF_W:
 767                 /* Emit 'mov eax, dword ptr [rax+0x14]' */
 768                 if (is_ereg(dst_reg) || is_ereg(src_reg))
 769                         EMIT2(add_2mod(0x40, src_reg, dst_reg), 0x8B);
 770                 else
 771                         EMIT1(0x8B);
 772                 break;
 773         case BPF_DW:
 774                 /* Emit 'mov rax, qword ptr [rax+0x14]' */
 775                 EMIT2(add_2mod(0x48, src_reg, dst_reg), 0x8B);
 776                 break;
 777         }
 778         emit_insn_suffix(&prog, src_reg, dst_reg, off);
 779         *pprog = prog;
 780 }
 781
 782 /* STX: *(u8*)(dst_reg + off) = src_reg */
 783 static void emit_stx(u8 **pprog, u32 size, u32 dst_reg, u32 src_reg, int off)
 784 {
 785         u8 *prog = *pprog;
 786
 787         switch (size) {
 788         case BPF_B:
 789                 /* Emit 'mov byte ptr [rax + off], al' */
 790                 if (is_ereg(dst_reg) || is_ereg_8l(src_reg))
 791                         /* Add extra byte for eregs or SIL,DIL,BPL in src_reg */
 792                         EMIT2(add_2mod(0x40, dst_reg, src_reg), 0x88);
 793                 else
 794                         EMIT1(0x88);
 795                 break;
 796         case BPF_H:
 797                 if (is_ereg(dst_reg) || is_ereg(src_reg))
 798                         EMIT3(0x66, add_2mod(0x40, dst_reg, src_reg), 0x89);
 799                 else
 800                         EMIT2(0x66, 0x89);
 801                 break;
 802         case BPF_W:
 803                 if (is_ereg(dst_reg) || is_ereg(src_reg))
 804                         EMIT2(add_2mod(0x40, dst_reg, src_reg), 0x89);
 805                 else
 806                         EMIT1(0x89);
 807                 break;
 808         case BPF_DW:
 809                 EMIT2(add_2mod(0x48, dst_reg, src_reg), 0x89);
 810                 break;
 811         }
 812         emit_insn_suffix(&prog, dst_reg, src_reg, off);
 813         *pprog = prog;
 814 }
 815
 816 static int emit_atomic(u8 **pprog, u8 atomic_op,
 817                        u32 dst_reg, u32 src_reg, s16 off, u8 bpf_size)
 818 {
 819         u8 *prog = *pprog;
 820
 821         EMIT1(0xF0); /* lock prefix */
 822
 823         maybe_emit_mod(&prog, dst_reg, src_reg, bpf_size == BPF_DW);
 824
 825         /* emit opcode */
 826         switch (atomic_op) {
 827         case BPF_ADD:
 828         case BPF_AND:
 829         case BPF_OR:
 830         case BPF_XOR:
 831                 /* lock *(u32/u64*)(dst_reg + off) <op>= src_reg */
 832                 EMIT1(simple_alu_opcodes[atomic_op]);
 833                 break;
 834         case BPF_ADD | BPF_FETCH:
 835                 /* src_reg = atomic_fetch_add(dst_reg + off, src_reg); */
 836                 EMIT2(0x0F, 0xC1);
 837                 break;
 838         case BPF_XCHG:
 839                 /* src_reg = atomic_xchg(dst_reg + off, src_reg); */
 840                 EMIT1(0x87);
 841                 break;
 842         case BPF_CMPXCHG:
 843                 /* r0 = atomic_cmpxchg(dst_reg + off, r0, src_reg); */
 844                 EMIT2(0x0F, 0xB1);
 845                 break;
 846         default:
 847                 pr_err("bpf_jit: unknown atomic opcode %02x\n", atomic_op);
 848                 return -EFAULT;
 849         }
 850
 851         emit_insn_suffix(&prog, dst_reg, src_reg, off);
 852
 853         *pprog = prog;
 854         return 0;
 855 }
 856
 857 bool ex_handler_bpf(const struct exception_table_entry *x, struct pt_regs *regs)
 858 {
 859         u32 reg = x->fixup >> 8;
 860
 861         /* jump over faulting load and clear dest register */
 862         *(unsigned long *)((void *)regs + reg) = 0;
 863         regs->ip += x->fixup & 0xff;
 864         return true;
 865 }
 866
 867 static void detect_reg_usage(struct bpf_insn *insn, int insn_cnt,
 868                              bool *regs_used, bool *tail_call_seen)
 869 {
 870         int i;
 871
 872         for (i = 1; i <= insn_cnt; i++, insn++) {
 873                 if (insn->code == (BPF_JMP | BPF_TAIL_CALL))
 874                         *tail_call_seen = true;
 875                 if (insn->dst_reg == BPF_REG_6 || insn->src_reg == BPF_REG_6)
 876                         regs_used[0] = true;
 877                 if (insn->dst_reg == BPF_REG_7 || insn->src_reg == BPF_REG_7)
 878                         regs_used[1] = true;
 879                 if (insn->dst_reg == BPF_REG_8 || insn->src_reg == BPF_REG_8)
 880                         regs_used[2] = true;
 881                 if (insn->dst_reg == BPF_REG_9 || insn->src_reg == BPF_REG_9)
 882                         regs_used[3] = true;
 883         }
 884 }
 885
 886 static void emit_nops(u8 **pprog, int len)
 887 {
 888         u8 *prog = *pprog;
 889         int i, noplen;
 890
 891         while (len > 0) {
 892                 noplen = len;
 893
 894                 if (noplen > ASM_NOP_MAX)
 895                         noplen = ASM_NOP_MAX;
 896
 897                 for (i = 0; i < noplen; i++)
 898                         EMIT1(x86_nops[noplen][i]);
 899                 len -= noplen;
 900         }
 901
 902         *pprog = prog;
 903 }
 904
 905 /* emit the 3-byte VEX prefix
 906  *
 907  * r: same as rex.r, extra bit for ModRM reg field
 908  * x: same as rex.x, extra bit for SIB index field
 909  * b: same as rex.b, extra bit for ModRM r/m, or SIB base
 910  * m: opcode map select, encoding escape bytes e.g. 0x0f38
 911  * w: same as rex.w (32 bit or 64 bit) or opcode specific
 912  * src_reg2: additional source reg (encoded as BPF reg)
 913  * l: vector length (128 bit or 256 bit) or reserved
 914  * pp: opcode prefix (none, 0x66, 0xf2 or 0xf3)
 915  */
 916 static void emit_3vex(u8 **pprog, bool r, bool x, bool b, u8 m,
 917                       bool w, u8 src_reg2, bool l, u8 pp)
 918 {
 919         u8 *prog = *pprog;
 920         const u8 b0 = 0xc4; /* first byte of 3-byte VEX prefix */
 921         u8 b1, b2;
 922         u8 vvvv = reg2hex[src_reg2];
 923
 924         /* reg2hex gives only the lower 3 bit of vvvv */
 925         if (is_ereg(src_reg2))
 926                 vvvv |= 1 << 3;
 927
 928         /*
 929          * 2nd byte of 3-byte VEX prefix
 930          * ~ means bit inverted encoding
 931          *
 932          *    7                           0
 933          *  +---+---+---+---+---+---+---+---+
 934          *  |~R |~X |~B |         m         |
 935          *  +---+---+---+---+---+---+---+---+
 936          */
 937         b1 = (!r << 7) | (!x << 6) | (!b << 5) | (m & 0x1f);
 938         /*
 939          * 3rd byte of 3-byte VEX prefix
 940          *
 941          *    7                           0
 942          *  +---+---+---+---+---+---+---+---+
 943          *  | W |     ~vvvv     | L |   pp  |
 944          *  +---+---+---+---+---+---+---+---+
 945          */
 946         b2 = (w << 7) | ((~vvvv & 0xf) << 3) | (l << 2) | (pp & 3);
 947
 948         EMIT3(b0, b1, b2);
 949         *pprog = prog;
 950 }
 951
 952 /* emit BMI2 shift instruction */
 953 static void emit_shiftx(u8 **pprog, u32 dst_reg, u8 src_reg, bool is64, u8 op)
 954 {
 955         u8 *prog = *pprog;
 956         bool r = is_ereg(dst_reg);
 957         u8 m = 2; /* escape code 0f38 */
 958
 959         emit_3vex(&prog, r, false, r, m, is64, src_reg, false, op);
 960         EMIT2(0xf7, add_2reg(0xC0, dst_reg, dst_reg));
 961         *pprog = prog;
 962 }
 963
 964 #define INSN_SZ_DIFF (((addrs[i] - addrs[i - 1]) - (prog - temp)))
 965
 966 static int do_jit(struct bpf_prog *bpf_prog, int *addrs, u8 *image, u8 *rw_image,
 967                   int oldproglen, struct jit_context *ctx, bool jmp_padding)
 968 {
 969         bool tail_call_reachable = bpf_prog->aux->tail_call_reachable;
 970         struct bpf_insn *insn = bpf_prog->insnsi;
 971         bool callee_regs_used[4] = {};
 972         int insn_cnt = bpf_prog->len;
 973         bool tail_call_seen = false;
 974         bool seen_exit = false;
 975         u8 temp[BPF_MAX_INSN_SIZE + BPF_INSN_SAFETY];
 976         int i, excnt = 0;
 977         int ilen, proglen = 0;
 978         u8 *prog = temp;
 979         int err;
 980
 981         detect_reg_usage(insn, insn_cnt, callee_regs_used,
 982                          &tail_call_seen);
 983
 984         /* tail call's presence in current prog implies it is reachable */
 985         tail_call_reachable |= tail_call_seen;
 986
 987         emit_prologue(&prog, bpf_prog->aux->stack_depth,
 988                       bpf_prog_was_classic(bpf_prog), tail_call_reachable,
 989                       bpf_prog->aux->func_idx != 0);
 990         push_callee_regs(&prog, callee_regs_used);
 991
 992         ilen = prog - temp;
 993         if (rw_image)
 994                 memcpy(rw_image + proglen, temp, ilen);
 995         proglen += ilen;
 996         addrs[0] = proglen;
 997         prog = temp;
 998
 999         for (i = 1; i <= insn_cnt; i++, insn++) {
1000                 const s32 imm32 = insn->imm;
1001                 u32 dst_reg = insn->dst_reg;
1002                 u32 src_reg = insn->src_reg;
1003                 u8 b2 = 0, b3 = 0;
1004                 u8 *start_of_ldx;
1005                 s64 jmp_offset;
1006                 u8 jmp_cond;
1007                 u8 *func;
1008                 int nops;
1009
1010                 switch (insn->code) {
1011                         /* ALU */
1012                 case BPF_ALU | BPF_ADD | BPF_X:
1013                 case BPF_ALU | BPF_SUB | BPF_X:
1014                 case BPF_ALU | BPF_AND | BPF_X:
1015                 case BPF_ALU | BPF_OR | BPF_X:
1016                 case BPF_ALU | BPF_XOR | BPF_X:
1017                 case BPF_ALU64 | BPF_ADD | BPF_X:
1018                 case BPF_ALU64 | BPF_SUB | BPF_X:
1019                 case BPF_ALU64 | BPF_AND | BPF_X:
1020                 case BPF_ALU64 | BPF_OR | BPF_X:
1021                 case BPF_ALU64 | BPF_XOR | BPF_X:
1022                         maybe_emit_mod(&prog, dst_reg, src_reg,
1023                                        BPF_CLASS(insn->code) == BPF_ALU64);
1024                         b2 = simple_alu_opcodes[BPF_OP(insn->code)];
1025                         EMIT2(b2, add_2reg(0xC0, dst_reg, src_reg));
1026                         break;
1027
1028                 case BPF_ALU64 | BPF_MOV | BPF_X:
1029                 case BPF_ALU | BPF_MOV | BPF_X:
1030                         emit_mov_reg(&prog,
1031                                      BPF_CLASS(insn->code) == BPF_ALU64,
1032                                      dst_reg, src_reg);
1033                         break;
1034
1035                         /* neg dst */
1036                 case BPF_ALU | BPF_NEG:
1037                 case BPF_ALU64 | BPF_NEG:
1038                         maybe_emit_1mod(&prog, dst_reg,
1039                                         BPF_CLASS(insn->code) == BPF_ALU64);
1040                         EMIT2(0xF7, add_1reg(0xD8, dst_reg));
1041                         break;
1042
1043                 case BPF_ALU | BPF_ADD | BPF_K:
1044                 case BPF_ALU | BPF_SUB | BPF_K:
1045                 case BPF_ALU | BPF_AND | BPF_K:
1046                 case BPF_ALU | BPF_OR | BPF_K:
1047                 case BPF_ALU | BPF_XOR | BPF_K:
1048                 case BPF_ALU64 | BPF_ADD | BPF_K:
1049                 case BPF_ALU64 | BPF_SUB | BPF_K:
1050                 case BPF_ALU64 | BPF_AND | BPF_K:
1051                 case BPF_ALU64 | BPF_OR | BPF_K:
1052                 case BPF_ALU64 | BPF_XOR | BPF_K:
1053                         maybe_emit_1mod(&prog, dst_reg,
1054                                         BPF_CLASS(insn->code) == BPF_ALU64);
1055
1056                         /*
1057                          * b3 holds 'normal' opcode, b2 short form only valid
1058                          * in case dst is eax/rax.
1059                          */
1060                         switch (BPF_OP(insn->code)) {
1061                         case BPF_ADD:
1062                                 b3 = 0xC0;
1063                                 b2 = 0x05;
1064                                 break;
1065                         case BPF_SUB:
1066                                 b3 = 0xE8;
1067                                 b2 = 0x2D;
1068                                 break;
1069                         case BPF_AND:
1070                                 b3 = 0xE0;
1071                                 b2 = 0x25;
1072                                 break;
1073                         case BPF_OR:
1074                                 b3 = 0xC8;
1075                                 b2 = 0x0D;
1076                                 break;
1077                         case BPF_XOR:
1078                                 b3 = 0xF0;
1079                                 b2 = 0x35;
1080                                 break;
1081                         }
1082
1083                         if (is_imm8(imm32))
1084                                 EMIT3(0x83, add_1reg(b3, dst_reg), imm32);
1085                         else if (is_axreg(dst_reg))
1086                                 EMIT1_off32(b2, imm32);
1087                         else
1088                                 EMIT2_off32(0x81, add_1reg(b3, dst_reg), imm32);
1089                         break;
1090
1091                 case BPF_ALU64 | BPF_MOV | BPF_K:
1092                 case BPF_ALU | BPF_MOV | BPF_K:
1093                         emit_mov_imm32(&prog, BPF_CLASS(insn->code) == BPF_ALU64,
1094                                        dst_reg, imm32);
1095                         break;
1096
1097                 case BPF_LD | BPF_IMM | BPF_DW:
1098                         emit_mov_imm64(&prog, dst_reg, insn[1].imm, insn[0].imm);
1099                         insn++;
1100                         i++;
1101                         break;
1102
1103                         /* dst %= src, dst /= src, dst %= imm32, dst /= imm32 */
1104                 case BPF_ALU | BPF_MOD | BPF_X:
1105                 case BPF_ALU | BPF_DIV | BPF_X:
1106                 case BPF_ALU | BPF_MOD | BPF_K:
1107                 case BPF_ALU | BPF_DIV | BPF_K:
1108                 case BPF_ALU64 | BPF_MOD | BPF_X:
1109                 case BPF_ALU64 | BPF_DIV | BPF_X:
1110                 case BPF_ALU64 | BPF_MOD | BPF_K:
1111                 case BPF_ALU64 | BPF_DIV | BPF_K: {
1112                         bool is64 = BPF_CLASS(insn->code) == BPF_ALU64;
1113
1114                         if (dst_reg != BPF_REG_0)
1115                                 EMIT1(0x50); /* push rax */
1116                         if (dst_reg != BPF_REG_3)
1117                                 EMIT1(0x52); /* push rdx */
1118
1119                         if (BPF_SRC(insn->code) == BPF_X) {
1120                                 if (src_reg == BPF_REG_0 ||
1121                                     src_reg == BPF_REG_3) {
1122                                         /* mov r11, src_reg */
1123                                         EMIT_mov(AUX_REG, src_reg);
1124                                         src_reg = AUX_REG;
1125                                 }
1126                         } else {
1127                                 /* mov r11, imm32 */
1128                                 EMIT3_off32(0x49, 0xC7, 0xC3, imm32);
1129                                 src_reg = AUX_REG;
1130                         }
1131
1132                         if (dst_reg != BPF_REG_0)
1133                                 /* mov rax, dst_reg */
1134                                 emit_mov_reg(&prog, is64, BPF_REG_0, dst_reg);
1135
1136                         /*
1137                          * xor edx, edx
1138                          * equivalent to 'xor rdx, rdx', but one byte less
1139                          */
1140                         EMIT2(0x31, 0xd2);
1141
1142                         /* div src_reg */
1143                         maybe_emit_1mod(&prog, src_reg, is64);
1144                         EMIT2(0xF7, add_1reg(0xF0, src_reg));
1145
1146                         if (BPF_OP(insn->code) == BPF_MOD &&
1147                             dst_reg != BPF_REG_3)
1148                                 /* mov dst_reg, rdx */
1149                                 emit_mov_reg(&prog, is64, dst_reg, BPF_REG_3);
1150                         else if (BPF_OP(insn->code) == BPF_DIV &&
1151                                  dst_reg != BPF_REG_0)
1152                                 /* mov dst_reg, rax */
1153                                 emit_mov_reg(&prog, is64, dst_reg, BPF_REG_0);
1154
1155                         if (dst_reg != BPF_REG_3)
1156                                 EMIT1(0x5A); /* pop rdx */
1157                         if (dst_reg != BPF_REG_0)
1158                                 EMIT1(0x58); /* pop rax */
1159                         break;
1160                 }
1161
1162                 case BPF_ALU | BPF_MUL | BPF_K:
1163                 case BPF_ALU64 | BPF_MUL | BPF_K:
1164                         maybe_emit_mod(&prog, dst_reg, dst_reg,
1165                                        BPF_CLASS(insn->code) == BPF_ALU64);
1166
1167                         if (is_imm8(imm32))
1168                                 /* imul dst_reg, dst_reg, imm8 */
1169                                 EMIT3(0x6B, add_2reg(0xC0, dst_reg, dst_reg),
1170                                       imm32);
1171                         else
1172                                 /* imul dst_reg, dst_reg, imm32 */
1173                                 EMIT2_off32(0x69,
1174                                             add_2reg(0xC0, dst_reg, dst_reg),
1175                                             imm32);
1176                         break;
1177
1178                 case BPF_ALU | BPF_MUL | BPF_X:
1179                 case BPF_ALU64 | BPF_MUL | BPF_X:
1180                         maybe_emit_mod(&prog, src_reg, dst_reg,
1181                                        BPF_CLASS(insn->code) == BPF_ALU64);
1182
1183                         /* imul dst_reg, src_reg */
1184                         EMIT3(0x0F, 0xAF, add_2reg(0xC0, src_reg, dst_reg));
1185                         break;
1186
1187                         /* Shifts */
1188                 case BPF_ALU | BPF_LSH | BPF_K:
1189                 case BPF_ALU | BPF_RSH | BPF_K:
1190                 case BPF_ALU | BPF_ARSH | BPF_K:
1191                 case BPF_ALU64 | BPF_LSH | BPF_K:
1192                 case BPF_ALU64 | BPF_RSH | BPF_K:
1193                 case BPF_ALU64 | BPF_ARSH | BPF_K:
1194                         maybe_emit_1mod(&prog, dst_reg,
1195                                         BPF_CLASS(insn->code) == BPF_ALU64);
1196
1197                         b3 = simple_alu_opcodes[BPF_OP(insn->code)];
1198                         if (imm32 == 1)
1199                                 EMIT2(0xD1, add_1reg(b3, dst_reg));
1200                         else
1201                                 EMIT3(0xC1, add_1reg(b3, dst_reg), imm32);
1202                         break;
1203
1204                 case BPF_ALU | BPF_LSH | BPF_X:
1205                 case BPF_ALU | BPF_RSH | BPF_X:
1206                 case BPF_ALU | BPF_ARSH | BPF_X:
1207                 case BPF_ALU64 | BPF_LSH | BPF_X:
1208                 case BPF_ALU64 | BPF_RSH | BPF_X:
1209                 case BPF_ALU64 | BPF_ARSH | BPF_X:
1210                         /* BMI2 shifts aren't better when shift count is already in rcx */
1211                         if (boot_cpu_has(X86_FEATURE_BMI2) && src_reg != BPF_REG_4) {
1212                                 /* shrx/sarx/shlx dst_reg, dst_reg, src_reg */
1213                                 bool w = (BPF_CLASS(insn->code) == BPF_ALU64);
1214                                 u8 op;
1215
1216                                 switch (BPF_OP(insn->code)) {
1217                                 case BPF_LSH:
1218                                         op = 1; /* prefix 0x66 */
1219                                         break;
1220                                 case BPF_RSH:
1221                                         op = 3; /* prefix 0xf2 */
1222                                         break;
1223                                 case BPF_ARSH:
1224                                         op = 2; /* prefix 0xf3 */
1225                                         break;
1226                                 }
1227
1228                                 emit_shiftx(&prog, dst_reg, src_reg, w, op);
1229
1230                                 break;
1231                         }
1232
1233                         if (src_reg != BPF_REG_4) { /* common case */
1234                                 /* Check for bad case when dst_reg == rcx */
1235                                 if (dst_reg == BPF_REG_4) {
1236                                         /* mov r11, dst_reg */
1237                                         EMIT_mov(AUX_REG, dst_reg);
1238                                         dst_reg = AUX_REG;
1239                                 } else {
1240                                         EMIT1(0x51); /* push rcx */
1241                                 }
1242                                 /* mov rcx, src_reg */
1243                                 EMIT_mov(BPF_REG_4, src_reg);
1244                         }
1245
1246                         /* shl %rax, %cl | shr %rax, %cl | sar %rax, %cl */
1247                         maybe_emit_1mod(&prog, dst_reg,
1248                                         BPF_CLASS(insn->code) == BPF_ALU64);
1249
1250                         b3 = simple_alu_opcodes[BPF_OP(insn->code)];
1251                         EMIT2(0xD3, add_1reg(b3, dst_reg));
1252
1253                         if (src_reg != BPF_REG_4) {
1254                                 if (insn->dst_reg == BPF_REG_4)
1255                                         /* mov dst_reg, r11 */
1256                                         EMIT_mov(insn->dst_reg, AUX_REG);
1257                                 else
1258                                         EMIT1(0x59); /* pop rcx */
1259                         }
1260
1261                         break;
1262
1263                 case BPF_ALU | BPF_END | BPF_FROM_BE:
1264                         switch (imm32) {
1265                         case 16:
1266                                 /* Emit 'ror %ax, 8' to swap lower 2 bytes */
1267                                 EMIT1(0x66);
1268                                 if (is_ereg(dst_reg))
1269                                         EMIT1(0x41);
1270                                 EMIT3(0xC1, add_1reg(0xC8, dst_reg), 8);
1271
1272                                 /* Emit 'movzwl eax, ax' */
1273                                 if (is_ereg(dst_reg))
1274                                         EMIT3(0x45, 0x0F, 0xB7);
1275                                 else
1276                                         EMIT2(0x0F, 0xB7);
1277                                 EMIT1(add_2reg(0xC0, dst_reg, dst_reg));
1278                                 break;
1279                         case 32:
1280                                 /* Emit 'bswap eax' to swap lower 4 bytes */
1281                                 if (is_ereg(dst_reg))
1282                                         EMIT2(0x41, 0x0F);
1283                                 else
1284                                         EMIT1(0x0F);
1285                                 EMIT1(add_1reg(0xC8, dst_reg));
1286                                 break;
1287                         case 64:
1288                                 /* Emit 'bswap rax' to swap 8 bytes */
1289                                 EMIT3(add_1mod(0x48, dst_reg), 0x0F,
1290                                       add_1reg(0xC8, dst_reg));
1291                                 break;
1292                         }
1293                         break;
1294
1295                 case BPF_ALU | BPF_END | BPF_FROM_LE:
1296                         switch (imm32) {
1297                         case 16:
1298                                 /*
1299                                  * Emit 'movzwl eax, ax' to zero extend 16-bit
1300                                  * into 64 bit
1301                                  */
1302                                 if (is_ereg(dst_reg))
1303                                         EMIT3(0x45, 0x0F, 0xB7);
1304                                 else
1305                                         EMIT2(0x0F, 0xB7);
1306                                 EMIT1(add_2reg(0xC0, dst_reg, dst_reg));
1307                                 break;
1308                         case 32:
1309                                 /* Emit 'mov eax, eax' to clear upper 32-bits */
1310                                 if (is_ereg(dst_reg))
1311                                         EMIT1(0x45);
1312                                 EMIT2(0x89, add_2reg(0xC0, dst_reg, dst_reg));
1313                                 break;
1314                         case 64:
1315                                 /* nop */
1316                                 break;
1317                         }
1318                         break;
1319
1320                         /* speculation barrier */
1321                 case BPF_ST | BPF_NOSPEC:
1322                         EMIT_LFENCE();
1323                         break;
1324
1325                         /* ST: *(u8*)(dst_reg + off) = imm */
1326                 case BPF_ST | BPF_MEM | BPF_B:
1327                         if (is_ereg(dst_reg))
1328                                 EMIT2(0x41, 0xC6);
1329                         else
1330                                 EMIT1(0xC6);
1331                         goto st;
1332                 case BPF_ST | BPF_MEM | BPF_H:
1333                         if (is_ereg(dst_reg))
1334                                 EMIT3(0x66, 0x41, 0xC7);
1335                         else
1336                                 EMIT2(0x66, 0xC7);
1337                         goto st;
1338                 case BPF_ST | BPF_MEM | BPF_W:
1339                         if (is_ereg(dst_reg))
1340                                 EMIT2(0x41, 0xC7);
1341                         else
1342                                 EMIT1(0xC7);
1343                         goto st;
1344                 case BPF_ST | BPF_MEM | BPF_DW:
1345                         EMIT2(add_1mod(0x48, dst_reg), 0xC7);
1346
1347 st:                     if (is_imm8(insn->off))
1348                                 EMIT2(add_1reg(0x40, dst_reg), insn->off);
1349                         else
1350                                 EMIT1_off32(add_1reg(0x80, dst_reg), insn->off);
1351
1352                         EMIT(imm32, bpf_size_to_x86_bytes(BPF_SIZE(insn->code)));
1353                         break;
1354
1355                         /* STX: *(u8*)(dst_reg + off) = src_reg */
1356                 case BPF_STX | BPF_MEM | BPF_B:
1357                 case BPF_STX | BPF_MEM | BPF_H:
1358                 case BPF_STX | BPF_MEM | BPF_W:
1359                 case BPF_STX | BPF_MEM | BPF_DW:
1360                         emit_stx(&prog, BPF_SIZE(insn->code), dst_reg, src_reg, insn->off);
1361                         break;
1362
1363                         /* LDX: dst_reg = *(u8*)(src_reg + off) */
1364                 case BPF_LDX | BPF_MEM | BPF_B:
1365                 case BPF_LDX | BPF_PROBE_MEM | BPF_B:
1366                 case BPF_LDX | BPF_MEM | BPF_H:
1367                 case BPF_LDX | BPF_PROBE_MEM | BPF_H:
1368                 case BPF_LDX | BPF_MEM | BPF_W:
1369                 case BPF_LDX | BPF_PROBE_MEM | BPF_W:
1370                 case BPF_LDX | BPF_MEM | BPF_DW:
1371                 case BPF_LDX | BPF_PROBE_MEM | BPF_DW:
1372                         if (BPF_MODE(insn->code) == BPF_PROBE_MEM) {
1373                                 /* Though the verifier prevents negative insn->off in BPF_PROBE_MEM
1374                                  * add abs(insn->off) to the limit to make sure that negative
1375                                  * offset won't be an issue.
1376                                  * insn->off is s16, so it won't affect valid pointers.
1377                                  */
1378                                 u64 limit = TASK_SIZE_MAX + PAGE_SIZE + abs(insn->off);
1379                                 u8 *end_of_jmp1, *end_of_jmp2;
1380
1381                                 /* Conservatively check that src_reg + insn->off is a kernel address:
1382                                  * 1. src_reg + insn->off >= limit
1383                                  * 2. src_reg + insn->off doesn't become small positive.
1384                                  * Cannot do src_reg + insn->off >= limit in one branch,
1385                                  * since it needs two spare registers, but JIT has only one.
1386                                  */
1387
1388                                 /* movabsq r11, limit */
1389                                 EMIT2(add_1mod(0x48, AUX_REG), add_1reg(0xB8, AUX_REG));
1390                                 EMIT((u32)limit, 4);
1391                                 EMIT(limit >> 32, 4);
1392                                 /* cmp src_reg, r11 */
1393                                 maybe_emit_mod(&prog, src_reg, AUX_REG, true);
1394                                 EMIT2(0x39, add_2reg(0xC0, src_reg, AUX_REG));
1395                                 /* if unsigned '<' goto end_of_jmp2 */
1396                                 EMIT2(X86_JB, 0);
1397                                 end_of_jmp1 = prog;
1398
1399                                 /* mov r11, src_reg */
1400                                 emit_mov_reg(&prog, true, AUX_REG, src_reg);
1401                                 /* add r11, insn->off */
1402                                 maybe_emit_1mod(&prog, AUX_REG, true);
1403                                 EMIT2_off32(0x81, add_1reg(0xC0, AUX_REG), insn->off);
1404                                 /* jmp if not carry to start_of_ldx
1405                                  * Otherwise ERR_PTR(-EINVAL) + 128 will be the user addr
1406                                  * that has to be rejected.
1407                                  */
1408                                 EMIT2(0x73 /* JNC */, 0);
1409                                 end_of_jmp2 = prog;
1410
1411                                 /* xor dst_reg, dst_reg */
1412                                 emit_mov_imm32(&prog, false, dst_reg, 0);
1413                                 /* jmp byte_after_ldx */
1414                                 EMIT2(0xEB, 0);
1415
1416                                 /* populate jmp_offset for JB above to jump to xor dst_reg */
1417                                 end_of_jmp1[-1] = end_of_jmp2 - end_of_jmp1;
1418                                 /* populate jmp_offset for JNC above to jump to start_of_ldx */
1419                                 start_of_ldx = prog;
1420                                 end_of_jmp2[-1] = start_of_ldx - end_of_jmp2;
1421                         }
1422                         emit_ldx(&prog, BPF_SIZE(insn->code), dst_reg, src_reg, insn->off);
1423                         if (BPF_MODE(insn->code) == BPF_PROBE_MEM) {
1424                                 struct exception_table_entry *ex;
1425                                 u8 *_insn = image + proglen + (start_of_ldx - temp);
1426                                 s64 delta;
1427
1428                                 /* populate jmp_offset for JMP above */
1429                                 start_of_ldx[-1] = prog - start_of_ldx;
1430
1431                                 if (!bpf_prog->aux->extable)
1432                                         break;
1433
1434                                 if (excnt >= bpf_prog->aux->num_exentries) {
1435                                         pr_err("ex gen bug\n");
1436                                         return -EFAULT;
1437                                 }
1438                                 ex = &bpf_prog->aux->extable[excnt++];
1439
1440                                 delta = _insn - (u8 *)&ex->insn;
1441                                 if (!is_simm32(delta)) {
1442                                         pr_err("extable->insn doesn't fit into 32-bit\n");
1443                                         return -EFAULT;
1444                                 }
1445                                 /* switch ex to rw buffer for writes */
1446                                 ex = (void *)rw_image + ((void *)ex - (void *)image);
1447
1448                                 ex->insn = delta;
1449
1450                                 ex->data = EX_TYPE_BPF;
1451
1452                                 if (dst_reg > BPF_REG_9) {
1453                                         pr_err("verifier error\n");
1454                                         return -EFAULT;
1455                                 }
1456                                 /*
1457                                  * Compute size of x86 insn and its target dest x86 register.
1458                                  * ex_handler_bpf() will use lower 8 bits to adjust
1459                                  * pt_regs->ip to jump over this x86 instruction
1460                                  * and upper bits to figure out which pt_regs to zero out.
1461                                  * End result: x86 insn "mov rbx, qword ptr [rax+0x14]"
1462                                  * of 4 bytes will be ignored and rbx will be zero inited.
1463                                  */
1464                                 ex->fixup = (prog - start_of_ldx) | (reg2pt_regs[dst_reg] << 8);
1465                         }
1466                         break;
1467
1468                 case BPF_STX | BPF_ATOMIC | BPF_W:
1469                 case BPF_STX | BPF_ATOMIC | BPF_DW:
1470                         if (insn->imm == (BPF_AND | BPF_FETCH) ||
1471                             insn->imm == (BPF_OR | BPF_FETCH) ||
1472                             insn->imm == (BPF_XOR | BPF_FETCH)) {
1473                                 bool is64 = BPF_SIZE(insn->code) == BPF_DW;
1474                                 u32 real_src_reg = src_reg;
1475                                 u32 real_dst_reg = dst_reg;
1476                                 u8 *branch_target;
1477
1478                                 /*
1479                                  * Can't be implemented with a single x86 insn.
1480                                  * Need to do a CMPXCHG loop.
1481                                  */
1482
1483                                 /* Will need RAX as a CMPXCHG operand so save R0 */
1484                                 emit_mov_reg(&prog, true, BPF_REG_AX, BPF_REG_0);
1485                                 if (src_reg == BPF_REG_0)
1486                                         real_src_reg = BPF_REG_AX;
1487                                 if (dst_reg == BPF_REG_0)
1488                                         real_dst_reg = BPF_REG_AX;
1489
1490                                 branch_target = prog;
1491                                 /* Load old value */
1492                                 emit_ldx(&prog, BPF_SIZE(insn->code),
1493                                          BPF_REG_0, real_dst_reg, insn->off);
1494                                 /*
1495                                  * Perform the (commutative) operation locally,
1496                                  * put the result in the AUX_REG.
1497                                  */
1498                                 emit_mov_reg(&prog, is64, AUX_REG, BPF_REG_0);
1499                                 maybe_emit_mod(&prog, AUX_REG, real_src_reg, is64);
1500                                 EMIT2(simple_alu_opcodes[BPF_OP(insn->imm)],
1501                                       add_2reg(0xC0, AUX_REG, real_src_reg));
1502                                 /* Attempt to swap in new value */
1503                                 err = emit_atomic(&prog, BPF_CMPXCHG,
1504                                                   real_dst_reg, AUX_REG,
1505                                                   insn->off,
1506                                                   BPF_SIZE(insn->code));
1507                                 if (WARN_ON(err))
1508                                         return err;
1509                                 /*
1510                                  * ZF tells us whether we won the race. If it's
1511                                  * cleared we need to try again.
1512                                  */
1513                                 EMIT2(X86_JNE, -(prog - branch_target) - 2);
1514                                 /* Return the pre-modification value */
1515                                 emit_mov_reg(&prog, is64, real_src_reg, BPF_REG_0);
1516                                 /* Restore R0 after clobbering RAX */
1517                                 emit_mov_reg(&prog, true, BPF_REG_0, BPF_REG_AX);
1518                                 break;
1519                         }
1520
1521                         err = emit_atomic(&prog, insn->imm, dst_reg, src_reg,
1522                                           insn->off, BPF_SIZE(insn->code));
1523                         if (err)
1524                                 return err;
1525                         break;
1526
1527                         /* call */
1528                 case BPF_JMP | BPF_CALL: {
1529                         int offs;
1530
1531                         func = (u8 *) __bpf_call_base + imm32;
1532                         if (tail_call_reachable) {
1533                                 /* mov rax, qword ptr [rbp - rounded_stack_depth - 8] */
1534                                 EMIT3_off32(0x48, 0x8B, 0x85,
1535                                             -round_up(bpf_prog->aux->stack_depth, 8) - 8);
1536                                 if (!imm32)
1537                                         return -EINVAL;
1538                                 offs = 7 + x86_call_depth_emit_accounting(&prog, func);
1539                         } else {
1540                                 if (!imm32)
1541                                         return -EINVAL;
1542                                 offs = x86_call_depth_emit_accounting(&prog, func);
1543                         }
1544                         if (emit_call(&prog, func, image + addrs[i - 1] + offs))
1545                                 return -EINVAL;
1546                         break;
1547                 }
1548
1549                 case BPF_JMP | BPF_TAIL_CALL:
1550                         if (imm32)
1551                                 emit_bpf_tail_call_direct(&bpf_prog->aux->poke_tab[imm32 - 1],
1552                                                           &prog, image + addrs[i - 1],
1553                                                           callee_regs_used,
1554                                                           bpf_prog->aux->stack_depth,
1555                                                           ctx);
1556                         else
1557                                 emit_bpf_tail_call_indirect(&prog,
1558                                                             callee_regs_used,
1559                                                             bpf_prog->aux->stack_depth,
1560                                                             image + addrs[i - 1],
1561                                                             ctx);
1562                         break;
1563
1564                         /* cond jump */
1565                 case BPF_JMP | BPF_JEQ | BPF_X:
1566                 case BPF_JMP | BPF_JNE | BPF_X:
1567                 case BPF_JMP | BPF_JGT | BPF_X:
1568                 case BPF_JMP | BPF_JLT | BPF_X:
1569                 case BPF_JMP | BPF_JGE | BPF_X:
1570                 case BPF_JMP | BPF_JLE | BPF_X:
1571                 case BPF_JMP | BPF_JSGT | BPF_X:
1572                 case BPF_JMP | BPF_JSLT | BPF_X:
1573                 case BPF_JMP | BPF_JSGE | BPF_X:
1574                 case BPF_JMP | BPF_JSLE | BPF_X:
1575                 case BPF_JMP32 | BPF_JEQ | BPF_X:
1576                 case BPF_JMP32 | BPF_JNE | BPF_X:
1577                 case BPF_JMP32 | BPF_JGT | BPF_X:
1578                 case BPF_JMP32 | BPF_JLT | BPF_X:
1579                 case BPF_JMP32 | BPF_JGE | BPF_X:
1580                 case BPF_JMP32 | BPF_JLE | BPF_X:
1581                 case BPF_JMP32 | BPF_JSGT | BPF_X:
1582                 case BPF_JMP32 | BPF_JSLT | BPF_X:
1583                 case BPF_JMP32 | BPF_JSGE | BPF_X:
1584                 case BPF_JMP32 | BPF_JSLE | BPF_X:
1585                         /* cmp dst_reg, src_reg */
1586                         maybe_emit_mod(&prog, dst_reg, src_reg,
1587                                        BPF_CLASS(insn->code) == BPF_JMP);
1588                         EMIT2(0x39, add_2reg(0xC0, dst_reg, src_reg));
1589                         goto emit_cond_jmp;
1590
1591                 case BPF_JMP | BPF_JSET | BPF_X:
1592                 case BPF_JMP32 | BPF_JSET | BPF_X:
1593                         /* test dst_reg, src_reg */
1594                         maybe_emit_mod(&prog, dst_reg, src_reg,
1595                                        BPF_CLASS(insn->code) == BPF_JMP);
1596                         EMIT2(0x85, add_2reg(0xC0, dst_reg, src_reg));
1597                         goto emit_cond_jmp;
1598
1599                 case BPF_JMP | BPF_JSET | BPF_K:
1600                 case BPF_JMP32 | BPF_JSET | BPF_K:
1601                         /* test dst_reg, imm32 */
1602                         maybe_emit_1mod(&prog, dst_reg,
1603                                         BPF_CLASS(insn->code) == BPF_JMP);
1604                         EMIT2_off32(0xF7, add_1reg(0xC0, dst_reg), imm32);
1605                         goto emit_cond_jmp;
1606
1607                 case BPF_JMP | BPF_JEQ | BPF_K:
1608                 case BPF_JMP | BPF_JNE | BPF_K:
1609                 case BPF_JMP | BPF_JGT | BPF_K:
1610                 case BPF_JMP | BPF_JLT | BPF_K:
1611                 case BPF_JMP | BPF_JGE | BPF_K:
1612                 case BPF_JMP | BPF_JLE | BPF_K:
1613                 case BPF_JMP | BPF_JSGT | BPF_K:
1614                 case BPF_JMP | BPF_JSLT | BPF_K:
1615                 case BPF_JMP | BPF_JSGE | BPF_K:
1616                 case BPF_JMP | BPF_JSLE | BPF_K:
1617                 case BPF_JMP32 | BPF_JEQ | BPF_K:
1618                 case BPF_JMP32 | BPF_JNE | BPF_K:
1619                 case BPF_JMP32 | BPF_JGT | BPF_K:
1620                 case BPF_JMP32 | BPF_JLT | BPF_K:
1621                 case BPF_JMP32 | BPF_JGE | BPF_K:
1622                 case BPF_JMP32 | BPF_JLE | BPF_K:
1623                 case BPF_JMP32 | BPF_JSGT | BPF_K:
1624                 case BPF_JMP32 | BPF_JSLT | BPF_K:
1625                 case BPF_JMP32 | BPF_JSGE | BPF_K:
1626                 case BPF_JMP32 | BPF_JSLE | BPF_K:
1627                         /* test dst_reg, dst_reg to save one extra byte */
1628                         if (imm32 == 0) {
1629                                 maybe_emit_mod(&prog, dst_reg, dst_reg,
1630                                                BPF_CLASS(insn->code) == BPF_JMP);
1631                                 EMIT2(0x85, add_2reg(0xC0, dst_reg, dst_reg));
1632                                 goto emit_cond_jmp;
1633                         }
1634
1635                         /* cmp dst_reg, imm8/32 */
1636                         maybe_emit_1mod(&prog, dst_reg,
1637                                         BPF_CLASS(insn->code) == BPF_JMP);
1638
1639                         if (is_imm8(imm32))
1640                                 EMIT3(0x83, add_1reg(0xF8, dst_reg), imm32);
1641                         else
1642                                 EMIT2_off32(0x81, add_1reg(0xF8, dst_reg), imm32);
1643
1644 emit_cond_jmp:          /* Convert BPF opcode to x86 */
1645                         switch (BPF_OP(insn->code)) {
1646                         case BPF_JEQ:
1647                                 jmp_cond = X86_JE;
1648                                 break;
1649                         case BPF_JSET:
1650                         case BPF_JNE:
1651                                 jmp_cond = X86_JNE;
1652                                 break;
1653                         case BPF_JGT:
1654                                 /* GT is unsigned '>', JA in x86 */
1655                                 jmp_cond = X86_JA;
1656                                 break;
1657                         case BPF_JLT:
1658                                 /* LT is unsigned '<', JB in x86 */
1659                                 jmp_cond = X86_JB;
1660                                 break;
1661                         case BPF_JGE:
1662                                 /* GE is unsigned '>=', JAE in x86 */
1663                                 jmp_cond = X86_JAE;
1664                                 break;
1665                         case BPF_JLE:
1666                                 /* LE is unsigned '<=', JBE in x86 */
1667                                 jmp_cond = X86_JBE;
1668                                 break;
1669                         case BPF_JSGT:
1670                                 /* Signed '>', GT in x86 */
1671                                 jmp_cond = X86_JG;
1672                                 break;
1673                         case BPF_JSLT:
1674                                 /* Signed '<', LT in x86 */
1675                                 jmp_cond = X86_JL;
1676                                 break;
1677                         case BPF_JSGE:
1678                                 /* Signed '>=', GE in x86 */
1679                                 jmp_cond = X86_JGE;
1680                                 break;
1681                         case BPF_JSLE:
1682                                 /* Signed '<=', LE in x86 */
1683                                 jmp_cond = X86_JLE;
1684                                 break;
1685                         default: /* to silence GCC warning */
1686                                 return -EFAULT;
1687                         }
1688                         jmp_offset = addrs[i + insn->off] - addrs[i];
1689                         if (is_imm8(jmp_offset)) {
1690                                 if (jmp_padding) {
1691                                         /* To keep the jmp_offset valid, the extra bytes are
1692                                          * padded before the jump insn, so we subtract the
1693                                          * 2 bytes of jmp_cond insn from INSN_SZ_DIFF.
1694                                          *
1695                                          * If the previous pass already emits an imm8
1696                                          * jmp_cond, then this BPF insn won't shrink, so
1697                                          * "nops" is 0.
1698                                          *
1699                                          * On the other hand, if the previous pass emits an
1700                                          * imm32 jmp_cond, the extra 4 bytes(*) is padded to
1701                                          * keep the image from shrinking further.
1702                                          *
1703                                          * (*) imm32 jmp_cond is 6 bytes, and imm8 jmp_cond
1704                                          *     is 2 bytes, so the size difference is 4 bytes.
1705                                          */
1706                                         nops = INSN_SZ_DIFF - 2;
1707                                         if (nops != 0 && nops != 4) {
1708                                                 pr_err("unexpected jmp_cond padding: %d bytes\n",
1709                                                        nops);
1710                                                 return -EFAULT;
1711                                         }
1712                                         emit_nops(&prog, nops);
1713                                 }
1714                                 EMIT2(jmp_cond, jmp_offset);
1715                         } else if (is_simm32(jmp_offset)) {
1716                                 EMIT2_off32(0x0F, jmp_cond + 0x10, jmp_offset);
1717                         } else {
1718                                 pr_err("cond_jmp gen bug %llx\n", jmp_offset);
1719                                 return -EFAULT;
1720                         }
1721
1722                         break;
1723
1724                 case BPF_JMP | BPF_JA:
1725                         if (insn->off == -1)
1726                                 /* -1 jmp instructions will always jump
1727                                  * backwards two bytes. Explicitly handling
1728                                  * this case avoids wasting too many passes
1729                                  * when there are long sequences of replaced
1730                                  * dead code.
1731                                  */
1732                                 jmp_offset = -2;
1733                         else
1734                                 jmp_offset = addrs[i + insn->off] - addrs[i];
1735
1736                         if (!jmp_offset) {
1737                                 /*
1738                                  * If jmp_padding is enabled, the extra nops will
1739                                  * be inserted. Otherwise, optimize out nop jumps.
1740                                  */
1741                                 if (jmp_padding) {
1742                                         /* There are 3 possible conditions.
1743                                          * (1) This BPF_JA is already optimized out in
1744                                          *     the previous run, so there is no need
1745                                          *     to pad any extra byte (0 byte).
1746                                          * (2) The previous pass emits an imm8 jmp,
1747                                          *     so we pad 2 bytes to match the previous
1748                                          *     insn size.
1749                                          * (3) Similarly, the previous pass emits an
1750                                          *     imm32 jmp, and 5 bytes is padded.
1751                                          */
1752                                         nops = INSN_SZ_DIFF;
1753                                         if (nops != 0 && nops != 2 && nops != 5) {
1754                                                 pr_err("unexpected nop jump padding: %d bytes\n",
1755                                                        nops);
1756                                                 return -EFAULT;
1757                                         }
1758                                         emit_nops(&prog, nops);
1759                                 }
1760                                 break;
1761                         }
1762 emit_jmp:
1763                         if (is_imm8(jmp_offset)) {
1764                                 if (jmp_padding) {
1765                                         /* To avoid breaking jmp_offset, the extra bytes
1766                                          * are padded before the actual jmp insn, so
1767                                          * 2 bytes is subtracted from INSN_SZ_DIFF.
1768                                          *
1769                                          * If the previous pass already emits an imm8
1770                                          * jmp, there is nothing to pad (0 byte).
1771                                          *
1772                                          * If it emits an imm32 jmp (5 bytes) previously
1773                                          * and now an imm8 jmp (2 bytes), then we pad
1774                                          * (5 - 2 = 3) bytes to stop the image from
1775                                          * shrinking further.
1776                                          */
1777                                         nops = INSN_SZ_DIFF - 2;
1778                                         if (nops != 0 && nops != 3) {
1779                                                 pr_err("unexpected jump padding: %d bytes\n",
1780                                                        nops);
1781                                                 return -EFAULT;
1782                                         }
1783                                         emit_nops(&prog, INSN_SZ_DIFF - 2);
1784                                 }
1785                                 EMIT2(0xEB, jmp_offset);
1786                         } else if (is_simm32(jmp_offset)) {
1787                                 EMIT1_off32(0xE9, jmp_offset);
1788                         } else {
1789                                 pr_err("jmp gen bug %llx\n", jmp_offset);
1790                                 return -EFAULT;
1791                         }
1792                         break;
1793
1794                 case BPF_JMP | BPF_EXIT:
1795                         if (seen_exit) {
1796                                 jmp_offset = ctx->cleanup_addr - addrs[i];
1797                                 goto emit_jmp;
1798                         }
1799                         seen_exit = true;
1800                         /* Update cleanup_addr */
1801                         ctx->cleanup_addr = proglen;
1802                         pop_callee_regs(&prog, callee_regs_used);
1803                         EMIT1(0xC9);         /* leave */
1804                         emit_return(&prog, image + addrs[i - 1] + (prog - temp));
1805                         break;
1806
1807                 default:
1808                         /*
1809                          * By design x86-64 JIT should support all BPF instructions.
1810                          * This error will be seen if new instruction was added
1811                          * to the interpreter, but not to the JIT, or if there is
1812                          * junk in bpf_prog.
1813                          */
1814                         pr_err("bpf_jit: unknown opcode %02x\n", insn->code);
1815                         return -EINVAL;
1816                 }
1817
1818                 ilen = prog - temp;
1819                 if (ilen > BPF_MAX_INSN_SIZE) {
1820                         pr_err("bpf_jit: fatal insn size error\n");
1821                         return -EFAULT;
1822                 }
1823
1824                 if (image) {
1825                         /*
1826                          * When populating the image, assert that:
1827                          *
1828                          *  i) We do not write beyond the allocated space, and
1829                          * ii) addrs[i] did not change from the prior run, in order
1830                          *     to validate assumptions made for computing branch
1831                          *     displacements.
1832                          */
1833                         if (unlikely(proglen + ilen > oldproglen ||
1834                                      proglen + ilen != addrs[i])) {
1835                                 pr_err("bpf_jit: fatal error\n");
1836                                 return -EFAULT;
1837                         }
1838                         memcpy(rw_image + proglen, temp, ilen);
1839                 }
1840                 proglen += ilen;
1841                 addrs[i] = proglen;
1842                 prog = temp;
1843         }
1844
1845         if (image && excnt != bpf_prog->aux->num_exentries) {
1846                 pr_err("extable is not populated\n");
1847                 return -EFAULT;
1848         }
1849         return proglen;
1850 }
1851
1852 static void save_regs(const struct btf_func_model *m, u8 **prog, int nr_args,
1853                       int stack_size)
1854 {
1855         int i, j, arg_size, nr_regs;
1856         /* Store function arguments to stack.
1857          * For a function that accepts two pointers the sequence will be:
1858          * mov QWORD PTR [rbp-0x10],rdi
1859          * mov QWORD PTR [rbp-0x8],rsi
1860          */
1861         for (i = 0, j = 0; i < min(nr_args, 6); i++) {
1862                 if (m->arg_flags[i] & BTF_FMODEL_STRUCT_ARG) {
1863                         nr_regs = (m->arg_size[i] + 7) / 8;
1864                         arg_size = 8;
1865                 } else {
1866                         nr_regs = 1;
1867                         arg_size = m->arg_size[i];
1868                 }
1869
1870                 while (nr_regs) {
1871                         emit_stx(prog, bytes_to_bpf_size(arg_size),
1872                                  BPF_REG_FP,
1873                                  j == 5 ? X86_REG_R9 : BPF_REG_1 + j,
1874                                  -(stack_size - j * 8));
1875                         nr_regs--;
1876                         j++;
1877                 }
1878         }
1879 }
1880
1881 static void restore_regs(const struct btf_func_model *m, u8 **prog, int nr_args,
1882                          int stack_size)
1883 {
1884         int i, j, arg_size, nr_regs;
1885
1886         /* Restore function arguments from stack.
1887          * For a function that accepts two pointers the sequence will be:
1888          * EMIT4(0x48, 0x8B, 0x7D, 0xF0); mov rdi,QWORD PTR [rbp-0x10]
1889          * EMIT4(0x48, 0x8B, 0x75, 0xF8); mov rsi,QWORD PTR [rbp-0x8]
1890          */
1891         for (i = 0, j = 0; i < min(nr_args, 6); i++) {
1892                 if (m->arg_flags[i] & BTF_FMODEL_STRUCT_ARG) {
1893                         nr_regs = (m->arg_size[i] + 7) / 8;
1894                         arg_size = 8;
1895                 } else {
1896                         nr_regs = 1;
1897                         arg_size = m->arg_size[i];
1898                 }
1899
1900                 while (nr_regs) {
1901                         emit_ldx(prog, bytes_to_bpf_size(arg_size),
1902                                  j == 5 ? X86_REG_R9 : BPF_REG_1 + j,
1903                                  BPF_REG_FP,
1904                                  -(stack_size - j * 8));
1905                         nr_regs--;
1906                         j++;
1907                 }
1908         }
1909 }
1910
1911 static int invoke_bpf_prog(const struct btf_func_model *m, u8 **pprog,
1912                            struct bpf_tramp_link *l, int stack_size,
1913                            int run_ctx_off, bool save_ret)
1914 {
1915         u8 *prog = *pprog;
1916         u8 *jmp_insn;
1917         int ctx_cookie_off = offsetof(struct bpf_tramp_run_ctx, bpf_cookie);
1918         struct bpf_prog *p = l->link.prog;
1919         u64 cookie = l->cookie;
1920
1921         /* mov rdi, cookie */
1922         emit_mov_imm64(&prog, BPF_REG_1, (long) cookie >> 32, (u32) (long) cookie);
1923
1924         /* Prepare struct bpf_tramp_run_ctx.
1925          *
1926          * bpf_tramp_run_ctx is already preserved by
1927          * arch_prepare_bpf_trampoline().
1928          *
1929          * mov QWORD PTR [rbp - run_ctx_off + ctx_cookie_off], rdi
1930          */
1931         emit_stx(&prog, BPF_DW, BPF_REG_FP, BPF_REG_1, -run_ctx_off + ctx_cookie_off);
1932
1933         /* arg1: mov rdi, progs[i] */
1934         emit_mov_imm64(&prog, BPF_REG_1, (long) p >> 32, (u32) (long) p);
1935         /* arg2: lea rsi, [rbp - ctx_cookie_off] */
1936         EMIT4(0x48, 0x8D, 0x75, -run_ctx_off);
1937
1938         if (emit_rsb_call(&prog, bpf_trampoline_enter(p), prog))
1939                 return -EINVAL;
1940         /* remember prog start time returned by __bpf_prog_enter */
1941         emit_mov_reg(&prog, true, BPF_REG_6, BPF_REG_0);
1942
1943         /* if (__bpf_prog_enter*(prog) == 0)
1944          *      goto skip_exec_of_prog;
1945          */
1946         EMIT3(0x48, 0x85, 0xC0);  /* test rax,rax */
1947         /* emit 2 nops that will be replaced with JE insn */
1948         jmp_insn = prog;
1949         emit_nops(&prog, 2);
1950
1951         /* arg1: lea rdi, [rbp - stack_size] */
1952         EMIT4(0x48, 0x8D, 0x7D, -stack_size);
1953         /* arg2: progs[i]->insnsi for interpreter */
1954         if (!p->jited)
1955                 emit_mov_imm64(&prog, BPF_REG_2,
1956                                (long) p->insnsi >> 32,
1957                                (u32) (long) p->insnsi);
1958         /* call JITed bpf program or interpreter */
1959         if (emit_rsb_call(&prog, p->bpf_func, prog))
1960                 return -EINVAL;
1961
1962         /*
1963          * BPF_TRAMP_MODIFY_RETURN trampolines can modify the return
1964          * of the previous call which is then passed on the stack to
1965          * the next BPF program.
1966          *
1967          * BPF_TRAMP_FENTRY trampoline may need to return the return
1968          * value of BPF_PROG_TYPE_STRUCT_OPS prog.
1969          */
1970         if (save_ret)
1971                 emit_stx(&prog, BPF_DW, BPF_REG_FP, BPF_REG_0, -8);
1972
1973         /* replace 2 nops with JE insn, since jmp target is known */
1974         jmp_insn[0] = X86_JE;
1975         jmp_insn[1] = prog - jmp_insn - 2;
1976
1977         /* arg1: mov rdi, progs[i] */
1978         emit_mov_imm64(&prog, BPF_REG_1, (long) p >> 32, (u32) (long) p);
1979         /* arg2: mov rsi, rbx <- start time in nsec */
1980         emit_mov_reg(&prog, true, BPF_REG_2, BPF_REG_6);
1981         /* arg3: lea rdx, [rbp - run_ctx_off] */
1982         EMIT4(0x48, 0x8D, 0x55, -run_ctx_off);
1983         if (emit_rsb_call(&prog, bpf_trampoline_exit(p), prog))
1984                 return -EINVAL;
1985
1986         *pprog = prog;
1987         return 0;
1988 }
1989
1990 static void emit_align(u8 **pprog, u32 align)
1991 {
1992         u8 *target, *prog = *pprog;
1993
1994         target = PTR_ALIGN(prog, align);
1995         if (target != prog)
1996                 emit_nops(&prog, target - prog);
1997
1998         *pprog = prog;
1999 }
2000
2001 static int emit_cond_near_jump(u8 **pprog, void *func, void *ip, u8 jmp_cond)
2002 {
2003         u8 *prog = *pprog;
2004         s64 offset;
2005
2006         offset = func - (ip + 2 + 4);
2007         if (!is_simm32(offset)) {
2008                 pr_err("Target %p is out of range\n", func);
2009                 return -EINVAL;
2010         }
2011         EMIT2_off32(0x0F, jmp_cond + 0x10, offset);
2012         *pprog = prog;
2013         return 0;
2014 }
2015
2016 static int invoke_bpf(const struct btf_func_model *m, u8 **pprog,
2017                       struct bpf_tramp_links *tl, int stack_size,
2018                       int run_ctx_off, bool save_ret)
2019 {
2020         int i;
2021         u8 *prog = *pprog;
2022
2023         for (i = 0; i < tl->nr_links; i++) {
2024                 if (invoke_bpf_prog(m, &prog, tl->links[i], stack_size,
2025                                     run_ctx_off, save_ret))
2026                         return -EINVAL;
2027         }
2028         *pprog = prog;
2029         return 0;
2030 }
2031
2032 static int invoke_bpf_mod_ret(const struct btf_func_model *m, u8 **pprog,
2033                               struct bpf_tramp_links *tl, int stack_size,
2034                               int run_ctx_off, u8 **branches)
2035 {
2036         u8 *prog = *pprog;
2037         int i;
2038
2039         /* The first fmod_ret program will receive a garbage return value.
2040          * Set this to 0 to avoid confusing the program.
2041          */
2042         emit_mov_imm32(&prog, false, BPF_REG_0, 0);
2043         emit_stx(&prog, BPF_DW, BPF_REG_FP, BPF_REG_0, -8);
2044         for (i = 0; i < tl->nr_links; i++) {
2045                 if (invoke_bpf_prog(m, &prog, tl->links[i], stack_size, run_ctx_off, true))
2046                         return -EINVAL;
2047
2048                 /* mod_ret prog stored return value into [rbp - 8]. Emit:
2049                  * if (*(u64 *)(rbp - 8) !=  0)
2050                  *      goto do_fexit;
2051                  */
2052                 /* cmp QWORD PTR [rbp - 0x8], 0x0 */
2053                 EMIT4(0x48, 0x83, 0x7d, 0xf8); EMIT1(0x00);
2054
2055                 /* Save the location of the branch and Generate 6 nops
2056                  * (4 bytes for an offset and 2 bytes for the jump) These nops
2057                  * are replaced with a conditional jump once do_fexit (i.e. the
2058                  * start of the fexit invocation) is finalized.
2059                  */
2060                 branches[i] = prog;
2061                 emit_nops(&prog, 4 + 2);
2062         }
2063
2064         *pprog = prog;
2065         return 0;
2066 }
2067
2068 /* Example:
2069  * __be16 eth_type_trans(struct sk_buff *skb, struct net_device *dev);
2070  * its 'struct btf_func_model' will be nr_args=2
2071  * The assembly code when eth_type_trans is executing after trampoline:
2072  *
2073  * push rbp
2074  * mov rbp, rsp
2075  * sub rsp, 16                     // space for skb and dev
2076  * push rbx                        // temp regs to pass start time
2077  * mov qword ptr [rbp - 16], rdi   // save skb pointer to stack
2078  * mov qword ptr [rbp - 8], rsi    // save dev pointer to stack
2079  * call __bpf_prog_enter           // rcu_read_lock and preempt_disable
2080  * mov rbx, rax                    // remember start time in bpf stats are enabled
2081  * lea rdi, [rbp - 16]             // R1==ctx of bpf prog
2082  * call addr_of_jited_FENTRY_prog
2083  * movabsq rdi, 64bit_addr_of_struct_bpf_prog  // unused if bpf stats are off
2084  * mov rsi, rbx                    // prog start time
2085  * call __bpf_prog_exit            // rcu_read_unlock, preempt_enable and stats math
2086  * mov rdi, qword ptr [rbp - 16]   // restore skb pointer from stack
2087  * mov rsi, qword ptr [rbp - 8]    // restore dev pointer from stack
2088  * pop rbx
2089  * leave
2090  * ret
2091  *
2092  * eth_type_trans has 5 byte nop at the beginning. These 5 bytes will be
2093  * replaced with 'call generated_bpf_trampoline'. When it returns
2094  * eth_type_trans will continue executing with original skb and dev pointers.
2095  *
2096  * The assembly code when eth_type_trans is called from trampoline:
2097  *
2098  * push rbp
2099  * mov rbp, rsp
2100  * sub rsp, 24                     // space for skb, dev, return value
2101  * push rbx                        // temp regs to pass start time
2102  * mov qword ptr [rbp - 24], rdi   // save skb pointer to stack
2103  * mov qword ptr [rbp - 16], rsi   // save dev pointer to stack
2104  * call __bpf_prog_enter           // rcu_read_lock and preempt_disable
2105  * mov rbx, rax                    // remember start time if bpf stats are enabled
2106  * lea rdi, [rbp - 24]             // R1==ctx of bpf prog
2107  * call addr_of_jited_FENTRY_prog  // bpf prog can access skb and dev
2108  * movabsq rdi, 64bit_addr_of_struct_bpf_prog  // unused if bpf stats are off
2109  * mov rsi, rbx                    // prog start time
2110  * call __bpf_prog_exit            // rcu_read_unlock, preempt_enable and stats math
2111  * mov rdi, qword ptr [rbp - 24]   // restore skb pointer from stack
2112  * mov rsi, qword ptr [rbp - 16]   // restore dev pointer from stack
2113  * call eth_type_trans+5           // execute body of eth_type_trans
2114  * mov qword ptr [rbp - 8], rax    // save return value
2115  * call __bpf_prog_enter           // rcu_read_lock and preempt_disable
2116  * mov rbx, rax                    // remember start time in bpf stats are enabled
2117  * lea rdi, [rbp - 24]             // R1==ctx of bpf prog
2118  * call addr_of_jited_FEXIT_prog   // bpf prog can access skb, dev, return value
2119  * movabsq rdi, 64bit_addr_of_struct_bpf_prog  // unused if bpf stats are off
2120  * mov rsi, rbx                    // prog start time
2121  * call __bpf_prog_exit            // rcu_read_unlock, preempt_enable and stats math
2122  * mov rax, qword ptr [rbp - 8]    // restore eth_type_trans's return value
2123  * pop rbx
2124  * leave
2125  * add rsp, 8                      // skip eth_type_trans's frame
2126  * ret                             // return to its caller
2127  */
2128 int arch_prepare_bpf_trampoline(struct bpf_tramp_image *im, void *image, void *image_end,
2129                                 const struct btf_func_model *m, u32 flags,
2130                                 struct bpf_tramp_links *tlinks,
2131                                 void *func_addr)
2132 {
2133         int ret, i, nr_args = m->nr_args, extra_nregs = 0;
2134         int regs_off, ip_off, args_off, stack_size = nr_args * 8, run_ctx_off;
2135         struct bpf_tramp_links *fentry = &tlinks[BPF_TRAMP_FENTRY];
2136         struct bpf_tramp_links *fexit = &tlinks[BPF_TRAMP_FEXIT];
2137         struct bpf_tramp_links *fmod_ret = &tlinks[BPF_TRAMP_MODIFY_RETURN];
2138         void *orig_call = func_addr;
2139         u8 **branches = NULL;
2140         u8 *prog;
2141         bool save_ret;
2142
2143         /* x86-64 supports up to 6 arguments. 7+ can be added in the future */
2144         if (nr_args > 6)
2145                 return -ENOTSUPP;
2146
2147         for (i = 0; i < MAX_BPF_FUNC_ARGS; i++) {
2148                 if (m->arg_flags[i] & BTF_FMODEL_STRUCT_ARG)
2149                         extra_nregs += (m->arg_size[i] + 7) / 8 - 1;
2150         }
2151         if (nr_args + extra_nregs > 6)
2152                 return -ENOTSUPP;
2153         stack_size += extra_nregs * 8;
2154
2155         /* Generated trampoline stack layout:
2156          *
2157          * RBP + 8         [ return address  ]
2158          * RBP + 0         [ RBP             ]
2159          *
2160          * RBP - 8         [ return value    ]  BPF_TRAMP_F_CALL_ORIG or
2161          *                                      BPF_TRAMP_F_RET_FENTRY_RET flags
2162          *
2163          *                 [ reg_argN        ]  always
2164          *                 [ ...             ]
2165          * RBP - regs_off  [ reg_arg1        ]  program's ctx pointer
2166          *
2167          * RBP - args_off  [ arg regs count  ]  always
2168          *
2169          * RBP - ip_off    [ traced function ]  BPF_TRAMP_F_IP_ARG flag
2170          *
2171          * RBP - run_ctx_off [ bpf_tramp_run_ctx ]
2172          */
2173
2174         /* room for return value of orig_call or fentry prog */
2175         save_ret = flags & (BPF_TRAMP_F_CALL_ORIG | BPF_TRAMP_F_RET_FENTRY_RET);
2176         if (save_ret)
2177                 stack_size += 8;
2178
2179         regs_off = stack_size;
2180
2181         /* args count  */
2182         stack_size += 8;
2183         args_off = stack_size;
2184
2185         if (flags & BPF_TRAMP_F_IP_ARG)
2186                 stack_size += 8; /* room for IP address argument */
2187
2188         ip_off = stack_size;
2189
2190         stack_size += (sizeof(struct bpf_tramp_run_ctx) + 7) & ~0x7;
2191         run_ctx_off = stack_size;
2192
2193         if (flags & BPF_TRAMP_F_SKIP_FRAME) {
2194                 /* skip patched call instruction and point orig_call to actual
2195                  * body of the kernel function.
2196                  */
2197                 if (is_endbr(*(u32 *)orig_call))
2198                         orig_call += ENDBR_INSN_SIZE;
2199                 orig_call += X86_PATCH_SIZE;
2200         }
2201
2202         prog = image;
2203
2204         EMIT_ENDBR();
2205         /*
2206          * This is the direct-call trampoline, as such it needs accounting
2207          * for the __fentry__ call.
2208          */
2209         x86_call_depth_emit_accounting(&prog, NULL);
2210         EMIT1(0x55);             /* push rbp */
2211         EMIT3(0x48, 0x89, 0xE5); /* mov rbp, rsp */
2212         EMIT4(0x48, 0x83, 0xEC, stack_size); /* sub rsp, stack_size */
2213         EMIT1(0x53);             /* push rbx */
2214
2215         /* Store number of argument registers of the traced function:
2216          *   mov rax, nr_args + extra_nregs
2217          *   mov QWORD PTR [rbp - args_off], rax
2218          */
2219         emit_mov_imm64(&prog, BPF_REG_0, 0, (u32) nr_args + extra_nregs);
2220         emit_stx(&prog, BPF_DW, BPF_REG_FP, BPF_REG_0, -args_off);
2221
2222         if (flags & BPF_TRAMP_F_IP_ARG) {
2223                 /* Store IP address of the traced function:
2224                  * movabsq rax, func_addr
2225                  * mov QWORD PTR [rbp - ip_off], rax
2226                  */
2227                 emit_mov_imm64(&prog, BPF_REG_0, (long) func_addr >> 32, (u32) (long) func_addr);
2228                 emit_stx(&prog, BPF_DW, BPF_REG_FP, BPF_REG_0, -ip_off);
2229         }
2230
2231         save_regs(m, &prog, nr_args, regs_off);
2232
2233         if (flags & BPF_TRAMP_F_CALL_ORIG) {
2234                 /* arg1: mov rdi, im */
2235                 emit_mov_imm64(&prog, BPF_REG_1, (long) im >> 32, (u32) (long) im);
2236                 if (emit_rsb_call(&prog, __bpf_tramp_enter, prog)) {
2237                         ret = -EINVAL;
2238                         goto cleanup;
2239                 }
2240         }
2241
2242         if (fentry->nr_links)
2243                 if (invoke_bpf(m, &prog, fentry, regs_off, run_ctx_off,
2244                                flags & BPF_TRAMP_F_RET_FENTRY_RET))
2245                         return -EINVAL;
2246
2247         if (fmod_ret->nr_links) {
2248                 branches = kcalloc(fmod_ret->nr_links, sizeof(u8 *),
2249                                    GFP_KERNEL);
2250                 if (!branches)
2251                         return -ENOMEM;
2252
2253                 if (invoke_bpf_mod_ret(m, &prog, fmod_ret, regs_off,
2254                                        run_ctx_off, branches)) {
2255                         ret = -EINVAL;
2256                         goto cleanup;
2257                 }
2258         }
2259
2260         if (flags & BPF_TRAMP_F_CALL_ORIG) {
2261                 restore_regs(m, &prog, nr_args, regs_off);
2262
2263                 if (flags & BPF_TRAMP_F_ORIG_STACK) {
2264                         emit_ldx(&prog, BPF_DW, BPF_REG_0, BPF_REG_FP, 8);
2265                         EMIT2(0xff, 0xd0); /* call *rax */
2266                 } else {
2267                         /* call original function */
2268                         if (emit_rsb_call(&prog, orig_call, prog)) {
2269                                 ret = -EINVAL;
2270                                 goto cleanup;
2271                         }
2272                 }
2273                 /* remember return value in a stack for bpf prog to access */
2274                 emit_stx(&prog, BPF_DW, BPF_REG_FP, BPF_REG_0, -8);
2275                 im->ip_after_call = prog;
2276                 memcpy(prog, x86_nops[5], X86_PATCH_SIZE);
2277                 prog += X86_PATCH_SIZE;
2278         }
2279
2280         if (fmod_ret->nr_links) {
2281                 /* From Intel 64 and IA-32 Architectures Optimization
2282                  * Reference Manual, 3.4.1.4 Code Alignment, Assembly/Compiler
2283                  * Coding Rule 11: All branch targets should be 16-byte
2284                  * aligned.
2285                  */
2286                 emit_align(&prog, 16);
2287                 /* Update the branches saved in invoke_bpf_mod_ret with the
2288                  * aligned address of do_fexit.
2289                  */
2290                 for (i = 0; i < fmod_ret->nr_links; i++)
2291                         emit_cond_near_jump(&branches[i], prog, branches[i],
2292                                             X86_JNE);
2293         }
2294
2295         if (fexit->nr_links)
2296                 if (invoke_bpf(m, &prog, fexit, regs_off, run_ctx_off, false)) {
2297                         ret = -EINVAL;
2298                         goto cleanup;
2299                 }
2300
2301         if (flags & BPF_TRAMP_F_RESTORE_REGS)
2302                 restore_regs(m, &prog, nr_args, regs_off);
2303
2304         /* This needs to be done regardless. If there were fmod_ret programs,
2305          * the return value is only updated on the stack and still needs to be
2306          * restored to R0.
2307          */
2308         if (flags & BPF_TRAMP_F_CALL_ORIG) {
2309                 im->ip_epilogue = prog;
2310                 /* arg1: mov rdi, im */
2311                 emit_mov_imm64(&prog, BPF_REG_1, (long) im >> 32, (u32) (long) im);
2312                 if (emit_rsb_call(&prog, __bpf_tramp_exit, prog)) {
2313                         ret = -EINVAL;
2314                         goto cleanup;
2315                 }
2316         }
2317         /* restore return value of orig_call or fentry prog back into RAX */
2318         if (save_ret)
2319                 emit_ldx(&prog, BPF_DW, BPF_REG_0, BPF_REG_FP, -8);
2320
2321         EMIT1(0x5B); /* pop rbx */
2322         EMIT1(0xC9); /* leave */
2323         if (flags & BPF_TRAMP_F_SKIP_FRAME)
2324                 /* skip our return address and return to parent */
2325                 EMIT4(0x48, 0x83, 0xC4, 8); /* add rsp, 8 */
2326         emit_return(&prog, prog);
2327         /* Make sure the trampoline generation logic doesn't overflow */
2328         if (WARN_ON_ONCE(prog > (u8 *)image_end - BPF_INSN_SAFETY)) {
2329                 ret = -EFAULT;
2330                 goto cleanup;
2331         }
2332         ret = prog - (u8 *)image;
2333
2334 cleanup:
2335         kfree(branches);
2336         return ret;
2337 }
2338
2339 static int emit_bpf_dispatcher(u8 **pprog, int a, int b, s64 *progs, u8 *image, u8 *buf)
2340 {
2341         u8 *jg_reloc, *prog = *pprog;
2342         int pivot, err, jg_bytes = 1;
2343         s64 jg_offset;
2344
2345         if (a == b) {
2346                 /* Leaf node of recursion, i.e. not a range of indices
2347                  * anymore.
2348                  */
2349                 EMIT1(add_1mod(0x48, BPF_REG_3));       /* cmp rdx,func */
2350                 if (!is_simm32(progs[a]))
2351                         return -1;
2352                 EMIT2_off32(0x81, add_1reg(0xF8, BPF_REG_3),
2353                             progs[a]);
2354                 err = emit_cond_near_jump(&prog,        /* je func */
2355                                           (void *)progs[a], image + (prog - buf),
2356                                           X86_JE);
2357                 if (err)
2358                         return err;
2359
2360                 emit_indirect_jump(&prog, 2 /* rdx */, image + (prog - buf));
2361
2362                 *pprog = prog;
2363                 return 0;
2364         }
2365
2366         /* Not a leaf node, so we pivot, and recursively descend into
2367          * the lower and upper ranges.
2368          */
2369         pivot = (b - a) / 2;
2370         EMIT1(add_1mod(0x48, BPF_REG_3));               /* cmp rdx,func */
2371         if (!is_simm32(progs[a + pivot]))
2372                 return -1;
2373         EMIT2_off32(0x81, add_1reg(0xF8, BPF_REG_3), progs[a + pivot]);
2374
2375         if (pivot > 2) {                                /* jg upper_part */
2376                 /* Require near jump. */
2377                 jg_bytes = 4;
2378                 EMIT2_off32(0x0F, X86_JG + 0x10, 0);
2379         } else {
2380                 EMIT2(X86_JG, 0);
2381         }
2382         jg_reloc = prog;
2383
2384         err = emit_bpf_dispatcher(&prog, a, a + pivot,  /* emit lower_part */
2385                                   progs, image, buf);
2386         if (err)
2387                 return err;
2388
2389         /* From Intel 64 and IA-32 Architectures Optimization
2390          * Reference Manual, 3.4.1.4 Code Alignment, Assembly/Compiler
2391          * Coding Rule 11: All branch targets should be 16-byte
2392          * aligned.
2393          */
2394         emit_align(&prog, 16);
2395         jg_offset = prog - jg_reloc;
2396         emit_code(jg_reloc - jg_bytes, jg_offset, jg_bytes);
2397
2398         err = emit_bpf_dispatcher(&prog, a + pivot + 1, /* emit upper_part */
2399                                   b, progs, image, buf);
2400         if (err)
2401                 return err;
2402
2403         *pprog = prog;
2404         return 0;
2405 }
2406
2407 static int cmp_ips(const void *a, const void *b)
2408 {
2409         const s64 *ipa = a;
2410         const s64 *ipb = b;
2411
2412         if (*ipa > *ipb)
2413                 return 1;
2414         if (*ipa < *ipb)
2415                 return -1;
2416         return 0;
2417 }
2418
2419 int arch_prepare_bpf_dispatcher(void *image, void *buf, s64 *funcs, int num_funcs)
2420 {
2421         u8 *prog = buf;
2422
2423         sort(funcs, num_funcs, sizeof(funcs[0]), cmp_ips, NULL);
2424         return emit_bpf_dispatcher(&prog, 0, num_funcs - 1, funcs, image, buf);
2425 }
2426
2427 struct x64_jit_data {
2428         struct bpf_binary_header *rw_header;
2429         struct bpf_binary_header *header;
2430         int *addrs;
2431         u8 *image;
2432         int proglen;
2433         struct jit_context ctx;
2434 };
2435
2436 #define MAX_PASSES 20
2437 #define PADDING_PASSES (MAX_PASSES - 5)
2438
2439 struct bpf_prog *bpf_int_jit_compile(struct bpf_prog *prog)
2440 {
2441         struct bpf_binary_header *rw_header = NULL;
2442         struct bpf_binary_header *header = NULL;
2443         struct bpf_prog *tmp, *orig_prog = prog;
2444         struct x64_jit_data *jit_data;
2445         int proglen, oldproglen = 0;
2446         struct jit_context ctx = {};
2447         bool tmp_blinded = false;
2448         bool extra_pass = false;
2449         bool padding = false;
2450         u8 *rw_image = NULL;
2451         u8 *image = NULL;
2452         int *addrs;
2453         int pass;
2454         int i;
2455
2456         if (!prog->jit_requested)
2457                 return orig_prog;
2458
2459         tmp = bpf_jit_blind_constants(prog);
2460         /*
2461          * If blinding was requested and we failed during blinding,
2462          * we must fall back to the interpreter.
2463          */
2464         if (IS_ERR(tmp))
2465                 return orig_prog;
2466         if (tmp != prog) {
2467                 tmp_blinded = true;
2468                 prog = tmp;
2469         }
2470
2471         jit_data = prog->aux->jit_data;
2472         if (!jit_data) {
2473                 jit_data = kzalloc(sizeof(*jit_data), GFP_KERNEL);
2474                 if (!jit_data) {
2475                         prog = orig_prog;
2476                         goto out;
2477                 }
2478                 prog->aux->jit_data = jit_data;
2479         }
2480         addrs = jit_data->addrs;
2481         if (addrs) {
2482                 ctx = jit_data->ctx;
2483                 oldproglen = jit_data->proglen;
2484                 image = jit_data->image;
2485                 header = jit_data->header;
2486                 rw_header = jit_data->rw_header;
2487                 rw_image = (void *)rw_header + ((void *)image - (void *)header);
2488                 extra_pass = true;
2489                 padding = true;
2490                 goto skip_init_addrs;
2491         }
2492         addrs = kvmalloc_array(prog->len + 1, sizeof(*addrs), GFP_KERNEL);
2493         if (!addrs) {
2494                 prog = orig_prog;
2495                 goto out_addrs;
2496         }
2497
2498         /*
2499          * Before first pass, make a rough estimation of addrs[]
2500          * each BPF instruction is translated to less than 64 bytes
2501          */
2502         for (proglen = 0, i = 0; i <= prog->len; i++) {
2503                 proglen += 64;
2504                 addrs[i] = proglen;
2505         }
2506         ctx.cleanup_addr = proglen;
2507 skip_init_addrs:
2508
2509         /*
2510          * JITed image shrinks with every pass and the loop iterates
2511          * until the image stops shrinking. Very large BPF programs
2512          * may converge on the last pass. In such case do one more
2513          * pass to emit the final image.
2514          */
2515         for (pass = 0; pass < MAX_PASSES || image; pass++) {
2516                 if (!padding && pass >= PADDING_PASSES)
2517                         padding = true;
2518                 proglen = do_jit(prog, addrs, image, rw_image, oldproglen, &ctx, padding);
2519                 if (proglen <= 0) {
2520 out_image:
2521                         image = NULL;
2522                         if (header) {
2523                                 bpf_arch_text_copy(&header->size, &rw_header->size,
2524                                                    sizeof(rw_header->size));
2525                                 bpf_jit_binary_pack_free(header, rw_header);
2526                         }
2527                         /* Fall back to interpreter mode */
2528                         prog = orig_prog;
2529                         if (extra_pass) {
2530                                 prog->bpf_func = NULL;
2531                                 prog->jited = 0;
2532                                 prog->jited_len = 0;
2533                         }
2534                         goto out_addrs;
2535                 }
2536                 if (image) {
2537                         if (proglen != oldproglen) {
2538                                 pr_err("bpf_jit: proglen=%d != oldproglen=%d\n",
2539                                        proglen, oldproglen);
2540                                 goto out_image;
2541                         }
2542                         break;
2543                 }
2544                 if (proglen == oldproglen) {
2545                         /*
2546                          * The number of entries in extable is the number of BPF_LDX
2547                          * insns that access kernel memory via "pointer to BTF type".
2548                          * The verifier changed their opcode from LDX|MEM|size
2549                          * to LDX|PROBE_MEM|size to make JITing easier.
2550                          */
2551                         u32 align = __alignof__(struct exception_table_entry);
2552                         u32 extable_size = prog->aux->num_exentries *
2553                                 sizeof(struct exception_table_entry);
2554
2555                         /* allocate module memory for x86 insns and extable */
2556                         header = bpf_jit_binary_pack_alloc(roundup(proglen, align) + extable_size,
2557                                                            &image, align, &rw_header, &rw_image,
2558                                                            jit_fill_hole);
2559                         if (!header) {
2560                                 prog = orig_prog;
2561                                 goto out_addrs;
2562                         }
2563                         prog->aux->extable = (void *) image + roundup(proglen, align);
2564                 }
2565                 oldproglen = proglen;
2566                 cond_resched();
2567         }
2568
2569         if (bpf_jit_enable > 1)
2570                 bpf_jit_dump(prog->len, proglen, pass + 1, image);
2571
2572         if (image) {
2573                 if (!prog->is_func || extra_pass) {
2574                         /*
2575                          * bpf_jit_binary_pack_finalize fails in two scenarios:
2576                          *   1) header is not pointing to proper module memory;
2577                          *   2) the arch doesn't support bpf_arch_text_copy().
2578                          *
2579                          * Both cases are serious bugs and justify WARN_ON.
2580                          */
2581                         if (WARN_ON(bpf_jit_binary_pack_finalize(prog, header, rw_header))) {
2582                                 /* header has been freed */
2583                                 header = NULL;
2584                                 goto out_image;
2585                         }
2586
2587                         bpf_tail_call_direct_fixup(prog);
2588                 } else {
2589                         jit_data->addrs = addrs;
2590                         jit_data->ctx = ctx;
2591                         jit_data->proglen = proglen;
2592                         jit_data->image = image;
2593                         jit_data->header = header;
2594                         jit_data->rw_header = rw_header;
2595                 }
2596                 prog->bpf_func = (void *)image;
2597                 prog->jited = 1;
2598                 prog->jited_len = proglen;
2599         } else {
2600                 prog = orig_prog;
2601         }
2602
2603         if (!image || !prog->is_func || extra_pass) {
2604                 if (image)
2605                         bpf_prog_fill_jited_linfo(prog, addrs + 1);
2606 out_addrs:
2607                 kvfree(addrs);
2608                 kfree(jit_data);
2609                 prog->aux->jit_data = NULL;
2610         }
2611 out:
2612         if (tmp_blinded)
2613                 bpf_jit_prog_release_other(prog, prog == orig_prog ?
2614                                            tmp : orig_prog);
2615         return prog;
2616 }
2617
2618 bool bpf_jit_supports_kfunc_call(void)
2619 {
2620         return true;
2621 }
2622
2623 void *bpf_arch_text_copy(void *dst, void *src, size_t len)
2624 {
2625         if (text_poke_copy(dst, src, len) == NULL)
2626                 return ERR_PTR(-EINVAL);
2627         return dst;
2628 }
2629
2630 /* Indicate the JIT backend supports mixing bpf2bpf and tailcalls. */
2631 bool bpf_jit_supports_subprog_tailcalls(void)
2632 {
2633         return true;
2634 }
2635
2636 void bpf_jit_free(struct bpf_prog *prog)
2637 {
2638         if (prog->jited) {
2639                 struct x64_jit_data *jit_data = prog->aux->jit_data;
2640                 struct bpf_binary_header *hdr;
2641
2642                 /*
2643                  * If we fail the final pass of JIT (from jit_subprogs),
2644                  * the program may not be finalized yet. Call finalize here
2645                  * before freeing it.
2646                  */
2647                 if (jit_data) {
2648                         bpf_jit_binary_pack_finalize(prog, jit_data->header,
2649                                                      jit_data->rw_header);
2650                         kvfree(jit_data->addrs);
2651                         kfree(jit_data);
2652                 }
2653                 hdr = bpf_jit_binary_pack_hdr(prog);
2654                 bpf_jit_binary_pack_free(hdr, NULL);
2655                 WARN_ON_ONCE(!bpf_prog_kallsyms_verify_off(prog));
2656         }
2657
2658         bpf_prog_unlock_free(prog);
2659 }