1 // SPDX-License-Identifier: GPL-2.0-only
3 * AMD CPU Microcode Update Driver for Linux
5 * This driver allows to upgrade microcode on F10h AMD
8 * Copyright (C) 2008-2011 Advanced Micro Devices Inc.
17 * Copyright (C) 2013 Advanced Micro Devices, Inc.
22 #define pr_fmt(fmt) "microcode: " fmt
24 #include <linux/earlycpio.h>
25 #include <linux/firmware.h>
26 #include <linux/uaccess.h>
27 #include <linux/vmalloc.h>
28 #include <linux/initrd.h>
29 #include <linux/kernel.h>
30 #include <linux/pci.h>
32 #include <asm/microcode_amd.h>
33 #include <asm/microcode.h>
34 #include <asm/processor.h>
35 #include <asm/setup.h>
39 static struct equiv_cpu_table {
40 unsigned int num_entries;
41 struct equiv_cpu_entry *entry;
45 * This points to the current valid container of microcode patches which we will
46 * save from the initrd/builtin before jettisoning its contents. @mc is the
47 * microcode patch we found to match.
50 struct microcode_amd *mc;
57 static u32 ucode_new_rev;
58 static u8 amd_ucode_patch[PATCH_MAX_SIZE];
61 * Microcode patch container file is prepended to the initrd in cpio
62 * format. See Documentation/x86/microcode.rst
65 ucode_path[] __maybe_unused = "kernel/x86/microcode/AuthenticAMD.bin";
67 static u16 find_equiv_id(struct equiv_cpu_table *et, u32 sig)
71 if (!et || !et->num_entries)
74 for (i = 0; i < et->num_entries; i++) {
75 struct equiv_cpu_entry *e = &et->entry[i];
77 if (sig == e->installed_cpu)
86 * Check whether there is a valid microcode container file at the beginning
87 * of @buf of size @buf_size. Set @early to use this function in the early path.
89 static bool verify_container(const u8 *buf, size_t buf_size, bool early)
93 if (buf_size <= CONTAINER_HDR_SZ) {
95 pr_debug("Truncated microcode container header.\n");
100 cont_magic = *(const u32 *)buf;
101 if (cont_magic != UCODE_MAGIC) {
103 pr_debug("Invalid magic value (0x%08x).\n", cont_magic);
112 * Check whether there is a valid, non-truncated CPU equivalence table at the
113 * beginning of @buf of size @buf_size. Set @early to use this function in the
116 static bool verify_equivalence_table(const u8 *buf, size_t buf_size, bool early)
118 const u32 *hdr = (const u32 *)buf;
119 u32 cont_type, equiv_tbl_len;
121 if (!verify_container(buf, buf_size, early))
125 if (cont_type != UCODE_EQUIV_CPU_TABLE_TYPE) {
127 pr_debug("Wrong microcode container equivalence table type: %u.\n",
133 buf_size -= CONTAINER_HDR_SZ;
135 equiv_tbl_len = hdr[2];
136 if (equiv_tbl_len < sizeof(struct equiv_cpu_entry) ||
137 buf_size < equiv_tbl_len) {
139 pr_debug("Truncated equivalence table.\n");
148 * Check whether there is a valid, non-truncated microcode patch section at the
149 * beginning of @buf of size @buf_size. Set @early to use this function in the
152 * On success, @sh_psize returns the patch size according to the section header,
156 __verify_patch_section(const u8 *buf, size_t buf_size, u32 *sh_psize, bool early)
161 if (buf_size < SECTION_HDR_SIZE) {
163 pr_debug("Truncated patch section.\n");
168 hdr = (const u32 *)buf;
172 if (p_type != UCODE_UCODE_TYPE) {
174 pr_debug("Invalid type field (0x%x) in container file section header.\n",
180 if (p_size < sizeof(struct microcode_header_amd)) {
182 pr_debug("Patch of size %u too short.\n", p_size);
193 * Check whether the passed remaining file @buf_size is large enough to contain
194 * a patch of the indicated @sh_psize (and also whether this size does not
195 * exceed the per-family maximum). @sh_psize is the size read from the section
198 static unsigned int __verify_patch_size(u8 family, u32 sh_psize, size_t buf_size)
203 return min_t(u32, sh_psize, buf_size);
205 #define F1XH_MPB_MAX_SIZE 2048
206 #define F14H_MPB_MAX_SIZE 1824
210 max_size = F1XH_MPB_MAX_SIZE;
213 max_size = F14H_MPB_MAX_SIZE;
216 WARN(1, "%s: WTF family: 0x%x\n", __func__, family);
220 if (sh_psize > min_t(u32, buf_size, max_size))
227 * Verify the patch in @buf.
231 * positive: patch is not for this family, skip it
235 verify_patch(u8 family, const u8 *buf, size_t buf_size, u32 *patch_size, bool early)
237 struct microcode_header_amd *mc_hdr;
243 if (!__verify_patch_section(buf, buf_size, &sh_psize, early))
247 * The section header length is not included in this indicated size
248 * but is present in the leftover file length so we need to subtract
249 * it before passing this value to the function below.
251 buf_size -= SECTION_HDR_SIZE;
254 * Check if the remaining buffer is big enough to contain a patch of
255 * size sh_psize, as the section claims.
257 if (buf_size < sh_psize) {
259 pr_debug("Patch of size %u truncated.\n", sh_psize);
264 ret = __verify_patch_size(family, sh_psize, buf_size);
267 pr_debug("Per-family patch size mismatch.\n");
271 *patch_size = sh_psize;
273 mc_hdr = (struct microcode_header_amd *)(buf + SECTION_HDR_SIZE);
274 if (mc_hdr->nb_dev_id || mc_hdr->sb_dev_id) {
276 pr_err("Patch-ID 0x%08x: chipset-specific code unsupported.\n", mc_hdr->patch_id);
280 proc_id = mc_hdr->processor_rev_id;
281 patch_fam = 0xf + (proc_id >> 12);
282 if (patch_fam != family)
289 * This scans the ucode blob for the proper container as we can have multiple
290 * containers glued together. Returns the equivalence ID from the equivalence
291 * table or 0 if none found.
292 * Returns the amount of bytes consumed while scanning. @desc contains all the
293 * data we're going to use in later stages of the application.
295 static size_t parse_container(u8 *ucode, size_t size, struct cont_desc *desc)
297 struct equiv_cpu_table table;
298 size_t orig_size = size;
299 u32 *hdr = (u32 *)ucode;
303 if (!verify_equivalence_table(ucode, size, true))
308 table.entry = (struct equiv_cpu_entry *)(buf + CONTAINER_HDR_SZ);
309 table.num_entries = hdr[2] / sizeof(struct equiv_cpu_entry);
312 * Find the equivalence ID of our CPU in this table. Even if this table
313 * doesn't contain a patch for the CPU, scan through the whole container
314 * so that it can be skipped in case there are other containers appended.
316 eq_id = find_equiv_id(&table, desc->cpuid_1_eax);
318 buf += hdr[2] + CONTAINER_HDR_SZ;
319 size -= hdr[2] + CONTAINER_HDR_SZ;
322 * Scan through the rest of the container to find where it ends. We do
323 * some basic sanity-checking too.
326 struct microcode_amd *mc;
330 ret = verify_patch(x86_family(desc->cpuid_1_eax), buf, size, &patch_size, true);
333 * Patch verification failed, skip to the next
334 * container, if there's one:
337 } else if (ret > 0) {
341 mc = (struct microcode_amd *)(buf + SECTION_HDR_SIZE);
342 if (eq_id == mc->hdr.processor_rev_id) {
343 desc->psize = patch_size;
348 /* Skip patch section header too: */
349 buf += patch_size + SECTION_HDR_SIZE;
350 size -= patch_size + SECTION_HDR_SIZE;
354 * If we have found a patch (desc->mc), it means we're looking at the
355 * container which has a patch for this CPU so return 0 to mean, @ucode
356 * already points to the proper container. Otherwise, we return the size
357 * we scanned so that we can advance to the next container in the
362 desc->size = orig_size - size;
368 return orig_size - size;
372 * Scan the ucode blob for the proper container as we can have multiple
373 * containers glued together.
375 static void scan_containers(u8 *ucode, size_t size, struct cont_desc *desc)
378 size_t s = parse_container(ucode, size, desc);
382 /* catch wraparound */
392 static int __apply_microcode_amd(struct microcode_amd *mc)
396 native_wrmsrl(MSR_AMD64_PATCH_LOADER, (u64)(long)&mc->hdr.data_code);
398 /* verify patch application was successful */
399 native_rdmsr(MSR_AMD64_PATCH_LEVEL, rev, dummy);
400 if (rev != mc->hdr.patch_id)
407 * Early load occurs before we can vmalloc(). So we look for the microcode
408 * patch container file in initrd, traverse equivalent cpu table, look for a
409 * matching microcode patch, and update, all in initrd memory in place.
410 * When vmalloc() is available for use later -- on 64-bit during first AP load,
411 * and on 32-bit during save_microcode_in_initrd_amd() -- we can call
412 * load_microcode_amd() to save equivalent cpu table and microcode patches in
413 * kernel heap memory.
415 * Returns true if container found (sets @desc), false otherwise.
418 apply_microcode_early_amd(u32 cpuid_1_eax, void *ucode, size_t size, bool save_patch)
420 struct cont_desc desc = { 0 };
421 u8 (*patch)[PATCH_MAX_SIZE];
422 struct microcode_amd *mc;
423 u32 rev, dummy, *new_rev;
427 new_rev = (u32 *)__pa_nodebug(&ucode_new_rev);
428 patch = (u8 (*)[PATCH_MAX_SIZE])__pa_nodebug(&amd_ucode_patch);
430 new_rev = &ucode_new_rev;
431 patch = &amd_ucode_patch;
434 desc.cpuid_1_eax = cpuid_1_eax;
436 scan_containers(ucode, size, &desc);
442 native_rdmsr(MSR_AMD64_PATCH_LEVEL, rev, dummy);
445 * Allow application of the same revision to pick up SMT-specific
446 * changes even if the revision of the other SMT thread is already
449 if (rev > mc->hdr.patch_id)
452 if (!__apply_microcode_amd(mc)) {
453 *new_rev = mc->hdr.patch_id;
457 memcpy(patch, mc, min_t(u32, desc.psize, PATCH_MAX_SIZE));
463 static bool get_builtin_microcode(struct cpio_data *cp, unsigned int family)
465 char fw_name[36] = "amd-ucode/microcode_amd.bin";
468 if (IS_ENABLED(CONFIG_X86_32))
472 snprintf(fw_name, sizeof(fw_name),
473 "amd-ucode/microcode_amd_fam%.2xh.bin", family);
475 if (firmware_request_builtin(&fw, fw_name)) {
477 cp->data = (void *)fw.data;
484 static void __load_ucode_amd(unsigned int cpuid_1_eax, struct cpio_data *ret)
486 struct ucode_cpu_info *uci;
491 if (IS_ENABLED(CONFIG_X86_32)) {
492 uci = (struct ucode_cpu_info *)__pa_nodebug(ucode_cpu_info);
493 path = (const char *)__pa_nodebug(ucode_path);
496 uci = ucode_cpu_info;
501 if (!get_builtin_microcode(&cp, x86_family(cpuid_1_eax)))
502 cp = find_microcode_in_initrd(path, use_pa);
504 /* Needed in load_microcode_amd() */
505 uci->cpu_sig.sig = cpuid_1_eax;
510 void __init load_ucode_amd_bsp(unsigned int cpuid_1_eax)
512 struct cpio_data cp = { };
514 __load_ucode_amd(cpuid_1_eax, &cp);
515 if (!(cp.data && cp.size))
518 apply_microcode_early_amd(cpuid_1_eax, cp.data, cp.size, true);
521 void load_ucode_amd_ap(unsigned int cpuid_1_eax)
523 struct microcode_amd *mc;
525 u32 *new_rev, rev, dummy;
527 if (IS_ENABLED(CONFIG_X86_32)) {
528 mc = (struct microcode_amd *)__pa_nodebug(amd_ucode_patch);
529 new_rev = (u32 *)__pa_nodebug(&ucode_new_rev);
531 mc = (struct microcode_amd *)amd_ucode_patch;
532 new_rev = &ucode_new_rev;
535 native_rdmsr(MSR_AMD64_PATCH_LEVEL, rev, dummy);
538 * Check whether a new patch has been saved already. Also, allow application of
539 * the same revision in order to pick up SMT-thread-specific configuration even
540 * if the sibling SMT thread already has an up-to-date revision.
542 if (*new_rev && rev <= mc->hdr.patch_id) {
543 if (!__apply_microcode_amd(mc)) {
544 *new_rev = mc->hdr.patch_id;
549 __load_ucode_amd(cpuid_1_eax, &cp);
550 if (!(cp.data && cp.size))
553 apply_microcode_early_amd(cpuid_1_eax, cp.data, cp.size, false);
556 static enum ucode_state
557 load_microcode_amd(bool save, u8 family, const u8 *data, size_t size);
559 int __init save_microcode_in_initrd_amd(unsigned int cpuid_1_eax)
561 struct cont_desc desc = { 0 };
562 enum ucode_state ret;
565 cp = find_microcode_in_initrd(ucode_path, false);
566 if (!(cp.data && cp.size))
569 desc.cpuid_1_eax = cpuid_1_eax;
571 scan_containers(cp.data, cp.size, &desc);
575 ret = load_microcode_amd(true, x86_family(cpuid_1_eax), desc.data, desc.size);
576 if (ret > UCODE_UPDATED)
582 void reload_ucode_amd(void)
584 struct microcode_amd *mc;
585 u32 rev, dummy __always_unused;
587 mc = (struct microcode_amd *)amd_ucode_patch;
589 rdmsr(MSR_AMD64_PATCH_LEVEL, rev, dummy);
591 if (rev < mc->hdr.patch_id) {
592 if (!__apply_microcode_amd(mc)) {
593 ucode_new_rev = mc->hdr.patch_id;
594 pr_info("reload patch_level=0x%08x\n", ucode_new_rev);
598 static u16 __find_equiv_id(unsigned int cpu)
600 struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
601 return find_equiv_id(&equiv_table, uci->cpu_sig.sig);
605 * a small, trivial cache of per-family ucode patches
607 static struct ucode_patch *cache_find_patch(u16 equiv_cpu)
609 struct ucode_patch *p;
611 list_for_each_entry(p, µcode_cache, plist)
612 if (p->equiv_cpu == equiv_cpu)
617 static void update_cache(struct ucode_patch *new_patch)
619 struct ucode_patch *p;
621 list_for_each_entry(p, µcode_cache, plist) {
622 if (p->equiv_cpu == new_patch->equiv_cpu) {
623 if (p->patch_id >= new_patch->patch_id) {
624 /* we already have the latest patch */
625 kfree(new_patch->data);
630 list_replace(&p->plist, &new_patch->plist);
636 /* no patch found, add it */
637 list_add_tail(&new_patch->plist, µcode_cache);
640 static void free_cache(void)
642 struct ucode_patch *p, *tmp;
644 list_for_each_entry_safe(p, tmp, µcode_cache, plist) {
645 __list_del(p->plist.prev, p->plist.next);
651 static struct ucode_patch *find_patch(unsigned int cpu)
655 equiv_id = __find_equiv_id(cpu);
659 return cache_find_patch(equiv_id);
662 static int collect_cpu_info_amd(int cpu, struct cpu_signature *csig)
664 struct cpuinfo_x86 *c = &cpu_data(cpu);
665 struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
666 struct ucode_patch *p;
668 csig->sig = cpuid_eax(0x00000001);
669 csig->rev = c->microcode;
672 * a patch could have been loaded early, set uci->mc so that
673 * mc_bp_resume() can call apply_microcode()
676 if (p && (p->patch_id == csig->rev))
679 pr_info("CPU%d: patch_level=0x%08x\n", cpu, csig->rev);
684 static enum ucode_state apply_microcode_amd(int cpu)
686 struct cpuinfo_x86 *c = &cpu_data(cpu);
687 struct microcode_amd *mc_amd;
688 struct ucode_cpu_info *uci;
689 struct ucode_patch *p;
690 enum ucode_state ret;
691 u32 rev, dummy __always_unused;
693 BUG_ON(raw_smp_processor_id() != cpu);
695 uci = ucode_cpu_info + cpu;
704 rdmsr(MSR_AMD64_PATCH_LEVEL, rev, dummy);
706 /* need to apply patch? */
707 if (rev >= mc_amd->hdr.patch_id) {
712 if (__apply_microcode_amd(mc_amd)) {
713 pr_err("CPU%d: update failed for patch_level=0x%08x\n",
714 cpu, mc_amd->hdr.patch_id);
718 rev = mc_amd->hdr.patch_id;
721 pr_info("CPU%d: new patch_level=0x%08x\n", cpu, rev);
724 uci->cpu_sig.rev = rev;
727 /* Update boot_cpu_data's revision too, if we're on the BSP: */
728 if (c->cpu_index == boot_cpu_data.cpu_index)
729 boot_cpu_data.microcode = rev;
734 static size_t install_equiv_cpu_table(const u8 *buf, size_t buf_size)
739 if (!verify_equivalence_table(buf, buf_size, false))
742 hdr = (const u32 *)buf;
743 equiv_tbl_len = hdr[2];
745 equiv_table.entry = vmalloc(equiv_tbl_len);
746 if (!equiv_table.entry) {
747 pr_err("failed to allocate equivalent CPU table\n");
751 memcpy(equiv_table.entry, buf + CONTAINER_HDR_SZ, equiv_tbl_len);
752 equiv_table.num_entries = equiv_tbl_len / sizeof(struct equiv_cpu_entry);
754 /* add header length */
755 return equiv_tbl_len + CONTAINER_HDR_SZ;
758 static void free_equiv_cpu_table(void)
760 vfree(equiv_table.entry);
761 memset(&equiv_table, 0, sizeof(equiv_table));
764 static void cleanup(void)
766 free_equiv_cpu_table();
771 * Return a non-negative value even if some of the checks failed so that
772 * we can skip over the next patch. If we return a negative value, we
773 * signal a grave error like a memory allocation has failed and the
774 * driver cannot continue functioning normally. In such cases, we tear
775 * down everything we've used up so far and exit.
777 static int verify_and_add_patch(u8 family, u8 *fw, unsigned int leftover,
778 unsigned int *patch_size)
780 struct microcode_header_amd *mc_hdr;
781 struct ucode_patch *patch;
785 ret = verify_patch(family, fw, leftover, patch_size, false);
789 patch = kzalloc(sizeof(*patch), GFP_KERNEL);
791 pr_err("Patch allocation failure.\n");
795 patch->data = kmemdup(fw + SECTION_HDR_SIZE, *patch_size, GFP_KERNEL);
797 pr_err("Patch data allocation failure.\n");
801 patch->size = *patch_size;
803 mc_hdr = (struct microcode_header_amd *)(fw + SECTION_HDR_SIZE);
804 proc_id = mc_hdr->processor_rev_id;
806 INIT_LIST_HEAD(&patch->plist);
807 patch->patch_id = mc_hdr->patch_id;
808 patch->equiv_cpu = proc_id;
810 pr_debug("%s: Added patch_id: 0x%08x, proc_id: 0x%04x\n",
811 __func__, patch->patch_id, proc_id);
813 /* ... and add to cache. */
819 static enum ucode_state __load_microcode_amd(u8 family, const u8 *data,
825 offset = install_equiv_cpu_table(data, size);
832 if (*(u32 *)fw != UCODE_UCODE_TYPE) {
833 pr_err("invalid type field in container file section header\n");
834 free_equiv_cpu_table();
839 unsigned int crnt_size = 0;
842 ret = verify_and_add_patch(family, fw, size, &crnt_size);
846 fw += crnt_size + SECTION_HDR_SIZE;
847 size -= (crnt_size + SECTION_HDR_SIZE);
853 static enum ucode_state
854 load_microcode_amd(bool save, u8 family, const u8 *data, size_t size)
856 struct ucode_patch *p;
857 enum ucode_state ret;
859 /* free old equiv table */
860 free_equiv_cpu_table();
862 ret = __load_microcode_amd(family, data, size);
863 if (ret != UCODE_OK) {
872 if (boot_cpu_data.microcode >= p->patch_id)
878 /* save BSP's matching patch for early load */
882 memset(amd_ucode_patch, 0, PATCH_MAX_SIZE);
883 memcpy(amd_ucode_patch, p->data, min_t(u32, p->size, PATCH_MAX_SIZE));
889 * AMD microcode firmware naming convention, up to family 15h they are in
892 * amd-ucode/microcode_amd.bin
894 * This legacy file is always smaller than 2K in size.
896 * Beginning with family 15h, they are in family-specific firmware files:
898 * amd-ucode/microcode_amd_fam15h.bin
899 * amd-ucode/microcode_amd_fam16h.bin
902 * These might be larger than 2K.
904 static enum ucode_state request_microcode_amd(int cpu, struct device *device)
906 char fw_name[36] = "amd-ucode/microcode_amd.bin";
907 struct cpuinfo_x86 *c = &cpu_data(cpu);
908 bool bsp = c->cpu_index == boot_cpu_data.cpu_index;
909 enum ucode_state ret = UCODE_NFOUND;
910 const struct firmware *fw;
912 /* reload ucode container only on the boot cpu */
917 snprintf(fw_name, sizeof(fw_name), "amd-ucode/microcode_amd_fam%.2xh.bin", c->x86);
919 if (request_firmware_direct(&fw, (const char *)fw_name, device)) {
920 pr_debug("failed to load file %s\n", fw_name);
925 if (!verify_container(fw->data, fw->size, false))
928 ret = load_microcode_amd(bsp, c->x86, fw->data, fw->size);
931 release_firmware(fw);
937 static void microcode_fini_cpu_amd(int cpu)
939 struct ucode_cpu_info *uci = ucode_cpu_info + cpu;
944 static struct microcode_ops microcode_amd_ops = {
945 .request_microcode_fw = request_microcode_amd,
946 .collect_cpu_info = collect_cpu_info_amd,
947 .apply_microcode = apply_microcode_amd,
948 .microcode_fini_cpu = microcode_fini_cpu_amd,
951 struct microcode_ops * __init init_amd_microcode(void)
953 struct cpuinfo_x86 *c = &boot_cpu_data;
955 if (c->x86_vendor != X86_VENDOR_AMD || c->x86 < 0x10) {
956 pr_warn("AMD CPU family 0x%x not supported\n", c->x86);
961 pr_info_once("microcode updated early to new patch_level=0x%08x\n",
964 return µcode_amd_ops;
967 void __exit exit_amd_microcode(void)