1 // SPDX-License-Identifier: GPL-2.0-or-later
3 * In-Memory Collection (IMC) Performance Monitor counter support.
5 * Copyright (C) 2017 Madhavan Srinivasan, IBM Corporation.
6 * (C) 2017 Anju T Sudhakar, IBM Corporation.
7 * (C) 2017 Hemant K Shaw, IBM Corporation.
10 #include <linux/perf_event.h>
11 #include <linux/slab.h>
13 #include <asm/imc-pmu.h>
14 #include <asm/cputhreads.h>
16 #include <linux/string.h>
18 /* Nest IMC data structures and variables */
21 * Used to avoid races in counting the nest-pmu units during hotplug
22 * register and unregister
24 static DEFINE_MUTEX(nest_init_lock);
25 static DEFINE_PER_CPU(struct imc_pmu_ref *, local_nest_imc_refc);
26 static struct imc_pmu **per_nest_pmu_arr;
27 static cpumask_t nest_imc_cpumask;
28 static struct imc_pmu_ref *nest_imc_refc;
31 /* Core IMC data structures and variables */
33 static cpumask_t core_imc_cpumask;
34 static struct imc_pmu_ref *core_imc_refc;
35 static struct imc_pmu *core_imc_pmu;
37 /* Thread IMC data structures and variables */
39 static DEFINE_PER_CPU(u64 *, thread_imc_mem);
40 static struct imc_pmu *thread_imc_pmu;
41 static int thread_imc_mem_size;
43 /* Trace IMC data structures */
44 static DEFINE_PER_CPU(u64 *, trace_imc_mem);
45 static struct imc_pmu_ref *trace_imc_refc;
46 static int trace_imc_mem_size;
49 * Global data structure used to avoid races between thread,
52 static struct imc_pmu_ref imc_global_refc = {
53 .lock = __MUTEX_INITIALIZER(imc_global_refc.lock),
58 static struct imc_pmu *imc_event_to_pmu(struct perf_event *event)
60 return container_of(event->pmu, struct imc_pmu, pmu);
63 PMU_FORMAT_ATTR(event, "config:0-61");
64 PMU_FORMAT_ATTR(offset, "config:0-31");
65 PMU_FORMAT_ATTR(rvalue, "config:32");
66 PMU_FORMAT_ATTR(mode, "config:33-40");
67 static struct attribute *imc_format_attrs[] = {
68 &format_attr_event.attr,
69 &format_attr_offset.attr,
70 &format_attr_rvalue.attr,
71 &format_attr_mode.attr,
75 static const struct attribute_group imc_format_group = {
77 .attrs = imc_format_attrs,
80 /* Format attribute for imc trace-mode */
81 PMU_FORMAT_ATTR(cpmc_reserved, "config:0-19");
82 PMU_FORMAT_ATTR(cpmc_event, "config:20-27");
83 PMU_FORMAT_ATTR(cpmc_samplesel, "config:28-29");
84 PMU_FORMAT_ATTR(cpmc_load, "config:30-61");
85 static struct attribute *trace_imc_format_attrs[] = {
86 &format_attr_event.attr,
87 &format_attr_cpmc_reserved.attr,
88 &format_attr_cpmc_event.attr,
89 &format_attr_cpmc_samplesel.attr,
90 &format_attr_cpmc_load.attr,
94 static const struct attribute_group trace_imc_format_group = {
96 .attrs = trace_imc_format_attrs,
99 /* Get the cpumask printed to a buffer "buf" */
100 static ssize_t imc_pmu_cpumask_get_attr(struct device *dev,
101 struct device_attribute *attr,
104 struct pmu *pmu = dev_get_drvdata(dev);
105 struct imc_pmu *imc_pmu = container_of(pmu, struct imc_pmu, pmu);
106 cpumask_t *active_mask;
108 switch(imc_pmu->domain){
109 case IMC_DOMAIN_NEST:
110 active_mask = &nest_imc_cpumask;
112 case IMC_DOMAIN_CORE:
113 active_mask = &core_imc_cpumask;
119 return cpumap_print_to_pagebuf(true, buf, active_mask);
122 static DEVICE_ATTR(cpumask, S_IRUGO, imc_pmu_cpumask_get_attr, NULL);
124 static struct attribute *imc_pmu_cpumask_attrs[] = {
125 &dev_attr_cpumask.attr,
129 static const struct attribute_group imc_pmu_cpumask_attr_group = {
130 .attrs = imc_pmu_cpumask_attrs,
133 /* device_str_attr_create : Populate event "name" and string "str" in attribute */
134 static struct attribute *device_str_attr_create(const char *name, const char *str)
136 struct perf_pmu_events_attr *attr;
138 attr = kzalloc(sizeof(*attr), GFP_KERNEL);
141 sysfs_attr_init(&attr->attr.attr);
143 attr->event_str = str;
144 attr->attr.attr.name = name;
145 attr->attr.attr.mode = 0444;
146 attr->attr.show = perf_event_sysfs_show;
148 return &attr->attr.attr;
151 static int imc_parse_event(struct device_node *np, const char *scale,
152 const char *unit, const char *prefix,
153 u32 base, struct imc_events *event)
158 if (of_property_read_u32(np, "reg", ®))
160 /* Add the base_reg value to the "reg" */
161 event->value = base + reg;
163 if (of_property_read_string(np, "event-name", &s))
166 event->name = kasprintf(GFP_KERNEL, "%s%s", prefix, s);
170 if (of_property_read_string(np, "scale", &s))
174 event->scale = kstrdup(s, GFP_KERNEL);
179 if (of_property_read_string(np, "unit", &s))
183 event->unit = kstrdup(s, GFP_KERNEL);
197 * imc_free_events: Function to cleanup the events list, having
200 static void imc_free_events(struct imc_events *events, int nr_entries)
204 /* Nothing to clean, return */
207 for (i = 0; i < nr_entries; i++) {
208 kfree(events[i].unit);
209 kfree(events[i].scale);
210 kfree(events[i].name);
217 * update_events_in_group: Update the "events" information in an attr_group
218 * and assign the attr_group to the pmu "pmu".
220 static int update_events_in_group(struct device_node *node, struct imc_pmu *pmu)
222 struct attribute_group *attr_group;
223 struct attribute **attrs, *dev_str;
224 struct device_node *np, *pmu_events;
225 u32 handle, base_reg;
226 int i = 0, j = 0, ct, ret;
227 const char *prefix, *g_scale, *g_unit;
228 const char *ev_val_str, *ev_scale_str, *ev_unit_str;
230 if (!of_property_read_u32(node, "events", &handle))
231 pmu_events = of_find_node_by_phandle(handle);
235 /* Did not find any node with a given phandle */
239 /* Get a count of number of child nodes */
240 ct = of_get_child_count(pmu_events);
242 /* Get the event prefix */
243 if (of_property_read_string(node, "events-prefix", &prefix)) {
244 of_node_put(pmu_events);
248 /* Get a global unit and scale data if available */
249 if (of_property_read_string(node, "scale", &g_scale))
252 if (of_property_read_string(node, "unit", &g_unit))
255 /* "reg" property gives out the base offset of the counters data */
256 of_property_read_u32(node, "reg", &base_reg);
258 /* Allocate memory for the events */
259 pmu->events = kcalloc(ct, sizeof(struct imc_events), GFP_KERNEL);
261 of_node_put(pmu_events);
266 /* Parse the events and update the struct */
267 for_each_child_of_node(pmu_events, np) {
268 ret = imc_parse_event(np, g_scale, g_unit, prefix, base_reg, &pmu->events[ct]);
273 of_node_put(pmu_events);
275 /* Allocate memory for attribute group */
276 attr_group = kzalloc(sizeof(*attr_group), GFP_KERNEL);
278 imc_free_events(pmu->events, ct);
283 * Allocate memory for attributes.
284 * Since we have count of events for this pmu, we also allocate
285 * memory for the scale and unit attribute for now.
286 * "ct" has the total event structs added from the events-parent node.
287 * So allocate three times the "ct" (this includes event, event_scale and
290 attrs = kcalloc(((ct * 3) + 1), sizeof(struct attribute *), GFP_KERNEL);
293 imc_free_events(pmu->events, ct);
297 attr_group->name = "events";
298 attr_group->attrs = attrs;
300 ev_val_str = kasprintf(GFP_KERNEL, "event=0x%x", pmu->events[i].value);
301 dev_str = device_str_attr_create(pmu->events[i].name, ev_val_str);
305 attrs[j++] = dev_str;
306 if (pmu->events[i].scale) {
307 ev_scale_str = kasprintf(GFP_KERNEL, "%s.scale", pmu->events[i].name);
308 dev_str = device_str_attr_create(ev_scale_str, pmu->events[i].scale);
312 attrs[j++] = dev_str;
315 if (pmu->events[i].unit) {
316 ev_unit_str = kasprintf(GFP_KERNEL, "%s.unit", pmu->events[i].name);
317 dev_str = device_str_attr_create(ev_unit_str, pmu->events[i].unit);
321 attrs[j++] = dev_str;
325 /* Save the event attribute */
326 pmu->attr_groups[IMC_EVENT_ATTR] = attr_group;
331 /* get_nest_pmu_ref: Return the imc_pmu_ref struct for the given node */
332 static struct imc_pmu_ref *get_nest_pmu_ref(int cpu)
334 return per_cpu(local_nest_imc_refc, cpu);
337 static void nest_change_cpu_context(int old_cpu, int new_cpu)
339 struct imc_pmu **pn = per_nest_pmu_arr;
341 if (old_cpu < 0 || new_cpu < 0)
345 perf_pmu_migrate_context(&(*pn)->pmu, old_cpu, new_cpu);
350 static int ppc_nest_imc_cpu_offline(unsigned int cpu)
352 int nid, target = -1;
353 const struct cpumask *l_cpumask;
354 struct imc_pmu_ref *ref;
357 * Check in the designated list for this cpu. Dont bother
358 * if not one of them.
360 if (!cpumask_test_and_clear_cpu(cpu, &nest_imc_cpumask))
364 * Check whether nest_imc is registered. We could end up here if the
365 * cpuhotplug callback registration fails. i.e, callback invokes the
366 * offline path for all successfully registered nodes. At this stage,
367 * nest_imc pmu will not be registered and we should return here.
369 * We return with a zero since this is not an offline failure. And
370 * cpuhp_setup_state() returns the actual failure reason to the caller,
371 * which in turn will call the cleanup routine.
377 * Now that this cpu is one of the designated,
378 * find a next cpu a) which is online and b) in same chip.
380 nid = cpu_to_node(cpu);
381 l_cpumask = cpumask_of_node(nid);
382 target = cpumask_last(l_cpumask);
385 * If this(target) is the last cpu in the cpumask for this chip,
386 * check for any possible online cpu in the chip.
388 if (unlikely(target == cpu))
389 target = cpumask_any_but(l_cpumask, cpu);
392 * Update the cpumask with the target cpu and
393 * migrate the context if needed
395 if (target >= 0 && target < nr_cpu_ids) {
396 cpumask_set_cpu(target, &nest_imc_cpumask);
397 nest_change_cpu_context(cpu, target);
399 opal_imc_counters_stop(OPAL_IMC_COUNTERS_NEST,
400 get_hard_smp_processor_id(cpu));
402 * If this is the last cpu in this chip then, skip the reference
403 * count mutex lock and make the reference count on this chip zero.
405 ref = get_nest_pmu_ref(cpu);
414 static int ppc_nest_imc_cpu_online(unsigned int cpu)
416 const struct cpumask *l_cpumask;
417 static struct cpumask tmp_mask;
420 /* Get the cpumask of this node */
421 l_cpumask = cpumask_of_node(cpu_to_node(cpu));
424 * If this is not the first online CPU on this node, then
427 if (cpumask_and(&tmp_mask, l_cpumask, &nest_imc_cpumask))
431 * If this is the first online cpu on this node
432 * disable the nest counters by making an OPAL call.
434 res = opal_imc_counters_stop(OPAL_IMC_COUNTERS_NEST,
435 get_hard_smp_processor_id(cpu));
439 /* Make this CPU the designated target for counter collection */
440 cpumask_set_cpu(cpu, &nest_imc_cpumask);
444 static int nest_pmu_cpumask_init(void)
446 return cpuhp_setup_state(CPUHP_AP_PERF_POWERPC_NEST_IMC_ONLINE,
447 "perf/powerpc/imc:online",
448 ppc_nest_imc_cpu_online,
449 ppc_nest_imc_cpu_offline);
452 static void nest_imc_counters_release(struct perf_event *event)
455 struct imc_pmu_ref *ref;
460 node_id = cpu_to_node(event->cpu);
463 * See if we need to disable the nest PMU.
464 * If no events are currently in use, then we have to take a
465 * mutex to ensure that we don't race with another task doing
466 * enable or disable the nest counters.
468 ref = get_nest_pmu_ref(event->cpu);
472 /* Take the mutex lock for this node and then decrement the reference count */
473 mutex_lock(&ref->lock);
474 if (ref->refc == 0) {
476 * The scenario where this is true is, when perf session is
477 * started, followed by offlining of all cpus in a given node.
479 * In the cpuhotplug offline path, ppc_nest_imc_cpu_offline()
480 * function set the ref->count to zero, if the cpu which is
481 * about to offline is the last cpu in a given node and make
482 * an OPAL call to disable the engine in that node.
485 mutex_unlock(&ref->lock);
489 if (ref->refc == 0) {
490 rc = opal_imc_counters_stop(OPAL_IMC_COUNTERS_NEST,
491 get_hard_smp_processor_id(event->cpu));
493 mutex_unlock(&ref->lock);
494 pr_err("nest-imc: Unable to stop the counters for core %d\n", node_id);
497 } else if (ref->refc < 0) {
498 WARN(1, "nest-imc: Invalid event reference count\n");
501 mutex_unlock(&ref->lock);
504 static int nest_imc_event_init(struct perf_event *event)
506 int chip_id, rc, node_id;
507 u32 l_config, config = event->attr.config;
508 struct imc_mem_info *pcni;
510 struct imc_pmu_ref *ref;
513 if (event->attr.type != event->pmu->type)
516 /* Sampling not supported */
517 if (event->hw.sample_period)
523 pmu = imc_event_to_pmu(event);
525 /* Sanity check for config (event offset) */
526 if ((config & IMC_EVENT_OFFSET_MASK) > pmu->counter_mem_size)
530 * Nest HW counter memory resides in a per-chip reserve-memory (HOMER).
531 * Get the base memory address for this cpu.
533 chip_id = cpu_to_chip_id(event->cpu);
535 /* Return, if chip_id is not valid */
539 pcni = pmu->mem_info;
541 if (pcni->id == chip_id) {
546 } while (pcni->vbase != 0);
552 * Add the event offset to the base address.
554 l_config = config & IMC_EVENT_OFFSET_MASK;
555 event->hw.event_base = (u64)pcni->vbase + l_config;
556 node_id = cpu_to_node(event->cpu);
559 * Get the imc_pmu_ref struct for this node.
560 * Take the mutex lock and then increment the count of nest pmu events
563 ref = get_nest_pmu_ref(event->cpu);
567 mutex_lock(&ref->lock);
568 if (ref->refc == 0) {
569 rc = opal_imc_counters_start(OPAL_IMC_COUNTERS_NEST,
570 get_hard_smp_processor_id(event->cpu));
572 mutex_unlock(&ref->lock);
573 pr_err("nest-imc: Unable to start the counters for node %d\n",
579 mutex_unlock(&ref->lock);
581 event->destroy = nest_imc_counters_release;
586 * core_imc_mem_init : Initializes memory for the current core.
588 * Uses alloc_pages_node() and uses the returned address as an argument to
589 * an opal call to configure the pdbar. The address sent as an argument is
590 * converted to physical address before the opal call is made. This is the
591 * base address at which the core imc counters are populated.
593 static int core_imc_mem_init(int cpu, int size)
595 int nid, rc = 0, core_id = (cpu / threads_per_core);
596 struct imc_mem_info *mem_info;
600 * alloc_pages_node() will allocate memory for core in the
603 nid = cpu_to_node(cpu);
604 mem_info = &core_imc_pmu->mem_info[core_id];
605 mem_info->id = core_id;
607 /* We need only vbase for core counters */
608 page = alloc_pages_node(nid,
609 GFP_KERNEL | __GFP_ZERO | __GFP_THISNODE |
610 __GFP_NOWARN, get_order(size));
613 mem_info->vbase = page_address(page);
616 core_imc_refc[core_id].id = core_id;
617 mutex_init(&core_imc_refc[core_id].lock);
619 rc = opal_imc_counters_init(OPAL_IMC_COUNTERS_CORE,
620 __pa((void *)mem_info->vbase),
621 get_hard_smp_processor_id(cpu));
623 free_pages((u64)mem_info->vbase, get_order(size));
624 mem_info->vbase = NULL;
630 static bool is_core_imc_mem_inited(int cpu)
632 struct imc_mem_info *mem_info;
633 int core_id = (cpu / threads_per_core);
635 mem_info = &core_imc_pmu->mem_info[core_id];
636 if (!mem_info->vbase)
642 static int ppc_core_imc_cpu_online(unsigned int cpu)
644 const struct cpumask *l_cpumask;
645 static struct cpumask tmp_mask;
648 /* Get the cpumask for this core */
649 l_cpumask = cpu_sibling_mask(cpu);
651 /* If a cpu for this core is already set, then, don't do anything */
652 if (cpumask_and(&tmp_mask, l_cpumask, &core_imc_cpumask))
655 if (!is_core_imc_mem_inited(cpu)) {
656 ret = core_imc_mem_init(cpu, core_imc_pmu->counter_mem_size);
658 pr_info("core_imc memory allocation for cpu %d failed\n", cpu);
663 /* set the cpu in the mask */
664 cpumask_set_cpu(cpu, &core_imc_cpumask);
668 static int ppc_core_imc_cpu_offline(unsigned int cpu)
670 unsigned int core_id;
672 struct imc_pmu_ref *ref;
675 * clear this cpu out of the mask, if not present in the mask,
676 * don't bother doing anything.
678 if (!cpumask_test_and_clear_cpu(cpu, &core_imc_cpumask))
682 * Check whether core_imc is registered. We could end up here
683 * if the cpuhotplug callback registration fails. i.e, callback
684 * invokes the offline path for all successfully registered cpus.
685 * At this stage, core_imc pmu will not be registered and we
686 * should return here.
688 * We return with a zero since this is not an offline failure.
689 * And cpuhp_setup_state() returns the actual failure reason
690 * to the caller, which inturn will call the cleanup routine.
692 if (!core_imc_pmu->pmu.event_init)
695 /* Find any online cpu in that core except the current "cpu" */
696 ncpu = cpumask_last(cpu_sibling_mask(cpu));
698 if (unlikely(ncpu == cpu))
699 ncpu = cpumask_any_but(cpu_sibling_mask(cpu), cpu);
701 if (ncpu >= 0 && ncpu < nr_cpu_ids) {
702 cpumask_set_cpu(ncpu, &core_imc_cpumask);
703 perf_pmu_migrate_context(&core_imc_pmu->pmu, cpu, ncpu);
706 * If this is the last cpu in this core then, skip taking refernce
707 * count mutex lock for this core and directly zero "refc" for
710 opal_imc_counters_stop(OPAL_IMC_COUNTERS_CORE,
711 get_hard_smp_processor_id(cpu));
712 core_id = cpu / threads_per_core;
713 ref = &core_imc_refc[core_id];
719 * Reduce the global reference count, if this is the
720 * last cpu in this core and core-imc event running
723 mutex_lock(&imc_global_refc.lock);
724 if (imc_global_refc.id == IMC_DOMAIN_CORE)
725 imc_global_refc.refc--;
727 mutex_unlock(&imc_global_refc.lock);
732 static int core_imc_pmu_cpumask_init(void)
734 return cpuhp_setup_state(CPUHP_AP_PERF_POWERPC_CORE_IMC_ONLINE,
735 "perf/powerpc/imc_core:online",
736 ppc_core_imc_cpu_online,
737 ppc_core_imc_cpu_offline);
740 static void reset_global_refc(struct perf_event *event)
742 mutex_lock(&imc_global_refc.lock);
743 imc_global_refc.refc--;
746 * If no other thread is running any
747 * event for this domain(thread/core/trace),
748 * set the global id to zero.
750 if (imc_global_refc.refc <= 0) {
751 imc_global_refc.refc = 0;
752 imc_global_refc.id = 0;
754 mutex_unlock(&imc_global_refc.lock);
757 static void core_imc_counters_release(struct perf_event *event)
760 struct imc_pmu_ref *ref;
765 * See if we need to disable the IMC PMU.
766 * If no events are currently in use, then we have to take a
767 * mutex to ensure that we don't race with another task doing
768 * enable or disable the core counters.
770 core_id = event->cpu / threads_per_core;
772 /* Take the mutex lock and decrement the refernce count for this core */
773 ref = &core_imc_refc[core_id];
777 mutex_lock(&ref->lock);
778 if (ref->refc == 0) {
780 * The scenario where this is true is, when perf session is
781 * started, followed by offlining of all cpus in a given core.
783 * In the cpuhotplug offline path, ppc_core_imc_cpu_offline()
784 * function set the ref->count to zero, if the cpu which is
785 * about to offline is the last cpu in a given core and make
786 * an OPAL call to disable the engine in that core.
789 mutex_unlock(&ref->lock);
793 if (ref->refc == 0) {
794 rc = opal_imc_counters_stop(OPAL_IMC_COUNTERS_CORE,
795 get_hard_smp_processor_id(event->cpu));
797 mutex_unlock(&ref->lock);
798 pr_err("IMC: Unable to stop the counters for core %d\n", core_id);
801 } else if (ref->refc < 0) {
802 WARN(1, "core-imc: Invalid event reference count\n");
805 mutex_unlock(&ref->lock);
807 reset_global_refc(event);
810 static int core_imc_event_init(struct perf_event *event)
813 u64 config = event->attr.config;
814 struct imc_mem_info *pcmi;
816 struct imc_pmu_ref *ref;
818 if (event->attr.type != event->pmu->type)
821 /* Sampling not supported */
822 if (event->hw.sample_period)
829 pmu = imc_event_to_pmu(event);
831 /* Sanity check for config (event offset) */
832 if (((config & IMC_EVENT_OFFSET_MASK) > pmu->counter_mem_size))
835 if (!is_core_imc_mem_inited(event->cpu))
838 core_id = event->cpu / threads_per_core;
839 pcmi = &core_imc_pmu->mem_info[core_id];
843 /* Get the core_imc mutex for this core */
844 ref = &core_imc_refc[core_id];
849 * Core pmu units are enabled only when it is used.
850 * See if this is triggered for the first time.
851 * If yes, take the mutex lock and enable the core counters.
852 * If not, just increment the count in core_imc_refc struct.
854 mutex_lock(&ref->lock);
855 if (ref->refc == 0) {
856 rc = opal_imc_counters_start(OPAL_IMC_COUNTERS_CORE,
857 get_hard_smp_processor_id(event->cpu));
859 mutex_unlock(&ref->lock);
860 pr_err("core-imc: Unable to start the counters for core %d\n",
866 mutex_unlock(&ref->lock);
869 * Since the system can run either in accumulation or trace-mode
870 * of IMC at a time, core-imc events are allowed only if no other
871 * trace/thread imc events are enabled/monitored.
873 * Take the global lock, and check the refc.id
874 * to know whether any other trace/thread imc
875 * events are running.
877 mutex_lock(&imc_global_refc.lock);
878 if (imc_global_refc.id == 0 || imc_global_refc.id == IMC_DOMAIN_CORE) {
880 * No other trace/thread imc events are running in
881 * the system, so set the refc.id to core-imc.
883 imc_global_refc.id = IMC_DOMAIN_CORE;
884 imc_global_refc.refc++;
886 mutex_unlock(&imc_global_refc.lock);
889 mutex_unlock(&imc_global_refc.lock);
891 event->hw.event_base = (u64)pcmi->vbase + (config & IMC_EVENT_OFFSET_MASK);
892 event->destroy = core_imc_counters_release;
897 * Allocates a page of memory for each of the online cpus, and load
899 * The physical base address of the page allocated for a cpu will be
900 * written to the LDBAR for that cpu, when the thread-imc event
903 * LDBAR Register Layout:
905 * 0 4 8 12 16 20 24 28
906 * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
907 * | | [ ] [ Counter Address [8:50]
912 * 32 36 40 44 48 52 56 60
913 * | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - | - - - - |
914 * Counter Address [8:50] ]
917 static int thread_imc_mem_alloc(int cpu_id, int size)
919 u64 *local_mem = per_cpu(thread_imc_mem, cpu_id);
920 int nid = cpu_to_node(cpu_id);
925 * This case could happen only once at start, since we dont
926 * free the memory in cpu offline path.
928 page = alloc_pages_node(nid,
929 GFP_KERNEL | __GFP_ZERO | __GFP_THISNODE |
930 __GFP_NOWARN, get_order(size));
933 local_mem = page_address(page);
935 per_cpu(thread_imc_mem, cpu_id) = local_mem;
938 mtspr(SPRN_LDBAR, 0);
942 static int ppc_thread_imc_cpu_online(unsigned int cpu)
944 return thread_imc_mem_alloc(cpu, thread_imc_mem_size);
947 static int ppc_thread_imc_cpu_offline(unsigned int cpu)
950 * Set the bit 0 of LDBAR to zero.
952 * If bit 0 of LDBAR is unset, it will stop posting
953 * the counter data to memory.
954 * For thread-imc, bit 0 of LDBAR will be set to 1 in the
955 * event_add function. So reset this bit here, to stop the updates
956 * to memory in the cpu_offline path.
958 mtspr(SPRN_LDBAR, (mfspr(SPRN_LDBAR) & (~(1UL << 63))));
960 /* Reduce the refc if thread-imc event running on this cpu */
961 mutex_lock(&imc_global_refc.lock);
962 if (imc_global_refc.id == IMC_DOMAIN_THREAD)
963 imc_global_refc.refc--;
964 mutex_unlock(&imc_global_refc.lock);
969 static int thread_imc_cpu_init(void)
971 return cpuhp_setup_state(CPUHP_AP_PERF_POWERPC_THREAD_IMC_ONLINE,
972 "perf/powerpc/imc_thread:online",
973 ppc_thread_imc_cpu_online,
974 ppc_thread_imc_cpu_offline);
977 static int thread_imc_event_init(struct perf_event *event)
979 u32 config = event->attr.config;
980 struct task_struct *target;
983 if (event->attr.type != event->pmu->type)
986 if (!perfmon_capable())
989 /* Sampling not supported */
990 if (event->hw.sample_period)
994 pmu = imc_event_to_pmu(event);
996 /* Sanity check for config offset */
997 if (((config & IMC_EVENT_OFFSET_MASK) > pmu->counter_mem_size))
1000 target = event->hw.target;
1004 mutex_lock(&imc_global_refc.lock);
1006 * Check if any other trace/core imc events are running in the
1007 * system, if not set the global id to thread-imc.
1009 if (imc_global_refc.id == 0 || imc_global_refc.id == IMC_DOMAIN_THREAD) {
1010 imc_global_refc.id = IMC_DOMAIN_THREAD;
1011 imc_global_refc.refc++;
1013 mutex_unlock(&imc_global_refc.lock);
1016 mutex_unlock(&imc_global_refc.lock);
1018 event->pmu->task_ctx_nr = perf_sw_context;
1019 event->destroy = reset_global_refc;
1023 static bool is_thread_imc_pmu(struct perf_event *event)
1025 if (!strncmp(event->pmu->name, "thread_imc", strlen("thread_imc")))
1031 static u64 * get_event_base_addr(struct perf_event *event)
1035 if (is_thread_imc_pmu(event)) {
1036 addr = (u64)per_cpu(thread_imc_mem, smp_processor_id());
1037 return (u64 *)(addr + (event->attr.config & IMC_EVENT_OFFSET_MASK));
1040 return (u64 *)event->hw.event_base;
1043 static void thread_imc_pmu_start_txn(struct pmu *pmu,
1044 unsigned int txn_flags)
1046 if (txn_flags & ~PERF_PMU_TXN_ADD)
1048 perf_pmu_disable(pmu);
1051 static void thread_imc_pmu_cancel_txn(struct pmu *pmu)
1053 perf_pmu_enable(pmu);
1056 static int thread_imc_pmu_commit_txn(struct pmu *pmu)
1058 perf_pmu_enable(pmu);
1062 static u64 imc_read_counter(struct perf_event *event)
1067 * In-Memory Collection (IMC) counters are free flowing counters.
1068 * So we take a snapshot of the counter value on enable and save it
1069 * to calculate the delta at later stage to present the event counter
1072 addr = get_event_base_addr(event);
1073 data = be64_to_cpu(READ_ONCE(*addr));
1074 local64_set(&event->hw.prev_count, data);
1079 static void imc_event_update(struct perf_event *event)
1081 u64 counter_prev, counter_new, final_count;
1083 counter_prev = local64_read(&event->hw.prev_count);
1084 counter_new = imc_read_counter(event);
1085 final_count = counter_new - counter_prev;
1087 /* Update the delta to the event count */
1088 local64_add(final_count, &event->count);
1091 static void imc_event_start(struct perf_event *event, int flags)
1094 * In Memory Counters are free flowing counters. HW or the microcode
1095 * keeps adding to the counter offset in memory. To get event
1096 * counter value, we snapshot the value here and we calculate
1097 * delta at later point.
1099 imc_read_counter(event);
1102 static void imc_event_stop(struct perf_event *event, int flags)
1105 * Take a snapshot and calculate the delta and update
1106 * the event counter values.
1108 imc_event_update(event);
1111 static int imc_event_add(struct perf_event *event, int flags)
1113 if (flags & PERF_EF_START)
1114 imc_event_start(event, flags);
1119 static int thread_imc_event_add(struct perf_event *event, int flags)
1122 struct imc_pmu_ref *ref;
1123 u64 ldbar_value, *local_mem = per_cpu(thread_imc_mem, smp_processor_id());
1125 if (flags & PERF_EF_START)
1126 imc_event_start(event, flags);
1128 if (!is_core_imc_mem_inited(smp_processor_id()))
1131 core_id = smp_processor_id() / threads_per_core;
1132 ldbar_value = ((u64)local_mem & THREAD_IMC_LDBAR_MASK) | THREAD_IMC_ENABLE;
1133 mtspr(SPRN_LDBAR, ldbar_value);
1136 * imc pmus are enabled only when it is used.
1137 * See if this is triggered for the first time.
1138 * If yes, take the mutex lock and enable the counters.
1139 * If not, just increment the count in ref count struct.
1141 ref = &core_imc_refc[core_id];
1145 mutex_lock(&ref->lock);
1146 if (ref->refc == 0) {
1147 if (opal_imc_counters_start(OPAL_IMC_COUNTERS_CORE,
1148 get_hard_smp_processor_id(smp_processor_id()))) {
1149 mutex_unlock(&ref->lock);
1150 pr_err("thread-imc: Unable to start the counter\
1151 for core %d\n", core_id);
1156 mutex_unlock(&ref->lock);
1160 static void thread_imc_event_del(struct perf_event *event, int flags)
1164 struct imc_pmu_ref *ref;
1166 core_id = smp_processor_id() / threads_per_core;
1167 ref = &core_imc_refc[core_id];
1169 pr_debug("imc: Failed to get event reference count\n");
1173 mutex_lock(&ref->lock);
1175 if (ref->refc == 0) {
1176 if (opal_imc_counters_stop(OPAL_IMC_COUNTERS_CORE,
1177 get_hard_smp_processor_id(smp_processor_id()))) {
1178 mutex_unlock(&ref->lock);
1179 pr_err("thread-imc: Unable to stop the counters\
1180 for core %d\n", core_id);
1183 } else if (ref->refc < 0) {
1186 mutex_unlock(&ref->lock);
1188 /* Set bit 0 of LDBAR to zero, to stop posting updates to memory */
1189 mtspr(SPRN_LDBAR, (mfspr(SPRN_LDBAR) & (~(1UL << 63))));
1192 * Take a snapshot and calculate the delta and update
1193 * the event counter values.
1195 imc_event_update(event);
1199 * Allocate a page of memory for each cpu, and load LDBAR with 0.
1201 static int trace_imc_mem_alloc(int cpu_id, int size)
1203 u64 *local_mem = per_cpu(trace_imc_mem, cpu_id);
1204 int phys_id = cpu_to_node(cpu_id), rc = 0;
1205 int core_id = (cpu_id / threads_per_core);
1210 page = alloc_pages_node(phys_id,
1211 GFP_KERNEL | __GFP_ZERO | __GFP_THISNODE |
1212 __GFP_NOWARN, get_order(size));
1215 local_mem = page_address(page);
1216 per_cpu(trace_imc_mem, cpu_id) = local_mem;
1218 /* Initialise the counters for trace mode */
1219 rc = opal_imc_counters_init(OPAL_IMC_COUNTERS_TRACE, __pa((void *)local_mem),
1220 get_hard_smp_processor_id(cpu_id));
1222 pr_info("IMC:opal init failed for trace imc\n");
1227 /* Init the mutex, if not already */
1228 trace_imc_refc[core_id].id = core_id;
1229 mutex_init(&trace_imc_refc[core_id].lock);
1231 mtspr(SPRN_LDBAR, 0);
1235 static int ppc_trace_imc_cpu_online(unsigned int cpu)
1237 return trace_imc_mem_alloc(cpu, trace_imc_mem_size);
1240 static int ppc_trace_imc_cpu_offline(unsigned int cpu)
1243 * No need to set bit 0 of LDBAR to zero, as
1244 * it is set to zero for imc trace-mode
1246 * Reduce the refc if any trace-imc event running
1249 mutex_lock(&imc_global_refc.lock);
1250 if (imc_global_refc.id == IMC_DOMAIN_TRACE)
1251 imc_global_refc.refc--;
1252 mutex_unlock(&imc_global_refc.lock);
1257 static int trace_imc_cpu_init(void)
1259 return cpuhp_setup_state(CPUHP_AP_PERF_POWERPC_TRACE_IMC_ONLINE,
1260 "perf/powerpc/imc_trace:online",
1261 ppc_trace_imc_cpu_online,
1262 ppc_trace_imc_cpu_offline);
1265 static u64 get_trace_imc_event_base_addr(void)
1267 return (u64)per_cpu(trace_imc_mem, smp_processor_id());
1271 * Function to parse trace-imc data obtained
1272 * and to prepare the perf sample.
1274 static int trace_imc_prepare_sample(struct trace_imc_data *mem,
1275 struct perf_sample_data *data,
1277 struct perf_event_header *header,
1278 struct perf_event *event)
1280 /* Sanity checks for a valid record */
1281 if (be64_to_cpu(READ_ONCE(mem->tb1)) > *prev_tb)
1282 *prev_tb = be64_to_cpu(READ_ONCE(mem->tb1));
1286 if ((be64_to_cpu(READ_ONCE(mem->tb1)) & IMC_TRACE_RECORD_TB1_MASK) !=
1287 be64_to_cpu(READ_ONCE(mem->tb2)))
1290 /* Prepare perf sample */
1291 data->ip = be64_to_cpu(READ_ONCE(mem->ip));
1292 data->period = event->hw.last_period;
1294 header->type = PERF_RECORD_SAMPLE;
1295 header->size = sizeof(*header) + event->header_size;
1298 if (cpu_has_feature(CPU_FTR_ARCH_31)) {
1299 switch (IMC_TRACE_RECORD_VAL_HVPR(be64_to_cpu(READ_ONCE(mem->val)))) {
1300 case 0:/* when MSR HV and PR not set in the trace-record */
1301 header->misc |= PERF_RECORD_MISC_GUEST_KERNEL;
1303 case 1: /* MSR HV is 0 and PR is 1 */
1304 header->misc |= PERF_RECORD_MISC_GUEST_USER;
1306 case 2: /* MSR HV is 1 and PR is 0 */
1307 header->misc |= PERF_RECORD_MISC_KERNEL;
1309 case 3: /* MSR HV is 1 and PR is 1 */
1310 header->misc |= PERF_RECORD_MISC_USER;
1313 pr_info("IMC: Unable to set the flag based on MSR bits\n");
1317 if (is_kernel_addr(data->ip))
1318 header->misc |= PERF_RECORD_MISC_KERNEL;
1320 header->misc |= PERF_RECORD_MISC_USER;
1322 perf_event_header__init_id(header, data, event);
1327 static void dump_trace_imc_data(struct perf_event *event)
1329 struct trace_imc_data *mem;
1333 mem = (struct trace_imc_data *)get_trace_imc_event_base_addr();
1334 for (i = 0; i < (trace_imc_mem_size / sizeof(struct trace_imc_data));
1336 struct perf_sample_data data;
1337 struct perf_event_header header;
1339 ret = trace_imc_prepare_sample(mem, &data, &prev_tb, &header, event);
1340 if (ret) /* Exit, if not a valid record */
1343 /* If this is a valid record, create the sample */
1344 struct perf_output_handle handle;
1346 if (perf_output_begin(&handle, &data, event, header.size))
1349 perf_output_sample(&handle, &header, &data, event);
1350 perf_output_end(&handle);
1355 static int trace_imc_event_add(struct perf_event *event, int flags)
1357 int core_id = smp_processor_id() / threads_per_core;
1358 struct imc_pmu_ref *ref = NULL;
1359 u64 local_mem, ldbar_value;
1361 /* Set trace-imc bit in ldbar and load ldbar with per-thread memory address */
1362 local_mem = get_trace_imc_event_base_addr();
1363 ldbar_value = ((u64)local_mem & THREAD_IMC_LDBAR_MASK) | TRACE_IMC_ENABLE;
1365 /* trace-imc reference count */
1367 ref = &trace_imc_refc[core_id];
1369 pr_debug("imc: Failed to get the event reference count\n");
1373 mtspr(SPRN_LDBAR, ldbar_value);
1374 mutex_lock(&ref->lock);
1375 if (ref->refc == 0) {
1376 if (opal_imc_counters_start(OPAL_IMC_COUNTERS_TRACE,
1377 get_hard_smp_processor_id(smp_processor_id()))) {
1378 mutex_unlock(&ref->lock);
1379 pr_err("trace-imc: Unable to start the counters for core %d\n", core_id);
1384 mutex_unlock(&ref->lock);
1388 static void trace_imc_event_read(struct perf_event *event)
1393 static void trace_imc_event_stop(struct perf_event *event, int flags)
1395 u64 local_mem = get_trace_imc_event_base_addr();
1396 dump_trace_imc_data(event);
1397 memset((void *)local_mem, 0, sizeof(u64));
1400 static void trace_imc_event_start(struct perf_event *event, int flags)
1405 static void trace_imc_event_del(struct perf_event *event, int flags)
1407 int core_id = smp_processor_id() / threads_per_core;
1408 struct imc_pmu_ref *ref = NULL;
1411 ref = &trace_imc_refc[core_id];
1413 pr_debug("imc: Failed to get event reference count\n");
1417 mutex_lock(&ref->lock);
1419 if (ref->refc == 0) {
1420 if (opal_imc_counters_stop(OPAL_IMC_COUNTERS_TRACE,
1421 get_hard_smp_processor_id(smp_processor_id()))) {
1422 mutex_unlock(&ref->lock);
1423 pr_err("trace-imc: Unable to stop the counters for core %d\n", core_id);
1426 } else if (ref->refc < 0) {
1429 mutex_unlock(&ref->lock);
1431 trace_imc_event_stop(event, flags);
1434 static int trace_imc_event_init(struct perf_event *event)
1436 if (event->attr.type != event->pmu->type)
1439 if (!perfmon_capable())
1442 /* Return if this is a couting event */
1443 if (event->attr.sample_period == 0)
1447 * Take the global lock, and make sure
1448 * no other thread is running any core/thread imc
1451 mutex_lock(&imc_global_refc.lock);
1452 if (imc_global_refc.id == 0 || imc_global_refc.id == IMC_DOMAIN_TRACE) {
1454 * No core/thread imc events are running in the
1455 * system, so set the refc.id to trace-imc.
1457 imc_global_refc.id = IMC_DOMAIN_TRACE;
1458 imc_global_refc.refc++;
1460 mutex_unlock(&imc_global_refc.lock);
1463 mutex_unlock(&imc_global_refc.lock);
1468 * There can only be a single PMU for perf_hw_context events which is assigned to
1469 * core PMU. Hence use "perf_sw_context" for trace_imc.
1471 event->pmu->task_ctx_nr = perf_sw_context;
1472 event->destroy = reset_global_refc;
1476 /* update_pmu_ops : Populate the appropriate operations for "pmu" */
1477 static int update_pmu_ops(struct imc_pmu *pmu)
1479 pmu->pmu.task_ctx_nr = perf_invalid_context;
1480 pmu->pmu.add = imc_event_add;
1481 pmu->pmu.del = imc_event_stop;
1482 pmu->pmu.start = imc_event_start;
1483 pmu->pmu.stop = imc_event_stop;
1484 pmu->pmu.read = imc_event_update;
1485 pmu->pmu.attr_groups = pmu->attr_groups;
1486 pmu->pmu.capabilities = PERF_PMU_CAP_NO_EXCLUDE;
1487 pmu->attr_groups[IMC_FORMAT_ATTR] = &imc_format_group;
1489 switch (pmu->domain) {
1490 case IMC_DOMAIN_NEST:
1491 pmu->pmu.event_init = nest_imc_event_init;
1492 pmu->attr_groups[IMC_CPUMASK_ATTR] = &imc_pmu_cpumask_attr_group;
1494 case IMC_DOMAIN_CORE:
1495 pmu->pmu.event_init = core_imc_event_init;
1496 pmu->attr_groups[IMC_CPUMASK_ATTR] = &imc_pmu_cpumask_attr_group;
1498 case IMC_DOMAIN_THREAD:
1499 pmu->pmu.event_init = thread_imc_event_init;
1500 pmu->pmu.add = thread_imc_event_add;
1501 pmu->pmu.del = thread_imc_event_del;
1502 pmu->pmu.start_txn = thread_imc_pmu_start_txn;
1503 pmu->pmu.cancel_txn = thread_imc_pmu_cancel_txn;
1504 pmu->pmu.commit_txn = thread_imc_pmu_commit_txn;
1506 case IMC_DOMAIN_TRACE:
1507 pmu->pmu.event_init = trace_imc_event_init;
1508 pmu->pmu.add = trace_imc_event_add;
1509 pmu->pmu.del = trace_imc_event_del;
1510 pmu->pmu.start = trace_imc_event_start;
1511 pmu->pmu.stop = trace_imc_event_stop;
1512 pmu->pmu.read = trace_imc_event_read;
1513 pmu->attr_groups[IMC_FORMAT_ATTR] = &trace_imc_format_group;
1522 /* init_nest_pmu_ref: Initialize the imc_pmu_ref struct for all the nodes */
1523 static int init_nest_pmu_ref(void)
1527 nest_imc_refc = kcalloc(num_possible_nodes(), sizeof(*nest_imc_refc),
1534 for_each_node(nid) {
1536 * Mutex lock to avoid races while tracking the number of
1537 * sessions using the chip's nest pmu units.
1539 mutex_init(&nest_imc_refc[i].lock);
1542 * Loop to init the "id" with the node_id. Variable "i" initialized to
1543 * 0 and will be used as index to the array. "i" will not go off the
1544 * end of the array since the "for_each_node" loops for "N_POSSIBLE"
1547 nest_imc_refc[i++].id = nid;
1551 * Loop to init the per_cpu "local_nest_imc_refc" with the proper
1552 * "nest_imc_refc" index. This makes get_nest_pmu_ref() alot simple.
1554 for_each_possible_cpu(cpu) {
1555 nid = cpu_to_node(cpu);
1556 for (i = 0; i < num_possible_nodes(); i++) {
1557 if (nest_imc_refc[i].id == nid) {
1558 per_cpu(local_nest_imc_refc, cpu) = &nest_imc_refc[i];
1566 static void cleanup_all_core_imc_memory(void)
1568 int i, nr_cores = DIV_ROUND_UP(num_possible_cpus(), threads_per_core);
1569 struct imc_mem_info *ptr = core_imc_pmu->mem_info;
1570 int size = core_imc_pmu->counter_mem_size;
1572 /* mem_info will never be NULL */
1573 for (i = 0; i < nr_cores; i++) {
1575 free_pages((u64)ptr[i].vbase, get_order(size));
1579 kfree(core_imc_refc);
1582 static void thread_imc_ldbar_disable(void *dummy)
1585 * By setting 0th bit of LDBAR to zero, we disable thread-imc
1586 * updates to memory.
1588 mtspr(SPRN_LDBAR, (mfspr(SPRN_LDBAR) & (~(1UL << 63))));
1591 void thread_imc_disable(void)
1593 on_each_cpu(thread_imc_ldbar_disable, NULL, 1);
1596 static void cleanup_all_thread_imc_memory(void)
1598 int i, order = get_order(thread_imc_mem_size);
1600 for_each_online_cpu(i) {
1601 if (per_cpu(thread_imc_mem, i))
1602 free_pages((u64)per_cpu(thread_imc_mem, i), order);
1607 static void cleanup_all_trace_imc_memory(void)
1609 int i, order = get_order(trace_imc_mem_size);
1611 for_each_online_cpu(i) {
1612 if (per_cpu(trace_imc_mem, i))
1613 free_pages((u64)per_cpu(trace_imc_mem, i), order);
1616 kfree(trace_imc_refc);
1619 /* Function to free the attr_groups which are dynamically allocated */
1620 static void imc_common_mem_free(struct imc_pmu *pmu_ptr)
1622 if (pmu_ptr->attr_groups[IMC_EVENT_ATTR])
1623 kfree(pmu_ptr->attr_groups[IMC_EVENT_ATTR]->attrs);
1624 kfree(pmu_ptr->attr_groups[IMC_EVENT_ATTR]);
1628 * Common function to unregister cpu hotplug callback and
1630 * TODO: Need to handle pmu unregistering, which will be
1631 * done in followup series.
1633 static void imc_common_cpuhp_mem_free(struct imc_pmu *pmu_ptr)
1635 if (pmu_ptr->domain == IMC_DOMAIN_NEST) {
1636 mutex_lock(&nest_init_lock);
1637 if (nest_pmus == 1) {
1638 cpuhp_remove_state(CPUHP_AP_PERF_POWERPC_NEST_IMC_ONLINE);
1639 kfree(nest_imc_refc);
1640 kfree(per_nest_pmu_arr);
1641 per_nest_pmu_arr = NULL;
1646 mutex_unlock(&nest_init_lock);
1649 /* Free core_imc memory */
1650 if (pmu_ptr->domain == IMC_DOMAIN_CORE) {
1651 cpuhp_remove_state(CPUHP_AP_PERF_POWERPC_CORE_IMC_ONLINE);
1652 cleanup_all_core_imc_memory();
1655 /* Free thread_imc memory */
1656 if (pmu_ptr->domain == IMC_DOMAIN_THREAD) {
1657 cpuhp_remove_state(CPUHP_AP_PERF_POWERPC_THREAD_IMC_ONLINE);
1658 cleanup_all_thread_imc_memory();
1661 if (pmu_ptr->domain == IMC_DOMAIN_TRACE) {
1662 cpuhp_remove_state(CPUHP_AP_PERF_POWERPC_TRACE_IMC_ONLINE);
1663 cleanup_all_trace_imc_memory();
1668 * Function to unregister thread-imc if core-imc
1669 * is not registered.
1671 void unregister_thread_imc(void)
1673 imc_common_cpuhp_mem_free(thread_imc_pmu);
1674 imc_common_mem_free(thread_imc_pmu);
1675 perf_pmu_unregister(&thread_imc_pmu->pmu);
1679 * imc_mem_init : Function to support memory allocation for core imc.
1681 static int imc_mem_init(struct imc_pmu *pmu_ptr, struct device_node *parent,
1685 int nr_cores, cpu, res = -ENOMEM;
1687 if (of_property_read_string(parent, "name", &s))
1690 switch (pmu_ptr->domain) {
1691 case IMC_DOMAIN_NEST:
1692 /* Update the pmu name */
1693 pmu_ptr->pmu.name = kasprintf(GFP_KERNEL, "%s%s_imc", "nest_", s);
1694 if (!pmu_ptr->pmu.name)
1697 /* Needed for hotplug/migration */
1698 if (!per_nest_pmu_arr) {
1699 per_nest_pmu_arr = kcalloc(get_max_nest_dev() + 1,
1700 sizeof(struct imc_pmu *),
1702 if (!per_nest_pmu_arr)
1705 per_nest_pmu_arr[pmu_index] = pmu_ptr;
1707 case IMC_DOMAIN_CORE:
1708 /* Update the pmu name */
1709 pmu_ptr->pmu.name = kasprintf(GFP_KERNEL, "%s%s", s, "_imc");
1710 if (!pmu_ptr->pmu.name)
1713 nr_cores = DIV_ROUND_UP(num_possible_cpus(), threads_per_core);
1714 pmu_ptr->mem_info = kcalloc(nr_cores, sizeof(struct imc_mem_info),
1717 if (!pmu_ptr->mem_info)
1720 core_imc_refc = kcalloc(nr_cores, sizeof(struct imc_pmu_ref),
1723 if (!core_imc_refc) {
1724 kfree(pmu_ptr->mem_info);
1728 core_imc_pmu = pmu_ptr;
1730 case IMC_DOMAIN_THREAD:
1731 /* Update the pmu name */
1732 pmu_ptr->pmu.name = kasprintf(GFP_KERNEL, "%s%s", s, "_imc");
1733 if (!pmu_ptr->pmu.name)
1736 thread_imc_mem_size = pmu_ptr->counter_mem_size;
1737 for_each_online_cpu(cpu) {
1738 res = thread_imc_mem_alloc(cpu, pmu_ptr->counter_mem_size);
1740 cleanup_all_thread_imc_memory();
1745 thread_imc_pmu = pmu_ptr;
1747 case IMC_DOMAIN_TRACE:
1748 /* Update the pmu name */
1749 pmu_ptr->pmu.name = kasprintf(GFP_KERNEL, "%s%s", s, "_imc");
1750 if (!pmu_ptr->pmu.name)
1753 nr_cores = DIV_ROUND_UP(num_possible_cpus(), threads_per_core);
1754 trace_imc_refc = kcalloc(nr_cores, sizeof(struct imc_pmu_ref),
1756 if (!trace_imc_refc)
1759 trace_imc_mem_size = pmu_ptr->counter_mem_size;
1760 for_each_online_cpu(cpu) {
1761 res = trace_imc_mem_alloc(cpu, trace_imc_mem_size);
1763 cleanup_all_trace_imc_memory();
1778 * init_imc_pmu : Setup and register the IMC pmu device.
1780 * @parent: Device tree unit node
1781 * @pmu_ptr: memory allocated for this pmu
1782 * @pmu_idx: Count of nest pmc registered
1784 * init_imc_pmu() setup pmu cpumask and registers for a cpu hotplug callback.
1785 * Handles failure cases and accordingly frees memory.
1787 int init_imc_pmu(struct device_node *parent, struct imc_pmu *pmu_ptr, int pmu_idx)
1791 ret = imc_mem_init(pmu_ptr, parent, pmu_idx);
1795 switch (pmu_ptr->domain) {
1796 case IMC_DOMAIN_NEST:
1798 * Nest imc pmu need only one cpu per chip, we initialize the
1799 * cpumask for the first nest imc pmu and use the same for the
1800 * rest. To handle the cpuhotplug callback unregister, we track
1801 * the number of nest pmus in "nest_pmus".
1803 mutex_lock(&nest_init_lock);
1804 if (nest_pmus == 0) {
1805 ret = init_nest_pmu_ref();
1807 mutex_unlock(&nest_init_lock);
1808 kfree(per_nest_pmu_arr);
1809 per_nest_pmu_arr = NULL;
1812 /* Register for cpu hotplug notification. */
1813 ret = nest_pmu_cpumask_init();
1815 mutex_unlock(&nest_init_lock);
1816 kfree(nest_imc_refc);
1817 kfree(per_nest_pmu_arr);
1818 per_nest_pmu_arr = NULL;
1823 mutex_unlock(&nest_init_lock);
1825 case IMC_DOMAIN_CORE:
1826 ret = core_imc_pmu_cpumask_init();
1828 cleanup_all_core_imc_memory();
1833 case IMC_DOMAIN_THREAD:
1834 ret = thread_imc_cpu_init();
1836 cleanup_all_thread_imc_memory();
1841 case IMC_DOMAIN_TRACE:
1842 ret = trace_imc_cpu_init();
1844 cleanup_all_trace_imc_memory();
1850 return -EINVAL; /* Unknown domain */
1853 ret = update_events_in_group(parent, pmu_ptr);
1855 goto err_free_cpuhp_mem;
1857 ret = update_pmu_ops(pmu_ptr);
1859 goto err_free_cpuhp_mem;
1861 ret = perf_pmu_register(&pmu_ptr->pmu, pmu_ptr->pmu.name, -1);
1863 goto err_free_cpuhp_mem;
1865 pr_debug("%s performance monitor hardware support registered\n",
1871 imc_common_cpuhp_mem_free(pmu_ptr);
1873 imc_common_mem_free(pmu_ptr);