1 /* SPDX-License-Identifier: GPL-2.0-or-later */
7 * Adapted for Power Macintosh by Paul Mackerras.
8 * Low-level exception handlers and MMU support
9 * rewritten by Paul Mackerras.
10 * Copyright (C) 1996 Paul Mackerras.
13 * This file contains the system call entry code, context switch
14 * code, and exception/interrupt return code for PowerPC.
17 #include <linux/objtool.h>
18 #include <linux/errno.h>
19 #include <linux/err.h>
20 #include <asm/cache.h>
21 #include <asm/unistd.h>
22 #include <asm/processor.h>
25 #include <asm/thread_info.h>
26 #include <asm/code-patching-asm.h>
27 #include <asm/ppc_asm.h>
28 #include <asm/asm-offsets.h>
29 #include <asm/cputable.h>
30 #include <asm/firmware.h>
32 #include <asm/ptrace.h>
33 #include <asm/irqflags.h>
34 #include <asm/hw_irq.h>
35 #include <asm/context_tracking.h>
36 #include <asm/ppc-opcode.h>
37 #include <asm/barrier.h>
38 #include <asm/export.h>
39 #include <asm/asm-compat.h>
40 #ifdef CONFIG_PPC_BOOK3S
41 #include <asm/exception-64s.h>
43 #include <asm/exception-64e.h>
45 #include <asm/feature-fixups.h>
53 #ifdef CONFIG_PPC_BOOK3S_64
55 #define FLUSH_COUNT_CACHE \
57 patch_site 1b, patch__call_flush_branch_caches1; \
59 patch_site 1b, patch__call_flush_branch_caches2; \
61 patch_site 1b, patch__call_flush_branch_caches3
70 .global flush_branch_caches
75 // Flush the link stack
77 ANNOTATE_INTRA_FUNCTION_CALL
87 // If we're just flushing the link stack, return here
89 patch_site 3b patch__flush_link_stack_return
97 patch_site 2b patch__flush_count_cache_return
109 #define FLUSH_COUNT_CACHE
110 #endif /* CONFIG_PPC_BOOK3S_64 */
113 * This routine switches between two different tasks. The process
114 * state of one is saved on its kernel stack. Then the state
115 * of the other is restored from its kernel stack. The memory
116 * management hardware is updated to the second process's state.
117 * Finally, we can return to the second process, via interrupt_return.
118 * On entry, r3 points to the THREAD for the current task, r4
119 * points to the THREAD for the new task.
121 * Note: there are two ways to get to the "going out" portion
122 * of this code; either by coming in via the entry (_switch)
123 * or via "fork" which must set up an environment equivalent
124 * to the "_switch" path. If you change this you'll have to change
125 * the fork code also.
127 * The code which creates the new task context is in 'copy_thread'
128 * in arch/powerpc/kernel/process.c
134 stdu r1,-SWITCH_FRAME_SIZE(r1)
135 /* r3-r13 are caller saved -- Cort */
137 std r0,_NIP(r1) /* Return to switch caller */
140 std r1,KSP(r3) /* Set old stack pointer */
142 kuap_check_amr r9, r10
144 FLUSH_COUNT_CACHE /* Clobbers r9, ctr */
147 * On SMP kernels, care must be taken because a task may be
148 * scheduled off CPUx and on to CPUy. Memory ordering must be
151 * Cacheable stores on CPUx will be visible when the task is
152 * scheduled on CPUy by virtue of the core scheduler barriers
153 * (see "Notes on Program-Order guarantees on SMP systems." in
154 * kernel/sched/core.c).
156 * Uncacheable stores in the case of involuntary preemption must
157 * be taken care of. The smp_mb__after_spinlock() in __schedule()
158 * is implemented as hwsync on powerpc, which orders MMIO too. So
159 * long as there is an hwsync in the context switch path, it will
160 * be executed on the source CPU after the task has performed
161 * all MMIO ops on that CPU, and on the destination CPU before the
162 * task performs any MMIO ops there.
166 * The kernel context switch path must contain a spin_lock,
167 * which contains larx/stcx, which will clear any reservation
168 * of the task being switched.
170 #ifdef CONFIG_PPC_BOOK3S
171 /* Cancel all explict user streams as they will have no use after context
172 * switch and will stop the HW from creating streams itself
174 DCBT_BOOK3S_STOP_ALL_STREAM_IDS(r6)
177 addi r6,r4,-THREAD /* Convert THREAD to 'current' */
178 std r6,PACACURRENT(r13) /* Set new 'current' */
179 #if defined(CONFIG_STACKPROTECTOR)
180 ld r6, TASK_CANARY(r6)
181 std r6, PACA_CANARY(r13)
184 ld r8,KSP(r4) /* new stack pointer */
185 #ifdef CONFIG_PPC_64S_HASH_MMU
186 BEGIN_MMU_FTR_SECTION
188 END_MMU_FTR_SECTION_IFSET(MMU_FTR_TYPE_RADIX)
190 clrrdi r6,r8,28 /* get its ESID */
191 clrrdi r9,r1,28 /* get current sp ESID */
193 clrrdi r6,r8,40 /* get its 1T ESID */
194 clrrdi r9,r1,40 /* get current sp 1T ESID */
195 ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_1T_SEGMENT)
196 clrldi. r0,r6,2 /* is new ESID c00000000? */
197 cmpd cr1,r6,r9 /* or is new ESID the same as current ESID? */
199 beq 2f /* if yes, don't slbie it */
201 /* Bolt in the new stack SLB entry */
202 ld r7,KSP_VSID(r4) /* Get new stack's VSID */
203 oris r0,r6,(SLB_ESID_V)@h
204 ori r0,r0,(SLB_NUM_BOLTED-1)@l
206 li r9,MMU_SEGSIZE_1T /* insert B field */
207 oris r6,r6,(MMU_SEGSIZE_1T << SLBIE_SSIZE_SHIFT)@h
208 rldimi r7,r9,SLB_VSID_SSIZE_SHIFT,0
209 END_MMU_FTR_SECTION_IFSET(MMU_FTR_1T_SEGMENT)
211 /* Update the last bolted SLB. No write barriers are needed
212 * here, provided we only update the current CPU's SLB shadow
215 ld r9,PACA_SLBSHADOWPTR(r13)
217 std r12,SLBSHADOW_STACKESID(r9) /* Clear ESID */
218 li r12,SLBSHADOW_STACKVSID
219 STDX_BE r7,r12,r9 /* Save VSID */
220 li r12,SLBSHADOW_STACKESID
221 STDX_BE r0,r12,r9 /* Save ESID */
223 /* No need to check for MMU_FTR_NO_SLBIE_B here, since when
224 * we have 1TB segments, the only CPUs known to have the errata
225 * only support less than 1TB of system memory and we'll never
226 * actually hit this code path.
232 slbie r6 /* Workaround POWER5 < DD2.1 issue */
233 END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
237 #endif /* CONFIG_PPC_64S_HASH_MMU */
239 clrrdi r7, r8, THREAD_SHIFT /* base of new stack */
240 /* Note: this uses SWITCH_FRAME_SIZE rather than INT_FRAME_SIZE
241 because we don't need to leave the 288-byte ABI gap at the
242 top of the kernel stack. */
243 addi r7,r7,THREAD_SIZE-SWITCH_FRAME_SIZE
246 * PMU interrupts in radix may come in here. They will use r1, not
247 * PACAKSAVE, so this stack switch will not cause a problem. They
248 * will store to the process stack, which may then be migrated to
249 * another CPU. However the rq lock release on this CPU paired with
250 * the rq lock acquire on the new CPU before the stack becomes
251 * active on the new CPU, will order those stores.
253 mr r1,r8 /* start using new stack pointer */
254 std r7,PACAKSAVE(r13)
259 /* r3-r13 are destroyed -- Cort */
262 /* convert old thread to its task_struct for return value */
264 ld r7,_NIP(r1) /* Return to _switch caller in new task */
266 addi r1,r1,SWITCH_FRAME_SIZE
272 stdu r1,-SWITCH_FRAME_SIZE(r1) /* Save SP and create stack space */
274 /* Because PROM is running in 32b mode, it clobbers the high order half
275 * of all registers that it saves. We therefore save those registers
276 * PROM might touch to the stack. (r0, r3-r13 are caller saved)
286 /* Put PROM address in SRR0 */
289 /* Setup our trampoline return addr in LR */
295 /* Prepare a 32-bit mode big endian MSR
297 #ifdef CONFIG_PPC_BOOK3E_64
298 rlwinm r11,r11,0,1,31
301 #else /* CONFIG_PPC_BOOK3E_64 */
302 LOAD_REG_IMMEDIATE(r12, MSR_SF | MSR_LE)
306 #endif /* CONFIG_PPC_BOOK3E_64 */
308 1: /* Return from OF */
311 /* Just make sure that r1 top 32 bits didn't get
316 /* Restore the MSR (back to 64 bits) */
321 /* Restore other registers */
328 addi r1,r1,SWITCH_FRAME_SIZE